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2017-12-12staging: fsl-dpaa2/eth: Fix potential endless loopIoana Radulescu
We incorrectly assumed that dpaa2_io_release() can only return -EBUSY as an error code, when in fact it can also fail in case some of its arguments don't have valid values. Make sure we only retry the operation while the portal is busy and abort for all other error cases, otherwise we risk entering an endless loop. Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com> Integrated-by: Guanhua Gao <guanhua.gao@nxp.com>
2017-12-12usb: fsl: Fix compilation errorRamneek Mehresh
Commit 42a1431068088 in the LSDK 4.9 kernel("usb: host: Add support to add/remove usb host driver") introduced the compilation error. We fix it now. Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
2017-12-12fsl/usb: Workarourd for USB erratum-A005697Ramneek Mehresh
As per USB specification, in the Suspend state, the status bit does not change until the port is suspended. However, there may be a delay in suspending a port if there is a transaction currently in progress on the bus. In the USBDR controller, the PORTSCx[SUSP] bit changes immediately when the application sets it and not when the port is actually suspended Workaround for this issue involves waiting for a minimum of 10ms to allow the controller to go into SUSPEND state before proceeding ahead Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Change-Id: I8d20619d7d62afc12981c2f913c3d3ec735f7e64 Reviewed-on: http://git.am.freescale.net:8181/3996 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Aggrwal Poonam-B10812 <Poonam.Aggrwal@freescale.com> Reviewed-by: Rivera Jose-B46482 <Jose.G.Rivera@freescale.com>
2017-12-12PCI: Do not disregard parent resources starting at 0x0Ard Biesheuvel
Commit f44116ae8818 ("PCI: Remove pci_find_parent_resource() use for allocation") updated the logic that iterates over all bus resources and compares them to a given resource, in order to decide whether one is the parent of the latter. This change inadvertently causes pci_find_parent_resource() to disregard resources starting at address 0x0, resulting in an error such as the one below on ARM systems whose I/O window starts at 0x0. pci_bus 0000:00: root bus resource [mem 0x10000000-0x3efeffff window] pci_bus 0000:00: root bus resource [io 0x0000-0xffff window] pci_bus 0000:00: root bus resource [mem 0x8000000000-0xffffffffff window] pci_bus 0000:00: root bus resource [bus 00-0f] pci 0000:00:01.0: PCI bridge to [bus 01] pci 0000:00:02.0: PCI bridge to [bus 02] pci 0000:00:03.0: PCI bridge to [bus 03] pci 0000:00:03.0: can't claim BAR 13 [io 0x0000-0x0fff]: no compatible bridge window pci 0000:03:01.0: can't claim BAR 0 [io 0x0000-0x001f]: no compatible bridge window While this never happens on x86, it is perfectly legal in general for a PCI MMIO or IO window to start at address 0x0, and it was supported in the code before commit f44116ae8818. Drop the test for res->start != 0; resource_contains() already checks whether [start, end) completely covers the resource, and so it should be redundant. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-12-12staging: fsl-dpaa2/eth: Fix compiling errors for backporting dash-ltsGuanhua Gao
Fix compiling errors for backporting dash-lts. Signed-off-by: Guanhua Gao <guanhua.gao>
2017-12-12staging: fsl-dpaa2/eth: Get PFC config from HWBogdan Purcareata
The dpaa2-eth PFC configuration is kept in a private driver variable. When getting PFC configuration via ieee_getpfc, get it straight from the Management Complex based on the Rx congestion notification setup. Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
2017-12-12staging: fsl-dpaa2/eth: Add dpni_get_congestion_notif APIBogdan Purcareata
Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
2017-12-12staging: fsl-dpaa2/eth: Configure PFC in MCBogdan Purcareata
Implement the following: - Enable PFC in DPNI options. - Set queue taildrops for priorities (traffic classes) that are not PFC enabled (pause frames are not sent in case of congestion). Since the buffer pool is shared, we can't risk other traffic to consume all available buffers. - Configure Rx congestion notifications for PFC enabled priorities. Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
2017-12-12staging: fsl-dpaa2/eth: Refactor fq taildrop setupBogdan Purcareata
With the introduction of PFC support, there are multiple ways taildrop is configured, based on the DPNI pause frame configuration: - no pause frames - per-queue taildrop thresholds. - pause frames - no taildrop thresholds (pause frames sent based on buffer depletion). - PFC pause frames - per-group (traffic class) taildrop thresholds for non-PFC enabled priorities (pause frames sent based on Rx congestion notifications). Refactor the fq taildrop setup area. Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
2017-12-12staging: fsl-dpaa2/eth: Add ingress classificationBogdan Purcareata
Configure static ingress classification based on VLAN PCP, required by PFC. Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
2017-12-12staging: fsl-dpaa2/eth: Add DCB supportBogdan Purcareata
Add initial DCB ops in the DPAA2 Ethernet driver. Currently they are dummy calls. Tested integration with userspace lldpad: - lldpad daemon running - bring interface up - lldptool -L -i niX adminStatus=rxtx - lldptool -T -i niX -V PFC -c enabled={prio comma separated list} - lldptool -t -i niX -V PFC -c enabled Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
2017-12-12staging: fsl-dpaa2/eth: Switch to v2 dpni_set_pools cmdBogdan Purcareata
The v2 dpni_set_pools command format allows sending an additional parameter, the priority mask for the buffer pool. This can be used to configure multiple buffer pools for the same dpni, to serve different priorities. Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
2017-12-12staging: fsl-dpaa2/eth: Add fs entries for all tcsBogdan Purcareata
The current MC (10.3.1) design uses a separate flow steering table for each traffic class. When adding a flow steering rule, add it for each traffic class. The location of the rule is the same in all tables. Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
2017-12-12staging: fsl-dpaa2/eth: Handle multiple traffic classesBogdan Purcareata
The driver only handles frame workqueues associated with traffic class 0. Add support for multiple traffic classes for the same flowid, based on the tc field in the fq struct, and the num_tcs parameter in the dpni atttributes. Create a separate fq for each tc x flowid. Display the information in debugfs. Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
2017-12-12mmc: sdhci-of-esdhc: Workaround for reducing the maximum speed on ls1021atwryinbo.zhu
In SDHC high speed AC timing, the tshivkh parameter is defined as input setup times:SDHC_CMD, SDHC_DATx, to SDHC_CLK. The value of the tshivkh should be 2.5 ns considering the round trip delay, board/data skew. However, because of this erratum, it needs at least 4.1 ns. eSDHC cannot run at the maximum clock speed for the high speed mode, or there is a limit on the length of the trace on the board for data, command, and clock lines of the SDHC. Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
2017-12-12mmc: sdhci-of-esdhc: fix eMMC couldn't work after kexecyinbo.zhu
The bit eSDHC_TBCTL[TB_EN] couldn't be reset by eSDHC_SYSCTL[RSTA] which is used to reset for all. The driver should make sure it's cleared before card initialization, otherwise the initialization would fail. Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
2017-12-12PCI: layerscape: Change default error response behaviorMinghuan Lian
[modify to adapt to 4.9, pcie have member pp instead of pci] By default, when the PCIe controller experiences an erroneous completion from an external completer for its outbound non-posted request, it sends an OKAY response to the device's internal AXI slave system interface. However, this default system error response behavior cannot be used for other types of outbound non-posted requests. For example, the outbound memory read transaction requires an actual ERROR response, like UR completion or completion timeout. Fix this by forwarding the error response of the non-posted request. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-12-12PCI: Disable MSI for Freescale Layerscape PCIe RC modeHou Zhiqiang
[context adjustment] The Freescale PCIe controller advertises the MSI/MSI-X capability in both RC and Endpoint mode, but in RC mode it doesn't support MSI/MSI-X by itself; it can only transfer MSI/MSI-X from downstream devices. Add a quirk to prevent use of MSI/MSI-X in RC mode. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Minghuan Lian <minghuan.Lian@nxp.com> Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-12-12crypto: caam/qi2 - add DKP support for tlsHoria Geantă
Add DKP support for tls using caam/qi2 as backend. Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
2017-12-12crypto: caam/qi - add DKP support for tlsHoria Geantă
Add DKP support for tls using caam/qi as backend. Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
2017-12-12crypto: caam/qi2 - add support for ahash algorithmsHoria Geantă
Add support for unkeyed and keyed (hmac) md5, sha algorithms. Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
2017-12-12crypto: caam/qi2 - add DKP support for authenc algosHoria Geantă
Add DKP support for authenc algorithms using caam/qi2 as backend. Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
2017-12-12crypto: caam - export ahash shared descriptor generationHoria Geantă
Upcoming caam/qi2 driver will support ahash algorithms, thus move ahash descriptors generation in a shared location. Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
2017-12-12crypto: caam - add Derived Key Protocol (DKP) supportHoria Geantă
Offload split key generation in CAAM engine, using DKP. DKP is supported starting with Era 6. Note that the way assoclen is transmitted from the job descriptor to the shared descriptor changes - DPOVRD register is used instead of MATH3 (where available), since DKP protocol thrashes the MATH registers. Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
2017-12-12crypto: caam - save Era in driver's private dataHoria Geantă
Save Era in driver's private data for further usage, like deciding whether an erratum applies or a feature is available based on its value. Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
2017-12-12crypto: caam - remove unused param of ctx_map_to_sec4_sg()Horia Geantă
ctx_map_to_sec4_sg() function, added in commit 045e36780f115 ("crypto: caam - ahash hmac support") has never used the "desc" parameter, so let's drop it. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> (cherry picked from commit dfcd8393efefb7a111f9cb6af69058ecaf4a4d72)
2017-12-12crypto: caam - remove unneeded edesc zeroizationHoria Geantă
Extended descriptor allocation has been changed by commit dde20ae9d6383 ("crypto: caam - Change kmalloc to kzalloc to avoid residual data") to provide zeroized memory, meaning we no longer have to sanitize its members - edesc->src_nents and edesc->dst_dma. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> (cherry picked from commit f2ac67746534fab0cbc0bc29bfc3e507b1f58474)
2017-12-12DPAA: adjust DPAA to adapt to Linux 4.9Zhao Qiang
2017-12-12soc/qbman: Disable IRQs for deferred QBMan workRoy Pledge
Work for Congestion State Notifications (CSCN) and Message Ring (MR) handling is handled via the workqueue mechanism. This requires the driver to disable those IRQs before scheduling the work and re-enabling it once the work is completed so that the interrupt doesn't continually fire. Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
2017-12-12fsl/soc/qbman: Enable FSL_LAYERSCAPE config on ARMMadalin Bucur
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> [Stuart: changed to use ARCH_LAYERSCAPE] Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
2017-12-12soc/fsl/qbman: Add missing headers on ARMClaudiu Manoil
Unlike PPC builds, ARM builds need following headers explicitly: +#include <linux/io.h> for ioread32be() +#include <linux/delay.h> for udelay() Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
2017-12-12soc/fsl/qbman: different register offsets on ARMMadalin Bucur
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
2017-12-12soc/fsl/qbman: add QMAN_REV32Madalin Bucur
Add revision 3.2 of the QBMan block. This is the version for LS1043A and LS1046A SoCs. Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
2017-12-12soc/fsl/qbman: Rework ioremap() calls for ARM/PPCRoy Pledge
Rework ioremap() for PPC and ARM. The PPC devices require a non-coherent mapping while ARM will work with a non-cachable/write combine mapping. Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
2017-12-12soc/fsl/qbman: Fix ARM32 typoValentin Rothberg
The Kconfig symbol for 32bit ARM is 'ARM', not 'ARM32'. Signed-off-by: Valentin Rothberg <valentinrothberg@gmail.com> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
2017-12-12soc/fsl/qbman: Drop L1_CACHE_BYTES compile time checkClaudiu Manoil
Not relevant and arch dependent. Overkill for PPC. Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
2017-12-12soc/fsl/qbman: Drop set/clear_bits usageMadalin Bucur
Replace PPC specific set/clear_bits API with standard bit twiddling so driver is portalable outside PPC. Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
2017-12-12soc/fsl/qbman: Use shared-dma-pool for QMan private memory allocationsRoy Pledge
Use the shared-memory-pool mechanism for frame queue descriptor and packed frame descriptor record area allocations. Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
2017-12-12soc/fsl/qbman: Use shared-dma-pool for BMan private memory allocationsRoy Pledge
Use the shared-memory-pool mechanism for free buffer proxy record area allocation. Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
2017-12-12soc/qman: export non-programmable FQD fields queryHoria Geantă
Export qman_query_fq_np() function and related structures. This will be needed in the caam/qi driver, where "queue empty" condition will be decided based on the frm_cnt. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-12-12soc/qman: add dedicated channel ID for CAAMHoria Geantă
Add and export the ID of the channel serviced by the CAAM (Cryptographic Acceleration and Assurance Module) DCP. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-12-12soc/qman: export volatile dequeue related structsHoria Geantă
Since qman_volatile_dequeue() is already exported, move the related structures into the public header too. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-12-12soc/fsl/qman: test: use DEFINE_SPINLOCK()Fabian Frederick
Signed-off-by: Fabian Frederick <fabf@skynet.be> Signed-off-by: Scott Wood <oss@buserror.net>
2017-12-12soc/fsl/bman: Use resource_size instead of computationWei Yongjun
Use resource_size function on resource object instead of explicit computation. Generated by: scripts/coccinelle/api/resource_size.cocci Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Scott Wood <oss@buserror.net>
2017-12-12soc/fsl/qbman: Convert to hotplug state machineSebastian Andrzej Siewior
Install the callbacks via the state machine. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Cc: Scott Wood <oss@buserror.net> Cc: Claudiu Manoil <claudiu.manoil@nxp.com> Cc: rt@linutronix.de Cc: Roy Pledge <roy.pledge@nxp.com> Link: http://lkml.kernel.org/r/20161126231350.10321-21-bigeasy@linutronix.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2017-12-12soc/fsl/qbman: Convert to hotplug state machineSebastian Andrzej Siewior
Install the callbacks via the state machine. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Cc: Scott Wood <oss@buserror.net> Cc: Claudiu Manoil <claudiu.manoil@nxp.com> Cc: rt@linutronix.de Cc: Roy Pledge <roy.pledge@nxp.com> Link: http://lkml.kernel.org/r/20161126231350.10321-20-bigeasy@linutronix.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2017-12-12soc/qman: Handle endianness of h/w descriptorsClaudiu Manoil
The hardware descriptors have big endian (BE) format. Provide proper endianness handling for the remaining descriptor fields, to ensure they are correctly accessed by non-BE CPUs too. Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
2017-12-12soc/qman: Clean up CGR CSCN target update operationsClaudiu Manoil
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
2017-12-12soc/qman: Change remaining contextB into context_bClaudiu Manoil
There are multiple occurences of both contextB and context_b in different h/w descriptors, referring to the same descriptor field known as "Context B". Stick with the "context_b" naming, for obvious reasons including consistency (see also context_a). Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
2017-12-12soc/qbman: Handle endianness of qm/bm_in/out()Claudiu Manoil
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>