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The codes of qe_ic init from a variety of platforms are redundant,
merge them to a common function and put it to irqchip/irq-qeic.c
For non-p1021_mds mpc85xx_mds boards, use "qe_ic_init(np, 0,
qe_ic_cascade_low_mpic, qe_ic_cascade_high_mpic);" instead of
"qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);".
qe_ic_cascade_muxed_mpic was used for boards has the same interrupt
number for low interrupt and high interrupt, qe_ic_init has checked
if "low interrupt == high interrupt"
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
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move the driver from drivers/soc/fsl/qe to drivers/irqchip,
merge qe_ic.h and qe_ic.c into irq-qeic.c.
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
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QE was supported on PowerPC, and dependent on PPC,
Now it is supported on other platforms. so remove PPCisms.
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
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1. modify bd_status from u32 to u16 in function hdlc_rx_done,
because bd_status register is 16bits
2. write bd_length register before writing bd_status register
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Numbering the ttyLPn space should not depend on the generic name
"serial<n>".
If don't add the alias node like:"serial0 = &lpuart0;", then lpuart
will probe failed:
[ 0.773410] fsl-lpuart 2950000.serial: failed to get alias id, errno -19
So remove the alias node dependence, and add the support for allocate the
line port automatically.
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Signed-off-by: Sriram Dash <Sriram.dash@nxp.com>
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The console write code is not entirely race free (e.g. the operations
to disabling the UART interrupts are not atomic) hence locking is
required. This has been become apparent with the PREEMPT RT patchset
applied: With the fully preemptible kernel configuration the system
often ended up in a freeze already at startup.
Disable interrupts and lock using read_lock_irqsave. Try to lock in
the sysrq/oops case, but don't bother if locking fails.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Problem found via lockdep:
- lpuart_set_termios() calls del_timer_sync(&sport->lpuart_timer) while
holding sport->port.lock
- sport->lpuart_timer routine is lpuart_timer_func() that calls
lpuart_copy_rx_to_tty() that acquires same lock.
To fix, move Rx DMA stopping out of lock, as it already is in other places
in the same file.
While at it, also make Rx DMA start/stop code to look the same is in
other places in the same file.
Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Tested-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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eSDHC is not a standard SD host controller. SDHCI_CAPABILITIES_1
register address is 0x44 while it's 0x114 (ESDHC_CAPABILITIES_1)
for eSDHC.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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Add basic support for Cortina PHY drivers. Support only CS4340 for now.
The phys are not compatible with IEEE 802.3 clause 22/45 registers.
Implement proper read_status support. The generic 10G phy driver causes
bus register access errors.
The driver should be described using the "ethernet-phy-id" device tree
compatible.
Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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-revert define value change
Signed-off-by: costi <constantin.tudor@freescale.com>
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Signed-off-by: costi <constantin.tudor@freescale.com>
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SD controller with SDHCI_QUIRK_NO_HISPD_BIT quirk probably
use high speed enable bit for other purpose. So this bit
shouldn't be changed for high speed enabling for this type of
SD controller.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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value of ios->timing is not related with SDCHI v3.0. If Controller version
is v3.0, SDHCI_QUIRK_NO_HISPD_BIT is meaningless. To prevent the setting
wrong bit moves into one condition checking. (e.g sdhci-s3c doesn't use
SDHCI_CTRL_HISPD bit, instead using this bit as other purpose.)
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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We used to set pass_timestamp parameter only for Tx
confirmation buffer layout config, when in fact MC
also looks at the Tx buffer layout when deciding whether
to enable Tx timestamping support or not.
Older versions of MC (< MC.1.x) enabled this support regardless
of user config, so the issue was hidden.
Copy the pass_timestamp setting to Tx buffer layout configuration.
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
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Make sure the memory area where the hardware writes the
congestion state is properly synchronized before reading it.
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
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If build_frag_skb() fails, we risk accessing the skb
pointer before checking it's not NULL.
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
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When inserting a flow steering rule through ethtool, the user
may specify a location index. Ethtool manual says the expected
behaviour is to overwrite any rule present in that location.
What currently happens is that the driver passes on the location
to MC with no further verifications and if there's already
a rule present at that index, MC returns an error.
Fix this by making sure the location is available, and if not
free the current entry before inserting the new one.
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
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Once a Tx frame descriptor is enqueued, an interrupt might be triggered
to process the Tx confirmation and free the skb, hitting a memory use
after free when updating the tx_bytes statistic based on skb->len.
Use the frame descriptor length instead.
Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
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Private structure fields "hash_fields" and "num_hash_fields" were
used in check_cls_support() even though they were initialized
later.
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
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'type' and 'flags' fields were missing from dprc_rsp_get_obj_region
structure therefore the MC Bus driver was not receiving proper flags
from MC like DPRC_REGION_CACHEABLE.
Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com>
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Add support for USB3 snooping by asserting bits
in register DWC3_GSBUSCFG0 for data and descriptor
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@freescale.com>
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
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It is not necessary for all device's maps to be CFI_HOST_ENDIAN. Maps
device can be big endian or little endian.
Currently it is being taken care using CONFIG_MTD_CFI_LE_BYTE_SWAP or
CONFIG_MTD_CFI_BE_BYTE_SWAP i.e. compile time.
Now update struct map_info's swap field based on device characteristics
defined in device tree.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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Bufnum mask is used to calculate page position in the internal SRAM.
As IFC version 2.0.0 has 16KB of internal SRAM as compared to older
versions which had 8KB. Hence bufnum mask needs to be updated.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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All IFC version >= 1.0 use 28nm technology for SRAM. Here SRAM has
a requirement to initialize before any read operation performed for
avoiding ECC Error.
So update condition check to initialize SRAM for all IFC version >=
1.0.0.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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SPI_NOR_DDR_QUAD_READ is set to the wrong number. This patch will fix the
bug and set SPI_NOR_DDR_QUAD_READ to the correct number.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
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Driver does not properly handle the case when signals interrupt
wait_for_completion_interruptible():
-it does not check for return value
-completion structure is allocated on stack; in case a signal interrupts
the sleep, it will go out of scope, causing the worker thread
(caam_jr_dequeue) to fail when it accesses it
wait_for_completion_interruptible() is replaced with uninterruptable
wait_for_completion().
We choose to block all signals while waiting for I/O (device executing
the split key generation job descriptor) since the alternative - in
order to have a deterministic device state - would be to flush the job
ring (aborting *all* in-progress jobs).
Cc: <stable@vger.kernel.org>
Fixes: 045e36780f115 ("crypto: caam - ahash hmac support")
Fixes: 4c1ec1f930154 ("crypto: caam - refactor key_gen, sg")
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
(cherry picked from commit 7459e1d25ffefa2b1be799477fcc1f6c62f6cec7)
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TLS 1.0 descriptors run on SEC 4.x or higher. For now, only
tls10(hmac(sha1),cbc(aes)) algorithm is registered by the driver.
Known limitations:
- when src == dst - there should be no element in the src scatterlist
array that contains both associated data and message data.
- when src != dst - associated data is not copied from source into
destination.
- for decryption when src != dst the size of the destination should be
large enough so that the buffer may contain the decrypted authenc and
padded data.
Signed-off-by: Radu Alexe <radu.alexe@nxp.com>
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TLS 1.0 descriptors run on SEC 4.x or higher.
For now, only tls10(hmac(sha1),cbc(aes)) algorithm
is registered by the driver.
Known limitations:
- when src == dst - there should be no element in the src scatterlist array
that contains both associated data and message data.
- when src != dst - associated data is not copied from source into
destination.
- for decryption when src != dst the size of the destination should be
large enough so that the buffer may contain the decrypted authenc and
padded data.
Signed-off-by: Tudor Ambarus <tudor-dan.ambarus@nxp.com>
Signed-off-by: Cristian Stoica <cristian.stoica@nxp.com>
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Radu Alexe <radu.alexe@nxp.com>
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CHAs of SEC work natively in BE mode. When moving
data to the alignment blocks, swapping is needed
for LE platforms. This is done by means of the MOVEB
command. This patch adds support
to DCL for this command.
Signed-off-by: Alex Porosanu <alexandru.porosanu@freescale.com>
Signed-off-by: Radu Alexe <radu.alexe@nxp.com>
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caam/qi frontend (i.e. caamalg_qi) mustn't be used in case it runs on a
DPAA2 part (this could happen when using a multiplatform kernel).
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
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sg_sw_sec4.h header is not used by caam/qi, thus remove its inclusion.
This also solves the compilation failure due to name clashes between
functions in sg_sw_qm.h and sg_sw_sec4.h -> sg_sw_qm2.h.
Fixes: dd1bcf32df59 ("crypto: caam/jr - add support for DPAA2 parts")
Reported-by: Radu Alexe <radu.alexe@nxp.com>
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
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Since ARM64 commit 1dccb598df549 ("arm64: simplify dma_get_ops"),
dma_ops no longer default to swiotlb_dma_ops, but to dummy_dma_ops.
We have to explicitly set dma_ops in the driver - at least for ARM64.
Fixes: 67c2315def06 ("crypto: caam - add Queue Interface (QI) backend support")
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
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Associated data (AD) length is read by CAAM from an S/G entry
that is initially filled by the GPP.
Accordingly, AD length has to be stored in CAAM endianness.
Fixes: b189817cf789 ("crypto: caam/qi - add ablkcipher and authenc algorithms")
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
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Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
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This patch adds support to read and write ioctls for
fsl-mc devices. Only read-write to DPRC/DPMCP devices
are supported while read writes on other fsl-mc devices
is not supported by this patch.
Also current patch limits userspace to write complete
64byte command once and read 64byte response by one ioctl.
This will be reworked later to add support read/write to
any offset
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
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dprc_reset_container() does complete cleanup and thus
allows re-run guest/user-space after abrupt guest kill.
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
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This patch allows to set an eventfd for fsl-mc device interrupt
and also to trigger the interrupt eventfd from userspace for testing.
All fsl-mc device interrupts are MSI type. This does not yet handler
correctly DPRC container interrupt where re-scanning on container is
required.
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
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This patch add interface of VFIO_DEVICE_SET_IRQS ioctl
for fsl-mc devices.
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
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This patch add support for VFIO_DEVICE_GET_IRQ_INFO
for fsl-mc devices
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
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Allow userspace to mmap device regions for direct access of
fsl-mc devices.
QBman CENA registers are cacheable and non-shareable but map
CENA region (marked as REGION_TYPE_CACHEABLE) to be the non-cacheable
to avoid coherency issues if a user migrates to another core.
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
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Add support for VFIO_DEVICE_GET_REGION_INFO ioctl call.
This allows usespace to know device mmap-able region details.
MC device (DPIO) have a region which is cacheable and
non-shareable. Describe these regions as cacheable
so that during mmap() they will be mapped accordingly.
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
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Allow userspace to get fsl-mc device info by making
VFIO_DEVICE_GET_INFO ioctl. With this usespace will get
basic device info such as number of regions and irqs.
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
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commit 7a3d5ea46413924daefb7d4af24d04d7c5f54b98
[context adjustment]
Enable building vfio FSL-MC driver to allow FSL-MC devices
binding with VFIO.
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
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Non-DPRC devices shares it's parent container MC portal
to communicate to MC hardware.
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
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DPRC (Data Path Resource Container) device is a bus devices and
have child devices within it. This patch add support for
initializing and scanning the DPRC container.
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
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commit f8adf3ce07cf0623b3e8e0df67f3bc12a110416f
[context adjustment]
This patch add framework of VFIO support for FSL-MC devices.
Subsequent patches will add support for binding and secure
assigning these devices using VFIO.
FSL-MC is a new bus (driver/bus/fsl-mc/) which is different
from PCI and Platform bus.
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
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Implement bus specific support for the fsl-mc bus including
registering the arm_smmu_ops and bus specific device add operations.
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
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For software initiated address translation, when domain type is
IOMMU_DOMAIN_IDENTITY i.e SMMU is bypassed, mimic HW behavior
i.e return the same IOVA as translated address.
This patch is an extension to Will Deacon's patchset
"Implement SMMU passthrough using the default domain".
Signed-off-by: Sunil Goutham <sgoutham@cavium.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
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Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Constantin Tudor <constantin.tudor@nxp.com>
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There are number of function calls, originating from user-space,
typically through the Ethernet driver that can make us crash by
dereferencing phydev->drv which will be NULL once we unbind the driver
from the PHY.
There are still functional issues that prevent an unbind then rebind to
work, but these will be addressed separately.
Suggested-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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