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2017-12-12phy: Add 2.5G SGMII interface modeBhaskar Upadhaya
Add 2.5G SGMII interface mode(PHY_INTERFACE_MODE_2500SGMII) in existing phy_interface list Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
2017-12-12net: ethernet: Remove PHY_INTERFACE_MODE_SGMII_2500Bhaskar Upadhaya
Remove PHY_INTERFACE_MODE_SGMII_2500 as the interface mode is not defined correctly. Correct way is PHY_INTERFACE_MODE_2500SGMII Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
2017-12-12soc/qman: export non-programmable FQD fields queryHoria Geantă
Export qman_query_fq_np() function and related structures. This will be needed in the caam/qi driver, where "queue empty" condition will be decided based on the frm_cnt. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-12-12soc/qman: add dedicated channel ID for CAAMHoria Geantă
Add and export the ID of the channel serviced by the CAAM (Cryptographic Acceleration and Assurance Module) DCP. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-12-12soc/qman: export volatile dequeue related structsHoria Geantă
Since qman_volatile_dequeue() is already exported, move the related structures into the public header too. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-12-12soc/qman: Handle endianness of h/w descriptorsClaudiu Manoil
The hardware descriptors have big endian (BE) format. Provide proper endianness handling for the remaining descriptor fields, to ensure they are correctly accessed by non-BE CPUs too. Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
2017-12-12soc/qman: Clean up CGR CSCN target update operationsClaudiu Manoil
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
2017-12-12soc/qman: Change remaining contextB into context_bClaudiu Manoil
There are multiple occurences of both contextB and context_b in different h/w descriptors, referring to the same descriptor field known as "Context B". Stick with the "context_b" naming, for obvious reasons including consistency (see also context_a). Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
2017-12-12soc/qman: Drop unused field from eqcr/dqrr descriptorsClaudiu Manoil
ORP ("Order Restoration Point") mechanism not supported. Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
2017-12-12soc/qman: Fix accesses to fqid, cleanupClaudiu Manoil
Preventively mask every access to the 'fqid' h/w field, since it is defined as a 24-bit field, for every h/w descriptor. Add generic accessors for this field to ensure correct access. Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
2017-12-12Extend FM MAC Statistics with frame size countersIordache Florinel-R70177
Signed-off-by: Iordache Florinel-R70177 <florinel.iordache@nxp.com>
2017-09-25sdk_dpaa: update the xmit timestamp to avoid watchdog timeoutsCamelia Groza
[core-linux part] Update txq0's trans_start in order to prevent the netdev watchdog from triggering too quickly. Since we set the LLTX flag, the stack won't update the jiffies for other tx queues. Prevent the watchdog from checking the other tx queues by adding the NETIF_HW_ACCEL_MQ flag. Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
2017-09-25iommu: Allow taking a reference on a group directlyRobin Murphy
iommu_group_get_for_dev() expects that the IOMMU driver's device_group callback return a group with a reference held for the given device. Whilst allocating a new group is fine, and pci_device_group() correctly handles reusing an existing group, there is no general means for IOMMU drivers doing their own group lookup to take additional references on an existing group pointer without having to also store device pointers or resort to elaborate trickery. Add an IOMMU-driver-specific function to fill the hole. Acked-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2017-09-25linux/core: export copy_skb_header() functionZhang Ying-22455
Signed-off-by: Camelia Groza camelia.groza@nxp.com
2017-09-25irqdomain: irq_domain_check_msi_remapEric Auger
This new function checks whether all MSI irq domains implement IRQ remapping. This is useful to understand whether VFIO passthrough is safe with respect to interrupts. On ARM typically an MSI controller can sit downstream to the IOMMU without preventing VFIO passthrough. As such any assigned device can write into the MSI doorbell. In case the MSI controller implements IRQ remapping, assigned devices will not be able to trigger interrupts towards the host. On the contrary, the assignment must be emphasized as unsafe with respect to interrupts. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Tomasz Nowicki <tomasz.nowicki@caviumnetworks.com> Tested-by: Tomasz Nowicki <tomasz.nowicki@caviumnetworks.com> Tested-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-09-25irqdomain: Add irq domain MSI and MSI_REMAP flagsEric Auger
We introduce two new enum values for the irq domain flag: - IRQ_DOMAIN_FLAG_MSI indicates the irq domain corresponds to an MSI domain - IRQ_DOMAIN_FLAG_MSI_REMAP indicates the irq domain has MSI remapping capabilities. Those values will be useful to check all MSI irq domains have MSI remapping support when assessing the safety of IRQ assignment to a guest. irq_domain_hierarchical_is_msi_remap() allows to check if an irq domain or any parent implements MSI remapping. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Tomasz Nowicki <tomasz.nowicki@caviumnetworks.com> Tested-by: Tomasz Nowicki <tomasz.nowicki@caviumnetworks.com> Tested-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-09-25iommu: Disambiguate MSI region typesRobin Murphy
commit 81ea50c9fe8b478e611d44d64eb14c4b478ee0c3 [iommu part] The introduction of reserved regions has left a couple of rough edges which we could do with sorting out sooner rather than later. Since we are not yet addressing the potential dynamic aspect of software-managed reservations and presenting them at arbitrary fixed addresses, it is incongruous that we end up displaying hardware vs. software-managed MSI regions to userspace differently, especially since ARM-based systems may actually require one or the other, or even potentially both at once, (which iommu-dma currently has no hope of dealing with at all). Let's resolve the former user-visible inconsistency ASAP before the ABI has been baked into a kernel release, in a way that also lays the groundwork for the latter shortcoming to be addressed by follow-up patches. For clarity, rename the software-managed type to IOMMU_RESV_SW_MSI, use IOMMU_RESV_MSI to describe the hardware type, and document everything a little bit. Since the x86 MSI remapping hardware falls squarely under this meaning of IOMMU_RESV_MSI, apply that type to their regions as well, so that we tell the same story to userspace across all platforms. Secondly, as the various region types require quite different handling, and it really makes little sense to ever try combining them, convert the bitfield-esque #defines to a plain enum in the process before anyone gets the wrong impression. Fixes: d30ddcaa7b02 ("iommu: Add a new type field in iommu_resv_region") Reviewed-by: Eric Auger <eric.auger@redhat.com> CC: Alex Williamson <alex.williamson@redhat.com> CC: David Woodhouse <dwmw2@infradead.org> CC: kvm@vger.kernel.org Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Joerg Roedel <jroedel@suse.de> [Bharat: porting to 4.9] Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-09-25iommu/dma: Make PCI window reservation genericRobin Murphy
Now that we're applying the IOMMU API reserved regions to our IOVA domains, we shouldn't need to privately special-case PCI windows, or indeed anything else which isn't specific to our iommu-dma layer. However, since those aren't IOMMU-specific either, rather than start duplicating code into IOMMU drivers let's transform the existing function into an iommu_get_resv_regions() helper that they can share. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2017-09-25iommu: iommu_get_group_resv_regionsEric Auger
Introduce iommu_get_group_resv_regions whose role consists in enumerating all devices from the group and collecting their reserved regions. The list is sorted and overlaps between regions of the same type are handled by merging the regions. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Tomasz Nowicki <tomasz.nowicki@caviumnetworks.com> Tested-by: Tomasz Nowicki <tomasz.nowicki@caviumnetworks.com> Tested-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-09-25iommu: iommu_alloc_resv_regionEric Auger
Introduce a new helper serving the purpose to allocate a reserved region. This will be used in iommu driver implementing reserved region callbacks. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Tomasz Nowicki <tomasz.nowicki@caviumnetworks.com> Tested-by: Tomasz Nowicki <tomasz.nowicki@caviumnetworks.com> Tested-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-09-25iommu: Add a new type field in iommu_resv_regionEric Auger
We introduce a new field to differentiate the reserved region types and specialize the apply_resv_region implementation. Legacy direct mapped regions have IOMMU_RESV_DIRECT type. We introduce 2 new reserved memory types: - IOMMU_RESV_MSI will characterize MSI regions that are mapped - IOMMU_RESV_RESERVED characterize regions that cannot by mapped. Signed-off-by: Eric Auger <eric.auger@redhat.com> Tested-by: Tomasz Nowicki <tomasz.nowicki@caviumnetworks.com> Tested-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-09-25iommu: Rename iommu_dm_regions into iommu_resv_regionsEric Auger
We want to extend the callbacks used for dm regions and use them for reserved regions. Reserved regions can be - directly mapped regions - regions that cannot be iommu mapped (PCI host bridge windows, ...) - MSI regions (because they belong to another address space or because they are not translated by the IOMMU and need special handling) So let's rename the struct and also the callbacks. Signed-off-by: Eric Auger <eric.auger@redhat.com> Acked-by: Robin Murphy <robin.murphy@arm.com> Reviewed-by: Tomasz Nowicki <tomasz.nowicki@caviumnetworks.com> Tested-by: Tomasz Nowicki <tomasz.nowicki@caviumnetworks.com> Tested-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-09-25iommu/dma: Allow MSI-only cookiesRobin Murphy
IOMMU domain users such as VFIO face a similar problem to DMA API ops with regard to mapping MSI messages in systems where the MSI write is subject to IOMMU translation. With the relevant infrastructure now in place for managed DMA domains, it's actually really simple for other users to piggyback off that and reap the benefits without giving up their own IOVA management, and without having to reinvent their own wheel in the MSI layer. Allow such users to opt into automatic MSI remapping by dedicating a region of their IOVA space to a managed cookie, and extend the mapping routine to implement a trivial linear allocator in such cases, to avoid the needless overhead of a full-blown IOVA domain. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Reviewed-by: Tomasz Nowicki <tomasz.nowicki@caviumnetworks.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Tested-by: Tomasz Nowicki <tomasz.nowicki@caviumnetworks.com> Tested-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
2017-09-25add ETH_MIN_MTUZhao Qiang
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-09-25irqchip/qeic: remove PPCisms for QEICZhao Qiang
QEIC was supported on PowerPC, and dependent on PPC, Now it is supported on other platforms, so remove PPCisms. Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-09-25irqchip/qeic: merge qeic_of_init into qe_ic_initZhao Qiang
qeic_of_init just get device_node of qeic from dtb and call qe_ic_init, pass the device_node to qe_ic_init. So merge qeic_of_init into qe_ic_init to get the qeic node in qe_ic_init. Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-09-25QE: remove PPCisms for QEZhao Qiang
QE was supported on PowerPC, and dependent on PPC, Now it is supported on other platforms. so remove PPCisms. Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-09-25crypto: acomp - add driver-side scomp interfaceGiovanni Cabiddu
Add a synchronous back-end (scomp) to acomp. This allows to easily expose the already present compression algorithms in LKCF via acomp. Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-09-25crypto: acomp - add asynchronous compression apiGiovanni Cabiddu
Add acomp, an asynchronous compression api that uses scatterlist buffers. Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-09-25vfio/fsl-mc: Add VFIO framework for fsl-mc devicesBharat Bhushan
commit f8adf3ce07cf0623b3e8e0df67f3bc12a110416f [context adjustment] This patch add framework of VFIO support for FSL-MC devices. Subsequent patches will add support for binding and secure assigning these devices using VFIO. FSL-MC is a new bus (driver/bus/fsl-mc/) which is different from PCI and Platform bus. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-09-25net: phy: add SGMII 2500 PHYMadalin Bucur
Signed-off-by: Madalin Bucur <madalin.bucur@freescale.com>
2017-09-25net: phy: Check phydev->drvFlorian Fainelli
There are number of function calls, originating from user-space, typically through the Ethernet driver that can make us crash by dereferencing phydev->drv which will be NULL once we unbind the driver from the PHY. There are still functional issues that prevent an unbind then rebind to work, but these will be addressed separately. Suggested-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-09-25mtd: spi-nor: add DDR quad read supportAlison Wang
This patch adds the DDR quad read support by the following: [1] add SPI_NOR_DDR_QUAD read mode. [2] add DDR Quad read opcodes: SPINOR_OP_READ_1_4_4_D / SPINOR_OP_READ4_1_4_4_D [3] add set_ddr_quad_mode() to initialize for the DDR quad read. Currently it only works for Spansion NOR. [4] set dummy with 6 for Spansion family Test this patch for Spansion s25fl128s NOR flash. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
2017-09-25mtd: spi-nor: rename SPINOR_OP_* macros of the 4-byte address op codesAlison Wang
This patch renames the SPINOR_OP_* macros of the 4-byte address instruction set so the new names all share a common pattern: the 4-byte address name is built from the 3-byte address name appending the "_4B" suffix. The patch also introduces new op codes to support other SPI protocols such as SPI 1-4-4 and SPI 1-2-2. This is a transitional patch and will help a later patch of spi-nor.c to automate the translation from the 3-byte address op codes into their 4-byte address version. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Marek Vasut <marek.vasut@gmail.com>
2017-09-25spi-nor: Add support for S3AN spi-nor devicesAlison Wang
Xilinx Spartan-3AN FPGAs contain an In-System Flash where they keep their configuration data and (optionally) some user data. The protocol of this flash follows most of the spi-nor standard. With the following differences: - Page size might not be a power of two. - The address calculation (default addressing mode). - The spi nor commands used. Protocol is described on Xilinx User Guide UG333 Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Brian Norris <computersforpeace@gmail.com> Cc: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25mtd: spi-nor: fsl-quad: Add flash S25FS extra supportYunhui Cui
There are some boards have the same QSPI controller but have different vendor falsh, So as to controller can use the same compatible and share the driver, Just for different flash to do the appropriate adaptation. Based on this, we need add the vendor field in spi-nor, Because we will use the field to distribute corresponding LUT for different flash operations. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
2017-09-25mtd: spi-nor: fsl-quadspi: extend support for some special requerment.Yunhui Cui
Add extra info in LUT table to support some special requerments. Spansion S25FS-S family flash need some special operations. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
2017-09-25pci:add support aer/pme interrupts with none MSI/MSI-X/INTx modePo Liu
[pcie part] On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode. When chip support the aer/pme interrupts with none MSI/MSI-X/INTx mode, maybe there is interrupt line for aer pme etc. Search the interrupt number in the fdt file. Then fixup the dev->irq with it. Signed-off-by: Po Liu <po.liu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-09-25usb: dwc3: add function of_usb_get_dr_modeyinbo.zhu
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
2017-09-25usb: host: Add support to add/remove usb host driverRamneek Mehresh
Add workqueue to add/remove host driver (outside interrupt context) upon each id change Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
2017-09-25fmd: SDK DPAA 1.x FMan driverMadalin Bucur
commit 40382fa630cac60ef72149e0f2bc074501f1e4b4 [sdk_fman part] Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-09-25fsl_qbman: SDK DPAA 1.x QBMan driversMadalin Bucur
commit 4b184a137767069ef1982c94da389f557e1681cb [qbman part] Signed-off-by: Roy Pledge <roy.pledge@nxp.com> Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-07-14soc: fsl: add GUTS driver for QorIQ platformsyangbo lu
The global utilities block controls power management, I/O device enabling, power-onreset(POR) configuration monitoring, alternate function selection for multiplexed signals,and clock control. This patch adds a driver to manage and access global utilities block. Initially only reading SVR and registering soc device are supported. Other guts accesses, such as reading RCW, should eventually be moved into this driver as well. Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> [remove makefile/kconfig] Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2017-07-14drivers/mtd: Add deep sleep support for IFCPrabhakar Kushwaha
Add support of suspend, resume function to support deep sleep. Also make sure of SRAM initialization during resume. Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2017-07-14add devm_alloc_percpu supportZhao Qiang
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-07-14net: readd skb_recycle()Madalin Bucur
Adding back skb_recycle() as it's used by the DPAA Ethernet driver. This was removed from the upstream kernel because it was lacking users. Signed-off-by: Madalin Bucur <madalin.bucur@freescale.com>
2017-07-14fmd: SDK DPAA 1.x FMan driverMadalin Bucur
commit 40382fa630cac60ef72149e0f2bc074501f1e4b4 [add svr.h] Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-07-14net: make ndo_get_stats64 a void functionstephen hemminger
The network device operation for reading statistics is only called in one place, and it ignores the return value. Having a structure return value is potentially confusing because some future driver could incorrectly assume that the return value was used. Fix all drivers with ndo_get_stats64 to have a void function. Signed-off-by: Stephen Hemminger <sthemmin@microsoft.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-07-14net: centralize net_device min/max MTU checkingJarod Wilson
While looking into an MTU issue with sfc, I started noticing that almost every NIC driver with an ndo_change_mtu function implemented almost exactly the same range checks, and in many cases, that was the only practical thing their ndo_change_mtu function was doing. Quite a few drivers have either 68, 64, 60 or 46 as their minimum MTU value checked, and then various sizes from 1500 to 65535 for their maximum MTU value. We can remove a whole lot of redundant code here if we simple store min_mtu and max_mtu in net_device, and check against those in net/core/dev.c's dev_set_mtu(). In theory, there should be zero functional change with this patch, it just puts the infrastructure in place. Subsequent patches will attempt to start using said infrastructure, with theoretically zero change in functionality. CC: netdev@vger.kernel.org Signed-off-by: Jarod Wilson <jarod@redhat.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-07-14base: soc: Introduce soc_device_match() interfaceArnd Bergmann
We keep running into cases where device drivers want to know the exact version of the a SoC they are currently running on. In the past, this has usually been done through a vendor specific API that can be called by a driver, or by directly accessing some kind of version register that is not part of the device itself but that belongs to a global register area of the chip. Common reasons for doing this include: - A machine is not using devicetree or similar for passing data about on-chip devices, but just announces their presence using boot-time platform devices, and the machine code itself does not care about the revision. - There is existing firmware or boot loaders with existing DT binaries with generic compatible strings that do not identify the particular revision of each device, but the driver knows which SoC revisions include which part. - A prerelease version of a chip has some quirks and we are using the same version of the bootloader and the DT blob on both the prerelease and the final version. An update of the DT binding seems inappropriate because that would involve maintaining multiple copies of the dts and/or bootloader. This patch introduces the soc_device_match() interface that is meant to work like of_match_node() but instead of identifying the version of a device, it identifies the SoC itself using a vendor-agnostic interface. Unlike of_match_node(), we do not do an exact string compare but instead use glob_match() to allow wildcards in strings. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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