1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
|
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
reg = <0>;
model = "ti,c64x+";
};
cpu@1 {
device_type = "cpu";
reg = <1>;
model = "ti,c64x+";
};
cpu@2 {
device_type = "cpu";
reg = <2>;
model = "ti,c64x+";
};
cpu@3 {
device_type = "cpu";
reg = <3>;
model = "ti,c64x+";
};
cpu@4 {
device_type = "cpu";
reg = <4>;
model = "ti,c64x+";
};
cpu@5 {
device_type = "cpu";
reg = <5>;
model = "ti,c64x+";
};
};
soc {
compatible = "simple-bus";
model = "tms320c6472";
#address-cells = <1>;
#size-cells = <1>;
ranges;
core_pic: interrupt-controller {
compatible = "ti,c64x+core-pic";
interrupt-controller;
#interrupt-cells = <1>;
};
megamod_pic: interrupt-controller@1800000 {
compatible = "ti,c64x+megamod-pic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x1800000 0x1000>;
interrupt-parent = <&core_pic>;
};
cache-controller@1840000 {
compatible = "ti,c64x+cache";
reg = <0x01840000 0x8400>;
};
timer0: timer@25e0000 {
compatible = "ti,c64x+timer64";
ti,core-mask = < 0x01 >;
reg = <0x25e0000 0x40>;
};
timer1: timer@25f0000 {
compatible = "ti,c64x+timer64";
ti,core-mask = < 0x02 >;
reg = <0x25f0000 0x40>;
};
timer2: timer@2600000 {
compatible = "ti,c64x+timer64";
ti,core-mask = < 0x04 >;
reg = <0x2600000 0x40>;
};
timer3: timer@2610000 {
compatible = "ti,c64x+timer64";
ti,core-mask = < 0x08 >;
reg = <0x2610000 0x40>;
};
timer4: timer@2620000 {
compatible = "ti,c64x+timer64";
ti,core-mask = < 0x10 >;
reg = <0x2620000 0x40>;
};
timer5: timer@2630000 {
compatible = "ti,c64x+timer64";
ti,core-mask = < 0x20 >;
reg = <0x2630000 0x40>;
};
clock-controller@29a0000 {
compatible = "ti,c6472-pll", "ti,c64x+pll";
reg = <0x029a0000 0x200>;
ti,c64x+pll-bypass-delay = <200>;
ti,c64x+pll-reset-delay = <12000>;
ti,c64x+pll-lock-delay = <80000>;
};
device-state-controller@2a80000 {
compatible = "ti,c64x+dscr";
reg = <0x02a80000 0x1000>;
ti,dscr-devstat = <0>;
ti,dscr-silicon-rev = <0x70c 16 0xff>;
ti,dscr-mac-fuse-regs = <0x700 1 2 3 4
0x704 5 6 0 0>;
ti,dscr-rmii-resets = <0x208 1
0x20c 1>;
ti,dscr-locked-regs = <0x200 0x204 0x0a1e183a
0x40c 0x420 0xbea7
0x41c 0x420 0xbea7>;
ti,dscr-privperm = <0x41c 0xaaaaaaaa>;
ti,dscr-devstate-ctl-regs = <0 13 0x200 1 0 0 1>;
};
};
};
|
