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authorLokesh Vutla <lokeshvutla@ti.com>2013-02-12 21:29:05 (GMT)
committerTom Rini <trini@ti.com>2013-03-11 15:06:11 (GMT)
commitea8eff1fe080bef7c5cdfea734d8ac4cdd957c4c (patch)
treecd8c94874ac1a497b86528f009434e7dd80a206f /.checkpatch.conf
parentd4e4129c31cf571824a1b34aa0b9210c876be718 (diff)
downloadu-boot-ea8eff1fe080bef7c5cdfea734d8ac4cdd957c4c.tar.xz
arm: dra7xx: clock: Add the dplls data
A new DPLL DDR is added in DRA7XX socs. Now clocks to EMIF CD is from DPLL DDR. So DPLL DDR should be locked before initializing RAM. Also adding other dpll data which are different from OMAP5 ES2.0. SYS_CLK running at 20MHz is introduced in DRA7xx socs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
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