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| author | Minghuan Lian <Minghuan.Lian@nxp.com> | 2016-12-13 06:54:12 (GMT) |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2017-01-18 17:25:38 (GMT) |
| commit | 048a04530700704af622dc80a192b59de2e65fa2 (patch) | |
| tree | 798af5e47f0c70781cedcbe78260acc0a386aaa0 | |
| parent | add73a1dad49236fd1f5b2ebaca87bed36db247d (diff) | |
| download | u-boot-048a04530700704af622dc80a192b59de2e65fa2.tar.xz | |
arm: ls1012a: add PCIe dts node
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
| -rw-r--r-- | arch/arm/dts/fsl-ls1012a.dtsi | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi index 024527e..c4ca9c1 100644 --- a/arch/arm/dts/fsl-ls1012a.dtsi +++ b/arch/arm/dts/fsl-ls1012a.dtsi @@ -103,5 +103,20 @@ status = "disabled"; }; + pcie@3400000 { + compatible = "fsl,ls-pcie", "snps,dw-pcie"; + reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ + 0x00 0x03480000 0x0 0x40000 /* lut registers */ + 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */ + 0x40 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "ctrl", "config"; + big-endian; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; }; }; |