diff options
author | Tom Rini <trini@ti.com> | 2013-04-18 20:16:01 (GMT) |
---|---|---|
committer | Tom Rini <trini@ti.com> | 2013-04-18 20:16:01 (GMT) |
commit | 17dcbfb0876385b13739b1b1f2026edc8163b629 (patch) | |
tree | 5faa5949a895040398e70f6e8ef81dc9da88557e | |
parent | 669dfc2ed8d853d6bcdcafa1de6aca22929465e5 (diff) | |
parent | f2e8a87305a55652488af140adcf65b1e688f287 (diff) | |
download | u-boot-17dcbfb0876385b13739b1b1f2026edc8163b629.tar.xz |
Merge branch 'master' of git://git.denx.de/u-boot-arm into HEAD
Quick manual fixup to merge the USB boot related defines and TPM related
defines.
Conflicts:
include/configs/exynos5250-dt.h
Signed-off-by: Tom Rini <trini@ti.com>
33 files changed, 467 insertions, 92 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index bbab5fe..643a5ac 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -994,6 +994,7 @@ Stephen Warren <swarren@nvidia.com> paz00 Tegra20 (ARM7 & A9 Dual Core) trimslice Tegra20 (ARM7 & A9 Dual Core) whistler Tegra20 (ARM7 & A9 Dual Core) + beaver Tegra30 (ARM7 & A9 Quad Core) Stephen Warren <swarren@wwwdotorg.org> diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c index 119342e..9294611 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.c +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c @@ -143,26 +143,34 @@ void init_pllx(void) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX]; - int chip_type; + int soc_type, sku_info, chip_sku; enum clock_osc_freq osc; struct clk_pll_table *sel; debug("init_pllx entry\n"); - /* get chip type */ - chip_type = tegra_get_chip_type(); - debug(" init_pllx: chip_type = %d\n", chip_type); + /* get SOC (chip) type */ + soc_type = tegra_get_chip(); + debug(" init_pllx: SoC = 0x%02X\n", soc_type); + + /* get SKU info */ + sku_info = tegra_get_sku_info(); + debug(" init_pllx: SKU info byte = 0x%02X\n", sku_info); + + /* get chip SKU, combo of the above info */ + chip_sku = tegra_get_chip_sku(); + debug(" init_pllx: Chip SKU = %d\n", chip_sku); /* get osc freq */ osc = clock_get_osc_freq(); - debug(" init_pllx: osc = %d\n", osc); + debug(" init_pllx: osc = %d\n", osc); /* set pllx */ - sel = &tegra_pll_x_table[chip_type][osc]; + sel = &tegra_pll_x_table[chip_sku][osc]; pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon); - /* adjust PLLP_out1-4 on T30/T114 */ - if (chip_type == TEGRA_SOC_T30 || chip_type == TEGRA_SOC_T114) { + /* adjust PLLP_out1-4 on T3x/T114 */ + if (soc_type >= CHIPID_TEGRA30) { debug(" init_pllx: adjusting PLLP out freqs\n"); adjust_pllp_out_freqs(); } @@ -287,7 +295,7 @@ void reset_A9_cpu(int reset) void clock_enable_coresight(int enable) { u32 rst, src = 2; - int chip; + int soc_type; debug("clock_enable_coresight entry\n"); clock_set_enable(PERIPH_ID_CORESIGHT, enable); @@ -295,21 +303,21 @@ void clock_enable_coresight(int enable) if (enable) { /* - * Put CoreSight on PLLP_OUT0 (216 MHz) and divide it down by - * 1.5, giving an effective frequency of 144MHz. - * Set PLLP_OUT0 [bits31:30 = 00], and use a 7.1 divisor - * (bits 7:0), so 00000001b == 1.5 (n+1 + .5) - * - * Clock divider request for 204MHz would setup CSITE clock as - * 144MHz for PLLP base 216MHz and 204MHz for PLLP base 408MHz + * Put CoreSight on PLLP_OUT0 and divide it down as per + * PLLP base frequency based on SoC type (T20/T30/T114). + * Clock divider request would setup CSITE clock as 144MHz + * for PLLP base 216MHz and 204MHz for PLLP base 408MHz */ - chip = tegra_get_chip_type(); - if (chip == TEGRA_SOC_T30 || chip == TEGRA_SOC_T114) + + soc_type = tegra_get_chip(); + if (soc_type == CHIPID_TEGRA30 || soc_type == CHIPID_TEGRA114) src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000); - else if (chip == TEGRA_SOC_T20 || chip == TEGRA_SOC_T25) + else if (soc_type == CHIPID_TEGRA20) src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000); else - printf("%s: Unknown chip type %X!\n", __func__, chip); + printf("%s: Unknown SoC type %X!\n", + __func__, soc_type); + clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src); /* Unlock the CPU CoreSight interfaces */ diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.h b/arch/arm/cpu/arm720t/tegra-common/cpu.h index e8e05d7..f9bfb32 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.h +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.h @@ -80,5 +80,7 @@ void init_pllx(void); void powerup_cpu(void); void reset_A9_cpu(int reset); void start_cpu(u32 reset_vector); -int tegra_get_chip_type(void); +int tegra_get_chip(void); +int tegra_get_sku_info(void); +int tegra_get_chip_sku(void); void adjust_pllp_out_freqs(void); diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/cpu/arm720t/tegra114/cpu.c index 6a94179..51ecff7 100644 --- a/arch/arm/cpu/arm720t/tegra114/cpu.c +++ b/arch/arm/cpu/arm720t/tegra114/cpu.c @@ -170,15 +170,13 @@ void t114_init_clocks(void) clock_set_enable(PERIPH_ID_MC1, 1); clock_set_enable(PERIPH_ID_DVFS, 1); - /* Switch MSELECT clock to PLLP (00) */ - clock_ll_set_source(PERIPH_ID_MSELECT, 0); - /* - * Clock divider request for 102MHz would setup MSELECT clock as - * 102MHz for PLLP base 408MHz + * Set MSELECT clock source as PLLP (00), and ask for a clock + * divider that would set the MSELECT clock at 102MHz for a + * PLLP base of 408MHz. */ clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, - (NVBL_PLLP_KHZ/102000)); + CLK_DIVIDER(NVBL_PLLP_KHZ, 102000)); /* I2C5 (DVC) gets CLK_M and a divisor of 17 */ clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16); diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/cpu/arm720t/tegra30/cpu.c index dedcdd9..e162357 100644 --- a/arch/arm/cpu/arm720t/tegra30/cpu.c +++ b/arch/arm/cpu/arm720t/tegra30/cpu.c @@ -110,8 +110,8 @@ void t30_init_clocks(void) reset_set_enable(PERIPH_ID_MSELECT, 1); clock_set_enable(PERIPH_ID_MSELECT, 1); - /* Switch MSELECT clock to PLLP (00) */ - clock_ll_set_source(PERIPH_ID_MSELECT, 0); + /* Switch MSELECT clock to PLLP (00) and use a divisor of 2 */ + clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, 2); /* * Our high-level clock routines are not available prior to diff --git a/arch/arm/cpu/armv7/s5p-common/timer.c b/arch/arm/cpu/armv7/s5p-common/timer.c index 6a0fa58..4adfaae 100644 --- a/arch/arm/cpu/armv7/s5p-common/timer.c +++ b/arch/arm/cpu/armv7/s5p-common/timer.c @@ -24,6 +24,7 @@ */ #include <common.h> +#include <div64.h> #include <asm/io.h> #include <asm/arch/pwm.h> #include <asm/arch/clk.h> @@ -76,6 +77,8 @@ int timer_init(void) */ unsigned long get_timer(unsigned long base) { + unsigned long long time_ms; + ulong now = timer_get_us_down(); /* @@ -87,7 +90,9 @@ unsigned long get_timer(unsigned long base) gd->arch.lastinc = now; /* Divide by 1000 to convert from us to ms */ - return gd->arch.timer_reset_value / 1000 - base; + time_ms = gd->arch.timer_reset_value; + do_div(time_ms, 1000); + return time_ms - base; } unsigned long timer_get_us(void) diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 5feae7a..e9e57e6 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -253,11 +253,9 @@ ENTRY(c_runtime_cpu_setup) /* * Move vector table */ -#if !defined(CONFIG_TEGRA) /* Set vector address in CP15 VBAR register */ ldr r0, =_start mcr p15, 0, r0, c12, c0, 0 @Set VBAR -#endif /* !Tegra */ bx lr diff --git a/arch/arm/cpu/tegra-common/Makefile b/arch/arm/cpu/tegra-common/Makefile index 8e95c7e..4e0301c 100644 --- a/arch/arm/cpu/tegra-common/Makefile +++ b/arch/arm/cpu/tegra-common/Makefile @@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)libcputegra-common.o SOBJS += lowlevel_init.o -COBJS-y += ap.o board.o sys_info.o timer.o clock.o +COBJS-y += ap.o board.o sys_info.o timer.o clock.o cache.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c index 236cda8..9b77b2b 100644 --- a/arch/arm/cpu/tegra-common/ap.c +++ b/arch/arm/cpu/tegra-common/ap.c @@ -34,25 +34,44 @@ #include <asm/arch-tegra/tegra.h> #include <asm/arch-tegra/warmboot.h> -int tegra_get_chip_type(void) +int tegra_get_chip(void) { - struct apb_misc_gp_ctlr *gp; - struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; - uint tegra_sku_id, rev; + int rev; + struct apb_misc_gp_ctlr *gp = + (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; /* * This is undocumented, Chip ID is bits 15:8 of the register * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for * Tegra30, and 0x35 for T114. */ - gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; + debug("%s: CHIPID is 0x%02X\n", __func__, rev); + + return rev; +} + +int tegra_get_sku_info(void) +{ + int sku_id; + struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; - tegra_sku_id = readl(&fuse->sku_info) & 0xff; + sku_id = readl(&fuse->sku_info) & 0xff; + debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id); - switch (rev) { + return sku_id; +} + +int tegra_get_chip_sku(void) +{ + uint sku_id, chip_id; + + chip_id = tegra_get_chip(); + sku_id = tegra_get_sku_info(); + + switch (chip_id) { case CHIPID_TEGRA20: - switch (tegra_sku_id) { + switch (sku_id) { case SKU_ID_T20: return TEGRA_SOC_T20; case SKU_ID_T25SE: @@ -64,19 +83,22 @@ int tegra_get_chip_type(void) } break; case CHIPID_TEGRA30: - switch (tegra_sku_id) { + switch (sku_id) { + case SKU_ID_T33: case SKU_ID_T30: return TEGRA_SOC_T30; } break; case CHIPID_TEGRA114: - switch (tegra_sku_id) { + switch (sku_id) { case SKU_ID_T114_ENG: return TEGRA_SOC_T114; } break; } - /* unknown sku id */ + /* unknown chip/sku id */ + printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n", + __func__, chip_id, sku_id); return TEGRA_SOC_UNKNOWN; } @@ -138,11 +160,6 @@ void s_init(void) enable_scu(); - /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */ - asm volatile( - "mrc p15, 0, r0, c1, c0, 1\n" - "orr r0, r0, #0x41\n" - "mcr p15, 0, r0, c1, c0, 1\n"); - - /* FIXME: should have SoC's L2 disabled too? */ + /* init the cache */ + config_cache(); } diff --git a/arch/arm/cpu/tegra-common/cache.c b/arch/arm/cpu/tegra-common/cache.c new file mode 100644 index 0000000..48e9319 --- /dev/null +++ b/arch/arm/cpu/tegra-common/cache.c @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/* Tegra cache routines */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch-tegra/ap.h> +#include <asm/arch/gp_padctrl.h> + +void config_cache(void) +{ + struct apb_misc_gp_ctlr *gp = + (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; + u32 reg = 0; + + /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */ + asm volatile( + "mrc p15, 0, r0, c1, c0, 1\n" + "orr r0, r0, #0x41\n" + "mcr p15, 0, r0, c1, c0, 1\n"); + + /* Currently, only T114 needs this L2 cache change to boot Linux */ + reg = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK); + if (reg != (CHIPID_TEGRA114 << HIDREV_CHIPID_SHIFT)) + return; + /* + * Systems with an architectural L2 cache must not use the PL310. + * Config L2CTLR here for a data RAM latency of 3 cycles. + */ + asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg)); + reg &= ~7; + reg |= 2; + asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg)); +} diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c index 49a0633..9156d00 100644 --- a/arch/arm/cpu/tegra-common/clock.c +++ b/arch/arm/cpu/tegra-common/clock.c @@ -557,4 +557,7 @@ void clock_init(void) debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]); debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]); debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]); + + /* Do any special system timer/TSC setup */ + arch_timer_init(); } diff --git a/arch/arm/cpu/tegra114-common/clock.c b/arch/arm/cpu/tegra114-common/clock.c index 9b29ce1..5c4305a 100644 --- a/arch/arm/cpu/tegra114-common/clock.c +++ b/arch/arm/cpu/tegra114-common/clock.c @@ -19,6 +19,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> +#include <asm/arch/sysctr.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/timer.h> @@ -653,3 +654,24 @@ void clock_early_init(void) writel(0x40000C10, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc); udelay(2); } + +void arch_timer_init(void) +{ + struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE; + u32 freq, val; + + freq = clock_get_rate(CLOCK_ID_OSC); + debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq); + + /* ARM CNTFRQ */ + asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq)); + + /* Only T114 has the System Counter regs */ + debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq); + writel(freq, &sysctr->cntfid0); + + val = readl(&sysctr->cntcr); + val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG; + writel(val, &sysctr->cntcr); + debug("%s: TSC CNTCR = 0x%08X\n", __func__, val); +} diff --git a/arch/arm/cpu/tegra20-common/clock.c b/arch/arm/cpu/tegra20-common/clock.c index ec93894..4afb205 100644 --- a/arch/arm/cpu/tegra20-common/clock.c +++ b/arch/arm/cpu/tegra20-common/clock.c @@ -559,3 +559,7 @@ void clock_early_init(void) break; } } + +void arch_timer_init(void) +{ +} diff --git a/arch/arm/cpu/tegra20-common/pmu.c b/arch/arm/cpu/tegra20-common/pmu.c index 2282953..4c5a533 100644 --- a/arch/arm/cpu/tegra20-common/pmu.c +++ b/arch/arm/cpu/tegra20-common/pmu.c @@ -44,7 +44,7 @@ int pmu_set_nominal(void) int core, cpu, bus; /* by default, the table has been filled with T25 settings */ - switch (tegra_get_chip_type()) { + switch (tegra_get_chip_sku()) { case TEGRA_SOC_T20: core = VDD_CORE_NOMINAL_T20; cpu = VDD_CPU_NOMINAL_T20; @@ -54,7 +54,7 @@ int pmu_set_nominal(void) cpu = VDD_CPU_NOMINAL_T25; break; default: - debug("%s: Unknown chip type\n", __func__); + debug("%s: Unknown SKU id\n", __func__); return -1; } diff --git a/arch/arm/cpu/tegra30-common/clock.c b/arch/arm/cpu/tegra30-common/clock.c index a93f2c9..74bd22b 100644 --- a/arch/arm/cpu/tegra30-common/clock.c +++ b/arch/arm/cpu/tegra30-common/clock.c @@ -616,3 +616,7 @@ void clock_early_init(void) break; } } + +void arch_timer_init(void) +{ +} diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h index 73dfd39..f6d08c6 100644 --- a/arch/arm/include/asm/arch-tegra/ap.h +++ b/arch/arm/include/asm/arch-tegra/ap.h @@ -59,8 +59,25 @@ extern void _start(void); /** - * Works out the SOC type used for clocks settings + * Works out the SOC/SKU type used for clocks settings * * @return SOC type - see TEGRA_SOC... */ -int tegra_get_chip_type(void); +int tegra_get_chip_sku(void); + +/** + * Returns the pure SOC (chip ID) from the HIDREV register + * + * @return SOC ID - see CHIPID_TEGRAxx... + */ +int tegra_get_chip(void); + +/** + * Returns the SKU ID from the sku_info register + * + * @return SKU ID - see SKU_ID_Txx... + */ +int tegra_get_sku_info(void); + +/* Do any chip-specific cache config */ +void config_cache(void); diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index c8677bd..c7a696c 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -317,4 +317,7 @@ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon); #define periphc_internal_id_isvalid(id) ((id) >= 0 && \ (id) < PERIPHC_COUNT) +/* SoC-specific TSC init */ +void arch_timer_init(void); + #endif /* _TEGRA_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h index bf7229d..3e642e9 100644 --- a/arch/arm/include/asm/arch-tegra/tegra.h +++ b/arch/arm/include/asm/arch-tegra/tegra.h @@ -78,6 +78,7 @@ enum { SKU_ID_T25 = 0x18, SKU_ID_AP25E = 0x1b, SKU_ID_T25E = 0x1c, + SKU_ID_T33 = 0x80, SKU_ID_T30 = 0x81, /* Cardhu value */ SKU_ID_T114_ENG = 0x00, /* Dalmore value, unfused */ }; diff --git a/arch/arm/include/asm/arch-tegra114/sysctr.h b/arch/arm/include/asm/arch-tegra114/sysctr.h new file mode 100644 index 0000000..c05e2c3 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra114/sysctr.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _TEGRA114_SYSCTR_H_ +#define _TEGRA114_SYSCTR_H_ + +struct sysctr_ctlr { + u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */ + u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */ + u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */ + u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */ + u32 reserved1[4]; /* 0x10 - 0x1C */ + u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */ + u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */ + u32 reserved2[1002]; /* 0x28 - 0xFCC */ + u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */ +}; + +#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */ +#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */ + +#endif /* _TEGRA114_SYSCTR_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/tegra.h b/arch/arm/include/asm/arch-tegra114/tegra.h index a3d12d6..5d426b5 100644 --- a/arch/arm/include/asm/arch-tegra114/tegra.h +++ b/arch/arm/include/asm/arch-tegra114/tegra.h @@ -18,6 +18,7 @@ #define _TEGRA114_H_ #define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */ +#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ #include <asm/arch-tegra/tegra.h> diff --git a/board/avionic-design/dts/tegra20-tamonten.dtsi b/board/avionic-design/dts/tegra20-tamonten.dtsi index 86c7bab..f379622 100644 --- a/board/avionic-design/dts/tegra20-tamonten.dtsi +++ b/board/avionic-design/dts/tegra20-tamonten.dtsi @@ -279,6 +279,17 @@ status = "okay"; }; + nand-controller@70008000 { + nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */ + nvidia,width = <8>; + nvidia,timing = <26 100 20 80 20 10 12 10 70>; + + nand@0 { + reg = <0>; + compatible = "hynix,hy27uf4g2b", "nand-flash"; + }; + }; + i2c@7000c000 { clock-frequency = <400000>; status = "okay"; diff --git a/board/avionic-design/dts/tegra20-tec.dts b/board/avionic-design/dts/tegra20-tec.dts index 1d7cf89..4c1b08d 100644 --- a/board/avionic-design/dts/tegra20-tec.dts +++ b/board/avionic-design/dts/tegra20-tec.dts @@ -32,17 +32,6 @@ clock-frequency = <216000000>; }; - nand-controller@70008000 { - nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */ - nvidia,width = <8>; - nvidia,timing = <26 100 20 80 20 10 12 10 70>; - - nand@0 { - reg = <0>; - compatible = "hynix,hy27uf4g2b", "nand-flash"; - }; - }; - i2c@7000c000 { status = "disabled"; }; diff --git a/board/nvidia/common/emc.c b/board/nvidia/common/emc.c index 26b6ec7..87d7aa2 100644 --- a/board/nvidia/common/emc.c +++ b/board/nvidia/common/emc.c @@ -40,7 +40,7 @@ int board_emc_init(void) { unsigned rate; - switch (tegra_get_chip_type()) { + switch (tegra_get_chip_sku()) { default: case TEGRA_SOC_T20: rate = EMC_SDRAM_RATE_T20; diff --git a/board/nvidia/dts/tegra30-beaver.dts b/board/nvidia/dts/tegra30-beaver.dts new file mode 100644 index 0000000..836169f --- /dev/null +++ b/board/nvidia/dts/tegra30-beaver.dts @@ -0,0 +1,71 @@ +/dts-v1/; + +#include "tegra30.dtsi" + +/ { + model = "NVIDIA Beaver"; + compatible = "nvidia,beaver", "nvidia,tegra30"; + + aliases { + i2c0 = "/i2c@7000d000"; + i2c1 = "/i2c@7000c000"; + i2c2 = "/i2c@7000c400"; + i2c3 = "/i2c@7000c500"; + i2c4 = "/i2c@7000c700"; + sdhci0 = "/sdhci@78000600"; + sdhci1 = "/sdhci@78000000"; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x7ff00000>; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + }; + + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + spi-flash@1 { + compatible = "winbond,w25q32"; + reg = <1>; + spi-max-frequency = <20000000>; + }; + }; + + sdhci@78000000 { + status = "okay"; + cd-gpios = <&gpio 69 1>; /* gpio PI5 */ + wp-gpios = <&gpio 155 0>; /* gpio PT3 */ + power-gpios = <&gpio 31 0>; /* gpio PD7 */ + bus-width = <4>; + }; + + sdhci@78000600 { + status = "okay"; + bus-width = <8>; + }; +}; diff --git a/board/samsung/dts/exynos5250-snow.dts b/board/samsung/dts/exynos5250-snow.dts index 8b303bf..24658c1 100644 --- a/board/samsung/dts/exynos5250-snow.dts +++ b/board/samsung/dts/exynos5250-snow.dts @@ -55,4 +55,18 @@ compatible = "maxim,max77686_pmic"; }; }; + + tmu@10060000 { + samsung,min-temp = <25>; + samsung,max-temp = <125>; + samsung,start-warning = <95>; + samsung,start-tripping = <105>; + samsung,hw-tripping = <110>; + samsung,efuse-min-value = <40>; + samsung,efuse-value = <55>; + samsung,efuse-max-value = <100>; + samsung,slope = <274761730>; + samsung,dc-value = <25>; + }; + }; diff --git a/board/samsung/smdk5250/spl_boot.c b/board/samsung/smdk5250/spl_boot.c index d8f3c1e..c0bcf46 100644 --- a/board/samsung/smdk5250/spl_boot.c +++ b/board/samsung/smdk5250/spl_boot.c @@ -32,6 +32,21 @@ enum boot_mode { }; typedef u32 (*spi_copy_func_t)(u32 offset, u32 nblock, u32 dst); + typedef u32 (*usb_copy_func_t)(void); + +/* + * Set/clear program flow prediction and return the previous state. + */ +static int config_branch_prediction(int set_cr_z) +{ + unsigned int cr; + + /* System Control Register: 11th bit Z Branch prediction enable */ + cr = get_cr(); + set_cr(set_cr_z ? cr | CR_Z : cr & ~CR_Z); + + return cr & CR_Z; +} /* * Copy U-boot from mmc to RAM: @@ -41,10 +56,20 @@ enum boot_mode { void copy_uboot_to_ram(void) { spi_copy_func_t spi_copy; - enum boot_mode bootmode; + usb_copy_func_t usb_copy; + + int is_cr_z_set; + unsigned int sec_boot_check; + enum boot_mode bootmode = BOOT_MODE_OM; u32 (*copy_bl2)(u32, u32, u32); - bootmode = readl(EXYNOS5_POWER_BASE) & OM_STAT; + /* Read iRAM location to check for secondary USB boot mode */ + sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE); + if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT) + bootmode = BOOT_MODE_USB; + + if (bootmode == BOOT_MODE_OM) + bootmode = readl(EXYNOS5_POWER_BASE) & OM_STAT; switch (bootmode) { case BOOT_MODE_SERIAL: @@ -57,6 +82,17 @@ void copy_uboot_to_ram(void) copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); break; + case BOOT_MODE_USB: + /* + * iROM needs program flow prediction to be disabled + * before copy from USB device to RAM + */ + is_cr_z_set = config_branch_prediction(0); + usb_copy = *(usb_copy_func_t *) + EXYNOS_COPY_USB_FNPTR_ADDR; + usb_copy(); + config_branch_prediction(is_cr_z_set); + break; default: break; } @@ -311,6 +311,7 @@ seaboard arm armv7:arm720t seaboard nvidia ventana arm armv7:arm720t ventana nvidia tegra20 whistler arm armv7:arm720t whistler nvidia tegra20 cardhu arm armv7:arm720t cardhu nvidia tegra30 +beaver arm armv7:arm720t cardhu nvidia tegra30 dalmore arm armv7:arm720t dalmore nvidia tegra114 colibri_t20_iris arm armv7:arm720t colibri_t20_iris toradex tegra20 u8500_href arm armv7 u8500 st-ericsson u8500 diff --git a/include/configs/beaver.h b/include/configs/beaver.h new file mode 100644 index 0000000..058da4f --- /dev/null +++ b/include/configs/beaver.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/sizes.h> + +#include "tegra30-common.h" + +/* Enable fdt support for Beaver. Flash the image in u-boot-dtb.bin */ +#define CONFIG_DEFAULT_DEVICE_TREE tegra30-beaver +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + +/* High-level configuration options */ +#define V_PROMPT "Tegra30 (Beaver) # " +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Beaver" + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#define MACH_TYPE_BEAVER 4597 /* not yet in mach-types.h */ +#define CONFIG_MACH_TYPE MACH_TYPE_BEAVER + +#define CONFIG_BOARD_EARLY_INIT_F + +/* I2C */ +#define CONFIG_TEGRA_I2C +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_CMD_I2C + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET ((1024 * 1024) - CONFIG_ENV_SIZE) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 + +/* SPI */ +#define CONFIG_TEGRA20_SLINK +#define CONFIG_TEGRA_SLINK_CTRLS 6 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 020048a..8a82892 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -134,6 +134,11 @@ #define CONFIG_USB_EHCI_EXYNOS #define CONFIG_USB_STORAGE +/* USB boot mode */ +#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070 +#define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 +#define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 + /* TPM */ #define CONFIG_TPM #define CONFIG_CMD_TPM diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h index 57a50d7..eebf385 100644 --- a/include/configs/medcom-wide.h +++ b/include/configs/medcom-wide.h @@ -44,14 +44,21 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_LATE_INIT -#define CONFIG_ENV_IS_NOWHERE - /* SD/MMC */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC #define CONFIG_TEGRA_MMC #define CONFIG_CMD_MMC +/* NAND support */ +#define CONFIG_CMD_NAND +#define CONFIG_TEGRA_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* Environment in NAND, aligned to start of last sector */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sectors */ + /* USB host support */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA @@ -66,13 +73,6 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP -#define CONFIG_FIT - -#define CONFIG_BOOTCOMMAND \ - "mmc rescan;" \ - "ext2load mmc 0 0x17000000 /boot/uImage;" \ - "bootm" - /* LCD support */ #define CONFIG_LCD #define CONFIG_PWM_TEGRA @@ -80,6 +80,9 @@ #define LCD_BPP LCD_COLOR16 #define CONFIG_SYS_WHITE_ON_BLACK +/* support the new (FDT-based) image format */ +#define CONFIG_FIT + #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/plutux.h b/include/configs/plutux.h index 4cfe88a..25ee83a 100644 --- a/include/configs/plutux.h +++ b/include/configs/plutux.h @@ -42,8 +42,7 @@ #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE #define CONFIG_BOARD_EARLY_INIT_F - -#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_BOARD_LATE_INIT /* SD/MMC */ #define CONFIG_MMC @@ -51,6 +50,15 @@ #define CONFIG_TEGRA_MMC #define CONFIG_CMD_MMC +/* NAND support */ +#define CONFIG_CMD_NAND +#define CONFIG_TEGRA_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* Environment in NAND, aligned to start of last sector */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sectors */ + /* USB host support */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA @@ -65,13 +73,9 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP +/* support the new (FDT-based) image format */ #define CONFIG_FIT -#define CONFIG_BOOTCOMMAND \ - "mmc rescan;" \ - "ext2load mmc 0 0x17000000 /boot/uImage;" \ - "bootm" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/tec.h b/include/configs/tec.h index f90f5c7..f280cc0 100644 --- a/include/configs/tec.h +++ b/include/configs/tec.h @@ -73,13 +73,6 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP -#define CONFIG_FIT - -#define CONFIG_BOOTCOMMAND \ - "mmc rescan;" \ - "ext2load mmc 0 0x17000000 /boot/uImage;" \ - "bootm" - /* LCD support */ #define CONFIG_LCD #define CONFIG_PWM_TEGRA @@ -87,6 +80,9 @@ #define LCD_BPP LCD_COLOR16 #define CONFIG_SYS_WHITE_ON_BLACK +/* support the new (FDT-based) image format */ +#define CONFIG_FIT + #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index e9241b8..cb9e7c3 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -168,7 +168,9 @@ #define CONFIG_SPL_GPIO_SUPPORT #define CONFIG_SYS_GENERIC_BOARD + /* Misc utility code */ #define CONFIG_BOUNCE_BUFFER +#define CONFIG_CRC32_VERIFY #endif /* _TEGRA_COMMON_H_ */ |