diff options
author | Stefan Roese <sr@denx.de> | 2008-06-10 13:34:11 (GMT) |
---|---|---|
committer | Stefan Roese <sr@denx.de> | 2008-06-12 13:50:31 (GMT) |
commit | 212ed90615c3d20fa6bd73d70d5153bd0d124e5f (patch) | |
tree | 3c4a9f6dc173dead6e0d4c13002c8de901e97d96 | |
parent | a94f22f08f280905926219e568568964cb9eeb9d (diff) | |
download | u-boot-212ed90615c3d20fa6bd73d70d5153bd0d124e5f.tar.xz |
ppc4xx: Canyonlands: Disable the RTC M41T62 square wave output
This patch disables the square wave output of the M41T62 RTC used on
Canyonlands & Glacier. Here the explanation:
The serial real-time clock part used in the design is an
STMicro M41T62. This part has a full-time 32KHz square wave
output that is connected to the TmrClk input to the
processor. The default state for this square wave output is
enabled so the output runs continuously when the board is
powered normally and also from the battery. The TmrClk input
to the processor goes to ground when the power is removed
from the board/processor, and therefore the running square
wave output is driving ground which drains the battery quickly.
Signed-off-by: Stefan Roese <sr@denx.de>
-rw-r--r-- | board/amcc/canyonlands/canyonlands.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index e0e0211..e9eba49 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -22,6 +22,7 @@ #include <ppc440.h> #include <libfdt.h> #include <fdt_support.h> +#include <i2c.h> #include <asm/processor.h> #include <asm/io.h> #include <asm/mmu.h> @@ -393,6 +394,7 @@ int misc_init_r(void) u32 sdr0_srst1 = 0; u32 eth_cfg; u32 pvr = get_pvr(); + u8 val; /* * Set EMAC mode/configuration (GMII, SGMII, RGMII...). @@ -420,6 +422,15 @@ int misc_init_r(void) sdr0_srst1 &= ~SDR0_SRST1_AHB; mtsdr(SDR0_SRST1, sdr0_srst1); + /* + * RTC/M41T62: + * Disable square wave output: Batterie will be drained + * quickly, when this output is not disabled + */ + val = i2c_reg_read(CFG_I2C_RTC_ADDR, 0xa); + val &= ~0x40; + i2c_reg_write(CFG_I2C_RTC_ADDR, 0xa, val); + return 0; } |