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author | Soren Brinkmann <soren.brinkmann@xilinx.com> | 2013-10-29 20:11:54 (GMT) |
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committer | Michal Simek <michal.simek@xilinx.com> | 2013-12-02 10:36:36 (GMT) |
commit | 2785a4ae76330dab5e792d52fc9c449ac3d1072e (patch) | |
tree | aeea0f276401201d42ea8511b7a77247eec1fc16 | |
parent | d19ad726bcd5d9106f7ba9c750462fcc369f1020 (diff) | |
download | u-boot-2785a4ae76330dab5e792d52fc9c449ac3d1072e.tar.xz |
serial: zynq: Remove unused #defines
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Series-to: trini, uboot
-rw-r--r-- | drivers/serial/serial_zynq.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 050b9c0..ff28f3c 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -21,10 +21,6 @@ #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ -/* Some clock/baud constants */ -#define ZYNQ_UART_BDIV 15 /* Default/reset BDIV value */ -#define ZYNQ_UART_BASECLK 3125000L /* master / (bdiv + 1) */ - struct uart_zynq { u32 control; /* Control Register [8:0] */ u32 mode; /* Mode Register [10:0] */ |