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| author | Simon Glass <sjg@chromium.org> | 2016-01-22 02:43:45 (GMT) |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2016-01-22 03:42:34 (GMT) |
| commit | 342999f9b3ce6c5c30b100549799e646e7fa70c5 (patch) | |
| tree | 76d71f38d165d80f94321b7257f2f4440d98a74c | |
| parent | 6d97786b4c695b45056a00bac07124cac0a81204 (diff) | |
| download | u-boot-342999f9b3ce6c5c30b100549799e646e7fa70c5.tar.xz | |
rockchip: mmc: Update the driver to use the new clock ID
We can use the new clk_get_by_index() function to get the correct clock.
Signed-off-by: Simon Glass <sjg@chromium.org>
| -rw-r--r-- | drivers/clk/clk_rk3288.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c index fdc5347..d294788 100644 --- a/drivers/clk/clk_rk3288.c +++ b/drivers/clk/clk_rk3288.c @@ -541,8 +541,8 @@ static ulong rk3288_get_periph_rate(struct udevice *dev, int periph) gclk_rate = clk_get_rate(gclk); switch (periph) { case HCLK_EMMC: + case HCLK_SDMMC: case HCLK_SDIO0: - case HCLK_SDIO1: new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, periph); break; case SCLK_SPI0: |