Grapeboard support added

19 files changed, 1032 insertions, 0 deletions

diff --git a/Makefile b/Makefile
index 025691b..ddc8624 100644
--- a/Makefile
+++ b/Makefile
@@ -762,6 +762,8 @@ endif
 # Always append ALL so that arch config.mk's can add custom ones
 ALL-y += u-boot.srec u-boot.bin u-boot.sym System.map binary_size_check
 
+ALL-$(CONFIG_PBL_IMAGE) += u-boot-pbl.bin
+
 ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
 ifeq ($(CONFIG_SPL_FSL_PBL),y)
 ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin
@@ -1198,6 +1200,14 @@ OBJCOPYFLAGS_u-boot-with-spl-pbl.bin = -I binary -O binary --pad-to=$(CONFIG_SPL
 
 u-boot-with-spl-pbl.bin: spl/u-boot-spl.pbl $(SPL_PAYLOAD) FORCE
 	$(call if_changed,pad_cat)
+	
+	
+#Concatenate PBL and U-boot binaries automatically
+OBJCOPYFLAGS_u-boot-pbl.bin := -I binary -O binary --pad-to=$(CONFIG_U_BOOT_PAD_TO) \
+			--gap-fill=0xff
+
+u-boot-pbl.bin: $(srctree)/$(CONFIG_PBL_BINARY:"%"=%) u-boot.bin FORCE 
+	$(call if_changed,pad_cat)
 
 # PPC4xx needs the SPL at the end of the image, since the reset vector
 # is located at 0xfffffffc. So we can't use the "u-boot-img.bin" target
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 31688ff..89f09c7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -886,6 +886,13 @@ config TARGET_LS1012AFRDM
 	  development platform that supports the QorIQ LS1012A
 	  Layerscape Architecture processor.
 
+config TARGET_GRAPEBOARD
+	bool "Support grapeboard"
+	select ARCH_LS1012A
+	select ARM64
+	help
+	  Support for Scalys LS1012A based Grapeboard platform.
+
 config TARGET_LS1088ARDB
 	bool "Support ls1088ardb"
 	select ARCH_LS1088A
@@ -1185,6 +1192,7 @@ source "board/freescale/ls1046ardb/Kconfig"
 source "board/freescale/ls1012aqds/Kconfig"
 source "board/freescale/ls1012ardb/Kconfig"
 source "board/freescale/ls1012afrdm/Kconfig"
+source "board/scalys/grapeboard/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
 source "board/freescale/mx25pdk/Kconfig"
 source "board/freescale/mx28evk/Kconfig"
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 12aba9d..935a194 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -90,6 +90,7 @@ config PSCI_RESET
 		   !TARGET_LS2080ARDB && !TARGET_LS1012AQDS && \
 		   !TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \
 		   !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
+		   !TARGET_GRAPEBOARD && \
 		   !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
 		   !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
 		   !TARGET_LS2081ARDB && \
diff --git a/arch/arm/dts/grapeboard.dts b/arch/arm/dts/grapeboard.dts
new file mode 100644
index 0000000..18ee0d3
--- /dev/null
+++ b/arch/arm/dts/grapeboard.dts
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+#include "grapeboard.dtsi"
+
+/ {
+       chosen {
+               stdout-path = &duart0;
+       };
+};
diff --git a/arch/arm/dts/grapeboard.dtsi b/arch/arm/dts/grapeboard.dtsi
new file mode 100644
index 0000000..7e61cbc
--- /dev/null
+++ b/arch/arm/dts/grapeboard.dtsi
@@ -0,0 +1,39 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/include/ "fsl-ls1012a.dtsi"
+
+/ {
+	model = "LS1012A Grape Board";
+	aliases {
+		spi0 = &qspi;
+	};
+};
+
+&qspi {
+	bus-num = <0>;
+	status = "okay";
+
+	qflash0: s25fl128s@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&duart0 {
+	status = "okay";
+};
diff --git a/board/scalys/grapeboard/Kconfig b/board/scalys/grapeboard/Kconfig
new file mode 100644
index 0000000..b038577
--- /dev/null
+++ b/board/scalys/grapeboard/Kconfig
@@ -0,0 +1,59 @@
+if TARGET_GRAPEBOARD
+
+config SYS_BOARD
+	default "grapeboard"
+	
+config SYS_VENDOR
+	default "scalys"
+	
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "grapeboard"
+	
+menu "Grapeboard configuration options"
+	depends on TARGET_GRAPEBOARD
+	
+choice
+	prompt "SERDES configuration for PCIE or SATA"
+	default SERDES_D_TO_SATA
+	
+config SERDES_D_TO_PCIE
+	bool
+	prompt "Support PCIe"
+	
+config SERDES_D_TO_SATA
+	bool
+	prompt "Support SATA (Eth1 disabled)"
+
+endchoice
+
+choice
+	prompt "U-boot environment configuration"
+	default STANDARD_UBOOT_CONFIG
+	
+config STANDARD_UBOOT_CONFIG
+	bool
+	prompt "Standard flash target"
+	
+config RESCUE_UBOOT_CONFIG
+	bool
+	prompt "Rescue flash target"
+	
+endchoice
+
+config PBL_BINARY
+	bool
+	
+config PBL_IMAGE
+	string
+	
+config U_BOOT_PAD_TO
+	string
+
+endmenu
+
+
+
+endif
diff --git a/board/scalys/grapeboard/Makefile b/board/scalys/grapeboard/Makefile
new file mode 100644
index 0000000..ad75e40
--- /dev/null
+++ b/board/scalys/grapeboard/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y	+= grapeboard.o
+obj-y   += eth.o
+obj-y   += usb_grapeboard.o
+
+obj-$(CONFIG_LAYERSCAPE_NS_ACCESS)	+= ns_access.o
+
+
diff --git a/board/scalys/grapeboard/PBL_0x33_0x05_750_250_1000.bin b/board/scalys/grapeboard/PBL_0x33_0x05_750_250_1000.bin
new file mode 100644
index 0000000..43cfa77
--- /dev/null
+++ b/board/scalys/grapeboard/PBL_0x33_0x05_750_250_1000.bin
diff --git a/board/scalys/grapeboard/PBL_0x33_0x08_750_250_1000.bin b/board/scalys/grapeboard/PBL_0x33_0x08_750_250_1000.bin
new file mode 100644
index 0000000..049d7bb
--- /dev/null
+++ b/board/scalys/grapeboard/PBL_0x33_0x08_750_250_1000.bin
diff --git a/board/scalys/grapeboard/PBL_0x35_0x08_750_250_1000.bin b/board/scalys/grapeboard/PBL_0x35_0x08_750_250_1000.bin
new file mode 100644
index 0000000..ad85162
--- /dev/null
+++ b/board/scalys/grapeboard/PBL_0x35_0x08_750_250_1000.bin
diff --git a/board/scalys/grapeboard/eth.c b/board/scalys/grapeboard/eth.c
new file mode 100644
index 0000000..e02611a
--- /dev/null
+++ b/board/scalys/grapeboard/eth.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <fsl_dtsec.h>
+#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/config.h>
+#include <asm/arch/fsl_serdes.h>
+
+#include <pfe_eth/pfe_eth.h>
+#include <asm/arch-fsl-layerscape/immap_lsch2.h>
+#include <i2c.h>
+
+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
+
+
+void reset_phy(void)
+{
+	/* No PHY reset control from LS1012A */
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FSL_PFE
+	struct mii_dev *bus;
+	struct mdio_info mac1_mdio_info;
+	struct mdio_info mac2_mdio_info;
+
+	reset_phy();
+
+	init_pfe_scfg_dcfg_regs();
+
+	/* Initialize SGMIIA on MDIO1 */
+	mac1_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
+	mac1_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
+
+	bus = ls1012a_mdio_init(&mac1_mdio_info);
+	if (!bus) {
+		printf("Failed to register mdio 1\n");
+		return -1;
+	}
+
+	/* Initialize SGMIIB on MDIO2 */
+	mac2_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR;
+	mac2_mdio_info.name = DEFAULT_PFE_MDIO1_NAME;
+
+	bus = ls1012a_mdio_init(&mac2_mdio_info);
+	if (!bus) {
+		printf("Failed to register mdio 2\n");
+		return -1;
+	}
+
+	/* Initialize PHYs on MDIO1 */
+	ls1012a_set_mdio(0, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
+	ls1012a_set_phy_address_mode(0, EMAC1_PHY_ADDR, PHY_INTERFACE_MODE_SGMII);
+
+	ls1012a_set_mdio(1, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
+	ls1012a_set_phy_address_mode(1, EMAC2_PHY_ADDR, PHY_INTERFACE_MODE_SGMII);
+
+	/* Initialize TI83867CS PHY LEDs */
+	miiphy_write(DEFAULT_PFE_MDIO_NAME,EMAC1_PHY_ADDR,0x18,0x61B6);
+	miiphy_write(DEFAULT_PFE_MDIO_NAME,EMAC2_PHY_ADDR,0x18,0x61B6);
+
+	cpu_eth_init(bis);
+#endif
+	return pci_eth_init(bis);
+}
diff --git a/board/scalys/grapeboard/grapeboard.c b/board/scalys/grapeboard/grapeboard.c
new file mode 100644
index 0000000..60d2a14
--- /dev/null
+++ b/board/scalys/grapeboard/grapeboard.c
@@ -0,0 +1,219 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ *
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#ifdef CONFIG_FSL_LS_PPA
+#include <asm/arch/ppa.h>
+#endif
+#include <asm/arch/mmu.h>
+#include <asm/arch/soc.h>
+#include <hwconfig.h>
+#include <ahci.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fsl_esdhc.h>
+#include <environment.h>
+#include <fsl_mmdc.h>
+#include <netdev.h>
+#include <fsl_sec.h>
+#include <fsl_csu.h>
+#include "usb_grapeboard.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPIO1 registers */
+#define CONFIG_SYS_GPIO1 0x2300000
+#define CONFIG_SYS_GPIO2 0x2310000
+#define GPIO_MASK(shift) (0x80000000 >> shift)
+
+/* =====================================================
+ * Grapeboard ExPI mapping (* pin name at ls1012a side)
+ * Note: The secondary options require modified RCW.
+ * =====================================================
+ *                 3V3 -| 1       2|- 5V0
+ *             I2C_SDA -| 3       4|- 5V0
+ *             I2C_SCL -| 5       6|- GND
+ *          CLK0_25MHZ -| 7       8|- UART_TXD
+ *                 GND -| 9      10|- UART_RXD
+ *           GPIO1_27* -|11      12|- GPIO2_04*
+ *           GPIO2_05* -|13      14|- GND
+ *           GPIO2_06* -|15      16|- GPIO2_07*
+ *                 3V3 -|17      18|- GPIO2_09*
+ *  SPI_MOSI/GPIO1_24* -|19      20|- GND
+ *  SPI_MISO/GPIO1_28* -|21      22|- GPIO2_10*
+ *   SPI_CLK/GPIO1_29* -|23      24|- SPI_CE0/GPIO1_25*
+ *                 GND -|25      26|- SPI_CE1/GPIO1_26*
+ */
+
+/* ExPI gpios */
+#define gpio1_27 GPIO_MASK(27) /* ExPI pin 11 */
+#define gpio2_04 GPIO_MASK(4)  /* ExPI pin 12 */
+#define gpio2_05 GPIO_MASK(5)  /* ExPI pin 13 */
+#define gpio2_06 GPIO_MASK(6)  /* ExPI pin 15 */
+#define gpio2_07 GPIO_MASK(7)  /* ExPI pin 16 */
+#define gpio2_09 GPIO_MASK(9)  /* ExPI pin 18 */
+#define gpio2_10 GPIO_MASK(10) /* ExPI pin 22 */
+
+/* M2 gpios */
+#define gpio1_22 GPIO_MASK(22)
+#define gpio2_00 GPIO_MASK(0)
+#define gpio2_01 GPIO_MASK(1)
+#define gpio2_02 GPIO_MASK(2)
+#define M2_CFG1  GPIO_MASK(11) /* gpio2_11 */
+#define M2_CFG0  GPIO_MASK(12) /* gpio2_12 */
+#define M2_CFG2  GPIO_MASK(13) /* gpio2_13 */
+#define M2_CFG3  GPIO_MASK(14) /* gpio2_14 */
+
+/* Other gpios */
+#define QSPI_MUX_N_MASK (0x80000000 >> 3) /* gpio2_03 */
+
+int checkboard(void)
+{
+	struct ccsr_gpio *pgpio = (void *)(CONFIG_SYS_GPIO2);
+	int m2_config = 0;
+
+	puts("Board: Grape board\n");
+	/* set QSPI chip select muxing to 0 */
+
+	setbits_be32(&pgpio->gpdir, QSPI_MUX_N_MASK);
+	clrbits_be32(&pgpio->gpdat, QSPI_MUX_N_MASK);
+
+	usb_hub_init();
+
+
+	/* M.2 init: read input values of M.2 config signals */
+	clrbits_be32(&pgpio->gpdir, (M2_CFG0 | M2_CFG1 | M2_CFG2 | M2_CFG3));
+	m2_config = (in_be32(&pgpio->gpdat) & (M2_CFG0 | M2_CFG1 | M2_CFG2 | M2_CFG3));
+
+	switch(m2_config >> 17) {
+	case 0:
+		printf("M.2: SATA SSD module found on M.2 port\n");
+#ifdef CONFIG_SERDES_D_TO_PCIE
+		printf("Warning: SERDES has not been configured in RCW for SATA!\n");
+#endif
+		break;
+	case 1:
+		printf("M.2: PCIe SSD module found on M.2 port\n");
+#ifdef CONFIG_SERDES_D_TO_SATA
+		printf("Warning: SERDES has not been configured in RCW for PCIe!\n");
+#endif
+		break;
+	case 0xf:
+		printf("M.2: No module detected on M.2 port\n");
+		break;
+	default:
+		printf("M.2: A module has been detected on M.2 port(TODO: add module type)\n");
+		break;
+	}
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	static const struct fsl_mmdc_info mparam = {
+		0x05180000,	/* mdctl */
+		0x00030035,	/* mdpdc */
+		0x12554000,	/* mdotc */
+		0xbabf7954,	/* mdcfg0 */
+		0xdb328f64,	/* mdcfg1 */
+		0x01ff00db,	/* mdcfg2 */
+		0x00001680,	/* mdmisc */
+		0x0f3c8000,	/* mdref */
+		0x00002000,	/* mdrwd */
+		0x00bf1023,	/* mdor */
+		0x0000003f,	/* mdasp */
+		0x0000022a,	/* mpodtctrl */
+		0xa1390003,	/* mpzqhwctrl */
+	};
+
+	mmdc_init(&mparam);
+
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+	/* This will break-before-make MMU for DDR */
+	update_early_mmu_table();
+#endif
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	fsl_lsch2_early_init_f();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
+					CONFIG_SYS_CCI400_OFFSET);
+	/*
+	 * Set CCI-400 control override register to enable barrier
+	 * transaction
+	 */
+	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
+	erratum_a010315();
+#endif
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+	gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+	sec_init();
+#endif
+
+#ifdef CONFIG_FSL_LS_PPA
+	ppa_init();
+#endif
+	return 0;
+}
+
+int esdhc_status_fixup(void *blob, const char *compat)
+{
+	/*char esdhc0_path[] = "/soc/esdhc@1560000";*/
+
+	return 0;
+}
+
+void scsi_init(void)
+{
+#if defined(CONFIG_SCSI_AHCI_PLAT) && defined(CONFIG_SERDES_D_TO_SATA)
+	struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
+
+	/* Disable SATA ECC */
+	out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
+	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
+	out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
+
+	ahci_init((void __iomem *)CONFIG_SYS_SATA);
+	scsi_scan(0);
+#else
+	printf("Disabled\n");
+#endif
+}
+
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	arch_fixup_fdt(blob);
+
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
diff --git a/board/scalys/grapeboard/ns_access.c b/board/scalys/grapeboard/ns_access.c
new file mode 100644
index 0000000..0c3a54c
--- /dev/null
+++ b/board/scalys/grapeboard/ns_access.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <fsl_csu.h>
+#include <asm/arch/ns_access.h>
+#include <asm/arch/fsl_serdes.h>
+
+void set_devices_ns_access(unsigned long index, u16 val)
+{
+	u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
+	u32 *reg;
+	uint32_t tmp;
+
+	reg = base + index / 2;
+	tmp = in_be32(reg);
+	if (index % 2 == 0) {
+		tmp &= 0x0000ffff;
+		tmp |= val << 16;
+	} else {
+		tmp &= 0xffff0000;
+		tmp |= val;
+	}
+
+	out_be32(reg, tmp);
+}
+
+static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
+{
+	int i;
+
+	for (i = 0; i < num; i++)
+		set_devices_ns_access(ns_dev[i].ind, ns_dev[i].val);
+}
+
+void enable_layerscape_ns_access(void)
+{
+#ifdef CONFIG_ARM64
+	if (current_el() == 3)
+#endif
+		enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+}
+
+void set_pcie_ns_access(int pcie, u16 val)
+{
+	switch (pcie) {
+#ifdef CONFIG_PCIE1
+	case PCIE1:
+		set_devices_ns_access(CSU_CSLX_PCIE1, val);
+		set_devices_ns_access(CSU_CSLX_PCIE1_IO, val);
+		return;
+#endif
+#ifdef CONFIG_PCIE2
+	case PCIE2:
+		set_devices_ns_access(CSU_CSLX_PCIE2, val);
+		set_devices_ns_access(CSU_CSLX_PCIE2_IO, val);
+		return;
+#endif
+#ifdef CONFIG_PCIE3
+	case PCIE3:
+		set_devices_ns_access(CSU_CSLX_PCIE3, val);
+		set_devices_ns_access(CSU_CSLX_PCIE3_IO, val);
+		return;
+#endif
+	default:
+		debug("The PCIE%d doesn't exist!\n", pcie);
+		return;
+	}
+}
diff --git a/board/scalys/grapeboard/usb_grapeboard.c b/board/scalys/grapeboard/usb_grapeboard.c
new file mode 100644
index 0000000..176c4be
--- /dev/null
+++ b/board/scalys/grapeboard/usb_grapeboard.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+
+#define MIN(X,Y) ((X) < (Y) ? (X) : (Y))
+
+#define I2C_ADDRESS_USB_HUB		0x60
+#define MAX_I2C_ATTEMPTS		10
+
+#define HX3_SETTINGS_SIZE		192
+
+/* Cypress HX3 hub settings blob */
+const uint8_t hx3_settings[5 + HX3_SETTINGS_SIZE] = {
+	'C', 'Y', /* Cypress magic signature */
+	0x30, /* I2C speed : 100kHz */
+	0xd4, /* Image type: Only settings, no firmware */
+	HX3_SETTINGS_SIZE, /* payload size (192) */
+	0xb4, 0x04, /* VID */
+	0x04, 0x65, /* PID */
+	0x0a, 0x50, /* DID */
+	0x00, /* Reserved */
+	0x0f, /* 4 SuperSpeed ports, no shared link */
+	0x32, /* bPwrOn2PwrGood : 100 ms */
+	0x7f, /* 4 Downstream ports : DS4 is non-removable (MCU) */
+	0xe1, /* LEDs disabled, Ganged power switching */
+	0xa0, /* suspend indicator disabled, power switch control is active high */
+	0x04, /* BC v1.2 disabled, apple charging 1A, ghost charging disabled */
+	0x00, /* port charging, cdp & dcp disabled */
+	0xd8, /* US is embedded port, overcurrent input is active high */
+	0x00, /* reserved */
+	0x08, /* USB String descriptors enabled */
+	0x00, 0x00,
+	0x12, 0x00, 0x2c,
+	0x66, 0x66, /* USB3.0 TX driver de-emphasis */
+	0x69, 0x29, 0x29, 0x29, 0x29, /* TX amplitude */
+	0x00, /* Reserved */
+	0x06, 0x65, /* USB 2.0 PID */
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* Reserved */
+	0x04, 0x03, 0x09, 0x04, /* LangID = 0x0409 US English */
+	0x18, 0x03, /* Manufacturer string descriptor */
+	0x32, 0x00, 0x30, 0x00, 0x31, 0x00, 0x37, 0x00,
+	0x20, 0x00, 0x53, 0x00, 0x63, 0x00, 0x61, 0x00,
+	0x6c, 0x00, 0x79, 0x00, 0x73, 0x00,
+	0x2c, 0x03, /* Product string descriptor */
+	0x47, 0x00, 0x72, 0x00, 0x61, 0x00, 0x70, 0x00,
+	0x65, 0x00, 0x62, 0x00, 0x6f, 0x00, 0x61, 0x00,
+	0x72, 0x00, 0x64, 0x00, 0x20, 0x00, 0x43, 0x00,
+	0x59, 0x00, 0x2d, 0x00, 0x48, 0x00, 0x58, 0x00,
+	0x33, 0x00, 0x20, 0x00, 0x48, 0x00, 0x55, 0x00,
+	0x42, 0x00,
+	0x1a, 0x03, /* Serial string descriptor */
+	0x47, 0x00,	0x72, 0x00, 0x61, 0x00, 0x70, 0x00,
+	0x65, 0x00, 0x62, 0x00, 0x6f, 0x00, 0x61, 0x00,
+	0x72, 0x00, 0x64, 0x00, 0x20, 0x00, 0x31, 0x00,
+	0x39, 0x00, 0x41, 0x00,
+	0x00
+};
+
+int usb_hub_init(void) {
+	int length, index = 0, i2c_attempts = 0;
+	const int settings_size = sizeof(hx3_settings);
+	uint8_t *data = (uint8_t *)hx3_settings;
+
+	/*
+	 * Configure USB hub slave
+	 *
+	 * The Hx3 starts in an i2c slave bootloader mode until sufficient and correct data is written to it over I2C.
+	 * If transferred data is incorrect then the device will hang until it has been reset.
+	 */
+	puts("USB: configuring hub....");
+
+	while(index <= settings_size - 1){
+		length = MIN(64, (settings_size - index));
+
+		if(i2c_write(I2C_ADDRESS_USB_HUB, index, 2, data, length)) {
+			if(i2c_attempts < 1)
+				printf("\nI2C error during configuring USB hub slave. retrying...\n");
+			if(++i2c_attempts >= MAX_I2C_ATTEMPTS){
+				printf("ERROR: Maximum USB hub configuration attempts reached. Exiting now\n");
+				return 1;
+			}
+			continue;
+		}
+		i2c_attempts = 0; /* reset error count */
+		index += length;
+		data += length;
+	}
+
+	puts("Done!\n");
+	return 0;
+}
+
+int usb_hub_reset(void) {
+	/* USB hub cannot be reset in software without resetting the ls1012a */
+	return 1;
+}
diff --git a/board/scalys/grapeboard/usb_grapeboard.h b/board/scalys/grapeboard/usb_grapeboard.h
new file mode 100644
index 0000000..b57f102
--- /dev/null
+++ b/board/scalys/grapeboard/usb_grapeboard.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef USB_GRAPEBOARD_H_
+#define USB_GRAPEBOARD_H_
+
+int usb_hub_init(void);
+int usb_hub_reset(void);
+
+#endif /* USB_GRAPEBOARD_H_ */
diff --git a/configs/grapeboard_pcie_qspi_defconfig b/configs/grapeboard_pcie_qspi_defconfig
new file mode 100644
index 0000000..621c547
--- /dev/null
+++ b/configs/grapeboard_pcie_qspi_defconfig
@@ -0,0 +1,59 @@
+CONFIG_ARM=y
+CONFIG_TARGET_GRAPEBOARD=y
+CONFIG_FSL_LS_PPA=y
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_DEFAULT_DEVICE_TREE="grapeboard"
+CONFIG_SERDES_D_TO_PCIE=y
+CONFIG_STANDARD_UBOOT_CONFIG=y
+CONFIG_CLUSTER_CLK_FREQ=125000000
+CONFIG_SYS_LS_PPA_FW_ADDR=0x40240000
+CONFIG_SYS_LS_PFE_FW_ADDR=0x40280000
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_QSPI_BOOT=y
+CONFIG_BOOTDELAY=10
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+# CONFIG_BLK is not set
+CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_FSL_PFE=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_TI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_DISTRO_DEFAULTS=y
+
diff --git a/configs/grapeboard_sata_qspi_defconfig b/configs/grapeboard_sata_qspi_defconfig
new file mode 100644
index 0000000..5483e22
--- /dev/null
+++ b/configs/grapeboard_sata_qspi_defconfig
@@ -0,0 +1,58 @@
+CONFIG_ARM=y
+CONFIG_TARGET_GRAPEBOARD=y
+CONFIG_FSL_LS_PPA=y
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_DEFAULT_DEVICE_TREE="grapeboard"
+CONFIG_SERDES_D_TO_SATA=y
+CONFIG_STANDARD_UBOOT_CONFIG=y
+CONFIG_CLUSTER_CLK_FREQ=125000000
+CONFIG_SYS_LS_PPA_FW_ADDR=0x40240000
+CONFIG_SYS_LS_PFE_FW_ADDR=0x40280000
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_QSPI_BOOT=y
+CONFIG_BOOTDELAY=10
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+# CONFIG_BLK is not set
+CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_FSL_PFE=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_TI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_DISTRO_DEFAULTS=y
diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c
index e45edeb..491f4af 100644
--- a/drivers/mtd/spi/spi_flash_ids.c
+++ b/drivers/mtd/spi/spi_flash_ids.c
@@ -102,6 +102,7 @@ const struct spi_flash_info spi_flash_ids[] = {
 	{"s25fl256s_64k",  INFO(0x010219, 0x4d01,  64 * 1024,   512, RD_FULL | WR_QPP) },
 	{"s25fs256s_64k",  INFO6(0x010219, 0x4d0181, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) },
 	{"s25fs512s",      INFO6(0x010220, 0x4d0081, 256 * 1024, 256, RD_FULL | WR_QPP | ADDR_4B) },
+	{"s25fs064s",      INFO6(0x010217, 0x4d0181, 64 * 1024, 128, RD_FULL | WR_QPP | ADDR_4B) },
 	{"s25fl512s_256k", INFO(0x010220, 0x4d00, 256 * 1024,   256, RD_FULL | WR_QPP) },
 	{"s25fl512s_64k",  INFO(0x010220, 0x4d01,  64 * 1024,  1024, RD_FULL | WR_QPP) },
 	{"s25fl512s_512k", INFO(0x010220, 0x4f00, 256 * 1024,   256, RD_FULL | WR_QPP) },
diff --git a/include/configs/grapeboard.h b/include/configs/grapeboard.h
new file mode 100644
index 0000000..89fe713
--- /dev/null
+++ b/include/configs/grapeboard.h
@@ -0,0 +1,282 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ *
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __GRAPEBOARD_H__
+#define __GRAPEBOARD_H__
+
+#define CONFIG_FSL_LAYERSCAPE
+#define CONFIG_GICV2
+
+#include <asm/arch/config.h>
+#include <asm/arch/stream_id_lsch2.h>
+#include <asm/arch/soc.h>
+
+#define CONFIG_PBL_IMAGE
+#ifdef CONFIG_PBL_IMAGE
+
+/* Set the PBL(RCW+PBI) depending on the chosen SERDES option */
+#if (defined(CONFIG_SERDES_D_TO_SATA))
+#define CONFIG_PBL_BINARY board/scalys/grapeboard/PBL_0x35_0x08_750_250_1000.bin
+#elif (defined(CONFIG_SERDES_D_TO_PCIE))
+#define CONFIG_PBL_BINARY board/scalys/grapeboard/PBL_0x33_0x05_750_250_1000.bin
+#else
+#error Invalid SERDES option
+#endif
+
+#endif /* CONFIG_PBL_IMAGE */
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/* Make sure text/u-boot base aligns with the pointer set in the PBL */
+#define CONFIG_U_BOOT_PAD_TO 0x1000
+#define CONFIG_SYS_TEXT_BASE 0x40001000
+
+#define CONFIG_SYS_CLK_FREQ					125000000
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SYS_INIT_SP_ADDR				(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+#define CONFIG_SYS_LOAD_ADDR				(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+
+
+/* DDR */
+#define CONFIG_SYS_DDR_SDRAM_BASE			0x80000000
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
+#define CONFIG_SYS_SDRAM_BASE				CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_BLOCK2_BASE     		0x880000000ULL
+#define CONFIG_DIMM_SLOTS_PER_CTLR			1
+#define CONFIG_CHIP_SELECTS_PER_CTRL		1
+#define CONFIG_NR_DRAM_BANKS				2
+#define CONFIG_SYS_SDRAM_SIZE				0x40000000
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START			0x80000000
+#define CONFIG_SYS_MEMTEST_END				0x9fffffff
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY					25000000	/* 25MHz */
+
+/* CSU */
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN				(CONFIG_ENV_SIZE + 128 * 1024)
+
+/* QSPI */
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR				0x400d0000
+#define CONFIG_ENV_SPI_BUS					0
+#define CONFIG_ENV_SPI_CS					0
+#define CONFIG_ENV_SPI_MAX_HZ				1000000
+#define CONFIG_ENV_SPI_MODE					0x03
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_FSL_SPI_INTERFACE
+#define CONFIG_SF_DATAFLASH
+#define CONFIG_FSL_QSPI
+#define QSPI0_AMBA_BASE						0x40000000
+#define CONFIG_SPI_FLASH_SPANSION
+#define FSL_QSPI_FLASH_SIZE					SZ_64M
+#define FSL_QSPI_FLASH_NUM					2
+
+/* QSPI Environment */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE						0x40000          /* 256KB */
+#define CONFIG_ENV_OFFSET					0x200000        /* 2MB */
+#define CONFIG_ENV_SECT_SIZE				0x40000
+#endif /* CONFIG_QSPI_BOOT */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1
+
+/* UART */
+#define CONFIG_CONS_INDEX       			1
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE     	1
+#define CONFIG_SYS_NS16550_CLK          	(get_serial_clock())
+#define CONFIG_SYS_BAUDRATE_TABLE			{ 9600, 19200, 38400, 57600, 115200 }
+
+/* Command line configuration */
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_SYS_HZ						1000
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE				128
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE					512	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE					(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE					CONFIG_SYS_CBSIZE /* Boot args buffer */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_MAXARGS					64	/* max command args */
+
+#define CONFIG_PANIC_HANG
+#define CONFIG_SYS_BOOTM_LEN   				(64 << 20)      /* Increase max gunzip size */
+
+/* PFE Ethernet */
+#ifdef CONFIG_FSL_PFE
+#define EMAC1_PHY_ADDR          			0x0 /* may be changed to 1 because of possible bug */
+#define EMAC2_PHY_ADDR          			0x2
+#endif
+
+/* USB */
+#define CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_MAX_CONTROLLER_COUNT    1
+
+/*  MMC  */
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#endif
+
+/* SATA */
+#define CONFIG_LIBATA
+#define	CONFIG_SCSI
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_CMD_SCSI
+#define CONFIG_SYS_SATA					AHCI_BASE_ADDR
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
+#define CONFIG_SYS_SCSI_MAX_LUN			1
+#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
+
+/* PCIE */
+#define CONFIG_PCIE1
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+
+/* Mtdparts configuration */
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+
+#define MTDIDS_DEFAULT \
+	"qspi0=40000000.qspi"
+
+#define MTDPART_DEFAULT_PARTITIONS \
+	"2M@0x0(u-boot)," \
+	"256k(env)," \
+	"256k(ppa)," \
+	"256k(pfe_ucode),"
+
+#define MTDPARTS_DEFAULT    \
+	"mtdparts=40000000.qspi:" \
+		MTDPART_DEFAULT_PARTITIONS \
+		"-(rootfs)"
+
+/* Default environment variables */
+#if CONFIG_STANDARD_UBOOT_CONFIG
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"verify=no\0"				\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"fdt_addr=0x00f00000\0"			\
+	"kernel_addr=0x01000000\0"		\
+	"kernelheader_addr=0x800000\0"		\
+	"scriptaddr=0x80000000\0"		\
+	"scripthdraddr=0x80080000\0"		\
+	"fdtheader_addr_r=0x80100000\0"		\
+	"kernelheader_addr_r=0x80200000\0"	\
+	"kernel_addr_r=0x81000000\0"		\
+	"fdt_addr_r=0x90000000\0"		\
+	"load_addr=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"kernelheader_size=0x40000\0"		\
+	"console=ttyS0,115200\0"		\
+	"ethprime=pfe_eth0\0" \
+	"ethaddr=02:00:00:ba:be:01\0" \
+	"eth1addr=02:00:00:ba:be:02\0" \
+	"tftp_path=\0" \
+	"autoload=no\0" \
+	"update_pbl_uboot_qspi_nor_nw=" \
+        "dhcp;" \
+        "tftp $load_addr $tftp_path/u-boot-pbl.bin;" \
+        "if test $? = \"0\"; then " \
+        	"sf probe 0:0;" \
+			"sf erase 0 200000;" \
+            "sf write $load_addr 0 $filesize;" \
+        "fi\0" \
+	"update_ppa_qspi_nor_nw=" \
+        "dhcp;" \
+        "tftp $load_addr $tftp_path/ppa.itb;" \
+        "if test $? = \"0\"; then " \
+        	"sf probe 0:0;" \
+			"sf erase 240000 40000;" \
+            "sf write $load_addr 240000 $filesize;" \
+        "fi\0" \
+	"update_pfe_qspi_nor_nw=" \
+        "dhcp;" \
+        "tftp $load_addr $tftp_path/pfe_fw_sbl.itb;" \
+        "if test $? = \"0\"; then " \
+        	"sf probe 0:0;" \
+			"sf erase 280000 40000;" \
+            "sf write $load_addr 280000 $filesize;" \
+        "fi\0" \
+	"mmcboot=" \
+		"ext4load mmc 0:1 $fdt_addr_r /boot/grapeboard.dtb;" \
+		"ext4load mmc 0:1 $kernel_addr_r /boot/uImage;" \
+		"if test $? = \"0\"; then " \
+			"pfe stop;" \
+			"bootm $kernel_addr_r - $fdt_addr_r;" \
+		"fi\0" \
+	"tftpboot=" \
+		"dhcp;" \
+		"tftp $fdt_addr_r $tftp_path/grapeboard.dtb;" \
+		"tftp $kernel_addr_r $tftp_path/uImage;" \
+		"if test $? = \"0\"; then " \
+			"pfe stop;" \
+			"bootm $kernel_addr_r - $fdt_addr_r;" \
+		"fi\0"
+
+#undef CONFIG_BOOTCOMMAND
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_BOOTCOMMAND "run mmcboot"
+#endif
+#ifdef CONFIG_BOOTARGS
+#undef CONFIG_BOOTARGS
+#endif
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 root=/dev/mmcblk0p1 rootfstype=ext4 rw " \
+				"earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000 noinitrd"
+#else /* if CONFIG_RESCUE_UBOOT_CONFIG */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"verify=no\0"				\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"fdt_addr=0x00f00000\0"			\
+	"kernel_addr=0x01000000\0"		\
+	"kernelheader_addr=0x800000\0"		\
+	"scriptaddr=0x80000000\0"		\
+	"scripthdraddr=0x80080000\0"		\
+	"fdtheader_addr_r=0x80100000\0"		\
+	"kernelheader_addr_r=0x80200000\0"	\
+	"kernel_addr_r=0x81000000\0"		\
+	"fdt_addr_r=0x90000000\0"		\
+	"load_addr=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"kernelheader_size=0x40000\0"
+
+#undef CONFIG_BOOTCOMMAND
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+/* recover from sd card */
+#define CONFIG_BOOTCOMMAND ""
+#endif
+
+#endif
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __GRAPEBOARD_H__ */