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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2015-06-03 09:13:27 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-06-12 16:43:07 (GMT) |
| commit | 536d87470869c4c3257d70f387146703a2dee7c5 (patch) | |
| tree | 610e3b1aea7b1cdaab7345460a1b96ff3aa1a983 | |
| parent | a5c5c5b500bd7cee5f5d260c538429fe1bcc0ae1 (diff) | |
| download | u-boot-536d87470869c4c3257d70f387146703a2dee7c5.tar.xz | |
ARM: DRA7: Update DDR IO registers
Update DDR IO register values.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/hw_data.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 868415d..bfdf1e0 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -592,11 +592,11 @@ const struct ctrl_ioregs ioregs_dra7xx_es1 = { .ctrl_ddrch = 0x40404040, .ctrl_lpddr2ch = 0x40404040, .ctrl_ddr3ch = 0x80808080, - .ctrl_ddrio_0 = 0xA2084210, - .ctrl_ddrio_1 = 0x84210840, + .ctrl_ddrio_0 = 0x00094A40, + .ctrl_ddrio_1 = 0x04A52000, .ctrl_ddrio_2 = 0x84210000, - .ctrl_emif_sdram_config_ext = 0x0001C1A7, - .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, + .ctrl_emif_sdram_config_ext = 0x0001C127, + .ctrl_emif_sdram_config_ext_final = 0x0001C127, .ctrl_ddr_ctrl_ext_0 = 0xA2000000, }; @@ -604,11 +604,11 @@ const struct ctrl_ioregs ioregs_dra72x_es1 = { .ctrl_ddrch = 0x40404040, .ctrl_lpddr2ch = 0x40404040, .ctrl_ddr3ch = 0x60606080, - .ctrl_ddrio_0 = 0xA2084210, - .ctrl_ddrio_1 = 0x84210840, + .ctrl_ddrio_0 = 0x00094A40, + .ctrl_ddrio_1 = 0x04A52000, .ctrl_ddrio_2 = 0x84210000, - .ctrl_emif_sdram_config_ext = 0x0001C1A7, - .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, + .ctrl_emif_sdram_config_ext = 0x0001C127, + .ctrl_emif_sdram_config_ext_final = 0x0001C127, .ctrl_ddr_ctrl_ext_0 = 0xA2000000, }; |