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author | Tom Rini <trini@ti.com> | 2013-04-16 14:56:55 (GMT) |
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committer | Tom Rini <trini@ti.com> | 2013-04-16 14:56:55 (GMT) |
commit | 5873d0fbad2b1a94db7b9c8c8f5d77c10479a9dd (patch) | |
tree | 8c76c25d17b3368756309cb3071327758aa81733 | |
parent | cba6494f24d711ba63afb22b1ee691a41fee121c (diff) | |
parent | c4a4e2e20ca226948b62ed116df98f7a3932f2ac (diff) | |
download | u-boot-5873d0fbad2b1a94db7b9c8c8f5d77c10479a9dd.tar.xz |
Merge branch 'master' of git://git.denx.de/u-boot-arm
-rw-r--r-- | arch/arm/cpu/armv7/start.S | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 61da7ac..5feae7a 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -130,11 +130,15 @@ IRQ_STACK_START_IN: reset: bl save_boot_params /* - * set the cpu to SVC32 mode + * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode, + * except if in HYP mode already */ mrs r0, cpsr - bic r0, r0, #0x1f - orr r0, r0, #0xd3 + and r1, r0, #0x1f @ mask mode bits + teq r1, #0x1a @ test for HYP mode + bicne r0, r0, #0x1f @ clear all mode bits + orrne r0, r0, #0x13 @ set SVC mode + orr r0, r0, #0xc0 @ disable FIQ and IRQ msr cpsr,r0 /* |