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| author | Anton Staaf <robotboy@chromium.org> | 2011-10-17 23:46:05 (GMT) |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2011-10-23 18:50:42 (GMT) |
| commit | 6fa6035ff2ac62258736ee9365c4b3135a68f4c3 (patch) | |
| tree | 01c87e5762f234cbb17f3167907a6a10138a0b18 | |
| parent | a8fc12eb8e7ff6a97c45d921fdf28dcaaba9c8b6 (diff) | |
| download | u-boot-6fa6035ff2ac62258736ee9365c4b3135a68f4c3.tar.xz | |
nios2: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Scott McNutt <smcnutt@psyent.com>
| -rw-r--r-- | arch/nios2/include/asm/cache.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/nios2/include/asm/cache.h b/arch/nios2/include/asm/cache.h index c78f343..2cc16e4 100644 --- a/arch/nios2/include/asm/cache.h +++ b/arch/nios2/include/asm/cache.h @@ -27,4 +27,15 @@ extern void flush_dcache (unsigned long start, unsigned long size); extern void flush_icache (unsigned long start, unsigned long size); +/* + * Valid L1 data cache line sizes for the NIOS2 architecture are 4, 16, and 32 + * bytes. If the board configuration has not specified one we default to the + * largest of these values for alignment of DMA buffers. + */ +#ifdef CONFIG_SYS_CACHELINE_SIZE +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#else +#define ARCH_DMA_MINALIGN 32 +#endif + #endif /* __ASM_NIOS2_CACHE_H_ */ |