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author | Tom Rini <trini@ti.com> | 2013-11-06 21:11:34 (GMT) |
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committer | Tom Rini <trini@ti.com> | 2013-11-06 21:11:34 (GMT) |
commit | 76a224104bc9c0147385da92fd78116ba4913b90 (patch) | |
tree | e3975b128f67406ebab68dc5e1f5c61f635b5cec | |
parent | edabc1bc6def0ec2b618d779964d2a2c554d7faf (diff) | |
parent | 32d7cdd366a1516fa498464c261851f3a76a62ef (diff) | |
download | u-boot-76a224104bc9c0147385da92fd78116ba4913b90.tar.xz |
Merge branch 'fpga' of git://www.denx.de/git/u-boot-microblaze
-rw-r--r-- | common/cmd_fpga.c | 22 | ||||
-rw-r--r-- | drivers/fpga/zynqpl.c | 15 |
2 files changed, 32 insertions, 5 deletions
diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c index c4b3c8f..010cd24 100644 --- a/common/cmd_fpga.c +++ b/common/cmd_fpga.c @@ -160,9 +160,25 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) image_header_t *hdr = (image_header_t *)fpga_data; ulong data; - - data = (ulong)image_get_data(hdr); - data_size = image_get_data_size(hdr); + uint8_t comp; + + comp = image_get_comp(hdr); + if (comp == IH_COMP_GZIP) { + ulong image_buf = image_get_data(hdr); + data = image_get_load(hdr); + ulong image_size = ~0UL; + + if (gunzip((void *)data, ~0UL, + (void *)image_buf, + &image_size) != 0) { + puts("GUNZIP: error\n"); + return 1; + } + data_size = image_size; + } else { + data = (ulong)image_get_data(hdr); + data_size = image_get_data_size(hdr); + } rc = fpga_load(dev, (void *)data, data_size); } break; diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 717c039..1effbad 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -10,6 +10,7 @@ #include <common.h> #include <asm/io.h> #include <zynqpl.h> +#include <asm/sizes.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> @@ -177,8 +178,14 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) return FPGA_FAIL; } - if ((u32)buf_start & 0x3) { - u32 *new_buf = (u32 *)((u32)buf & ~0x3); + if ((u32)buf < SZ_1M) { + printf("%s: Bitstream has to be placed up to 1MB (%x)\n", + __func__, (u32)buf); + return FPGA_FAIL; + } + + if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) { + u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN); printf("%s: Align buffer at %x to %x(swap %d)\n", __func__, (u32)buf_start, (u32)new_buf, swap); @@ -284,6 +291,10 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) debug("%s: Source = 0x%08X\n", __func__, (u32)buf); debug("%s: Size = %zu\n", __func__, bsize); + /* flush(clean & invalidate) d-cache range buf */ + flush_dcache_range((u32)buf, (u32)buf + + roundup(bsize, ARCH_DMA_MINALIGN)); + /* Set up the transfer */ writel((u32)buf | 1, &devcfg_base->dma_src_addr); writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr); |