diff options
| author | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2017-02-15 15:10:35 (GMT) |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2017-03-28 16:09:22 (GMT) |
| commit | 7b45b383fd0a05e6b6ee42676210b728596c86bc (patch) | |
| tree | bd859f8d71f122a3d7dea69ef5c5bcb319719c95 | |
| parent | 1b7dba990f60b461fb7af92464590cc0f326ae81 (diff) | |
| download | u-boot-7b45b383fd0a05e6b6ee42676210b728596c86bc.tar.xz | |
armv8:fsl-layerscape: Avoid RCWSR28 register hard-coding
SerDes information is not necessary to be present in RCWSR29 register.
It may vary from SoC to SoC.
So Avoid RCWSR28 register hard-coding.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 28 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 9 |
2 files changed, 25 insertions, 12 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index c2fc646..955e0b7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -51,20 +51,22 @@ int is_serdes_configured(enum srds_prtcl device) int serdes_get_first_lane(u32 sd, enum srds_prtcl device) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - u32 cfg = gur_in32(&gur->rcwsr[28]); + u32 cfg = 0; int i; switch (sd) { #ifdef CONFIG_SYS_FSL_SRDS_1 case FSL_SRDS_1: - cfg &= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; - cfg >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]); + cfg &= FSL_CHASSIS3_SRDS1_PRTCL_MASK; + cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT; break; #endif #ifdef CONFIG_SYS_FSL_SRDS_2 case FSL_SRDS_2: - cfg &= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; - cfg >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; + cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]); + cfg &= FSL_CHASSIS3_SRDS2_PRTCL_MASK; + cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT; break; #endif default: @@ -83,8 +85,8 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device) return -ENODEV; } -void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, - u8 serdes_prtcl_map[SERDES_PRCTL_COUNT]) +void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, + u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT]) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 cfg; @@ -95,7 +97,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT); - cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask; + cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask; cfg >>= sd_prctl_shift; printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); @@ -152,15 +154,17 @@ void fsl_serdes_init(void) #ifdef CONFIG_SYS_FSL_SRDS_1 serdes_init(FSL_SRDS_1, CONFIG_SYS_FSL_LSCH3_SERDES_ADDR, - FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK, - FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT, + FSL_CHASSIS3_SRDS1_REGSR, + FSL_CHASSIS3_SRDS1_PRTCL_MASK, + FSL_CHASSIS3_SRDS1_PRTCL_SHIFT, serdes1_prtcl_map); #endif #ifdef CONFIG_SYS_FSL_SRDS_2 serdes_init(FSL_SRDS_2, CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000, - FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK, - FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT, + FSL_CHASSIS3_SRDS2_REGSR, + FSL_CHASSIS3_SRDS2_PRTCL_MASK, + FSL_CHASSIS3_SRDS2_PRTCL_SHIFT, serdes2_prtcl_map); #endif } diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 08ea8fb..80c421f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -230,10 +230,19 @@ struct ccsr_gur { #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f + +#if defined(CONFIG_ARCH_LS2080A) #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24 +#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK +#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK +#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS1_REGSR 29 +#define FSL_CHASSIS3_SRDS2_REGSR 29 +#endif #define RCW_SB_EN_REG_INDEX 9 #define RCW_SB_EN_MASK 0x00000400 |