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| author | Michal Simek <michal.simek@xilinx.com> | 2015-07-22 08:40:51 (GMT) |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2015-07-28 09:56:22 (GMT) |
| commit | 8a8c46a65de5ec03564930820992c136d17023f7 (patch) | |
| tree | 00692bed8cc54de05946a8971c41f9f19afec5d3 | |
| parent | bece06ce0ce3810cd60930da7ef97e75960da673 (diff) | |
| download | u-boot-8a8c46a65de5ec03564930820992c136d17023f7.tar.xz | |
ARM: zynq: DT: Migrate UART to Cadence binding
The Zynq UART is Cadence IP and the driver has been renamed accordingly.
Migrate the DT to use the new binding for the UART driver.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Acked-by: Rob Herring <robh@kernel.org>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| -rw-r--r-- | arch/arm/dts/zynq-7000.dtsi | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 326ab67..a4bfc62 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -149,19 +149,19 @@ }; uart0: serial@e0000000 { - compatible = "xlnx,xuartps"; + compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; - clock-names = "ref_clk", "aper_clk"; + clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { - compatible = "xlnx,xuartps"; + compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; - clock-names = "ref_clk", "aper_clk"; + clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; |