diff options
| author | Thierry Reding <treding@nvidia.com> | 2015-09-08 09:38:04 (GMT) |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2015-09-16 23:11:31 (GMT) |
| commit | 8e1601d994e2fa8b8c7826470c3d923a684492a4 (patch) | |
| tree | be4bc580ea0ce2f4005efbf1f54a5f346e5c8c21 | |
| parent | aba11d4476b56eb7712184597eb303ae544f0c69 (diff) | |
| download | u-boot-8e1601d994e2fa8b8c7826470c3d923a684492a4.tar.xz | |
ARM: tegra114: Clear IDDQ when enabling PLLC
Enabling a PLL while IDDQ is high. The Linux kernel checks for this
condition and warns about it verbosely, so while this seems to work
fine, fix it up according to the programming guidelines provided in
the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup
Sequence"). The Tegra114 TRM doesn't contain this information, but
the programming of PLLC is the same on Tegra114 and Tegra124.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
| -rw-r--r-- | arch/arm/include/asm/arch-tegra114/clock.h | 3 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/tegra114/clock.c | 5 |
2 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-tegra114/clock.h b/arch/arm/include/asm/arch-tegra114/clock.h index abbefcd..9bee397 100644 --- a/arch/arm/include/asm/arch-tegra114/clock.h +++ b/arch/arm/include/asm/arch-tegra114/clock.h @@ -25,4 +25,7 @@ #define OSC_FREQ_SHIFT 28 #define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) +/* CLK_RST_CONTROLLER_PLLC_MISC_0 */ +#define PLLC_IDDQ (1 << 26) + #endif /* _TEGRA114_CLOCK_H_ */ diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c index cec843b..e6ef873 100644 --- a/arch/arm/mach-tegra/tegra114/clock.c +++ b/arch/arm/mach-tegra/tegra114/clock.c @@ -629,6 +629,11 @@ void clock_early_init(void) tegra30_set_up_pllp(); + /* clear IDDQ before accessing any other PLLC registers */ + pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; + clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); + udelay(2); + /* * PLLC output frequency set to 600Mhz * PLLD output frequency set to 925Mhz |