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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-08-10 07:08:46 (GMT) |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-08-11 08:49:44 (GMT) |
| commit | 8fca073271706f3d856c6554c2b5400ac9c83c10 (patch) | |
| tree | 06c882eb921d1931b3fea21dbd0ec81fd3452f86 | |
| parent | 7382d1782648e6e8e5be878e9b9a3cbfd1912001 (diff) | |
| download | u-boot-8fca073271706f3d856c6554c2b5400ac9c83c10.tar.xz | |
ARM: uniphier: fix CONFIG_SYS_CACHELINE_SIZE when outer cache is on
The UniPhier outer cache (L2 cache on ARMv7 SoCs) has 128 byte line
length and its tags are also managed per 128 byte line.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| -rw-r--r-- | include/configs/uniphier.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 2606e53..9ee125f 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -25,7 +25,11 @@ /* #define CONFIG_SYS_ICACHE_OFF */ /* #define CONFIG_SYS_DCACHE_OFF */ +#ifdef CONFIG_CACHE_UNIPHIER +#define CONFIG_SYS_CACHELINE_SIZE 128 +#else #define CONFIG_SYS_CACHELINE_SIZE 32 +#endif #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO |