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| author | York Sun <york.sun@nxp.com> | 2017-09-08 16:33:49 (GMT) |
|---|---|---|
| committer | Alison Wang <b18965@freescale.com> | 2017-09-11 13:00:10 (GMT) |
| commit | 96cc4d72500150db31f062e296f9964e1e78a76e (patch) | |
| tree | 78c633b55bbb5203ba39aeee1247f99831ae9d55 | |
| parent | bdf9c1af48954fbf6dac8540fae5abf3f9ddf570 (diff) | |
| download | u-boot-96cc4d72500150db31f062e296f9964e1e78a76e.tar.xz | |
armv8: fsl-layerscape: Add back L3 flushing for all exception levels
CCN-504 HPF registers were believed to be accessible only from EL3.
However, recent tests proved otherwise. Remove checking for exception
level to re-enable L3 cache flushing for all levels.
Signed-off-by: York Sun <york.sun@nxp.com>
Tested-by: Zhao Qiang <qiang.zhao@nxp.com>
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index e91be19..28a31b2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -396,9 +396,6 @@ ENTRY(__asm_flush_l3_dcache) mov x29, lr mov x8, #0 - switch_el x0, 1f, 100f, 100f /* skip if not in EL3 */ - -1: dsb sy mov x0, #0x1 /* HNFPSTAT_SFONLY */ bl hnf_set_pstate @@ -416,7 +413,6 @@ ENTRY(__asm_flush_l3_dcache) bl hnf_pstate_poll cbz x0, 1f add x8, x8, #0x2 -100: 1: mov x0, x8 mov lr, x29 |