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author | Bin Meng <bmeng.cn@gmail.com> | 2015-07-22 08:21:14 (GMT) |
---|---|---|
committer | Simon Glass <sjg@chromium.org> | 2015-07-28 16:36:25 (GMT) |
commit | 9830d2ebb4f1683ff7f50b3420374a1843839378 (patch) | |
tree | f00ef30f3dbb7b151bb0b27db32bba0ef7904e92 | |
parent | a8ebf283e98d0eda0b7c76647cdcd3f36f34837c (diff) | |
download | u-boot-9830d2ebb4f1683ff7f50b3420374a1843839378.tar.xz |
x86: qemu: Turn on PCIe ECAM address range decoding on Q35
Turn on PCIe ECAM address range decoding on Q35.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
-rw-r--r-- | arch/x86/cpu/qemu/pci.c | 4 | ||||
-rw-r--r-- | arch/x86/include/asm/arch-qemu/qemu.h | 4 |
2 files changed, 8 insertions, 0 deletions
diff --git a/arch/x86/cpu/qemu/pci.c b/arch/x86/cpu/qemu/pci.c index acbd922..2e94456 100644 --- a/arch/x86/cpu/qemu/pci.c +++ b/arch/x86/cpu/qemu/pci.c @@ -90,6 +90,10 @@ int board_pci_post_scan(struct pci_controller *hose) xbcs = x86_pci_read_config16(PIIX_ISA, XBCS); xbcs |= APIC_EN; x86_pci_write_config16(PIIX_ISA, XBCS, xbcs); + } else { + /* Configure PCIe ECAM base address */ + x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR, + CONFIG_PCIE_ECAM_BASE | BAR_EN); } /* diff --git a/arch/x86/include/asm/arch-qemu/qemu.h b/arch/x86/include/asm/arch-qemu/qemu.h index 8c8e4ac..b67d342 100644 --- a/arch/x86/include/asm/arch-qemu/qemu.h +++ b/arch/x86/include/asm/arch-qemu/qemu.h @@ -22,6 +22,10 @@ #define IDE1_TIM 0x42 #define IDE_DECODE_EN (1 << 15) +/* PCIe ECAM Base Address Register */ +#define PCIEX_BAR 0x60 +#define BAR_EN (1 << 0) + /* I/O Ports */ #define CMOS_ADDR_PORT 0x70 #define CMOS_DATA_PORT 0x71 |