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| author | Bhupesh Sharma <bhupesh.sharma@freescale.com> | 2015-03-19 16:20:44 (GMT) |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-04-21 17:27:07 (GMT) |
| commit | b7f57ac0d8a7ac16c893170b9b9a72bda138eb23 (patch) | |
| tree | 818a0f0b73ed3a25f700844a990aa9a78b2f669a | |
| parent | 422cb08acb1bc9a05ffa68ba68b4e196dad1af5b (diff) | |
| download | u-boot-b7f57ac0d8a7ac16c893170b9b9a72bda138eb23.tar.xz | |
fsl-ch3/README: Add description for NOR flash layout (firmware images)
This patch adds description for NOR flash layout (firmware images)
in the README file for LS2085A platforms.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-lsch3/README | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-lsch3/README index cc47466..99fc39a 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/README +++ b/arch/arm/cpu/armv8/fsl-lsch3/README @@ -8,3 +8,28 @@ Freescale LayerScape with Chassis Generation 3 This architecture supports Freescale ARMv8 SoCs with Chassis generation 3, for example LS2085A. + +Flash Layout +============ +A typical layout of various images (including Linux and other firmware images) +is shown below considering a 32MB NOR flash device: + + ------------------------- + | linux | + ------------------------- ----> 0x0120_0000 + | Debug Server | + ------------------------- ----> 0x00C0_0000 + | AIOP SW | + ------------------------- ----> 0x0070_0000 + | MC FW | + ------------------------- ----> 0x006C_0000 + | MC Data Path Layout | + ------------------------- ----> 0x0020_0000 + | BootLoader | + ------------------------- ----> 0x0000_1000 + | PBI | + ------------------------- ----> 0x0000_0080 + | RCW | + ------------------------- ----> 0x0000_0000 + + 32-MB NOR flash layout |