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| author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2017-04-24 11:13:30 (GMT) |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2017-09-04 07:05:23 (GMT) |
| commit | bce0688369da7425a5ea8d150b140da378ccef10 (patch) | |
| tree | 6d17a03afcf0d8da85d6fe32500ea2d9955a01a7 | |
| parent | ead5d46d818cdf29660b7939554201a49d5f5b4e (diff) | |
| download | u-boot-bce0688369da7425a5ea8d150b140da378ccef10.tar.xz | |
armv8: ls1088a: add PCIe dts node
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
| -rw-r--r-- | arch/arm/dts/fsl-ls1088a.dtsi | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index d89f00d..64b4fcf 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -89,4 +89,52 @@ interrupts = <0 81 0x4>; /* Level high type */ dr_mode = "host"; }; + + pcie@3400000 { + compatible = "fsl,ls-pcie", "snps,dw-pcie"; + reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ + 0x00 0x03480000 0x0 0x80000 /* lut registers */ + 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */ + 0x20 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x20 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; + + pcie@3500000 { + compatible = "fsl,ls-pcie", "snps,dw-pcie"; + reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */ + 0x00 0x03580000 0x0 0x80000 /* lut registers */ + 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */ + 0x28 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x28 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; + + pcie@3600000 { + compatible = "fsl,ls-pcie", "snps,dw-pcie"; + reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */ + 0x00 0x03680000 0x0 0x80000 /* lut registers */ + 0x00 0x036c0000 0x0 0x40000 /* pf controls registers */ + 0x30 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <8>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x30 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + }; }; |