diff options
| author | Heiko Stübner <heiko@sntech.de> | 2017-02-18 18:46:23 (GMT) |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2017-03-16 22:03:44 (GMT) |
| commit | bd7e6086c5a1e83975fa87f7958b52c5d23881fb (patch) | |
| tree | 2f1e09f12b63d5ad8a45bb217eac646644f44d7e | |
| parent | 6496498a626dbde4d0ed96406e4efee9ff2ab0c0 (diff) | |
| download | u-boot-bd7e6086c5a1e83975fa87f7958b52c5d23881fb.tar.xz | |
rockchip: rk3288: sdram: use constants in ddrconf table
Use defines to describe the bit shifts used to create the
table for ddrconf register values.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
| -rw-r--r-- | arch/arm/include/asm/arch-rockchip/ddr_rk3288.h | 8 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 20 |
2 files changed, 18 insertions, 10 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h index fccabcd..9a59075 100644 --- a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h @@ -425,6 +425,14 @@ enum { #define START_CMD (1u << 31) +/* + * DDRCONF + * [5:4] row(13+n) + * [1:0] col(9+n), assume bw=2 + */ +#define DDRCONF_ROW_SHIFT 4 +#define DDRCONF_COL_SHIFT 0 + /* DEVTODEV */ #define BUSWRTORD_SHIFT 4 #define BUSRDTOWR_SHIFT 2 diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c index 89fd8e6..868b96d 100644 --- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c @@ -596,16 +596,16 @@ static void dram_all_config(const struct dram_info *dram, const int ddrconf_table[] = { /* row col,bw */ 0, - ((1 << 4) | 1), - ((2 << 4) | 1), - ((3 << 4) | 1), - ((4 << 4) | 1), - ((1 << 4) | 2), - ((2 << 4) | 2), - ((3 << 4) | 2), - ((1 << 4) | 0), - ((2 << 4) | 0), - ((3 << 4) | 0), + ((1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), + ((2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), + ((3 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), + ((4 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), + ((1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT), + ((2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT), + ((3 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT), + ((1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT), + ((2 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT), + ((3 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT), 0, 0, 0, |