diff options
| author | Lokesh Vutla <lokeshvutla@ti.com> | 2013-12-12 10:06:21 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-12-12 22:43:39 (GMT) |
| commit | d2c7074b9593d822e2359a09c21747248fdf5fac (patch) | |
| tree | 830f2ae042d2bf233e0c3d0b75d0bf05542404f3 | |
| parent | 5298f21ab3781a8cb7fecd5ef559c81e7605d1f5 (diff) | |
| download | u-boot-d2c7074b9593d822e2359a09c21747248fdf5fac.tar.xz | |
ARM: OMAP5: clocks: Update MPU settings for OPP_NOM
As per the latest 0.6 version of DM for OMAP5430 ES2.0,
MPU_GCLK is given as 1000MHz. In order to achieve this DPLL_MPU
should be locked at 2000MHz. Fixing the same and cleaning the
previously used dpll values.
Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/hw_data.c | 14 |
1 files changed, 2 insertions, 12 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index a0d69a7..5268a1f 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -39,17 +39,6 @@ static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = { {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; -/* OPP NOM FREQUENCY for ES2.0, OPP HIGH for ES1.0 */ -static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = { - {275, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {550, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - /* OPP NOM FREQUENCY for ES1.0 */ static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = { {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ @@ -83,6 +72,7 @@ static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = { {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; +/* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */ static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = { {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ @@ -272,7 +262,7 @@ struct dplls omap5_dplls_es1 = { }; struct dplls omap5_dplls_es2 = { - .mpu = mpu_dpll_params_1100mhz, + .mpu = mpu_dpll_params_1ghz, .core = core_dpll_params_2128mhz_ddr532_es2, .per = per_dpll_params_768mhz_es2, .iva = iva_dpll_params_2330mhz, |