diff options
| author | Diego Dorta <diego.dorta@nxp.com> | 2016-10-11 14:09:27 (GMT) |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2016-10-17 07:18:01 (GMT) |
| commit | d96796ca23b2ebcb7ce58c250e5a44152a652a45 (patch) | |
| tree | 00a7fbb488fa682df3c6180de460b5e37d946ac8 | |
| parent | 940afa4e544bdc2365d85bca78e0dcb847002eab (diff) | |
| download | u-boot-d96796ca23b2ebcb7ce58c250e5a44152a652a45.tar.xz | |
mx6sabresd: Add Falcon mode support
Allow i.MX6Q Sabre SD to load the kernel and dtb via SPL in Falcon mode.
Based on the Falcon mode code for MX6 Gateworks Ventana board.
Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
| -rw-r--r-- | board/freescale/mx6sabresd/mx6sabresd.c | 12 | ||||
| -rw-r--r-- | include/configs/mx6sabresd.h | 12 |
2 files changed, 24 insertions, 0 deletions
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index e58c03c..2b6d7be 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -57,6 +57,8 @@ DECLARE_GLOBAL_DATA_PTR; #define DISP0_PWR_EN IMX_GPIO_NR(1, 21) +#define KEY_VOL_UP IMX_GPIO_NR(1, 4) + int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -682,6 +684,16 @@ int checkboard(void) #include <spl.h> #include <libfdt.h> +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + gpio_direction_input(KEY_VOL_UP); + + /* Only enter in Falcon mode if KEY_VOL_UP is pressed */ + return gpio_get_value(KEY_VOL_UP); +} +#endif + static void ccgr_init(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 5c2734d..6a7a0d3 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -11,6 +11,7 @@ #ifdef CONFIG_SPL #include "imx6_spl.h" +#undef CONFIG_SPL_EXT_SUPPORT #endif #define CONFIG_MACH_TYPE 3980 @@ -22,6 +23,17 @@ #include "mx6sabre_common.h" +/* Falcon Mode */ +#define CONFIG_CMD_SPL +#define CONFIG_SPL_OS_BOOT +#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 +#define CONFIG_CMD_SPL_WRITE_SIZE (128 * SZ_1K) + +/* Falcon Mode - MMC support: args@1MB kernel@2MB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ + #define CONFIG_SYS_FSL_USDHC_NUM 3 #if defined(CONFIG_ENV_IS_IN_MMC) #define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC3 */ |