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| author | Suresh Gupta <suresh.gupta@nxp.com> | 2017-08-25 09:24:18 (GMT) |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2017-08-30 10:05:10 (GMT) |
| commit | dc80131333f67c6f14aae5907f122e1a2e451d39 (patch) | |
| tree | 6de27ed62f5c222db0ca0eb5bf126a3df323c022 | |
| parent | 92874184c2f880d761b117a21aaf49acba0e96c2 (diff) | |
| download | u-boot-dc80131333f67c6f14aae5907f122e1a2e451d39.tar.xz | |
armv8: fsl-layerscape: Fix final MMU table for QSPI and IFC
For QSPI and IFC addresses execution shouldn't be allowed
when u-boot running from DDR. Revise the MMU final table
to enforce execute-never bits.
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 0126783..a0dac86 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -203,7 +203,8 @@ static struct mm_region final_map[] = { }, { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_SIZE1, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_SIZE2, @@ -212,7 +213,8 @@ static struct mm_region final_map[] = { }, { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_SIZE2, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_SIZE, |