diff options
| author | Shengzhou Liu <Shengzhou.Liu@freescale.com> | 2013-11-22 09:39:12 (GMT) |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-11-25 20:36:55 (GMT) |
| commit | f7f155e1e180e2e7743a036016ed917bba581d98 (patch) | |
| tree | ae0fab6b92ade3fd6e715946f9e7fc861654cd2b | |
| parent | c4d0e81156a4b5108057eeaa3999e2aa27b10d4c (diff) | |
| download | u-boot-f7f155e1e180e2e7743a036016ed917bba581d98.tar.xz | |
t2080qds/ramboot: enable PBL tool for t2080qds
Add the default RCW(SerDes 0x66_0x16) and PBI configure file for
T2080QDS board, so we can use PBL tool to generate the ramboot
image to support boot from NAND/SPI/SD.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
| -rw-r--r-- | board/freescale/t2080qds/t2080_pbi.cfg | 41 | ||||
| -rw-r--r-- | board/freescale/t2080qds/t2080_rcw.cfg | 8 | ||||
| -rw-r--r-- | boards.cfg | 4 | ||||
| -rw-r--r-- | include/configs/T2080QDS.h | 2 |
4 files changed, 55 insertions, 0 deletions
diff --git a/board/freescale/t2080qds/t2080_pbi.cfg b/board/freescale/t2080qds/t2080_pbi.cfg new file mode 100644 index 0000000..e200d92 --- /dev/null +++ b/board/freescale/t2080qds/t2080_pbi.cfg @@ -0,0 +1,41 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Refer doc/README.pblimage for more details about how-to configure +# and create PBL boot image +# + +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#512KB SRAM +09010100 00000000 +09010104 fff80009 +09010f00 08000000 +#enable CPC1 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff80000 +09000d08 81000012 +#Initialize eSPI controller, default configuration is slow for eSPI to +#load data, this configuration comes from u-boot eSPI driver. +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Errata for slowing down the MDC clock to make it <= 2.5 MHZ +094fc030 00008148 +094fd030 00008148 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Flush PBL data +09138000 00000000 +091380c0 00000000 diff --git a/board/freescale/t2080qds/t2080_rcw.cfg b/board/freescale/t2080qds/t2080_rcw.cfg new file mode 100644 index 0000000..c2ad0fd --- /dev/null +++ b/board/freescale/t2080qds/t2080_rcw.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +#SerDes Protocol: 0x66_0x16 +#Core/DDR: 1533Mhz/2133MT/s +12100017 15000000 00000000 00000000 +66160002 00008400 e8104000 c1000000 +00000000 00000000 00000000 000307fc +00000000 00000000 00000000 00000004 @@ -966,6 +966,10 @@ Active powerpc mpc85xx - freescale t1040qds Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com> Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal <poonam.aggrwal@freescale.com> Active powerpc mpc85xx - freescale t2080qds T2080QDS T2080QDS:PPC_T2080 +Active powerpc mpc85xx - freescale t2080qds T2080QDS_SDCARD T2080QDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 +Active powerpc mpc85xx - freescale t2080qds T2080QDS_SPIFLASH T2080QDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 +Active powerpc mpc85xx - freescale t2080qds T2080QDS_NAND T2080QDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 +Active powerpc mpc85xx - freescale t2080qds T2080QDS_SRIO_PCIE_BOOT T2080QDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach <eibach@gdsys.de> Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach <eibach@gdsys.de> Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach <eibach@gdsys.de> diff --git a/include/configs/T2080QDS.h b/include/configs/T2080QDS.h index f85ccf5..ad09816 100644 --- a/include/configs/T2080QDS.h +++ b/include/configs/T2080QDS.h @@ -45,6 +45,8 @@ #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t2080qds/t2080_pbi.cfg +#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t2080qds/t2080_rcw.cfg #endif #define CONFIG_SRIO_PCIE_BOOT_MASTER |