diff options
| author | Tom Rini <trini@ti.com> | 2014-10-27 15:03:00 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-10-27 15:03:00 (GMT) |
| commit | 0cf876154922118d8fb1b4c30f527c95a113bef3 (patch) | |
| tree | 83eb6a7966a1949526e1e6066470952162f51c1d | |
| parent | 0ce4af99c07acebf4fce9a91f1099d2460629293 (diff) | |
| parent | f06f9a1fb1cd332435b9e8660355f57d7d3f98d8 (diff) | |
| download | u-boot-0cf876154922118d8fb1b4c30f527c95a113bef3.tar.xz | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxx
205 files changed, 44 insertions, 62636 deletions
diff --git a/arch/powerpc/cpu/74xx_7xx/Kconfig b/arch/powerpc/cpu/74xx_7xx/Kconfig index 3378c91..b2f1a59 100644 --- a/arch/powerpc/cpu/74xx_7xx/Kconfig +++ b/arch/powerpc/cpu/74xx_7xx/Kconfig @@ -19,30 +19,14 @@ config TARGET_PPMC7XX config TARGET_ELPPC bool "Support ELPPC" -config TARGET_CPCI750 - bool "Support CPCI750" - config TARGET_MPC7448HPC2 bool "Support mpc7448hpc2" -config TARGET_DB64360 - bool "Support DB64360" - -config TARGET_DB64460 - bool "Support DB64460" - -config TARGET_P3MX - bool "Support p3mx" - endchoice -source "board/Marvell/db64360/Kconfig" -source "board/Marvell/db64460/Kconfig" source "board/eltec/elppc/Kconfig" -source "board/esd/cpci750/Kconfig" source "board/evb64260/Kconfig" source "board/freescale/mpc7448hpc2/Kconfig" source "board/ppmc7xx/Kconfig" -source "board/prodrive/p3mx/Kconfig" endmenu diff --git a/arch/powerpc/cpu/74xx_7xx/start.S b/arch/powerpc/cpu/74xx_7xx/start.S index b0e102c..8393781 100644 --- a/arch/powerpc/cpu/74xx_7xx/start.S +++ b/arch/powerpc/cpu/74xx_7xx/start.S @@ -28,13 +28,6 @@ #include <asm/mmu.h> #include <asm/u-boot.h> -#if !defined(CONFIG_DB64360) && \ - !defined(CONFIG_DB64460) && \ - !defined(CONFIG_CPCI750) && \ - !defined(CONFIG_P3Mx) -#include <galileo/gt64260R.h> -#endif - /* We don't want the MMU yet. */ #undef MSR_KERNEL @@ -712,11 +705,7 @@ in_ram: bne 5b 6: mr r3, r10 /* Destination Address */ -#if defined(CONFIG_DB64360) || \ - defined(CONFIG_DB64460) || \ - defined(CONFIG_CPCI750) || \ - defined(CONFIG_PPMC7XX) || \ - defined(CONFIG_P3Mx) +#if defined(CONFIG_PPMC7XX) mr r4, r9 /* Use RAM copy of the global data */ #endif bl after_reloc diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig index 41e4e5f..2541400 100644 --- a/arch/powerpc/cpu/mpc8260/Kconfig +++ b/arch/powerpc/cpu/mpc8260/Kconfig @@ -28,9 +28,6 @@ config TARGET_EP82XXM config TARGET_GW8260 bool "Support gw8260" -config TARGET_HYMOD - bool "Support hymod" - config TARGET_IPHASE4539 bool "Support IPHASE4539" @@ -55,18 +52,9 @@ config TARGET_MPC8266ADS config TARGET_VOVPN_GW bool "Support VoVPN-GW" -config TARGET_IDS8247 - bool "Support IDS8247" - config TARGET_KM82XX bool "Support km82xx" -config TARGET_TQM8260 - bool "Support TQM8260" - -config TARGET_TQM8272 - bool "Support TQM8272" - endchoice source "board/atc/Kconfig" @@ -78,8 +66,6 @@ source "board/ep82xxm/Kconfig" source "board/freescale/mpc8266ads/Kconfig" source "board/funkwerk/vovpn-gw/Kconfig" source "board/gw8260/Kconfig" -source "board/hymod/Kconfig" -source "board/ids/ids8247/Kconfig" source "board/iphase4539/Kconfig" source "board/keymile/km82xx/Kconfig" source "board/muas3001/Kconfig" @@ -87,7 +73,5 @@ source "board/pm826/Kconfig" source "board/pm828/Kconfig" source "board/ppmc8260/Kconfig" source "board/sacsng/Kconfig" -source "board/tqc/tqm8260/Kconfig" -source "board/tqc/tqm8272/Kconfig" endmenu diff --git a/arch/powerpc/cpu/mpc8260/ether_fcc.c b/arch/powerpc/cpu/mpc8260/ether_fcc.c index d93a991..f9f15b5 100644 --- a/arch/powerpc/cpu/mpc8260/ether_fcc.c +++ b/arch/powerpc/cpu/mpc8260/ether_fcc.c @@ -645,32 +645,7 @@ eth_loopback_test (void) /* 28.9 - (1-2): ioports have been set up already */ -#if defined(CONFIG_HYMOD) - /* - * Attention: this is board-specific - * 0, FCC1 - * 1, FCC2 - * 2, FCC3 - */ -# define FCC_START_LOOP 0 -# define FCC_END_LOOP 2 - - /* - * Attention: this is board-specific - * - FCC1 Rx-CLK is CLK10 - * - FCC1 Tx-CLK is CLK11 - * - FCC2 Rx-CLK is CLK13 - * - FCC2 Tx-CLK is CLK14 - * - FCC3 Rx-CLK is CLK15 - * - FCC3 Tx-CLK is CLK16 - */ - - /* 28.9 - (3): connect FCC's tx and rx clocks */ - immr->im_cpmux.cmx_uar = 0; - immr->im_cpmux.cmx_fcr = CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11|\ - CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14|\ - CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16; -#elif defined(CONFIG_SACSng) +#if defined(CONFIG_SACSng) /* * Attention: this is board-specific * 1, FCC2 diff --git a/arch/powerpc/cpu/mpc8260/interrupts.c b/arch/powerpc/cpu/mpc8260/interrupts.c index 30125a7..41d2c04 100644 --- a/arch/powerpc/cpu/mpc8260/interrupts.c +++ b/arch/powerpc/cpu/mpc8260/interrupts.c @@ -142,15 +142,7 @@ int interrupt_init_cpu (unsigned *decrementer_count) immr->im_intctl.ic_sipnrh = 0xffffffff; immr->im_intctl.ic_sipnrl = 0xffffffff; -#ifdef CONFIG_HYMOD - /* - * ensure all external interrupt sources default to trigger on - * high-to-low transition (i.e. edge triggered active low) - */ - immr->im_intctl.ic_siexr = -1; -#endif - - return (0); + return 0; } /****************************************************************************/ diff --git a/arch/powerpc/cpu/mpc8260/pci.c b/arch/powerpc/cpu/mpc8260/pci.c index 0a47fdc..f7bb05d 100644 --- a/arch/powerpc/cpu/mpc8260/pci.c +++ b/arch/powerpc/cpu/mpc8260/pci.c @@ -262,8 +262,6 @@ void pci_mpc8250_init (struct pci_controller *hose) | SIUMCR_CS10PC00 | SIUMCR_BCTLC00 | SIUMCR_MMR11; -#elif defined(CONFIG_TQM8272) -/* nothing to do for this Board here */ #else /* * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]), diff --git a/arch/powerpc/cpu/mpc8260/start.S b/arch/powerpc/cpu/mpc8260/start.S index d7eaf13..5f1e174 100644 --- a/arch/powerpc/cpu/mpc8260/start.S +++ b/arch/powerpc/cpu/mpc8260/start.S @@ -48,9 +48,6 @@ GOT_ENTRY(__init_end) GOT_ENTRY(__bss_end) GOT_ENTRY(__bss_start) -#if defined(CONFIG_HYMOD) - GOT_ENTRY(environment) -#endif END_GOT /* @@ -878,18 +875,7 @@ clear_bss: * Now clear BSS segment */ lwz r3,GOT(__bss_start) -#if defined(CONFIG_HYMOD) - /* - * For HYMOD - the environment is the very last item in flash. - * The real .bss stops just before environment starts, so only - * clear up to that point. - * - * taken from mods for FADS board - */ - lwz r4,GOT(environment) -#else lwz r4,GOT(__bss_end) -#endif cmplw 0, r3, r4 beq 6f diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index 36724e5..af75c63 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -958,18 +958,7 @@ clear_bss: * Now clear BSS segment */ lwz r3,GOT(__bss_start) -#if defined(CONFIG_HYMOD) - /* - * For HYMOD - the environment is the very last item in flash. - * The real .bss stops just before environment starts, so only - * clear up to that point. - * - * taken from mods for FADS board - */ - lwz r4,GOT(environment) -#else lwz r4,GOT(__bss_end) -#endif cmplw 0, r3, r4 beq 6f diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 8c1c01c..c0bb67b 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -13,9 +13,6 @@ config TARGET_SBC8548 config TARGET_SOCRATES bool "Support socrates" -config TARGET_HWW1U1A - bool "Support HWW1U1A" - config TARGET_B4860QDS bool "Support B4860QDS" @@ -144,7 +141,6 @@ config TARGET_XPEDITE550X endchoice -source "board/exmeritus/hww1u1a/Kconfig" source "board/freescale/b4860qds/Kconfig" source "board/freescale/bsc9131rdb/Kconfig" source "board/freescale/bsc9132qds/Kconfig" diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig index f1dca90..4c150a8 100644 --- a/arch/powerpc/cpu/mpc8xx/Kconfig +++ b/arch/powerpc/cpu/mpc8xx/Kconfig @@ -16,9 +16,6 @@ config TARGET_ESTEEM192E config TARGET_HERMES bool "Support hermes" -config TARGET_ICU862 - bool "Support ICU862" - config TARGET_IP860 bool "Support IP860" @@ -43,9 +40,6 @@ config TARGET_RRVISION config TARGET_SPD823TS bool "Support SPD823TS" -config TARGET_MHPC - bool "Support MHPC" - config TARGET_TOP860 bool "Support TOP860" @@ -120,11 +114,9 @@ endchoice source "board/LEOX/elpt860/Kconfig" source "board/RRvision/Kconfig" source "board/cogent/Kconfig" -source "board/eltec/mhpc/Kconfig" source "board/emk/top860/Kconfig" source "board/esteem192e/Kconfig" source "board/hermes/Kconfig" -source "board/icu862/Kconfig" source "board/ip860/Kconfig" source "board/ivm/Kconfig" source "board/kup/kup4k/Kconfig" diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index 90c7e61..60c401e 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -126,12 +126,10 @@ void cpu_init_f (volatile immap_t * immr) */ #if defined(CONFIG_HERMES) || \ - defined(CONFIG_ICU862) || \ defined(CONFIG_IP860) || \ defined(CONFIG_IVML24) || \ defined(CONFIG_IVMS8) || \ defined(CONFIG_LWMON) || \ - defined(CONFIG_MHPC) || \ defined(CONFIG_R360MPI) || \ defined(CONFIG_RMU) || \ defined(CONFIG_SPD823TS) diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c index d12b3df..22b8ec7 100644 --- a/arch/powerpc/cpu/mpc8xx/fec.c +++ b/arch/powerpc/cpu/mpc8xx/fec.c @@ -205,11 +205,7 @@ static int fec_send(struct eth_device *dev, void *packet, int length) j = 0; while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) { -#if defined(CONFIG_ICU862) - udelay(10); -#else udelay(1); -#endif j++; } if (j>=TOUT_LOOP) { @@ -424,7 +420,7 @@ static void fec_pin_init(int fecidx) #endif /* !CONFIG_RMII */ -#elif !defined(CONFIG_ICU862) +#else /* * Configure all of port D for MII. */ @@ -437,42 +433,8 @@ static void fec_pin_init(int fecidx) immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */ else immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */ -#else - /* - * Configure port A for MII. - */ - -#if defined(CONFIG_ICU862) && defined(CONFIG_SYS_DISCOVER_PHY) - - /* - * On the ICU862 board the MII-MDC pin is routed to PD8 pin - * * of CPU, so for this board we need to configure Utopia and - * * enable PD8 to MII-MDC function - */ - immr->im_ioport.iop_pdpar |= 0x4080; #endif - /* - * Has Utopia been configured? - */ - if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) { - /* - * YES - Use MUXED mode for UTOPIA bus. - * This frees Port A for use by MII (see 862UM table 41-6). - */ - immr->im_ioport.utmode &= ~0x80; - } else { - /* - * NO - set SPLIT mode for UTOPIA bus. - * - * This doesn't really effect UTOPIA (which isn't - * enabled anyway) but just tells the 862 - * to use port A for MII (see 862UM table 41-6). - */ - immr->im_ioport.utmode |= 0x80; - } -#endif /* !defined(CONFIG_ICU862) */ - #endif /* CONFIG_ETHER_ON_FEC1 */ } else if (fecidx == 1) { diff --git a/arch/powerpc/include/asm/immap_512x.h b/arch/powerpc/include/asm/immap_512x.h index 6086a73..bed80aa 100644 --- a/arch/powerpc/include/asm/immap_512x.h +++ b/arch/powerpc/include/asm/immap_512x.h @@ -59,6 +59,7 @@ typedef struct sysconf512x { u8 res2[0x28]; law512x_t ddrlaw; /* DDR Local Access Window */ u8 res3[0x18]; + u32 mbxbar; /* MBX Base Address */ u32 srambar; /* SRAM Base Address */ u32 nfcbar; /* NFC Base Address */ u8 res4[0x34]; diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h index e1b566f..a61e998 100644 --- a/arch/powerpc/include/asm/u-boot.h +++ b/arch/powerpc/include/asm/u-boot.h @@ -77,9 +77,6 @@ typedef struct bd_info { unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ #endif -#if defined(CONFIG_HYMOD) - hymod_conf_t bi_hymod_conf; /* hymod configuration information */ -#endif #ifdef CONFIG_HAS_ETH1 unsigned char bi_enet1addr[6]; /* OLD: see README.enetaddr */ diff --git a/board/Marvell/common/flash.c b/board/Marvell/common/flash.c deleted file mode 100644 index 32f226d..0000000 --- a/board/Marvell/common/flash.c +++ /dev/null @@ -1,1056 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * flash.c - flash support for the 512k, 8bit boot flash - and the 8MB 32bit extra flash on the DB64360 - * most of this file was based on the existing U-Boot - * flash drivers. - * - * written or collected and sometimes rewritten by - * Ingo Assmus <ingo.assmus@keymile.com> - * - */ - -#include <common.h> -#include <mpc8xx.h> -#include "../include/mv_gen_reg.h" -#include "../include/memory.h" -#include "intel_flash.h" - -#define FLASH_ROM 0xFFFD /* unknown flash type */ -#define FLASH_RAM 0xFFFE /* unknown flash type */ -#define FLASH_MAN_UNKNOWN 0xFFFF0000 - -/* #define DEBUG */ - -/* Intel flash commands */ -int flash_erase_intel (flash_info_t * info, int s_first, int s_last); -int write_word_intel (bank_addr_t addr, bank_word_t value); - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (int portwidth, vu_long * addr, - flash_info_t * info); -static int write_word (flash_info_t * info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned int i; - unsigned long size_b0 = 0, size_b1 = 0; - unsigned long base, flash_size; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* the boot flash */ - base = CONFIG_SYS_FLASH_BASE; - size_b0 = - flash_get_size (CONFIG_SYS_BOOT_FLASH_WIDTH, (vu_long *) base, - &flash_info[0]); - - printf ("[%ldkB@%lx] ", size_b0 / 1024, base); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n", base, size_b0, size_b0 << 20); - } - - base = memoryGetDeviceBaseAddress (CONFIG_SYS_EXTRA_FLASH_DEVICE); -/* base = memoryGetDeviceBaseAddress(DEV_CS3_BASE_ADDR);*/ - for (i = 1; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - unsigned long size = - flash_get_size (CONFIG_SYS_EXTRA_FLASH_WIDTH, - (vu_long *) base, &flash_info[i]); - - printf ("[%ldMB@%lx] ", size >> 20, base); - - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - if (i == 1) { - printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n", base, size_b1, size_b1 << 20); - } - break; - } - size_b1 += size; - base += size; - } - - flash_size = size_b0 + size_b1; - return flash_size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - int sector_size; - - if (!info->sector_count) - return; - - /* set up sector start address table */ - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - case FLASH_28F128J3A: - case FLASH_28F640J3A: - case FLASH_RAM: - /* this chip has uniformly spaced sectors */ - sector_size = info->size / info->sector_count; - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * sector_size); - break; - default: - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_STM: - printf ("STM "); - break; - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf ("AM29LV040B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400B: - printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_28F640J3A: - printf ("28F640J3A (64 Mbit)\n"); - break; - case FLASH_28F128J3A: - printf ("28F128J3A (128 Mbit)\n"); - break; - case FLASH_ROM: - printf ("ROM\n"); - break; - case FLASH_RAM: - printf ("RAM\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - if ((info->size >> 20) > 0) { - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - } else { - printf (" Size: %ld kB in %d Sectors\n", - info->size >> 10, info->sector_count); - } - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static inline void flash_cmd (int width, volatile unsigned char *addr, - int offset, unsigned char cmd) -{ - /* supports 1x8, 1x16, and 2x16 */ - /* 2x8 and 4x8 are not supported */ - if (width == 4) { - /* assuming chips are in 16 bit mode */ - /* 2x16 */ - unsigned long cmd32 = (cmd << 16) | cmd; - - *(volatile unsigned long *) (addr + offset * 2) = cmd32; - } else { - /* 1x16 or 1x8 */ - *(volatile unsigned char *) (addr + offset) = cmd; - } -} - -static ulong -flash_get_size (int portwidth, vu_long * addr, flash_info_t * info) -{ - short i; - volatile unsigned char *caddr = (unsigned char *) addr; - volatile unsigned short *saddr = (unsigned short *) addr; - volatile unsigned long *laddr = (unsigned long *) addr; - char old[2], save; - ulong id = 0, manu = 0, base = (ulong) addr; - -#ifdef DEBUG - printf ("%s: enter\n", __FUNCTION__); -#endif - info->portwidth = portwidth; - - save = *caddr; - - flash_cmd (portwidth, caddr, 0, 0xf0); - flash_cmd (portwidth, caddr, 0, 0xf0); - - udelay (10); - - old[0] = caddr[0]; - old[1] = caddr[1]; - - - if (old[0] != 0xf0) { - flash_cmd (portwidth, caddr, 0, 0xf0); - flash_cmd (portwidth, caddr, 0, 0xf0); - - udelay (10); - - if (*caddr == 0xf0) { - /* this area is ROM */ - *caddr = save; - info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN; - info->sector_count = 8; - info->size = 0x80000; - flash_get_offsets (base, info); - return info->size; - } - } else { - *caddr = 0; - - udelay (10); - - if (*caddr == 0) { - /* this area is RAM */ - *caddr = save; - info->flash_id = FLASH_RAM + FLASH_MAN_UNKNOWN; - info->sector_count = 8; - info->size = 0x80000; - flash_get_offsets (base, info); - return info->size; - } - flash_cmd (portwidth, caddr, 0, 0xf0); - - udelay (10); - } - - /* Write auto select command: read Manufacturer ID */ - flash_cmd (portwidth, caddr, 0x555, 0xAA); - flash_cmd (portwidth, caddr, 0x2AA, 0x55); - flash_cmd (portwidth, caddr, 0x555, 0x90); - - udelay (10); - - if ((caddr[0] == old[0]) && (caddr[1] == old[1])) { - - /* this area is ROM */ - info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN; - info->sector_count = 8; - info->size = 0x80000; - flash_get_offsets (base, info); - return info->size; -#ifdef DEBUG - } else { - printf ("%px%d: %02x:%02x -> %02x:%02x\n", - caddr, portwidth, old[0], old[1], caddr[0], caddr[1]); -#endif - } - - switch (portwidth) { - case 1: - manu = caddr[0]; - manu |= manu << 16; - id = caddr[1]; - break; - case 2: - manu = saddr[0]; - manu |= manu << 16; - id = saddr[1]; - id |= id << 16; - break; - case 4: - manu = laddr[0]; - id = laddr[1]; - break; - } - -#ifdef DEBUG - flash_cmd (portwidth, caddr, 0, 0xf0); - - printf ("\n%08lx:%08lx:%08lx\n", base, manu, id); - printf ("%08lx %08lx %08lx %08lx\n", - laddr[0], laddr[1], laddr[2], laddr[3]); -#endif - - switch (manu) { - case STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - flash_cmd (portwidth, caddr, 0, 0xf0); - - printf ("Unknown Mfr [%08lx]:%08lx\n", manu, id); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - switch (id) { - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - info->chipwidth = 1; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - info->chipwidth = 1; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - info->chipwidth = 1; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - info->chipwidth = 1; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - info->chipwidth = 1; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - info->chipwidth = 1; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - case AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x80000; - info->chipwidth = 1; - break; /* => 512 kB */ - - case INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 128 * 1024 * 64; /* 128kbytes x 64 blocks */ - info->chipwidth = 2; - if (portwidth == 4) - info->size *= 2; /* 2x16 */ - break; - - case INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 128 * 1024 * 128; /* 128kbytes x 128 blocks */ - info->chipwidth = 2; - if (portwidth == 4) - info->size *= 2; /* 2x16 */ - break; - - default: - flash_cmd (portwidth, caddr, 0, 0xf0); - - printf ("Unknown id %lx:[%lx]\n", manu, id); - info->flash_id = FLASH_UNKNOWN; - info->chipwidth = 1; - return (0); /* => no or unknown flash */ - - } - - flash_get_offsets (base, info); - - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0)=0x02 */ - /* D0 = 1 if protected */ - caddr = (volatile unsigned char *) (info->start[i]); - saddr = (volatile unsigned short *) (info->start[i]); - laddr = (volatile unsigned long *) (info->start[i]); - if (portwidth == 1) - info->protect[i] = caddr[2] & 1; - else if (portwidth == 2) - info->protect[i] = saddr[2] & 1; - else - info->protect[i] = laddr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - caddr = (volatile unsigned char *) info->start[0]; - - flash_cmd (portwidth, caddr, 0, 0xF0); /* reset bank */ - } - - return (info->size); -} - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - volatile unsigned char *addr = (uchar *) (info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - -/* modified to support 2x16 Intel flash */ -/* Note that the code will not exit on a flash erasure error or timeout */ -/* but will print and error message and continue processing sectors */ -/* until they are all erased. */ -/* 10-16-2002 P. Marchese */ - ulong mask; - int timeout; - - if (info->portwidth == 4) -/* { - printf ("- Warning: erasing of 32Bit (2*16Bit i.e. 2*28F640J3A) not supported yet !!!! \n"); - return 1; - }*/ - { - /* make sure it's Intel flash */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - /* yup! it's an Intel flash */ - /* is it 16-bits wide? */ - if (info->chipwidth == 2) { - /* yup! it's 16-bits wide */ - /* are there any sectors to process? */ - if ((s_first < 0) || (s_first > s_last)) { - printf ("Error: There are no sectors to erase\n"); - printf ("Either sector %d is less than zero\n", s_first); - printf ("or sector %d is greater than sector %d\n", s_first, s_last); - return 1; - } - /* check for protected sectors */ - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) - if (info->protect[sect]) - prot++; - /* if variable "prot" is nonzero, there are protected sectors */ - if (prot) - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - /* reset the flash */ - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_RST); - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - /* Clear the status register */ - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_CLR_STAT); - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_RST); - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - /* is the sector unprotected? */ - if (info->protect[sect] == 0) { /* not protected */ - /* issue the single block erase command, 0x20 */ - flash_cmd (info->portwidth, - (volatile unsigned - char *) info-> - start[sect], 0, - CHIP_CMD_ERASE1); - /* issue the erase confirm command, 0xD0 */ - flash_cmd (info->portwidth, - (volatile unsigned - char *) info-> - start[sect], 0, - CHIP_CMD_ERASE2); - l_sect = sect; - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - /* poll for erasure completion */ - /* put flash into read status mode by writing 0x70 to it */ - flash_cmd (info->portwidth, - addr, 0, - CHIP_CMD_RD_STAT); - /* setup the status register mask */ - mask = CHIP_STAT_RDY | - (CHIP_STAT_RDY << 16); - /* init. the timeout counter */ - start = get_timer (0); - /* keep looping while the flash is not ready */ - /* exit the loop by timing out or the flash */ - /* becomes ready again */ - timeout = 0; - while ((* - (volatile unsigned - long *) info-> - start[sect] & mask) != - mask) { - /* has the timeout limit been reached? */ - if (get_timer (start) - > - CONFIG_SYS_FLASH_ERASE_TOUT) - { - /* timeout limit reached */ - printf ("Time out limit reached erasing sector at address %08lx\n", info->start[sect]); - printf ("Continuing with next sector\n"); - timeout = 1; - goto timed_out_error; - } - /* put flash into read status mode by writing 0x70 to it */ - flash_cmd (info-> - portwidth, - addr, 0, - CHIP_CMD_RD_STAT); - } - /* did we timeout? */ - timed_out_error:if (timeout == 0) - { - /* didn't timeout, so check the status register */ - /* create the status mask to check for errors */ - mask = CHIP_STAT_ECLBS; - mask = mask | (mask << - 16); - /* put flash into read status mode by writing 0x70 to it */ - flash_cmd (info-> - portwidth, - addr, 0, - CHIP_CMD_RD_STAT); - /* are there any errors? */ - if ((* - (volatile - unsigned long *) - info-> - start[sect] & - mask) != 0) { - /* We got an erasure error */ - printf ("Flash erasure error at address 0x%08lx\n", info->start[sect]); - printf ("Continuing with next sector\n"); - /* reset the flash */ - flash_cmd - (info-> - portwidth, - addr, - 0, - CHIP_CMD_RST); - } - } - /* erasure completed without errors */ - /* reset the flash */ - flash_cmd (info->portwidth, - addr, 0, - CHIP_CMD_RST); - } /* end if not protected */ - } /* end for loop */ - printf ("Flash erasure done\n"); - return 0; - } else { - /* The Intel flash is not 16-bit wide */ - /* print and error message and return */ - /* NOTE: you can add routines here to handle other size flash */ - printf ("Error: Intel flash device is only %d-bits wide\n", info->chipwidth * 8); - printf ("The erasure code only handles Intel 16-bit wide flash memory\n"); - return 1; - } - } else { - /* Not Intel flash so return an error as a write timeout */ - /* NOTE: if it's another type flash, stick its routine here */ - printf ("Error: The flash device is not Intel type\n"); - printf ("The erasure code only supports Intel flash in a 32-bit port width\n"); - return 1; - } - } - - /* end 32-bit wide flash code */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) - return 1; /* Rom can not be erased */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) { /* RAM just copy 0s to RAM */ - for (sect = s_first; sect <= s_last; sect++) { - int sector_size = info->size / info->sector_count; - - addr = (uchar *) (info->start[sect]); - memset ((void *) addr, 0, sector_size); - } - return 0; - } - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { /* Intel works spezial */ - return flash_erase_intel (info, - (unsigned short) s_first, - (unsigned short) s_last); - } -#if 0 - if ((info->flash_id == FLASH_UNKNOWN) || /* Flash is unknown to PPCBoot */ - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } -#endif - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - flash_cmd (info->portwidth, addr, 0x555, 0xAA); /* start erase routine */ - flash_cmd (info->portwidth, addr, 0x2AA, 0x55); - flash_cmd (info->portwidth, addr, 0x555, 0x80); - flash_cmd (info->portwidth, addr, 0x555, 0xAA); - flash_cmd (info->portwidth, addr, 0x2AA, 0x55); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (uchar *) (info->start[sect]); - flash_cmd (info->portwidth, addr, 0, 0x30); - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (volatile unsigned char *) (info->start[l_sect]); - /* broken for 2x16: TODO */ - while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (volatile unsigned char *) info->start[0]; - flash_cmd (info->portwidth, addr, 0, 0xf0); - flash_cmd (info->portwidth, addr, 0, 0xf0); - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -/* broken for 2x16: TODO */ -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - -/* Commented out since the below code should work for 32-bit(2x 16 flash) */ -/* 10-16-2002 P. Marchese */ -/* if(info->portwidth==4) return 1; */ -/* if(info->portwidth==4) { - printf ("- Warning: writting of 32Bit (2*16Bit i.e. 2*28F640J3A) not supported yet !!!! \n"); - return 1; - }*/ - - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) - return 0; - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) { - memcpy ((void *) addr, src, cnt); - return 0; - } - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -/* broken for 2x16: TODO */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile unsigned char *addr = (uchar *) (info->start[0]); - ulong start; - int flag, i; - ulong mask; - -/* modified so that it handles 32-bit(2x16 Intel flash programming */ -/* 10-16-2002 P. Marchese */ - - if (info->portwidth == 4) -/* { - printf ("- Warning: writting of 32Bit (2*16Bit i.e. 2*28F640J3A) not supported yet !!!! \n"); - return 1; - }*/ - { - /* make sure it's Intel flash */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - /* yup! it's an Intel flash */ - /* is it 16-bits wide? */ - if (info->chipwidth == 2) { - /* yup! it's 16-bits wide */ - /* so we know how to program it */ - /* reset the flash */ - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_RST); - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - /* Clear the status register */ - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_CLR_STAT); - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_RST); - /* 1st cycle of word/byte program */ - /* write 0x40 to the location to program */ - flash_cmd (info->portwidth, (uchar *) dest, 0, - CHIP_CMD_PROG); - /* 2nd cycle of word/byte program */ - /* write the data to the destination address */ - *(ulong *) dest = data; - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - /* setup the status register mask */ - mask = CHIP_STAT_RDY | (CHIP_STAT_RDY << 16); - /* put flash into read status mode by writing 0x70 to it */ - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_RD_STAT); - /* init. the timeout counter */ - start = get_timer (0); - /* keep looping while the flash is not ready */ - /* exit the loop by timing out or the flash */ - /* becomes ready again */ -/* 11-13-2002 Paul Marchese */ -/* modified while loop conditional statement */ -/* because we were always timing out. */ -/* there is a type mismatch, "addr[0]" */ -/* returns a byte but "mask" is a 32-bit value */ - while ((*(volatile unsigned long *) info-> - start[0] & mask) != mask) -/* original code */ -/* while (addr[0] & mask) != mask) */ - { - /* has the timeout limit been reached? */ - if (get_timer (start) > - CONFIG_SYS_FLASH_WRITE_TOUT) { - /* timeout limit reached */ - printf ("Time out limit reached programming address %08lx with data %08lx\n", dest, data); - /* reset the flash */ - flash_cmd (info->portwidth, - addr, 0, - CHIP_CMD_RST); - return (1); - } - /* put flash into read status mode by writing 0x70 to it */ - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_RD_STAT); - } - /* flash is ready, so check the status */ - /* create the status mask to check for errors */ - mask = CHIP_STAT_DPS | CHIP_STAT_VPPS | - CHIP_STAT_PSLBS; - mask = mask | (mask << 16); - /* put flash into read status mode by writing 0x70 to it */ - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_RD_STAT); - /* are there any errors? */ - if ((addr[0] & mask) != 0) { - /* We got a one of the following errors: */ - /* Voltage range, Device protect, or programming */ - /* return the error as a device timeout */ - /* put flash into read status mode by writing 0x70 to it */ - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_RD_STAT); - printf ("Flash programming error at address 0x%08lx\n", dest); - printf ("Flash status register contains 0x%08lx\n", (unsigned long) addr[0]); - /* reset the flash */ - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_RST); - return 1; - } - /* write completed without errors */ - /* reset the flash */ - flash_cmd (info->portwidth, addr, 0, - CHIP_CMD_RST); - return 0; - } else { - /* it's not 16-bits wide, so return an error as a write timeout */ - /* NOTE: you can add routines here to handle other size flash */ - printf ("Error: Intel flash device is only %d-bits wide\n", info->chipwidth * 8); - printf ("The write code only handles Intel 16-bit wide flash memory\n"); - return 1; - } - } else { - /* not Intel flash so return an error as a write timeout */ - /* NOTE: if it's another type flash, stick its routine here */ - printf ("Error: The flash device is not Intel type\n"); - printf ("The code only supports Intel flash in a 32-bit port width\n"); - return 1; - } - } - - /* end of 32-bit flash code */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) - return 1; - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) { - *(unsigned long *) dest = data; - return 0; - } - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - unsigned short low = data & 0xffff; - unsigned short hi = (data >> 16) & 0xffff; - int ret = write_word_intel ((bank_addr_t) dest, hi); - - if (!ret) - ret = write_word_intel ((bank_addr_t) (dest + 2), - low); - - return ret; - } - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *) dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* first, perform an unlock bypass command to speed up flash writes */ - addr[0x555] = 0xAA; - addr[0x2AA] = 0x55; - addr[0x555] = 0x20; - - /* write each byte out */ - for (i = 0; i < 4; i++) { - char *data_ch = (char *) &data; - - addr[0] = 0xA0; - *(((char *) dest) + i) = data_ch[i]; - udelay (10); /* XXX */ - } - - /* we're done, now do an unlock bypass reset */ - addr[0] = 0x90; - addr[0] = 0x00; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *) dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} diff --git a/board/Marvell/common/i2c.c b/board/Marvell/common/i2c.c deleted file mode 100644 index abdde86..0000000 --- a/board/Marvell/common/i2c.c +++ /dev/null @@ -1,521 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Hacked for the DB64360 board by Ingo.Assmus@keymile.com - * extra improvments by Brain Waite - */ -#include <common.h> -#include <mpc8xx.h> -#include <malloc.h> -#include <i2c.h> -#include "../include/mv_gen_reg.h" -#include "../include/core.h" - -#define MAX_I2C_RETRYS 10 -#define I2C_DELAY 1000 /* Should be at least the # of MHz of Tclk */ -#undef DEBUG_I2C -/*#define DEBUG_I2C*/ - -#ifdef DEBUG_I2C -#define DP(x) x -#else -#define DP(x) -#endif - -/* Assuming that there is only one master on the bus (us) */ - -void i2c_init (int speed, int slaveaddr) -{ - unsigned int n, m, freq, margin, power; - unsigned int actualN = 0, actualM = 0; - unsigned int control, status; - unsigned int minMargin = 0xffffffff; - unsigned int tclk = CONFIG_SYS_TCLK; - unsigned int i2cFreq = speed; /* 100000 max. Fast mode not supported */ - - DP (puts ("i2c_init\n")); -/* gtI2cMasterInit */ - for (n = 0; n < 8; n++) { - for (m = 0; m < 16; m++) { - power = 2 << n; /* power = 2^(n+1) */ - freq = tclk / (10 * (m + 1) * power); - if (i2cFreq > freq) - margin = i2cFreq - freq; - else - margin = freq - i2cFreq; - if (margin < minMargin) { - minMargin = margin; - actualN = n; - actualM = m; - } - } - } - - DP (puts ("setup i2c bus\n")); - - /* Setup bus */ -/* gtI2cReset */ - GT_REG_WRITE (I2C_SOFT_RESET, 0); - - DP (puts ("udelay...\n")); - - udelay (I2C_DELAY); - - DP (puts ("set baudrate\n")); - - GT_REG_WRITE (I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN); - GT_REG_WRITE (I2C_CONTROL, (0x1 << 2) | (0x1 << 6)); - - udelay (I2C_DELAY * 10); - - DP (puts ("read control, baudrate\n")); - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - GT_REG_READ (I2C_CONTROL, &control); -} - -static uchar i2c_start (void) -{ /* DB64360 checked -> ok */ - unsigned int control, status; - int count = 0; - - DP (puts ("i2c_start\n")); - - /* Set the start bit */ - -/* gtI2cGenerateStartBit() */ - - GT_REG_READ (I2C_CONTROL, &control); - control |= (0x1 << 5); /* generate the I2C_START_BIT */ - GT_REG_WRITE (I2C_CONTROL, control); - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - - count = 0; - while ((status & 0xff) != 0x08) { - udelay (I2C_DELAY); - if (count > 20) { - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - return (status); - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - - return (0); -} - -static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit) -{ - unsigned int status, data, bits = 7; - int count = 0; - - DP (puts ("i2c_select_device\n")); - - /* Output slave address */ - - if (ten_bit) { - bits = 10; - } - - data = (dev_addr << 1); - /* set the read bit */ - data |= read; - GT_REG_WRITE (I2C_DATA, data); - /* assert the address */ - RESET_REG_BITS (I2C_CONTROL, BIT3); - - udelay (I2C_DELAY); - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count = 0; - while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) { - udelay (I2C_DELAY); - if (count > 20) { - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - return (status); - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - - if (bits == 10) { - printf ("10 bit I2C addressing not yet implemented\n"); - return (0xff); - } - - return (0); -} - -static uchar i2c_get_data (uchar * return_data, int len) -{ - - unsigned int data, status = 0; - int count = 0; - - DP (puts ("i2c_get_data\n")); - - while (len) { - - /* Get and return the data */ - - RESET_REG_BITS (I2C_CONTROL, (0x1 << 3)); - - udelay (I2C_DELAY * 5); - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - while ((status & 0xff) != 0x50) { - udelay (I2C_DELAY); - if (count > 2) { - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - return 0; - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - GT_REG_READ (I2C_DATA, &data); - len--; - *return_data = (uchar) data; - return_data++; - } - RESET_REG_BITS (I2C_CONTROL, BIT2 | BIT3); - while ((status & 0xff) != 0x58) { - udelay (I2C_DELAY); - if (count > 200) { - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - return (status); - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /* stop */ - - return (0); -} - -static uchar i2c_write_data (unsigned int *data, int len) -{ - unsigned int status; - int count = 0; - unsigned int temp; - unsigned int *temp_ptr = data; - - DP (puts ("i2c_write_data\n")); - - while (len) { - temp = (unsigned int) (*temp_ptr); - GT_REG_WRITE (I2C_DATA, temp); - RESET_REG_BITS (I2C_CONTROL, (0x1 << 3)); - - udelay (I2C_DELAY); - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - while ((status & 0xff) != 0x28) { - udelay (I2C_DELAY); - if (count > 20) { - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - return (status); - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - len--; - temp_ptr++; - } -/* 11-14-2002 Paul Marchese */ -/* Can't have the write issuing a stop command */ -/* it's wrong to have a stop bit in read stream or write stream */ -/* since we don't know if it's really the end of the command */ -/* or whether we have just send the device address + offset */ -/* we will push issuing the stop command off to the original */ -/* calling function */ - /* set the interrupt bit in the control register */ - GT_REG_WRITE (I2C_CONTROL, (0x1 << 3)); - udelay (I2C_DELAY * 10); - return (0); -} - -/* 11-14-2002 Paul Marchese */ -/* created this function to get the i2c_write() */ -/* function working properly. */ -/* function to write bytes out on the i2c bus */ -/* this is identical to the function i2c_write_data() */ -/* except that it requires a buffer that is an */ -/* unsigned character array. You can't use */ -/* i2c_write_data() to send an array of unsigned characters */ -/* since the byte of interest ends up on the wrong end of the bus */ -/* aah, the joys of big endian versus little endian! */ -/* */ -/* returns 0 = success */ -/* anything other than zero is failure */ -static uchar i2c_write_byte (unsigned char *data, int len) -{ - unsigned int status; - int count = 0; - unsigned int temp; - unsigned char *temp_ptr = data; - - DP (puts ("i2c_write_byte\n")); - - while (len) { - /* Set and assert the data */ - temp = *temp_ptr; - GT_REG_WRITE (I2C_DATA, temp); - RESET_REG_BITS (I2C_CONTROL, (0x1 << 3)); - - udelay (I2C_DELAY); - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - while ((status & 0xff) != 0x28) { - udelay (I2C_DELAY); - if (count > 20) { - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - return (status); - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - len--; - temp_ptr++; - } -/* Can't have the write issuing a stop command */ -/* it's wrong to have a stop bit in read stream or write stream */ -/* since we don't know if it's really the end of the command */ -/* or whether we have just send the device address + offset */ -/* we will push issuing the stop command off to the original */ -/* calling function */ -/* GT_REG_WRITE(I2C_CONTROL, (0x1 << 3) | (0x1 << 4)); - GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); */ - /* set the interrupt bit in the control register */ - GT_REG_WRITE (I2C_CONTROL, (0x1 << 3)); - udelay (I2C_DELAY * 10); - - return (0); -} - -static uchar -i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit, - int alen) -{ - uchar status; - unsigned int table[2]; - -/* initialize the table of address offset bytes */ -/* utilized for 2 byte address offsets */ -/* NOTE: the order is high byte first! */ - table[1] = offset & 0xff; /* low byte */ - table[0] = offset / 0x100; /* high byte */ - - DP (puts ("i2c_set_dev_offset\n")); - - status = i2c_select_device (dev_addr, 0, ten_bit); - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to select device setting offset: 0x%02x\n", - status); -#endif - return status; - } -/* check the address offset length */ - if (alen == 0) - /* no address offset */ - return (0); - else if (alen == 1) { - /* 1 byte address offset */ - status = i2c_write_data (&offset, 1); - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to write data: 0x%02x\n", status); -#endif - return status; - } - } else if (alen == 2) { - /* 2 bytes address offset */ - status = i2c_write_data (table, 2); - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to write data: 0x%02x\n", status); -#endif - return status; - } - } else { - /* address offset unknown or not supported */ - printf ("Address length offset %d is not supported\n", alen); - return 1; - } - return 0; /* sucessful completion */ -} - -int -i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data, - int len) -{ - uchar status = 0; - unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED; - - DP (puts ("i2c_read\n")); - - /* set the i2c frequency */ - i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE); - - status = i2c_start (); - - if (status) { -#ifdef DEBUG_I2C - printf ("Transaction start failed: 0x%02x\n", status); -#endif - return status; - } - - status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */ - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to set slave address & offset: 0x%02x\n", - status); -#endif - return status; - } - - /* set the i2c frequency again */ - i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE); - - status = i2c_start (); - if (status) { -#ifdef DEBUG_I2C - printf ("Transaction restart failed: 0x%02x\n", status); -#endif - return status; - } - - status = i2c_select_device (dev_addr, 1, 0); /* send the slave address */ - if (status) { -#ifdef DEBUG_I2C - printf ("Address not acknowledged: 0x%02x\n", status); -#endif - return status; - } - - status = i2c_get_data (data, len); - if (status) { -#ifdef DEBUG_I2C - printf ("Data not received: 0x%02x\n", status); -#endif - return status; - } - - return 0; -} - -/* 11-14-2002 Paul Marchese */ -/* Function to set the I2C stop bit */ -void i2c_stop (void) -{ - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); -} - -/* 11-14-2002 Paul Marchese */ -/* I2C write function */ -/* dev_addr = device address */ -/* offset = address offset */ -/* alen = length in bytes of the address offset */ -/* data = pointer to buffer to read data into */ -/* len = # of bytes to read */ -/* */ -/* returns 0 = succesful */ -/* anything but zero is failure */ -int -i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data, - int len) -{ - uchar status = 0; - unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED; - - DP (puts ("i2c_write\n")); - - /* set the i2c frequency */ - i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE); - - status = i2c_start (); /* send a start bit */ - - if (status) { -#ifdef DEBUG_I2C - printf ("Transaction start failed: 0x%02x\n", status); -#endif - return status; - } - - status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */ - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to set slave address & offset: 0x%02x\n", - status); -#endif - return status; - } - - - status = i2c_write_byte (data, len); /* write the data */ - if (status) { -#ifdef DEBUG_I2C - printf ("Data not written: 0x%02x\n", status); -#endif - return status; - } - /* issue a stop bit */ - i2c_stop (); - return 0; -} - -/* 11-14-2002 Paul Marchese */ -/* function to determine if an I2C device is present */ -/* chip = device address of chip to check for */ -/* */ -/* returns 0 = sucessful, the device exists */ -/* anything other than zero is failure, no device */ -int i2c_probe (uchar chip) -{ - - /* We are just looking for an <ACK> back. */ - /* To see if the device/chip is there */ - -#ifdef DEBUG_I2C - unsigned int i2c_status; -#endif - uchar status = 0; - unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED; - - DP (puts ("i2c_probe\n")); - - /* set the i2c frequency */ - i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE); - - status = i2c_start (); /* send a start bit */ - - if (status) { -#ifdef DEBUG_I2C - printf ("Transaction start failed: 0x%02x\n", status); -#endif - return (int) status; - } - - status = i2c_set_dev_offset (chip, 0, 0, 0); /* send the slave address + no offset */ - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to set slave address: 0x%02x\n", status); -#endif - return (int) status; - } -#ifdef DEBUG_I2C - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &i2c_status); - printf ("address %#x returned %#x\n", chip, i2c_status); -#endif - /* issue a stop bit */ - i2c_stop (); - return 0; /* successful completion */ -} diff --git a/board/Marvell/common/intel_flash.c b/board/Marvell/common/intel_flash.c deleted file mode 100644 index d6970d4..0000000 --- a/board/Marvell/common/intel_flash.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Hacked for the marvell db64360 eval board by - * Ingo Assmus <ingo.assmus@keymile.com> - */ - -#include <common.h> -#include <mpc8xx.h> -#include "../include/mv_gen_reg.h" -#include "../include/memory.h" -#include "intel_flash.h" - - -/*----------------------------------------------------------------------- - * Protection Flags: - */ -#define FLAG_PROTECT_SET 0x01 -#define FLAG_PROTECT_CLEAR 0x02 - -static void bank_reset (flash_info_t * info, int sect) -{ - bank_addr_t addrw, eaddrw; - - addrw = (bank_addr_t) info->start[sect]; - eaddrw = BANK_ADDR_NEXT_WORD (addrw); - - while (addrw < eaddrw) { -#ifdef FLASH_DEBUG - printf (" writing reset cmd to addr 0x%08lx\n", - (unsigned long) addrw); -#endif - *addrw = BANK_CMD_RST; - addrw++; - } -} - -static void bank_erase_init (flash_info_t * info, int sect) -{ - bank_addr_t addrw, saddrw, eaddrw; - int flag; - -#ifdef FLASH_DEBUG - printf ("0x%08x BANK_CMD_PROG\n", BANK_CMD_PROG); - printf ("0x%08x BANK_CMD_ERASE1\n", BANK_CMD_ERASE1); - printf ("0x%08x BANK_CMD_ERASE2\n", BANK_CMD_ERASE2); - printf ("0x%08x BANK_CMD_CLR_STAT\n", BANK_CMD_CLR_STAT); - printf ("0x%08x BANK_CMD_RST\n", BANK_CMD_RST); - printf ("0x%08x BANK_STAT_RDY\n", BANK_STAT_RDY); - printf ("0x%08x BANK_STAT_ERR\n", BANK_STAT_ERR); -#endif - - saddrw = (bank_addr_t) info->start[sect]; - eaddrw = BANK_ADDR_NEXT_WORD (saddrw); - -#ifdef FLASH_DEBUG - printf ("erasing sector %d, start addr = 0x%08lx " - "(bank next word addr = 0x%08lx)\n", sect, - (unsigned long) saddrw, (unsigned long) eaddrw); -#endif - - /* Disable intrs which might cause a timeout here */ - flag = disable_interrupts (); - - for (addrw = saddrw; addrw < eaddrw; addrw++) { -#ifdef FLASH_DEBUG - printf (" writing erase cmd to addr 0x%08lx\n", - (unsigned long) addrw); -#endif - *addrw = BANK_CMD_ERASE1; - *addrw = BANK_CMD_ERASE2; - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); -} - -static int bank_erase_poll (flash_info_t * info, int sect) -{ - bank_addr_t addrw, saddrw, eaddrw; - int sectdone, haderr; - - saddrw = (bank_addr_t) info->start[sect]; - eaddrw = BANK_ADDR_NEXT_WORD (saddrw); - - sectdone = 1; - haderr = 0; - - for (addrw = saddrw; addrw < eaddrw; addrw++) { - bank_word_t stat = *addrw; - -#ifdef FLASH_DEBUG - printf (" checking status at addr " - "0x%08x [0x%08x]\n", (unsigned long) addrw, stat); -#endif - if ((stat & BANK_STAT_RDY) != BANK_STAT_RDY) - sectdone = 0; - else if ((stat & BANK_STAT_ERR) != 0) { - printf (" failed on sector %d " - "(stat = 0x%08x) at " - "address 0x%p\n", sect, stat, addrw); - *addrw = BANK_CMD_CLR_STAT; - haderr = 1; - } - } - - if (haderr) - return (-1); - else - return (sectdone); -} - -int write_word_intel (bank_addr_t addr, bank_word_t value) -{ - bank_word_t stat; - ulong start; - int flag, retval; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = BANK_CMD_PROG; - - *addr = value; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - retval = 0; - - /* data polling for D7 */ - start = get_timer (0); - do { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - retval = 1; - goto done; - } - stat = *addr; - } while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY); - - if ((stat & BANK_STAT_ERR) != 0) { - printf ("flash program failed (stat = 0x%08lx) " - "at address 0x%08lx\n", (ulong) stat, (ulong) addr); - *addr = BANK_CMD_CLR_STAT; - retval = 3; - } - - done: - /* reset to read mode */ - *addr = BANK_CMD_RST; - - return (retval); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase_intel (flash_info_t * info, int s_first, int s_last) -{ - int prot, sect, haderr; - ulong start, now, last; - -#ifdef FLASH_DEBUG - printf ("\nflash_erase: erase %d sectors (%d to %d incl.) from\n" - " Bank # %d: ", s_last - s_first + 1, s_first, s_last, - (info - flash_info) + 1); - flash_print_info (info); -#endif - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sector%s will not be erased!\n", prot, (prot > 1 ? "s" : "")); - } - - start = get_timer (0); - last = 0; - haderr = 0; - - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - ulong estart; - int sectdone; - - bank_erase_init (info, sect); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - estart = get_timer (start); - - do { - now = get_timer (start); - - if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout (sect %d)\n", sect); - haderr = 1; - break; - } -#ifndef FLASH_DEBUG - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } -#endif - - sectdone = bank_erase_poll (info, sect); - - if (sectdone < 0) { - haderr = 1; - break; - } - - } while (!sectdone); - - if (haderr) - break; - } - } - - if (haderr > 0) - printf (" failed\n"); - else - printf (" done\n"); - - /* reset to read mode */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - bank_reset (info, sect); - } - } - return haderr; -} diff --git a/board/Marvell/common/misc.S b/board/Marvell/common/misc.S deleted file mode 100644 index b3a0898..0000000 --- a/board/Marvell/common/misc.S +++ /dev/null @@ -1,235 +0,0 @@ -#include <config.h> -#include <74xx_7xx.h> -#include "version.h" - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#include <asm/cache.h> -#include <asm/mmu.h> - -#include "../include/mv_gen_reg.h" - -#ifdef CONFIG_ECC - /* Galileo specific asm code for initializing ECC */ - .globl board_relocate_rom -board_relocate_rom: - mflr r7 - /* update the location of the GT registers */ - lis r11, CONFIG_SYS_GT_REGS@h - /* if we're using ECC, we must use the DMA engine to copy ourselves */ - bl start_idma_transfer_0 - bl wait_for_idma_0 - bl stop_idma_engine_0 - - mtlr r7 - blr - - .globl board_init_ecc -board_init_ecc: - mflr r7 - /* NOTE: r10 still contains the location we've been relocated to - * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */ - - /* now that we're running from ram, init the rest of main memory - * for ECC use */ - lis r8, CONFIG_SYS_MONITOR_LEN@h - ori r8, r8, CONFIG_SYS_MONITOR_LEN@l - - divw r3, r10, r8 - - /* set up the counter, and init the starting address */ - mtctr r3 - li r12, 0 - - /* bytes per transfer */ - mr r5, r8 -about_to_init_ecc: -1: mr r3, r12 - mr r4, r12 - bl start_idma_transfer_0 - bl wait_for_idma_0 - bl stop_idma_engine_0 - add r12, r12, r8 - bdnz 1b - - mtlr r7 - blr - - /* r3: dest addr - * r4: source addr - * r5: byte count - * r11: gt regbase - * trashes: r6, r5 - */ -start_idma_transfer_0: - /* set the byte count, including the OWN bit */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_BYTE_COUNT - stwbrx r5, 0, (r6) - - /* set the source address */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS - stwbrx r4, 0, (r6) - - /* set the dest address */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS - stwbrx r3, 0, (r6) - - /* set the next record pointer */ - li r5, 0 - mr r6, r11 - ori r6, r6, CHANNEL0NEXT_RECORD_POINTER - stwbrx r5, 0, (r6) - - /* set the low control register */ - /* bit 9 is NON chained mode, bit 31 is new style descriptors. - bit 12 is channel enable */ - ori r5, r5, (1 << 12) | (1 << 12) | (1 << 11) - /* 15 shifted by 16 (oris) == bit 31 */ - oris r5, r5, (1 << 15) - mr r6, r11 - ori r6, r6, CHANNEL0CONTROL - stwbrx r5, 0, (r6) - - blr - - /* this waits for the bytecount to return to zero, indicating - * that the trasfer is complete */ -wait_for_idma_0: - mr r5, r11 - lis r6, 0xff - ori r6, r6, 0xffff - ori r5, r5, CHANNEL0_DMA_BYTE_COUNT -1: lwbrx r4, 0, (r5) - and. r4, r4, r6 - bne 1b - - blr - - /* this turns off channel 0 of the idma engine */ -stop_idma_engine_0: - /* shut off the DMA engine */ - li r5, 0 - mr r6, r11 - ori r6, r6, CHANNEL0CONTROL - stwbrx r5, 0, (r6) - - blr -#endif - -#ifdef CONFIG_SYS_BOARD_ASM_INIT - /* NOTE: trashes r3-r7 */ - .globl board_asm_init -board_asm_init: - /* just move the GT registers to where they belong */ - lis r3, CONFIG_SYS_DFL_GT_REGS@h - ori r3, r3, CONFIG_SYS_DFL_GT_REGS@l - lis r4, CONFIG_SYS_GT_REGS@h - ori r4, r4, CONFIG_SYS_GT_REGS@l - li r5, INTERNAL_SPACE_DECODE - - /* test to see if we've already moved */ - lwbrx r6, r5, r4 - andi. r6, r6, 0xffff - /* check loading of R7 is: 0x0F80 should: 0xf800: DONE */ -/* rlwinm r7, r4, 8, 16, 31 - rlwinm r7, r4, 12, 16, 31 */ /* original */ - rlwinm r7, r4, 16, 16, 31 - /* -----------------------------------------------------*/ - cmp cr0, r7, r6 - beqlr - - /* nope, have to move the registers */ - lwbrx r6, r5, r3 - andis. r6, r6, 0xffff - or r6, r6, r7 - stwbrx r6, r5, r3 - - /* now, poll for the change */ -1: lwbrx r7, r5, r4 - cmp cr0, r7, r6 - bne 1b - - /* done! */ - blr -#endif - -/* For use of the debug LEDs */ - .global led_on0_relocated -led_on0_relocated: - xor r21, r21, r21 - xor r18, r18, r18 - lis r18, 0xFC80 - ori r18, r18, 0x8000 - stw r21, 0x0(r18) -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_off0_relocated -led_off0_relocated: - xor r21, r21, r21 - xor r18, r18, r18 - lis r18, 0xFC81 - ori r18, r18, 0x4000 - stw r21, 0x0(r18) -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_on0 -led_on0: - xor r18, r18, r18 - lis r18, 0x1c80 - ori r18, r18, 0x8000 - stw r18, 0x0(r18) - sync - blr - - .global led_off0 -led_off0: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0x4000 - stw r18, 0x0(r18) - sync - blr - - .global led_on1 -led_on1: - xor r18, r18, r18 - lis r18, 0x1c80 - ori r18, r18, 0xc000 - stw r18, 0x0(r18) - sync - blr - - .global led_off1 -led_off1: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0x8000 - stw r18, 0x0(r18) - sync - blr - - .global led_on2 -led_on2: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0x0000 - stw r18, 0x0(r18) - sync - blr - - .global led_off2 -led_off2: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0xc000 - stw r18, 0x0(r18) - sync - blr diff --git a/board/Marvell/common/serial.c b/board/Marvell/common/serial.c index 752492f..432aa06 100644 --- a/board/Marvell/common/serial.c +++ b/board/Marvell/common/serial.c @@ -21,14 +21,6 @@ #include "../include/memory.h" -#ifdef CONFIG_DB64360 -#include "../db64360/mpsc.h" -#endif - -#ifdef CONFIG_DB64460 -#include "../db64460/mpsc.h" -#endif - #include "ns16550.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/Marvell/db64360/64360.h b/board/Marvell/db64360/64360.h deleted file mode 100644 index 9951262..0000000 --- a/board/Marvell/db64360/64360.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus <ingo.assmus@keymile.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * main board support/init for the Galileo Eval board DB64360. - */ - -#ifndef __64360_H__ -#define __64360_H__ - -/* CPU Configuration bits */ -#define CPU_CONF_ADDR_MISS_EN (1 << 8) -#define CPU_CONF_SINGLE_CPU (1 << 11) -#define CPU_CONF_ENDIANESS (1 << 12) -#define CPU_CONF_PIPELINE (1 << 13) -#define CPU_CONF_STOP_RETRY (1 << 17) -#define CPU_CONF_MULTI_DECODE (1 << 18) -#define CPU_CONF_DP_VALID (1 << 19) -#define CPU_CONF_PERR_PROP (1 << 22) -#define CPU_CONF_AACK_DELAY_2 (1 << 25) -#define CPU_CONF_AP_VALID (1 << 26) -#define CPU_CONF_REMAP_WR_DIS (1 << 27) - -/* CPU Master Control bits */ -#define CPU_MAST_CTL_ARB_EN (1 << 8) -#define CPU_MAST_CTL_MASK_BR_1 (1 << 9) -#define CPU_MAST_CTL_M_WR_TRIG (1 << 10) -#define CPU_MAST_CTL_M_RD_TRIG (1 << 11) -#define CPU_MAST_CTL_CLEAN_BLK (1 << 12) -#define CPU_MAST_CTL_FLUSH_BLK (1 << 13) - -#endif /* __64360_H__ */ diff --git a/board/Marvell/db64360/Kconfig b/board/Marvell/db64360/Kconfig deleted file mode 100644 index c5118f8..0000000 --- a/board/Marvell/db64360/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_DB64360 - -config SYS_BOARD - default "db64360" - -config SYS_VENDOR - default "Marvell" - -config SYS_CONFIG_NAME - default "DB64360" - -endif diff --git a/board/Marvell/db64360/MAINTAINERS b/board/Marvell/db64360/MAINTAINERS deleted file mode 100644 index af3eb24..0000000 --- a/board/Marvell/db64360/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -DB64360 BOARD -#M: - -S: Maintained -F: board/Marvell/db64360/ -F: include/configs/DB64360.h -F: configs/DB64360_defconfig diff --git a/board/Marvell/db64360/Makefile b/board/Marvell/db64360/Makefile deleted file mode 100644 index aefe0a7..0000000 --- a/board/Marvell/db64360/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2001 -# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = db64360.o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \ - mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \ - sdram_init.o ../common/intel_flash.o ../common/misc.o diff --git a/board/Marvell/db64360/README b/board/Marvell/db64360/README deleted file mode 100644 index ebac4ce..0000000 --- a/board/Marvell/db64360/README +++ /dev/null @@ -1,105 +0,0 @@ -This file contains status information for the port of the U-Boot to the Marvell Development Board DB64360. - -Author: Ronen Shitrit <rshitrit@il.marvell.com> - -This U-Boot version is based on the work of Brian Waite and his team from Sky Computers, THANKS A LOT. - -Supported CPU Types : -+++++++++++++++++++++ - IBM750FX (ver 2.3) - MPC7455 (ver 2.1) - -Supported CPU Cache Library: -++++++++++++++++++++++++++++ - L1 and L2 only. - -CPU Control: -++++++++++++ - Marvell optimized CPU control settings: - Big Endian - Enable CPU pipeline - Data and address parity checking - AACK# assert after 2 cycles - -U-Boot I/O Interface Support: -+++++++++++++++++++++++++++++ -- Serial Interface (UART) - This version of U-Boot supports the SIO U-Boot interface driver, with a PC standard baud rate up to 115200 BPS on the ST16C2552 DUART device located on DB-64360-BP device module. -- Network Interface - This LSP supports the following network devices: - o MV64360 Gigabit Ethernet Controller device - o Intel 82559 PCI NIC device -- PCI Interface - This LSP supports the following capabilities over the Marvell(r) device PCI0/1 units: - o Local PCI configuration header control. - o External PCI configuration header control (for other agents on the bus). - o PCI configuration application. Scans and configures the PCI agents on the bus. - o PCI Internal Arbiter activation and configuration. - -Memory Interface Support: -+++++++++++++++++++++++++ -- DDR - o DDR auto-detection and configuration. Enables access up to 256 MB, due to the limitations of using only four Base Address Translations (BATs). - o Enable DDR ECC in case both DIMM support ECC, and initialize the entire DDR memory by using the idma. - -- Devices - o Initializes the MV64360 device's chip-selects 0-3 to enable access to the boot flash, main flash, real time clock (RTC), and external SRAM. - o JFFS2 - JFFS2 is a crash/power down safe file system for disk-less embedded devices. - This version of U-Boot supports scanning a JFFS2 file system on the large flash and loading files from it. - -Unsupported Features: -+++++++++++++++++++++ - Messaging unit - No support for MV64360 Messaging unit. - Watchdog Timer - No support for MV64360 Watchdog unit. - L3 cache - No support for L3 cache on MPC7455 - Dual PCU - No support for Dual CPU - PCI-X was never tested - IDMA driver - No support for MV64360 IDMA unit. - -BSP Special Considerations: -+++++++++++++++++++++++++++ -- DDR DIMM location: Due to PCI specifications, place the larger DIMM module in the MAIN DIMM slot, in order to have full access from the PCI to the DDR while using both DDR slots. -- DDR DIMM types: Due to architectural and software limitations, the registration, CAS Latency, and ECC of both DIMMS should be identical. - -Test Cases: -########### -UART: -+++++ -Check that the UART baud rate is configured to 57600 and 115200, and check: - Transmit (to the hyper terminal) and Receive (using the keyboard) using Linux minicom. - Load S-Record file over the UART using Windows HyperTerminal. - -Network: -++++++++ -Use TFTP application to load a debugged executable and execute it. -Insert Intel PCI NIC 82557 rev 08 to PCI slots 0-3 Check correct detection of the PCI NIC, correct configuration of the NIC BARs , and load files by using tftp through the PCI NIC. - -Memory: -+++++++ -Test DDR DIMMs on DB-64360-BP. See that Uboot report their correct parameters: -o 128MB DIMM consist of 16 x 64Mbit devices -o 128MB DIMM consist of 09 x 128Mbit devices @ 266MHz. -o 256MB DIMM consist of 16 x 128Mbit devices @ 266MHz. -o 256MB DIMM consist of 09 x 256Mbit devices @ 400MHz. -o 512MB DIMM consist of 16 x 256Mbit devices @ 333MHz. -o 512MB DIMM consist of 18 x 256Mbit devices @ 266MHz. -o GigaB DIMM consist of 36 x 256Mbit devices @ 266MHz registered - -For each chip select device perform data access to verify its accessibility. - -Create a JFFS2 on the large flash through the Linux holding few files, few dirs and a uImage. -Load the U-Boot and: -use the ls command to check correct scan of the JFFS2 on the large flash. -Use the floads command to copy the uImage from the JFFS2 on the large flash to the DIMM SDRAM, and boot the uImage. - -PCI: -++++ -1)Insert different PCI cards: -Galileo 64120A rev 10 and 12, Intel Nic 82557 rev 08 and Real Tech NIC 8139 rev10 -on different slots (0-3) of the PCI and check: -o Correct detection of the PCI devices. -o Correct address mapping of the PCI devices. -2)Insert Galileo 64120A rev 10 on different slots (0-3) of the PCI and check writing and reading pci configuration register through the U-Boot. - -Booting Linux through the U-Boot (use the bootargs of the U-Boot as a bootcmd to the kernal) diff --git a/board/Marvell/db64360/db64360.c b/board/Marvell/db64360/db64360.c deleted file mode 100644 index 36d26e3..0000000 --- a/board/Marvell/db64360/db64360.c +++ /dev/null @@ -1,922 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com - */ - -/* - * db64360.c - main board support/init for the Galileo Eval board. - */ - -#include <common.h> -#include <74xx_7xx.h> -#include "../include/memory.h" -#include "../include/pci.h" -#include "../include/mv_gen_reg.h" -#include <net.h> -#include <netdev.h> -#include <linux/compiler.h> - -#include "eth.h" -#include "mpsc.h" -#include "i2c.h" -#include "64360.h" -#include "mv_regs.h" - -#undef DEBUG -/*#define DEBUG */ - -#define MAP_PCI - -#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -/* ------------------------------------------------------------------------- */ - -/* this is the current GT register space location */ -/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */ - -/* Unfortunately, we cant change it while we are in flash, so we initialize it - * to the "final" value. This means that any debug_led calls before - * board_early_init_f wont work right (like in cpu_init_f). - * See also my_remap_gt_regs below. (NTL) - */ - -void board_prebootm_init (void); -unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS; -int display_mem_map (void); - -/* ------------------------------------------------------------------------- */ - -/* - * This is a version of the GT register space remapping function that - * doesn't touch globals (meaning, it's ok to run from flash.) - * - * Unfortunately, this has the side effect that a writable - * INTERNAL_REG_BASE_ADDR is impossible. Oh well. - */ - -void my_remap_gt_regs (u32 cur_loc, u32 new_loc) -{ - u32 temp; - - /* check and see if it's already moved */ - -/* original ppcboot 1.1.6 source - - temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 20) - return; - - temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 20); - - out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp); - - while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp); -original ppcboot 1.1.6 source end */ - - temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 16) - return; - - temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 16); - - out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp); - - while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp); -} - -#ifdef CONFIG_PCI - -static void gt_pci_config (void) -{ - unsigned int stat; - unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */ - - /* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's - * config registers by writing ones to the bus and device. - * We then update the Virtual register with the correct value for the bus and device. - */ - if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ - GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); - - GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat); - - GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); - GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); - - } - if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ - GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); - GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat); - - GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); - GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); - } - - /* Enable master */ - PCI_MASTER_ENABLE (0, SELF); - PCI_MASTER_ENABLE (1, SELF); - - /* Enable PCI0/1 Mem0 and IO 0 disable all others */ - GT_REG_READ (BASE_ADDR_ENABLE, &stat); - stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1 - << - 18); - stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15)); - GT_REG_WRITE (BASE_ADDR_ENABLE, stat); - - /* ronen- add write to pci remap registers for 64460. - in 64360 when writing to pci base go and overide remap automaticaly, - in 64460 it doesn't */ - GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_BASE >> 16); - GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_BASE >> 16); - GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_BASE >> 16); - GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_BASE >> 16); - GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16); - - /* PCI interface settings */ - /* Timeout set to retry forever */ - GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0); - GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0); - - /* ronen - enable only CS0 and Internal reg!! */ - GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); - GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); - -/*ronen update the pci internal registers base address.*/ -#ifdef MAP_PCI - for (stat = 0; stat <= PCI_HOST1; stat++) - pciWriteConfigReg (stat, - PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, - SELF, CONFIG_SYS_GT_REGS); -#endif - -} -#endif - -/* Setup CPU interface paramaters */ -static void gt_cpu_config (void) -{ - cpu_t cpu = get_cpu_type (); - ulong tmp; - - /* cpu configuration register */ - tmp = GTREGREAD (CPU_CONFIGURATION); - - /* set the SINGLE_CPU bit see MV64360 P.399 */ -#ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ - tmp |= CPU_CONF_SINGLE_CPU; -#endif - - tmp &= ~CPU_CONF_AACK_DELAY_2; - - tmp |= CPU_CONF_DP_VALID; - tmp |= CPU_CONF_AP_VALID; - - tmp |= CPU_CONF_PIPELINE; - - GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */ - - /* CPU master control register */ - tmp = GTREGREAD (CPU_MASTER_CONTROL); - - tmp |= CPU_MAST_CTL_ARB_EN; - - if ((cpu == CPU_7400) || - (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) { - - tmp |= CPU_MAST_CTL_CLEAN_BLK; - tmp |= CPU_MAST_CTL_FLUSH_BLK; - - } else { - /* cleanblock must be cleared for CPUs - * that do not support this command (603e, 750) - * see Res#1 */ - tmp &= ~CPU_MAST_CTL_CLEAN_BLK; - tmp &= ~CPU_MAST_CTL_FLUSH_BLK; - } - GT_REG_WRITE (CPU_MASTER_CONTROL, tmp); -} - -/* - * board_early_init_f. - * - * set up gal. device mappings, etc. - */ -int board_early_init_f (void) -{ - uchar sram_boot = 0; - - /* - * set up the GT the way the kernel wants it - * the call to move the GT register space will obviously - * fail if it has already been done, but we're going to assume - * that if it's not at the power-on location, it's where we put - * it last time. (huber) - */ - - my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS); - - /* No PCI in first release of Port To_do: enable it. */ -#ifdef CONFIG_PCI - gt_pci_config (); -#endif - /* mask all external interrupt sources */ - GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0); - /* new in MV6436x */ - GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0); - /* --------------------- */ - GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); - GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); - /* does not exist in MV6436x - GT_REG_WRITE(CPU_INT_0_MASK, 0); - GT_REG_WRITE(CPU_INT_1_MASK, 0); - GT_REG_WRITE(CPU_INT_2_MASK, 0); - GT_REG_WRITE(CPU_INT_3_MASK, 0); - --------------------- */ - - - /* ----- DEVICE BUS SETTINGS ------ */ - - /* - * EVB - * 0 - SRAM ???? - * 1 - RTC ???? - * 2 - UART ???? - * 3 - Flash checked 32Bit Intel Strata - * boot - BootCS checked 8Bit 29LV040B - * - * Zuma - * 0 - Flash - * boot - BootCS - */ - - /* - * the dual 7450 module requires burst access to the boot - * device, so the serial rom copies the boot device to the - * on-board sram on the eval board, and updates the correct - * registers to boot from the sram. (device0) - */ - if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) - sram_boot = 1; - if (!sram_boot) - memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE); - - memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE); - memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE); - memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE); - - - /* configure device timing */ -#ifdef CONFIG_SYS_DEV0_PAR /* set port parameters for SRAM device module access */ - if (!sram_boot) - GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR); -#endif - -#ifdef CONFIG_SYS_DEV1_PAR /* set port parameters for RTC device module access */ - GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR); -#endif -#ifdef CONFIG_SYS_DEV2_PAR /* set port parameters for DUART device module access */ - GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR); -#endif - -#ifdef CONFIG_SYS_32BIT_BOOT_PAR /* set port parameters for Flash device module access */ - /* detect if we are booting from the 32 bit flash */ - if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) { - /* 32 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); - GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, - CONFIG_SYS_32BIT_BOOT_PAR); - } else { - /* 8 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR); - GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); - } -#else - /* 8 bit boot flash only */ -/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/ -#endif - - - gt_cpu_config (); - - /* MPP setup */ - GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0); - GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1); - GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2); - GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3); - - GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL); - DEBUG_LED0_ON (); - DEBUG_LED1_ON (); - DEBUG_LED2_ON (); - - return 0; -} - -/* various things to do after relocation */ - -int misc_init_r () -{ - icache_enable (); -#ifdef CONFIG_SYS_L2 - l2cache_enable (); -#endif -#ifdef CONFIG_MPSC - - mpsc_sdma_init (); - mpsc_init2 (); -#endif - -#if 0 - /* disable the dcache and MMU */ - dcache_lock (); -#endif - return 0; -} - -void after_reloc (ulong dest_addr, gd_t * gd) -{ - /* check to see if we booted from the sram. If so, move things - * back to the way they should be. (we're running from main - * memory at this point now */ - if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) { - memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE); - memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_DFL_BOOTCS_BASE, _8M); - } - display_mem_map (); - /* now, jump to the main ppcboot board init code */ - board_init_r (gd, dest_addr); - /* NOTREACHED */ -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - * - * right now, assume borad type. (there is just one...after all) - */ - -int checkboard (void) -{ - int l_type = 0; - - printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME); - return (l_type); -} - -/* utility functions */ -void debug_led (int led, int mode) -{ - volatile int *addr = 0; - __maybe_unused int dummy; - - if (mode == 1) { - switch (led) { - case 0: - addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | - 0x08000); - break; - - case 1: - addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | - 0x0c000); - break; - - case 2: - addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | - 0x10000); - break; - } - } else if (mode == 0) { - switch (led) { - case 0: - addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | - 0x14000); - break; - - case 1: - addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | - 0x18000); - break; - - case 2: - addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | - 0x1c000); - break; - } - } - - dummy = *addr; -} - -int display_mem_map (void) -{ - int i, j; - unsigned int base, size, width; - - /* SDRAM */ - printf ("SD (DDR) RAM\n"); - for (i = 0; i <= BANK3; i++) { - base = memoryGetBankBaseAddress (i); - size = memoryGetBankSize (i); - if (size != 0) { - printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n", - i, base, size >> 20); - } - } - - /* CPU's PCI windows */ - for (i = 0; i <= PCI_HOST1; i++) { - printf ("\nCPU's PCI %d windows\n", i); - base = pciGetSpaceBase (i, PCI_IO); - size = pciGetSpaceSize (i, PCI_IO); - printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base, - size >> 20); - for (j = 0; - j <= - PCI_REGION0 - /*ronen currently only first PCI MEM is used 3 */ ; - j++) { - base = pciGetSpaceBase (i, j); - size = pciGetSpaceSize (i, j); - printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20); - } - } - - /* Devices */ - printf ("\nDEVICES\n"); - for (i = 0; i <= DEVICE3; i++) { - base = memoryGetDeviceBaseAddress (i); - size = memoryGetDeviceSize (i); - width = memoryGetDeviceWidth (i) * 8; - printf ("DEV %d: base - 0x%08x size - %dM bytes\twidth - %d bits", i, base, size >> 20, width); - if (i == 0) - printf ("\t- EXT SRAM (actual - 1M)\n"); - else if (i == 1) - printf ("\t- RTC\n"); - else if (i == 2) - printf ("\t- UART\n"); - else - printf ("\t- LARGE FLASH\n"); - } - - /* Bootrom */ - base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */ - size = memoryGetDeviceSize (BOOT_DEVICE); - width = memoryGetDeviceWidth (BOOT_DEVICE) * 8; - printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\n", - base, size >> 20, width); - return (0); -} - -/* DRAM check routines copied from gw8260 */ - -#if defined (CONFIG_SYS_DRAM_TEST) - -/*********************************************************************/ -/* NAME: move64() - moves a double word (64-bit) */ -/* */ -/* DESCRIPTION: */ -/* this function performs a double word move from the data at */ -/* the source pointer to the location at the destination pointer. */ -/* */ -/* INPUTS: */ -/* unsigned long long *src - pointer to data to move */ -/* */ -/* OUTPUTS: */ -/* unsigned long long *dest - pointer to locate to move data */ -/* */ -/* RETURNS: */ -/* None */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* May cloober fr0. */ -/* */ -/*********************************************************************/ -static void move64 (unsigned long long *src, unsigned long long *dest) -{ - asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ - "stfd 0, 0(4)" /* *dest = fpr0 */ - : : : "fr0"); /* Clobbers fr0 */ - return; -} - - -#if defined (CONFIG_SYS_DRAM_TEST_DATA) - -unsigned long long pattern[] = { - 0xaaaaaaaaaaaaaaaaULL, - 0xccccccccccccccccULL, - 0xf0f0f0f0f0f0f0f0ULL, - 0xff00ff00ff00ff00ULL, - 0xffff0000ffff0000ULL, - 0xffffffff00000000ULL, - 0x00000000ffffffffULL, - 0x0000ffff0000ffffULL, - 0x00ff00ff00ff00ffULL, - 0x0f0f0f0f0f0f0f0fULL, - 0x3333333333333333ULL, - 0x5555555555555555ULL, -}; - -/*********************************************************************/ -/* NAME: mem_test_data() - test data lines for shorts and opens */ -/* */ -/* DESCRIPTION: */ -/* Tests data lines for shorts and opens by forcing adjacent data */ -/* to opposite states. Because the data lines could be routed in */ -/* an arbitrary manner the must ensure test patterns ensure that */ -/* every case is tested. By using the following series of binary */ -/* patterns every combination of adjacent bits is test regardless */ -/* of routing. */ -/* */ -/* ...101010101010101010101010 */ -/* ...110011001100110011001100 */ -/* ...111100001111000011110000 */ -/* ...111111110000000011111111 */ -/* */ -/* Carrying this out, gives us six hex patterns as follows: */ -/* */ -/* 0xaaaaaaaaaaaaaaaa */ -/* 0xcccccccccccccccc */ -/* 0xf0f0f0f0f0f0f0f0 */ -/* 0xff00ff00ff00ff00 */ -/* 0xffff0000ffff0000 */ -/* 0xffffffff00000000 */ -/* */ -/* The number test patterns will always be given by: */ -/* */ -/* log(base 2)(number data bits) = log2 (64) = 6 */ -/* */ -/* To test for short and opens to other signals on our boards. we */ -/* simply */ -/* test with the 1's complemnt of the paterns as well. */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* Assumes only one one SDRAM bank */ -/* */ -/*********************************************************************/ -int mem_test_data (void) -{ - unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START; - unsigned long long temp64 = 0; - int num_patterns = sizeof (pattern) / sizeof (pattern[0]); - int i; - unsigned int hi, lo; - - for (i = 0; i < num_patterns; i++) { - move64 (&(pattern[i]), pmem); - move64 (pmem, &temp64); - - /* hi = (temp64>>32) & 0xffffffff; */ - /* lo = temp64 & 0xffffffff; */ - /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */ - - hi = (pattern[i] >> 32) & 0xffffffff; - lo = pattern[i] & 0xffffffff; - /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */ - - if (temp64 != pattern[i]) { - printf ("\n Data Test Failed, pattern 0x%08x%08x", - hi, lo); - return 1; - } - } - - return 0; -} -#endif /* CONFIG_SYS_DRAM_TEST_DATA */ - -#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS) -/*********************************************************************/ -/* NAME: mem_test_address() - test address lines */ -/* */ -/* DESCRIPTION: */ -/* This function performs a test to verify that each word im */ -/* memory is uniquly addressable. The test sequence is as follows: */ -/* */ -/* 1) write the address of each word to each word. */ -/* 2) verify that each location equals its address */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern and address */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_test_address (void) -{ - volatile unsigned int *pmem = - (volatile unsigned int *) CONFIG_SYS_MEMTEST_START; - const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4; - unsigned int i; - - /* write address to each location */ - for (i = 0; i < size; i++) { - pmem[i] = i; - } - - /* verify each loaction */ - for (i = 0; i < size; i++) { - if (pmem[i] != i) { - printf ("\n Address Test Failed at 0x%x", i); - return 1; - } - } - return 0; -} -#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */ - -#if defined (CONFIG_SYS_DRAM_TEST_WALK) -/*********************************************************************/ -/* NAME: mem_march() - memory march */ -/* */ -/* DESCRIPTION: */ -/* Marches up through memory. At each location verifies rmask if */ -/* read = 1. At each location write wmask if write = 1. Displays */ -/* failing address and pattern. */ -/* */ -/* INPUTS: */ -/* volatile unsigned long long * base - start address of test */ -/* unsigned int size - number of dwords(64-bit) to test */ -/* unsigned long long rmask - read verify mask */ -/* unsigned long long wmask - wrtie verify mask */ -/* short read - verifies rmask if read = 1 */ -/* short write - writes wmask if write = 1 */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern and address */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_march (volatile unsigned long long *base, - unsigned int size, - unsigned long long rmask, - unsigned long long wmask, short read, short write) -{ - unsigned int i; - unsigned long long temp = 0; - unsigned int hitemp, lotemp, himask, lomask; - - for (i = 0; i < size; i++) { - if (read != 0) { - /* temp = base[i]; */ - move64 ((unsigned long long *) &(base[i]), &temp); - if (rmask != temp) { - hitemp = (temp >> 32) & 0xffffffff; - lotemp = temp & 0xffffffff; - himask = (rmask >> 32) & 0xffffffff; - lomask = rmask & 0xffffffff; - - printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp); - return 1; - } - } - if (write != 0) { - /* base[i] = wmask; */ - move64 (&wmask, (unsigned long long *) &(base[i])); - } - } - return 0; -} -#endif /* CONFIG_SYS_DRAM_TEST_WALK */ - -/*********************************************************************/ -/* NAME: mem_test_walk() - a simple walking ones test */ -/* */ -/* DESCRIPTION: */ -/* Performs a walking ones through entire physical memory. The */ -/* test uses as series of memory marches, mem_march(), to verify */ -/* and write the test patterns to memory. The test sequence is as */ -/* follows: */ -/* 1) march writing 0000...0001 */ -/* 2) march verifying 0000...0001 , writing 0000...0010 */ -/* 3) repeat step 2 shifting masks left 1 bit each time unitl */ -/* the write mask equals 1000...0000 */ -/* 4) march verifying 1000...0000 */ -/* The test fails if any of the memory marches return a failure. */ -/* */ -/* OUTPUTS: */ -/* Displays which pass on the memory test is executing */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_test_walk (void) -{ - unsigned long long mask; - volatile unsigned long long *pmem = - (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START; - const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8; - - unsigned int i; - - mask = 0x01; - - printf ("Initial Pass"); - mem_march (pmem, size, 0x0, 0x1, 0, 1); - - printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); - printf (" "); - printf (" "); - printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); - - for (i = 0; i < 63; i++) { - printf ("Pass %2d", i + 2); - if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) { - /*printf("mask: 0x%x, pass: %d, ", mask, i); */ - return 1; - } - mask = mask << 1; - printf ("\b\b\b\b\b\b\b"); - } - - printf ("Last Pass"); - if (mem_march (pmem, size, 0, mask, 0, 1) != 0) { - /* printf("mask: 0x%x", mask); */ - return 1; - } - printf ("\b\b\b\b\b\b\b\b\b"); - printf (" "); - printf ("\b\b\b\b\b\b\b\b\b"); - - return 0; -} - -/*********************************************************************/ -/* NAME: testdram() - calls any enabled memory tests */ -/* */ -/* DESCRIPTION: */ -/* Runs memory tests if the environment test variables are set to */ -/* 'y'. */ -/* */ -/* INPUTS: */ -/* testdramdata - If set to 'y', data test is run. */ -/* testdramaddress - If set to 'y', address test is run. */ -/* testdramwalk - If set to 'y', walking ones test is run */ -/* */ -/* OUTPUTS: */ -/* None */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int testdram (void) -{ - int rundata, runaddress, runwalk; - - rundata = getenv_yesno("testdramdata") == 1; - runaddress = getenv_yesno("testdramaddress") == 1; - runwalk = getenv_yesno("testdramwalk") == 1; - -/* rundata = 1; */ -/* runaddress = 0; */ -/* runwalk = 0; */ - - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END); - } -#ifdef CONFIG_SYS_DRAM_TEST_DATA - if (rundata == 1) { - printf ("Test DATA ... "); - if (mem_test_data () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif -#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS - if (runaddress == 1) { - printf ("Test ADDRESS ... "); - if (mem_test_address () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif -#ifdef CONFIG_SYS_DRAM_TEST_WALK - if (runwalk == 1) { - printf ("Test WALKING ONEs ... "); - if (mem_test_walk () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("passed\n"); - } - return 0; - -} -#endif /* CONFIG_SYS_DRAM_TEST */ - -/* ronen - the below functions are used by the bootm function */ -/* - we map the base register to fbe00000 (same mapping as in the LSP) */ -/* - we turn off the RX gig dmas - to prevent the dma from overunning */ -/* the kernel data areas. */ -/* - we diable and invalidate the icache and dcache. */ -void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc) -{ - u32 temp; - - temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 16) - return; - - temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 16); - - out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp); - - while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE | - new_loc | - (INTERNAL_SPACE_DECODE))))) - != temp); - -} - -void board_prebootm_init () -{ - -/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */ - GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16); - -/* Stop GigE Rx DMA engines */ - GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00); - GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00); -/* MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0x0000ff00); */ - -/* Relocate MV64360 internal regs */ - my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, BRIDGE_REG_BASE_BOOTM); - - icache_disable (); - dcache_disable (); -} - -int board_eth_init(bd_t *bis) -{ - int ret; - ret = pci_eth_init(bis); - if (!ret) - ret = mv6436x_eth_initialize(bis); - return ret; -} diff --git a/board/Marvell/db64360/eth.h b/board/Marvell/db64360/eth.h deleted file mode 100644 index 4e42768..0000000 --- a/board/Marvell/db64360/eth.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * eth.h - header file for the polled mode GT ethernet driver - */ - -#ifndef __EVB64360_ETH_H__ -#define __EVB64360_ETH_H__ - -#include <asm/types.h> -#include <asm/io.h> -#include <asm/byteorder.h> -#include <common.h> - - -int db64360_eth0_poll(void); -int db64360_eth0_transmit(unsigned int s, volatile char *p); -void db64360_eth0_disable(void); -bool network_start(bd_t *bis); - -int mv6436x_eth_initialize(bd_t *); - -#endif /* __EVB64360_ETH_H__ */ diff --git a/board/Marvell/db64360/mpsc.c b/board/Marvell/db64360/mpsc.c deleted file mode 100644 index d87f18e..0000000 --- a/board/Marvell/db64360/mpsc.c +++ /dev/null @@ -1,1001 +0,0 @@ -/* - * (C) Copyright 2001 - * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com> - * - ************************************************************************/ - -/* - * mpsc.c - driver for console over the MPSC. - */ - - -#include <common.h> -#include <config.h> -#include <asm/cache.h> - -#include <malloc.h> -#include "mpsc.h" - -#include "mv_regs.h" - -#include "../include/memory.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* Define this if you wish to use the MPSC as a register based UART. - * This will force the serial port to not use the SDMA engine at all. - */ -#undef CONFIG_MPSC_DEBUG_PORT - - -int (*mpsc_putchar) (char ch) = mpsc_putchar_early; -char (*mpsc_getchar) (void) = mpsc_getchar_debug; -int (*mpsc_test_char) (void) = mpsc_test_char_debug; - - -static volatile unsigned int *rx_desc_base = NULL; -static unsigned int rx_desc_index = 0; -static volatile unsigned int *tx_desc_base = NULL; -static unsigned int tx_desc_index = 0; - -/* local function declarations */ -static int galmpsc_connect (int channel, int connect); -static int galmpsc_route_rx_clock (int channel, int brg); -static int galmpsc_route_tx_clock (int channel, int brg); -static int galmpsc_write_config_regs (int mpsc, int mode); -static int galmpsc_config_channel_regs (int mpsc); -static int galmpsc_set_char_length (int mpsc, int value); -static int galmpsc_set_stop_bit_length (int mpsc, int value); -static int galmpsc_set_parity (int mpsc, int value); -static int galmpsc_enter_hunt (int mpsc); -static int galmpsc_set_brkcnt (int mpsc, int value); -static int galmpsc_set_tcschar (int mpsc, int value); -static int galmpsc_set_snoop (int mpsc, int value); -static int galmpsc_shutdown (int mpsc); - -static int galsdma_set_RFT (int channel); -static int galsdma_set_SFM (int channel); -static int galsdma_set_rxle (int channel); -static int galsdma_set_txle (int channel); -static int galsdma_set_burstsize (int channel, unsigned int value); -static int galsdma_set_RC (int channel, unsigned int value); - -static int galbrg_set_CDV (int channel, int value); -static int galbrg_enable (int channel); -static int galbrg_disable (int channel); -static int galbrg_set_clksrc (int channel, int value); -static int galbrg_set_CUV (int channel, int value); - -static void galsdma_enable_rx (void); -static int galsdma_set_mem_space (unsigned int memSpace, - unsigned int memSpaceTarget, - unsigned int memSpaceAttr, - unsigned int baseAddress, - unsigned int size); - - -#define SOFTWARE_CACHE_MANAGEMENT - -#ifdef SOFTWARE_CACHE_MANAGEMENT -#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));} -#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));} -#else -#define FLUSH_DCACHE(a,b) -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) -#define INVALIDATE_DCACHE(a,b) -#endif - -#ifdef CONFIG_MPSC_DEBUG_PORT -static void mpsc_debug_init (void) -{ - - volatile unsigned int temp; - - /* Clear the CFR (CHR4) */ - /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */ - temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP)); - temp &= 0xffffff00; - temp |= BIT29; - GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP), - temp); - - /* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */ - temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP)); - temp |= (BIT12 | BIT15); - GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP), - temp); - - /* Set int mask */ - temp = GTREGREAD (GALMPSC_0_INT_MASK); - temp |= BIT6; - GT_REG_WRITE (GALMPSC_0_INT_MASK, temp); -} -#endif - -char mpsc_getchar_debug (void) -{ - volatile int temp; - volatile unsigned int cause; - - cause = GTREGREAD (GALMPSC_0_INT_CAUSE); - while ((cause & BIT6) == 0) { - cause = GTREGREAD (GALMPSC_0_INT_CAUSE); - } - - temp = GTREGREAD (GALMPSC_CHANNELREG_10 + - (CHANNEL * GALMPSC_REG_GAP)); - /* By writing 1's to the set bits, the register is cleared */ - GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP), - temp); - GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6); - return (temp >> 16) & 0xff; -} - -/* special function for running out of flash. doesn't modify any - * global variables [josh] */ -int mpsc_putchar_early (char ch) -{ - int mpsc = CHANNEL; - int temp = - GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - galmpsc_set_tcschar (mpsc, ch); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), - temp | 0x200); - -#define MAGIC_FACTOR (10*1000000) - - udelay (MAGIC_FACTOR / gd->baudrate); - return 0; -} - -/* This is used after relocation, see serial.c and mpsc_init2 */ -static int mpsc_putchar_sdma (char ch) -{ - volatile unsigned int *p; - unsigned int temp; - - - /* align the descriptor */ - p = tx_desc_base; - memset ((void *) p, 0, 8 * sizeof (unsigned int)); - - /* fill one 64 bit buffer */ - /* word swap, pad with 0 */ - p[4] = 0; /* x */ - p[5] = (unsigned int) ch; /* x */ - - /* CHANGED completely according to GT64260A dox - NTL */ - p[0] = 0x00010001; /* 0 */ - p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* 4 */ - p[2] = 0; /* 8 */ - p[3] = (unsigned int) &p[4]; /* c */ - -#if 0 - p[9] = DESC_FIRST | DESC_LAST; - p[10] = (unsigned int) &p[0]; - p[11] = (unsigned int) &p[12]; -#endif - - FLUSH_DCACHE (&p[0], &p[8]); - - GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &p[0]); - GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &p[0]); - - temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF)); - temp |= (TX_DEMAND | TX_STOP); - GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp); - - INVALIDATE_DCACHE (&p[1], &p[2]); - - while (p[1] & DESC_OWNER_BIT) { - udelay (100); - INVALIDATE_DCACHE (&p[1], &p[2]); - } - return 0; -} - -char mpsc_getchar_sdma (void) -{ - static unsigned int done = 0; - volatile char ch; - unsigned int len = 0, idx = 0, temp; - - volatile unsigned int *p; - - - do { - p = &rx_desc_base[rx_desc_index * 8]; - - INVALIDATE_DCACHE (&p[0], &p[1]); - /* Wait for character */ - while (p[1] & DESC_OWNER_BIT) { - udelay (100); - INVALIDATE_DCACHE (&p[0], &p[1]); - } - - /* Handle error case */ - if (p[1] & (1 << 15)) { - printf ("oops, error: %08x\n", p[1]); - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + - (CHANNEL * GALMPSC_REG_GAP)); - temp |= (1 << 23); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + - (CHANNEL * GALMPSC_REG_GAP), temp); - - /* Can't poll on abort bit, so we just wait. */ - udelay (100); - - galsdma_enable_rx (); - } - - /* Number of bytes left in this descriptor */ - len = p[0] & 0xffff; - - if (len) { - /* Where to look */ - idx = 5; - if (done > 3) - idx = 4; - if (done > 7) - idx = 7; - if (done > 11) - idx = 6; - - INVALIDATE_DCACHE (&p[idx], &p[idx + 1]); - ch = p[idx] & 0xff; - done++; - } - - if (done < len) { - /* this descriptor has more bytes still - * shift down the char we just read, and leave the - * buffer in place for the next time around - */ - p[idx] = p[idx] >> 8; - FLUSH_DCACHE (&p[idx], &p[idx + 1]); - } - - if (done == len) { - /* nothing left in this descriptor. - * go to next one - */ - p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; - p[0] = 0x00100000; - FLUSH_DCACHE (&p[0], &p[1]); - /* Next descriptor */ - rx_desc_index = (rx_desc_index + 1) % RX_DESC; - done = 0; - } - } while (len == 0); /* galileo bug.. len might be zero */ - - return ch; -} - - -int mpsc_test_char_debug (void) -{ - if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0) - return 0; - else { - return 1; - } -} - - -int mpsc_test_char_sdma (void) -{ - volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8]; - - INVALIDATE_DCACHE (&p[1], &p[2]); - - if (p[1] & DESC_OWNER_BIT) - return 0; - else - return 1; -} - -int mpsc_init (int baud) -{ - /* BRG CONFIG */ - galbrg_set_baudrate (CHANNEL, baud); - galbrg_set_clksrc (CHANNEL, 8); /* set source=Tclk */ - galbrg_set_CUV (CHANNEL, 0); /* set up CountUpValue */ - galbrg_enable (CHANNEL); /* Enable BRG */ - - /* Set up clock routing */ - galmpsc_connect (CHANNEL, GALMPSC_CONNECT); /* connect it */ - - galmpsc_route_rx_clock (CHANNEL, CHANNEL); /* chosse BRG0 for Rx */ - galmpsc_route_tx_clock (CHANNEL, CHANNEL); /* chose BRG0 for Tx */ - - /* reset MPSC state */ - galmpsc_shutdown (CHANNEL); - - /* SDMA CONFIG */ - galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8); /* in 64 bit words (8 bytes) */ - galsdma_set_txle (CHANNEL); - galsdma_set_rxle (CHANNEL); - galsdma_set_RC (CHANNEL, 0xf); - galsdma_set_SFM (CHANNEL); - galsdma_set_RFT (CHANNEL); - - /* MPSC CONFIG */ - galmpsc_write_config_regs (CHANNEL, GALMPSC_UART); - galmpsc_config_channel_regs (CHANNEL); - galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8); /* 8 */ - galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE); /* N */ - galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */ - -#ifdef CONFIG_MPSC_DEBUG_PORT - mpsc_debug_init (); -#endif - - /* COMM_MPSC CONFIG */ -#ifdef SOFTWARE_CACHE_MANAGEMENT - galmpsc_set_snoop (CHANNEL, 0); /* disable snoop */ -#else - galmpsc_set_snoop (CHANNEL, 1); /* enable snoop */ -#endif - - return 0; -} - - -void mpsc_sdma_init (void) -{ -/* Setup SDMA channel0 SDMA_CONFIG_REG*/ - GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff); - -/* Enable MPSC-Window0 for DRAM Bank0 */ - if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT, - MV64360_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_0_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK0)) != true) - printf ("%s: SDMA_Window0 memory setup failed !!! \n", - __FUNCTION__); - - -/* Disable MPSC-Window1 */ - if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_1_BIT, - MV64360_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_1_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK3)) != true) - printf ("%s: SDMA_Window1 memory setup failed !!! \n", - __FUNCTION__); - - -/* Disable MPSC-Window2 */ - if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_2_BIT, - MV64360_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_2_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK3)) != true) - printf ("%s: SDMA_Window2 memory setup failed !!! \n", - __FUNCTION__); - - -/* Disable MPSC-Window3 */ - if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_3_BIT, - MV64360_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_3_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK3)) != true) - printf ("%s: SDMA_Window3 memory setup failed !!! \n", - __FUNCTION__); - -/* Setup MPSC0 access mode Window0 full access */ - GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG, - (MV64360_SDMA_WIN_ACCESS_FULL << - (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); - -/* Setup MPSC1 access mode Window1 full access */ - GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG, - (MV64360_SDMA_WIN_ACCESS_FULL << - (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); - -/* Setup MPSC internal address space base address */ - GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS); - -/* no high address remap*/ - GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00); - GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00); - -/* clear interrupt cause register for MPSC (fault register)*/ - GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00); -} - - -void mpsc_init2 (void) -{ - int i; - -#ifndef CONFIG_MPSC_DEBUG_PORT - mpsc_putchar = mpsc_putchar_sdma; - mpsc_getchar = mpsc_getchar_sdma; - mpsc_test_char = mpsc_test_char_sdma; -#endif - /* RX descriptors */ - rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) * - sizeof (unsigned int)); - - /* align descriptors */ - rx_desc_base = (unsigned int *) - (((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0); - - rx_desc_index = 0; - - memset ((void *) rx_desc_base, 0, - (RX_DESC * 8) * sizeof (unsigned int)); - - for (i = 0; i < RX_DESC; i++) { - rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4]; /* Buffer */ - rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8]; /* Next descriptor */ - rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* Command & control */ - rx_desc_base[i * 8] = 0x00100000; - } - rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0]; - - FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]); - GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &rx_desc_base[0]); - - /* TX descriptors */ - tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) * - sizeof (unsigned int)); - - /* align descriptors */ - tx_desc_base = (unsigned int *) - (((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0); - - tx_desc_index = -1; - - memset ((void *) tx_desc_base, 0, - (TX_DESC * 8) * sizeof (unsigned int)); - - for (i = 0; i < TX_DESC; i++) { - tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323; - tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323; - tx_desc_base[i * 8 + 3] = - (unsigned int) &tx_desc_base[i * 8 + 4]; - tx_desc_base[i * 8 + 2] = - (unsigned int) &tx_desc_base[(i + 1) * 8]; - tx_desc_base[i * 8 + 1] = - DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; - - /* set sbytecnt and shadow byte cnt to 1 */ - tx_desc_base[i * 8] = 0x00010001; - } - tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0]; - - FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]); - - udelay (100); - - galsdma_enable_rx (); - - return; -} - -int galbrg_set_baudrate (int channel, int rate) -{ - int clock; - - galbrg_disable (channel); /*ok */ - -#ifdef ZUMA_NTL - /* from tclk */ - clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; -#else - clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; -#endif - - galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */ - - galbrg_enable (channel); - - gd->baudrate = rate; - - return 0; -} - -/* ------------------------------------------------------------------ */ - -/* Below are all the private functions that no one else needs */ - -static int galbrg_set_CDV (int channel, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFFF0000; - temp |= (value & 0x0000FFFF); - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_enable (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp |= 0x00010000; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_disable (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFFEFFFF; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_set_clksrc (int channel, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFC3FFFF; /* Bit 18 - 21 (MV 64260 18-22) */ - temp |= (value << 18); - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - return 0; -} - -static int galbrg_set_CUV (int channel, int value) -{ - /* set CountUpValue */ - GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value); - - return 0; -} - -#if 0 -static int galbrg_reset (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp |= 0x20000; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} -#endif - -static int galsdma_set_RFT (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000001; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_SFM (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000002; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_rxle (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000040; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_txle (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000080; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_RC (int channel, unsigned int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp &= ~0x0000003c; - temp |= (value << 2); - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_burstsize (int channel, unsigned int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp &= 0xFFFFCFFF; - switch (value) { - case 8: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x3 << 12))); - break; - - case 4: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x2 << 12))); - break; - - case 2: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x1 << 12))); - break; - - case 1: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x0 << 12))); - break; - - default: - return -1; - break; - } - - return 0; -} - -static int galmpsc_connect (int channel, int connect) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_ROUTING_REGISTER); - - if ((channel == 0) && connect) - temp &= ~0x00000007; - else if ((channel == 1) && connect) - temp &= ~(0x00000007 << 6); - else if ((channel == 0) && !connect) - temp |= 0x00000007; - else - temp |= (0x00000007 << 6); - - /* Just in case... */ - temp &= 0x3fffffff; - - GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp); - - return 0; -} - -static int galmpsc_route_rx_clock (int channel, int brg) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_RxC_ROUTE); - - if (channel == 0) { - temp &= ~0x0000000F; - temp |= brg; - } else { - temp &= ~0x00000F00; - temp |= (brg << 8); - } - - GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp); - - return 0; -} - -static int galmpsc_route_tx_clock (int channel, int brg) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_TxC_ROUTE); - - if (channel == 0) { - temp &= ~0x0000000F; - temp |= brg; - } else { - temp &= ~0x00000F00; - temp |= (brg << 8); - } - - GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp); - - return 0; -} - -static int galmpsc_write_config_regs (int mpsc, int mode) -{ - if (mode == GALMPSC_UART) { - /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */ - GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP), - 0x000004c4); - - /* Main config reg High (32x Rx/Tx clock mode, width=8bits */ - GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP), - 0x024003f8); - /* 22 2222 1111 */ - /* 54 3210 9876 */ - /* 0000 0010 0000 0000 */ - /* 1 */ - /* 098 7654 3210 */ - /* 0000 0011 1111 1000 */ - } else - return -1; - - return 0; -} - -static int galmpsc_config_channel_regs (int mpsc) -{ - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1); - GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0); - - galmpsc_set_brkcnt (mpsc, 0x3); - galmpsc_set_tcschar (mpsc, 0xab); - - return 0; -} - -static int galmpsc_set_brkcnt (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP)); - temp &= 0x0000FFFF; - temp |= (value << 16); - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_tcschar (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFF0000; - temp |= value; - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_char_length (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFFCFFF; - temp |= (value << 12); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_stop_bit_length (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFFBFFF; - temp |= (value << 14); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_parity (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - if (value != -1) { - temp &= 0xFFF3FFF3; - temp |= ((value << 18) | (value << 2)); - temp |= ((value << 17) | (value << 1)); - } else { - temp &= 0xFFF1FFF1; - } - - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_enter_hunt (int mpsc) -{ - int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - temp |= 0x80000000; - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) & - MPSC_ENTER_HUNT) { - udelay (1); - } - return 0; -} - - -static int galmpsc_shutdown (int mpsc) -{ - unsigned int temp; - - /* cause RX abort (clears RX) */ - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - temp |= MPSC_RX_ABORT | MPSC_TX_ABORT; - temp &= ~MPSC_ENTER_HUNT; - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - GT_REG_WRITE (GALSDMA_0_COM_REG, 0); - GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT); - - /* shut down the MPSC */ - GT_REG_WRITE (GALMPSC_MCONF_LOW, 0); - GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0); - - udelay (100); - - /* shut down the sdma engines. */ - /* reset config to default */ - GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc); - - udelay (100); - - /* clear the SDMA current and first TX and RX pointers */ - GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0); - GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0); - GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0); - - udelay (100); - - return 0; -} - -static void galsdma_enable_rx (void) -{ - int temp; - - /* Enable RX processing */ - temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF)); - temp |= RX_ENABLE; - GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp); - - galmpsc_enter_hunt (CHANNEL); -} - -static int galmpsc_set_snoop (int mpsc, int value) -{ - int reg = - mpsc ? MPSC_1_ADDRESS_CONTROL_LOW : - MPSC_0_ADDRESS_CONTROL_LOW; - int temp = GTREGREAD (reg); - - if (value) - temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30); - else - temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30)); - GT_REG_WRITE (reg, temp); - return 0; -} - -/******************************************************************************* -* galsdma_set_mem_space - Set MV64360 IDMA memory decoding map. -* -* DESCRIPTION: -* the MV64360 SDMA has its own address decoding map that is de-coupled -* from the CPU interface address decoding windows. The SDMA channels -* share four address windows. Each region can be individually configured -* by this function by associating it to a target interface and setting -* base and size values. -* -* NOTE!!! -* The size must be in 64Kbyte granularity. -* The base address must be aligned to the size. -* The size must be a series of 1s followed by a series of zeros -* -* OUTPUT: -* None. -* -* RETURN: -* true for success, false otherwise. -* -*******************************************************************************/ - -static int galsdma_set_mem_space (unsigned int memSpace, - unsigned int memSpaceTarget, - unsigned int memSpaceAttr, - unsigned int baseAddress, unsigned int size) -{ - unsigned int temp; - - if (size == 0) { - GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG, - 1 << memSpace); - return true; - } - - /* The base address must be aligned to the size. */ - if (baseAddress % size != 0) { - return false; - } - if (size < 0x10000) { - return false; - } - - /* Align size and base to 64K */ - baseAddress &= 0xffff0000; - size &= 0xffff0000; - temp = size >> 16; - - /* Checking that the size is a sequence of '1' followed by a - sequence of '0' starting from LSB to MSB. */ - while ((temp > 0) && (temp & 0x1)) { - temp = temp >> 1; - } - - if (temp != 0) { - GT_REG_WRITE (MV64360_CUNIT_BASE_ADDR_REG0 + memSpace * 8, - (baseAddress | memSpaceTarget | memSpaceAttr)); - GT_REG_WRITE ((MV64360_CUNIT_SIZE0 + memSpace * 8), - (size - 1) & 0xffff0000); - GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG, - 1 << memSpace); - } else { - /* An invalid size was specified */ - return false; - } - return true; -} diff --git a/board/Marvell/db64360/mpsc.h b/board/Marvell/db64360/mpsc.h deleted file mode 100644 index ca1e89a..0000000 --- a/board/Marvell/db64360/mpsc.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * (C) Copyright 2001 - * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com> - * - ************************************************************************/ - - -/* - * mpsc.h - header file for MPSC in uart mode (console driver) - */ - -#ifndef __MPSC_H__ -#define __MPSC_H__ - -/* include actual Galileo defines */ -#include "../include/mv_gen_reg.h" - -/* driver related defines */ - -int mpsc_init(int baud); -void mpsc_sdma_init(void); -void mpsc_init2(void); -int galbrg_set_baudrate(int channel, int rate); - -int mpsc_putchar_early(char ch); -char mpsc_getchar_debug(void); -int mpsc_test_char_debug(void); - -int mpsc_test_char_sdma(void); - -extern int (*mpsc_putchar)(char ch); -extern char (*mpsc_getchar)(void); -extern int (*mpsc_test_char)(void); - -#define CHANNEL CONFIG_MPSC_PORT - -#define TX_DESC 5 -#define RX_DESC 20 - -#define DESC_FIRST 0x00010000 -#define DESC_LAST 0x00020000 -#define DESC_OWNER_BIT 0x80000000 - -#define TX_DEMAND 0x00800000 -#define TX_STOP 0x00010000 -#define RX_ENABLE 0x00000080 - -#define SDMA_RX_ABORT (1 << 15) -#define SDMA_TX_ABORT (1 << 31) -#define MPSC_TX_ABORT (1 << 7) -#define MPSC_RX_ABORT (1 << 23) -#define MPSC_ENTER_HUNT (1 << 31) - -/* MPSC defines */ - -#define GALMPSC_CONNECT 0x1 -#define GALMPSC_DISCONNECT 0x0 - -#define GALMPSC_UART 0x1 - -#define GALMPSC_STOP_BITS_1 0x0 -#define GALMPSC_STOP_BITS_2 0x1 -#define GALMPSC_CHAR_LENGTH_8 0x3 -#define GALMPSC_CHAR_LENGTH_7 0x2 - -#define GALMPSC_PARITY_ODD 0x0 -#define GALMPSC_PARITY_EVEN 0x2 -#define GALMPSC_PARITY_MARK 0x3 -#define GALMPSC_PARITY_SPACE 0x1 -#define GALMPSC_PARITY_NONE -1 - -#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */ -#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */ -#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */ -#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */ -#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */ -#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */ -#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */ - -#define GALMPSC_REG_GAP 0x1000 - -#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */ -#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */ -#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */ -#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */ -#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */ -#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */ -#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */ -#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */ -#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */ -#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */ -#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */ -#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */ - -#define GALSDMA_COMMAND_FIRST (1 << 16) -#define GALSDMA_COMMAND_LAST (1 << 17) -#define GALSDMA_COMMAND_ENABLEINT (1 << 23) -#define GALSDMA_COMMAND_AUTO (1 << 30) -#define GALSDMA_COMMAND_OWNER (1 << 31) - -#define GALSDMA_RX 0 -#define GALSDMA_TX 1 - -/* CHANNEL2 should be CHANNEL1, according to documentation, - * but to work with the current GTREGS file... - */ -#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */ -#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */ -#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */ -#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */ -#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */ -#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */ -#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */ -#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */ -#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */ -#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */ -#define GALSDMA_REG_DIFF 0x2000 - -/* WRONG in gt64260R.h */ -#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */ -#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */ -#define GALMPSC_0_INT_CAUSE 0xb804 -#define GALMPSC_0_INT_MASK 0xb884 - -#define GALSDMA_MODE_UART 0 -#define GALSDMA_MODE_BISYNC 1 -#define GALSDMA_MODE_HDLC 2 -#define GALSDMA_MODE_TRANSPARENT 3 - -#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */ -#define GALBRG_REG_GAP 0x0008 -#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */ - -#endif /* __MPSC_H__ */ diff --git a/board/Marvell/db64360/mv_eth.c b/board/Marvell/db64360/mv_eth.c deleted file mode 100644 index b2df1f7..0000000 --- a/board/Marvell/db64360/mv_eth.c +++ /dev/null @@ -1,3128 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus <ingo.assmus@keymile.com> - * - * based on - Driver for MV64360X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mv_eth.c - header file for the polled mode GT ethernet driver - */ -#include <common.h> -#include <net.h> -#include <malloc.h> - -#include "mv_eth.h" - -/* enable Debug outputs */ - -#undef DEBUG_MV_ETH - -#ifdef DEBUG_MV_ETH -#define DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -#undef MV64360_CHECKSUM_OFFLOAD -/************************************************************************* -************************************************************************** -************************************************************************** -* The first part is the high level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ - -/* Definition for configuring driver */ -/* #define UPDATE_STATS_BY_SOFTWARE */ -#undef MV64360_RX_QUEUE_FILL_ON_TASK - - -/* Constants */ -#define MAGIC_ETH_RUNNING 8031971 -#define MV64360_INTERNAL_SRAM_SIZE _256K -#define EXTRA_BYTES 32 -#define WRAP ETH_HLEN + 2 + 4 + 16 -#define BUFFER_MTU dev->mtu + WRAP -#define INT_CAUSE_UNMASK_ALL 0x0007ffff -#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff -#ifdef MV64360_RX_FILL_ON_TASK -#define INT_CAUSE_MASK_ALL 0x00000000 -#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL -#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT -#endif - -/* Read/Write to/from MV64360 internal registers */ -#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset)) -#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data) -#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits))) -#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits))) - -/* Static function declarations */ -static int mv64360_eth_real_open (struct eth_device *eth); -static int mv64360_eth_real_stop (struct eth_device *eth); -static struct net_device_stats *mv64360_eth_get_stats (struct eth_device - *dev); -static void eth_port_init_mac_tables (ETH_PORT eth_port_num); -static void mv64360_eth_update_stat (struct eth_device *dev); -bool db64360_eth_start (struct eth_device *eth); -unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, - unsigned int mib_offset); -int mv64360_eth_receive (struct eth_device *dev); - -int mv64360_eth_xmit (struct eth_device *, volatile void *packet, int length); - -#ifndef UPDATE_STATS_BY_SOFTWARE -static void mv64360_eth_print_stat (struct eth_device *dev); -#endif - -extern unsigned int INTERNAL_REG_BASE_ADDR; - -/************************************************* - *Helper functions - used inside the driver only * - *************************************************/ -#ifdef DEBUG_MV_ETH -void print_globals (struct eth_device *dev) -{ - printf ("Ethernet PRINT_Globals-Debug function\n"); - printf ("Base Address for ETH_PORT_INFO: %08x\n", - (unsigned int) dev->priv); - printf ("Base Address for mv64360_eth_priv: %08x\n", - (unsigned int) &(((ETH_PORT_INFO *) dev->priv)-> - port_private)); - - printf ("GT Internal Base Address: %08x\n", - INTERNAL_REG_BASE_ADDR); - printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64360_TX_QUEUE_SIZE); - printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64360_RX_QUEUE_SIZE); - printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n", - (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> - p_rx_buffer_base[0], - (MV64360_RX_QUEUE_SIZE * MV64360_RX_BUFFER_SIZE) + 32); - printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n", - (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> - p_tx_buffer_base[0], - (MV64360_TX_QUEUE_SIZE * MV64360_TX_BUFFER_SIZE) + 32); -} -#endif - -#define my_cpu_to_le32(x) my_le32_to_cpu((x)) - -unsigned long my_le32_to_cpu (unsigned long x) -{ - return (((x & 0x000000ffU) << 24) | - ((x & 0x0000ff00U) << 8) | - ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24)); -} - - -/********************************************************************** - * mv64360_eth_print_phy_status - * - * Prints gigabit ethenret phy status - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64360_eth_print_phy_status (struct eth_device *dev) -{ - struct mv64360_eth_priv *port_private; - unsigned int port_num; - ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv; - unsigned int port_status, phy_reg_data; - - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Check Link status on phy */ - eth_port_read_smi_reg (port_num, 1, &phy_reg_data); - if (!(phy_reg_data & 0x20)) { - printf ("Ethernet port changed link status to DOWN\n"); - } else { - port_status = - MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num)); - printf ("Ethernet status port %d: Link up", port_num); - printf (", %s", - (port_status & BIT2) ? "Full Duplex" : "Half Duplex"); - if (port_status & BIT4) - printf (", Speed 1 Gbps"); - else - printf (", %s", - (port_status & BIT5) ? "Speed 100 Mbps" : - "Speed 10 Mbps"); - printf ("\n"); - } -} - -/********************************************************************** - * u-boot entry functions for mv64360_eth - * - **********************************************************************/ -int db64360_eth_probe (struct eth_device *dev) -{ - return ((int) db64360_eth_start (dev)); -} - -int db64360_eth_poll (struct eth_device *dev) -{ - return mv64360_eth_receive (dev); -} - -int db64360_eth_transmit(struct eth_device *dev, void *packet, int length) -{ - mv64360_eth_xmit (dev, packet, length); - return 0; -} - -void db64360_eth_disable (struct eth_device *dev) -{ - mv64360_eth_stop (dev); -} - - -void mv6436x_eth_initialize (bd_t * bis) -{ - struct eth_device *dev; - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - int devnum, x, temp; - char *s, *e, buf[64]; - - for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) { - dev = calloc (sizeof (*dev), 1); - if (!dev) { - printf ("%s: mv_enet%d allocation failure, %s\n", - __FUNCTION__, devnum, "eth_device structure"); - return; - } - - /* must be less than sizeof(dev->name) */ - sprintf (dev->name, "mv_enet%d", devnum); - -#ifdef DEBUG - printf ("Initializing %s\n", dev->name); -#endif - - /* Extract the MAC address from the environment */ - switch (devnum) { - case 0: - s = "ethaddr"; - break; - - case 1: - s = "eth1addr"; - break; - - case 2: - s = "eth2addr"; - break; - - default: /* this should never happen */ - printf ("%s: Invalid device number %d\n", - __FUNCTION__, devnum); - return; - } - - temp = getenv_f(s, buf, sizeof (buf)); - s = (temp > 0) ? buf : NULL; - -#ifdef DEBUG - printf ("Setting MAC %d to %s\n", devnum, s); -#endif - for (x = 0; x < 6; ++x) { - dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - /* ronen - set the MAC addr in the HW */ - eth_port_uc_addr_set (devnum, dev->enetaddr, 0); - - dev->init = (void *) db64360_eth_probe; - dev->halt = (void *) ethernet_phy_reset; - dev->send = (void *) db64360_eth_transmit; - dev->recv = (void *) db64360_eth_poll; - - ethernet_private = calloc (sizeof (*ethernet_private), 1); - dev->priv = (void *) ethernet_private; - - if (!ethernet_private) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Private Device Structure"); - free (dev); - return; - } - /* start with an zeroed ETH_PORT_INFO */ - memset (ethernet_private, 0, sizeof (ETH_PORT_INFO)); - memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); - - /* set pointer to memory for stats data structure etc... */ - port_private = calloc (sizeof (*ethernet_private), 1); - ethernet_private->port_private = (void *)port_private; - if (!port_private) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Port Private Device Structure"); - - free (ethernet_private); - free (dev); - return; - } - - port_private->stats = - calloc (sizeof (struct net_device_stats), 1); - if (!port_private->stats) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Net stat Structure"); - - free (port_private); - free (ethernet_private); - free (dev); - return; - } - memset (ethernet_private->port_private, 0, - sizeof (struct mv64360_eth_priv)); - switch (devnum) { - case 0: - ethernet_private->port_num = ETH_0; - break; - case 1: - ethernet_private->port_num = ETH_1; - break; - case 2: - ethernet_private->port_num = ETH_2; - break; - default: - printf ("Invalid device number %d\n", devnum); - break; - }; - - port_private->port_num = devnum; - /* - * Read MIB counter on the GT in order to reset them, - * then zero all the stats fields in memory - */ - mv64360_eth_update_stat (dev); - memset (port_private->stats, 0, - sizeof (struct net_device_stats)); - /* Extract the MAC address from the environment */ - switch (devnum) { - case 0: - s = "ethaddr"; - break; - - case 1: - s = "eth1addr"; - break; - - case 2: - s = "eth2addr"; - break; - - default: /* this should never happen */ - printf ("%s: Invalid device number %d\n", - __FUNCTION__, devnum); - return; - } - - temp = getenv_f(s, buf, sizeof (buf)); - s = (temp > 0) ? buf : NULL; - -#ifdef DEBUG - printf ("Setting MAC %d to %s\n", devnum, s); -#endif - for (x = 0; x < 6; ++x) { - dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - - DP (printf ("Allocating descriptor and buffer rings\n")); - - ethernet_private->p_rx_desc_area_base[0] = - (ETH_RX_DESC *) memalign (16, - RX_DESC_ALIGNED_SIZE * - MV64360_RX_QUEUE_SIZE + 1); - ethernet_private->p_tx_desc_area_base[0] = - (ETH_TX_DESC *) memalign (16, - TX_DESC_ALIGNED_SIZE * - MV64360_TX_QUEUE_SIZE + 1); - - ethernet_private->p_rx_buffer_base[0] = - (char *) memalign (16, - MV64360_RX_QUEUE_SIZE * - MV64360_TX_BUFFER_SIZE + 1); - ethernet_private->p_tx_buffer_base[0] = - (char *) memalign (16, - MV64360_RX_QUEUE_SIZE * - MV64360_TX_BUFFER_SIZE + 1); - -#ifdef DEBUG_MV_ETH - /* DEBUG OUTPUT prints adresses of globals */ - print_globals (dev); -#endif - eth_register (dev); - - } - DP (printf ("%s: exit\n", __FUNCTION__)); - -} - -/********************************************************************** - * mv64360_eth_open - * - * This function is called when openning the network device. The function - * should initialize all the hardware, initialize cyclic Rx/Tx - * descriptors chain and buffers and allocate an IRQ to the network - * device. - * - * Input : a pointer to the network device structure - * / / ronen - changed the output to match net/eth.c needs - * Output : nonzero of success , zero if fails. - * under construction - **********************************************************************/ - -int mv64360_eth_open (struct eth_device *dev) -{ - return (mv64360_eth_real_open (dev)); -} - -/* Helper function for mv64360_eth_open */ -static int mv64360_eth_real_open (struct eth_device *dev) -{ - - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - u32 phy_reg_data; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - /* ronen - when we update the MAC env params we only update dev->enetaddr - see ./net/eth.c eth_set_enetaddr() */ - memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); - - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Stop RX Queues */ - MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Clear the ethernet port interrupts */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0); - MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); - - /* Unmask RX buffer and TX end interrupt */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), - INT_CAUSE_UNMASK_ALL); - - /* Unmask phy and link status changes interrupts */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), - INT_CAUSE_UNMASK_ALL_EXT); - - /* Set phy address of the port */ - ethernet_private->port_phy_addr = 0x8 + port_num; - - /* Activate the DMA channels etc */ - eth_port_init (ethernet_private); - - - /* "Allocate" setup TX rings */ - - for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) { - unsigned int size; - - port_private->tx_ring_size[queue] = MV64360_TX_QUEUE_SIZE; - size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */ - ethernet_private->tx_desc_area_size[queue] = size; - - /* first clear desc area completely */ - memset ((void *) ethernet_private->p_tx_desc_area_base[queue], - 0, ethernet_private->tx_desc_area_size[queue]); - - /* initialize tx desc ring with low level driver */ - if (ether_init_tx_desc_ring - (ethernet_private, ETH_Q0, - port_private->tx_ring_size[queue], - MV64360_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , - (unsigned int) ethernet_private-> - p_tx_desc_area_base[queue], - (unsigned int) ethernet_private-> - p_tx_buffer_base[queue]) == false) - printf ("### Error initializing TX Ring\n"); - } - - /* "Allocate" setup RX rings */ - for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) { - unsigned int size; - - /* Meantime RX Ring are fixed - but must be configurable by user */ - port_private->rx_ring_size[queue] = MV64360_RX_QUEUE_SIZE; - size = (port_private->rx_ring_size[queue] * - RX_DESC_ALIGNED_SIZE); - ethernet_private->rx_desc_area_size[queue] = size; - - /* first clear desc area completely */ - memset ((void *) ethernet_private->p_rx_desc_area_base[queue], - 0, ethernet_private->rx_desc_area_size[queue]); - if ((ether_init_rx_desc_ring - (ethernet_private, ETH_Q0, - port_private->rx_ring_size[queue], - MV64360_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , - (unsigned int) ethernet_private-> - p_rx_desc_area_base[queue], - (unsigned int) ethernet_private-> - p_rx_buffer_base[queue])) == false) - printf ("### Error initializing RX Ring\n"); - } - - eth_port_start (ethernet_private); - - /* Set maximum receive buffer to 9700 bytes */ - MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num), - (0x5 << 17) | - (MV_REG_READ - (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num)) - & 0xfff1ffff)); - - /* - * Set ethernet MTU for leaky bucket mechanism to 0 - this will - * disable the leaky bucket mechanism . - */ - - MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0); - MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num)); - - /* Check Link status on phy */ - eth_port_read_smi_reg (port_num, 1, &phy_reg_data); - if (!(phy_reg_data & 0x20)) { - /* Reset PHY */ - if ((ethernet_phy_reset (port_num)) != true) { - printf ("$$ Warnning: No link on port %d \n", - port_num); - return 0; - } else { - eth_port_read_smi_reg (port_num, 1, &phy_reg_data); - if (!(phy_reg_data & 0x20)) { - printf ("### Error: Phy is not active\n"); - return 0; - } - } - } else { - mv64360_eth_print_phy_status (dev); - } - port_private->eth_running = MAGIC_ETH_RUNNING; - return 1; -} - - -static int mv64360_eth_free_tx_rings (struct eth_device *dev) -{ - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - volatile ETH_TX_DESC *p_tx_curr_desc; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Stop Tx Queues */ - MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Free TX rings */ - DP (printf ("Clearing previously allocated TX queues... ")); - for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) { - /* Free on TX rings */ - for (p_tx_curr_desc = - ethernet_private->p_tx_desc_area_base[queue]; - ((unsigned int) p_tx_curr_desc <= (unsigned int) - ethernet_private->p_tx_desc_area_base[queue] + - ethernet_private->tx_desc_area_size[queue]); - p_tx_curr_desc = - (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc + - TX_DESC_ALIGNED_SIZE)) { - /* this is inside for loop */ - if (p_tx_curr_desc->return_info != 0) { - p_tx_curr_desc->return_info = 0; - DP (printf ("freed\n")); - } - } - DP (printf ("Done\n")); - } - return 0; -} - -static int mv64360_eth_free_rx_rings (struct eth_device *dev) -{ - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - volatile ETH_RX_DESC *p_rx_curr_desc; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - - /* Stop RX Queues */ - MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Free RX rings */ - DP (printf ("Clearing previously allocated RX queues... ")); - for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) { - /* Free preallocated skb's on RX rings */ - for (p_rx_curr_desc = - ethernet_private->p_rx_desc_area_base[queue]; - (((unsigned int) p_rx_curr_desc < - ((unsigned int) ethernet_private-> - p_rx_desc_area_base[queue] + - ethernet_private->rx_desc_area_size[queue]))); - p_rx_curr_desc = - (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc + - RX_DESC_ALIGNED_SIZE)) { - if (p_rx_curr_desc->return_info != 0) { - p_rx_curr_desc->return_info = 0; - DP (printf ("freed\n")); - } - } - DP (printf ("Done\n")); - } - return 0; -} - -/********************************************************************** - * mv64360_eth_stop - * - * This function is used when closing the network device. - * It updates the hardware, - * release all memory that holds buffers and descriptors and release the IRQ. - * Input : a pointer to the device structure - * Output : zero if success , nonzero if fails - *********************************************************************/ - -int mv64360_eth_stop (struct eth_device *dev) -{ - /* Disable all gigE address decoder */ - MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f); - DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__)); - mv64360_eth_real_stop (dev); - - return 0; -}; - -/* Helper function for mv64360_eth_stop */ - -static int mv64360_eth_real_stop (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - - mv64360_eth_free_tx_rings (dev); - mv64360_eth_free_rx_rings (dev); - - eth_port_reset (ethernet_private->port_num); - /* Disable ethernet port interrupts */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0); - MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); - /* Mask RX buffer and TX end interrupt */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), 0); - /* Mask phy and link status changes interrupts */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0); - MV_RESET_REG_BITS (MV64360_CPU_INTERRUPT0_MASK_HIGH, - BIT0 << port_num); - /* Print Network statistics */ -#ifndef UPDATE_STATS_BY_SOFTWARE - /* - * Print statistics (only if ethernet is running), - * then zero all the stats fields in memory - */ - if (port_private->eth_running == MAGIC_ETH_RUNNING) { - port_private->eth_running = 0; - mv64360_eth_print_stat (dev); - } - memset (port_private->stats, 0, sizeof (struct net_device_stats)); -#endif - DP (printf ("\nEthernet stopped ... \n")); - return 0; -} - - -/********************************************************************** - * mv64360_eth_start_xmit - * - * This function is queues a packet in the Tx descriptor for - * required port. - * - * Input : skb - a pointer to socket buffer - * dev - a pointer to the required port - * - * Output : zero upon success - **********************************************************************/ - -int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr, - int dataSize) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - PKT_INFO pkt_info; - ETH_FUNC_RET_STATUS status; - struct net_device_stats *stats; - ETH_FUNC_RET_STATUS release_result; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - - stats = port_private->stats; - - /* Update packet info data structure */ - pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */ - pkt_info.byte_cnt = dataSize; - pkt_info.buf_ptr = (unsigned int) dataPtr; - pkt_info.return_info = 0; - - status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info); - if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) { - printf ("Error on transmitting packet .."); - if (status == ETH_QUEUE_FULL) - printf ("ETH Queue is full. \n"); - if (status == ETH_QUEUE_LAST_RESOURCE) - printf ("ETH Queue: using last available resource. \n"); - goto error; - } - - /* Update statistics and start of transmittion time */ - stats->tx_bytes += dataSize; - stats->tx_packets++; - - /* Check if packet(s) is(are) transmitted correctly (release everything) */ - do { - release_result = - eth_tx_return_desc (ethernet_private, ETH_Q0, - &pkt_info); - switch (release_result) { - case ETH_OK: - DP (printf ("descriptor released\n")); - if (pkt_info.cmd_sts & BIT0) { - printf ("Error in TX\n"); - stats->tx_errors++; - - } - break; - case ETH_RETRY: - DP (printf ("transmission still in process\n")); - break; - - case ETH_ERROR: - printf ("routine can not access Tx desc ring\n"); - break; - - case ETH_END_OF_JOB: - DP (printf ("the routine has nothing to release\n")); - break; - default: /* should not happen */ - break; - } - } while (release_result == ETH_OK); - - - return 0; /* success */ - error: - return 1; /* Failed - higher layers will free the skb */ -} - -/********************************************************************** - * mv64360_eth_receive - * - * This function is forward packets that are received from the port's - * queues toward kernel core or FastRoute them to another interface. - * - * Input : dev - a pointer to the required interface - * max - maximum number to receive (0 means unlimted) - * - * Output : number of served packets - **********************************************************************/ - -int mv64360_eth_receive (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - PKT_INFO pkt_info; - struct net_device_stats *stats; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - stats = port_private->stats; - - while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) == - ETH_OK)) { - -#ifdef DEBUG_MV_ETH - if (pkt_info.byte_cnt != 0) { - printf ("%s: Received %d byte Packet @ 0x%x\n", - __FUNCTION__, pkt_info.byte_cnt, - pkt_info.buf_ptr); - } -#endif - /* Update statistics. Note byte count includes 4 byte CRC count */ - stats->rx_packets++; - stats->rx_bytes += pkt_info.byte_cnt; - - /* - * In case received a packet without first / last bits on OR the error - * summary bit is on, the packets needs to be dropeed. - */ - if (((pkt_info. - cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != - (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) - || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) { - stats->rx_dropped++; - - printf ("Received packet spread on multiple descriptors\n"); - - /* Is this caused by an error ? */ - if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) { - stats->rx_errors++; - } - - /* free these descriptors again without forwarding them to the higher layers */ - pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ - pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ - - if (eth_rx_return_buff - (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { - printf ("Error while returning the RX Desc to Ring\n"); - } else { - DP (printf ("RX Desc returned to Ring\n")); - } - /* /free these descriptors again */ - } else { - -/* !!! call higher layer processing */ -#ifdef DEBUG_MV_ETH - printf ("\nNow send it to upper layer protocols (NetReceive) ...\n"); -#endif - /* let the upper layer handle the packet */ - NetReceive ((uchar *) pkt_info.buf_ptr, - (int) pkt_info.byte_cnt); - -/* **************************************************************** */ -/* free descriptor */ - pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ - pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ - DP (printf - ("RX: pkt_info.buf_ptr = %x\n", - pkt_info.buf_ptr)); - if (eth_rx_return_buff - (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { - printf ("Error while returning the RX Desc to Ring\n"); - } else { - DP (printf ("RX Desc returned to Ring\n")); - } - -/* **************************************************************** */ - - } - } - mv64360_eth_get_stats (dev); /* update statistics */ - return 1; -} - -/********************************************************************** - * mv64360_eth_get_stats - * - * Returns a pointer to the interface statistics. - * - * Input : dev - a pointer to the required interface - * - * Output : a pointer to the interface's statistics - **********************************************************************/ - -static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - - mv64360_eth_update_stat (dev); - - return port_private->stats; -} - - -/********************************************************************** - * mv64360_eth_update_stat - * - * Update the statistics structure in the private data structure - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64360_eth_update_stat (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - struct net_device_stats *stats; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - stats = port_private->stats; - - /* These are false updates */ - stats->rx_packets += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_FRAMES_RECEIVED); - stats->tx_packets += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_FRAMES_SENT); - stats->rx_bytes += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_RECEIVED_LOW); - /* - * Ideally this should be as follows - - * - * stats->rx_bytes += stats->rx_bytes + - * ((unsigned long) ethReadMibCounter (ethernet_private->port_num , - * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32); - * - * But the unsigned long in PowerPC and MIPS are 32bit. So the next read - * is just a dummy read for proper work of the GigE port - */ - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH); - stats->tx_bytes += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_SENT_LOW); - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_SENT_HIGH); - stats->rx_errors += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_MAC_RECEIVE_ERROR); - - /* Rx dropped is for received packet with CRC error */ - stats->rx_dropped += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_BAD_CRC_EVENT); - stats->multicast += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_MULTICAST_FRAMES_RECEIVED); - stats->collisions += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_COLLISION) + - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_LATE_COLLISION); - /* detailed rx errors */ - stats->rx_length_errors += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_UNDERSIZE_RECEIVED) - + - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_OVERSIZE_RECEIVED); - /* detailed tx errors */ -} - -#ifndef UPDATE_STATS_BY_SOFTWARE -/********************************************************************** - * mv64360_eth_print_stat - * - * Update the statistics structure in the private data structure - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64360_eth_print_stat (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - struct net_device_stats *stats; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - stats = port_private->stats; - - /* These are false updates */ - printf ("\n### Network statistics: ###\n"); - printf ("--------------------------\n"); - printf (" Packets received: %ld\n", stats->rx_packets); - printf (" Packets send: %ld\n", stats->tx_packets); - printf (" Received bytes: %ld\n", stats->rx_bytes); - printf (" Send bytes: %ld\n", stats->tx_bytes); - if (stats->rx_errors != 0) - printf (" Rx Errors: %ld\n", - stats->rx_errors); - if (stats->rx_dropped != 0) - printf (" Rx dropped (CRC Errors): %ld\n", - stats->rx_dropped); - if (stats->multicast != 0) - printf (" Rx mulicast frames: %ld\n", - stats->multicast); - if (stats->collisions != 0) - printf (" No. of collisions: %ld\n", - stats->collisions); - if (stats->rx_length_errors != 0) - printf (" Rx length errors: %ld\n", - stats->rx_length_errors); -} -#endif - -/************************************************************************** - *network_start - Network Kick Off Routine UBoot - *Inputs : - *Outputs : - **************************************************************************/ - -bool db64360_eth_start (struct eth_device *dev) -{ - return (mv64360_eth_open (dev)); /* calls real open */ -} - -/************************************************************************* -************************************************************************** -************************************************************************** -* The second part is the low level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ -/* - * based on Linux code - * arch/powerpc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * SPDX-License-Identifier: GPL-2.0+ - */ - -/******************************************************************************** - * Marvell's Gigabit Ethernet controller low level driver - * - * DESCRIPTION: - * This file introduce low level API to Marvell's Gigabit Ethernet - * controller. This Gigabit Ethernet Controller driver API controls - * 1) Operations (i.e. port init, start, reset etc'). - * 2) Data flow (i.e. port send, receive etc'). - * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO - * struct. - * This struct includes user configuration information as well as - * driver internal data needed for its operations. - * - * Supported Features: - * - This low level driver is OS independent. Allocating memory for - * the descriptor rings and buffers are not within the scope of - * this driver. - * - The user is free from Rx/Tx queue managing. - * - This low level driver introduce functionality API that enable - * the to operate Marvell's Gigabit Ethernet Controller in a - * convenient way. - * - Simple Gigabit Ethernet port operation API. - * - Simple Gigabit Ethernet port data flow API. - * - Data flow and operation API support per queue functionality. - * - Support cached descriptors for better performance. - * - Enable access to all four DRAM banks and internal SRAM memory - * spaces. - * - PHY access and control API. - * - Port control register configuration API. - * - Full control over Unicast and Multicast MAC configurations. - * - * Operation flow: - * - * Initialization phase - * This phase complete the initialization of the ETH_PORT_INFO - * struct. - * User information regarding port configuration has to be set - * prior to calling the port initialization routine. For example, - * the user has to assign the port_phy_addr field which is board - * depended parameter. - * In this phase any port Tx/Rx activity is halted, MIB counters - * are cleared, PHY address is set according to user parameter and - * access to DRAM and internal SRAM memory spaces. - * - * Driver ring initialization - * Allocating memory for the descriptor rings and buffers is not - * within the scope of this driver. Thus, the user is required to - * allocate memory for the descriptors ring and buffers. Those - * memory parameters are used by the Rx and Tx ring initialization - * routines in order to curve the descriptor linked list in a form - * of a ring. - * Note: Pay special attention to alignment issues when using - * cached descriptors/buffers. In this phase the driver store - * information in the ETH_PORT_INFO struct regarding each queue - * ring. - * - * Driver start - * This phase prepares the Ethernet port for Rx and Tx activity. - * It uses the information stored in the ETH_PORT_INFO struct to - * initialize the various port registers. - * - * Data flow: - * All packet references to/from the driver are done using PKT_INFO - * struct. - * This struct is a unified struct used with Rx and Tx operations. - * This way the user is not required to be familiar with neither - * Tx nor Rx descriptors structures. - * The driver's descriptors rings are management by indexes. - * Those indexes controls the ring resources and used to indicate - * a SW resource error: - * 'current' - * This index points to the current available resource for use. For - * example in Rx process this index will point to the descriptor - * that will be passed to the user upon calling the receive routine. - * In Tx process, this index will point to the descriptor - * that will be assigned with the user packet info and transmitted. - * 'used' - * This index points to the descriptor that need to restore its - * resources. For example in Rx process, using the Rx buffer return - * API will attach the buffer returned in packet info to the - * descriptor pointed by 'used'. In Tx process, using the Tx - * descriptor return will merely return the user packet info with - * the command status of the transmitted buffer pointed by the - * 'used' index. Nevertheless, it is essential to use this routine - * to update the 'used' index. - * 'first' - * This index supports Tx Scatter-Gather. It points to the first - * descriptor of a packet assembled of multiple buffers. For example - * when in middle of Such packet we have a Tx resource error the - * 'curr' index get the value of 'first' to indicate that the ring - * returned to its state before trying to transmit this packet. - * - * Receive operation: - * The eth_port_receive API set the packet information struct, - * passed by the caller, with received information from the - * 'current' SDMA descriptor. - * It is the user responsibility to return this resource back - * to the Rx descriptor ring to enable the reuse of this source. - * Return Rx resource is done using the eth_rx_return_buff API. - * - * Transmit operation: - * The eth_port_send API supports Scatter-Gather which enables to - * send a packet spanned over multiple buffers. This means that - * for each packet info structure given by the user and put into - * the Tx descriptors ring, will be transmitted only if the 'LAST' - * bit will be set in the packet info command status field. This - * API also consider restriction regarding buffer alignments and - * sizes. - * The user must return a Tx resource after ensuring the buffer - * has been transmitted to enable the Tx ring indexes to update. - * - * BOARD LAYOUT - * This device is on-board. No jumper diagram is necessary. - * - * EXTERNAL INTERFACE - * - * Prior to calling the initialization routine eth_port_init() the user - * must set the following fields under ETH_PORT_INFO struct: - * port_num User Ethernet port number. - * port_phy_addr User PHY address of Ethernet port. - * port_mac_addr[6] User defined port MAC address. - * port_config User port configuration value. - * port_config_extend User port config extend value. - * port_sdma_config User port SDMA config value. - * port_serial_control User port serial control value. - * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr. - * *port_private User scratch pad for user specific data structures. - * - * This driver introduce a set of default values: - * PORT_CONFIG_VALUE Default port configuration value - * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value - * PORT_SDMA_CONFIG_VALUE Default sdma control value - * PORT_SERIAL_CONTROL_VALUE Default port serial control value - * - * This driver data flow is done using the PKT_INFO struct which is - * a unified struct for Rx and Tx operations: - * byte_cnt Tx/Rx descriptor buffer byte count. - * l4i_chk CPU provided TCP Checksum. For Tx operation only. - * cmd_sts Tx/Rx descriptor command status. - * buf_ptr Tx/Rx descriptor buffer pointer. - * return_info Tx/Rx user resource return information. - * - * - * EXTERNAL SUPPORT REQUIREMENTS - * - * This driver requires the following external support: - * - * D_CACHE_FLUSH_LINE (address, address offset) - * - * This macro applies assembly code to flush and invalidate cache - * line. - * address - address base. - * address offset - address offset - * - * - * CPU_PIPE_FLUSH - * - * This macro applies assembly code to flush the CPU pipeline. - * - *******************************************************************************/ -/* includes */ - -/* defines */ -/* SDMA command macros */ -#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \ - MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue)) - -#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \ - MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\ - (1 << (8 + tx_queue))) - -#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \ -MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue)) - -#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \ -MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue))) - -#define CURR_RFD_GET(p_curr_desc, queue) \ - ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue]) - -#define CURR_RFD_SET(p_curr_desc, queue) \ - (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc)) - -#define USED_RFD_GET(p_used_desc, queue) \ - ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue]) - -#define USED_RFD_SET(p_used_desc, queue)\ -(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc)) - - -#define CURR_TFD_GET(p_curr_desc, queue) \ - ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue]) - -#define CURR_TFD_SET(p_curr_desc, queue) \ - (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc)) - -#define USED_TFD_GET(p_used_desc, queue) \ - ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue]) - -#define USED_TFD_SET(p_used_desc, queue) \ - (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc)) - -#define FIRST_TFD_GET(p_first_desc, queue) \ - ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue]) - -#define FIRST_TFD_SET(p_first_desc, queue) \ - (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc)) - - -/* Macros that save access to desc in order to find next desc pointer */ -#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) - -#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) - -#define LINK_UP_TIMEOUT 100000 -#define PHY_BUSY_TIMEOUT 10000000 - -/* locals */ - -/* PHY routines */ -static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr); -static int ethernet_phy_get (ETH_PORT eth_port_num); - -/* Ethernet Port routines */ -static void eth_set_access_control (ETH_PORT eth_port_num, - ETH_WIN_PARAM * param); -static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble, - ETH_QUEUE queue, int option); -#if 0 /* FIXME */ -static bool eth_port_smc_addr (ETH_PORT eth_port_num, - unsigned char mc_byte, - ETH_QUEUE queue, int option); -static bool eth_port_omc_addr (ETH_PORT eth_port_num, - unsigned char crc8, - ETH_QUEUE queue, int option); -#endif - -static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, - int byte_count); - -void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl); - - -typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK; -u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank) -{ - u32 result = 0; - u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE); - - if (enable & (1 << bank)) - return 0; - if (bank == BANK0) - result = MV_REG_READ (MV64360_CS_0_BASE_ADDR); - if (bank == BANK1) - result = MV_REG_READ (MV64360_CS_1_BASE_ADDR); - if (bank == BANK2) - result = MV_REG_READ (MV64360_CS_2_BASE_ADDR); - if (bank == BANK3) - result = MV_REG_READ (MV64360_CS_3_BASE_ADDR); - result &= 0x0000ffff; - result = result << 16; - return result; -} - -u32 mv_get_dram_bank_size (MEMORY_BANK bank) -{ - u32 result = 0; - u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE); - - if (enable & (1 << bank)) - return 0; - if (bank == BANK0) - result = MV_REG_READ (MV64360_CS_0_SIZE); - if (bank == BANK1) - result = MV_REG_READ (MV64360_CS_1_SIZE); - if (bank == BANK2) - result = MV_REG_READ (MV64360_CS_2_SIZE); - if (bank == BANK3) - result = MV_REG_READ (MV64360_CS_3_SIZE); - result += 1; - result &= 0x0000ffff; - result = result << 16; - return result; -} - -u32 mv_get_internal_sram_base (void) -{ - u32 result; - - result = MV_REG_READ (MV64360_INTEGRATED_SRAM_BASE_ADDR); - result &= 0x0000ffff; - result = result << 16; - return result; -} - -/******************************************************************************* -* eth_port_init - Initialize the Ethernet port driver -* -* DESCRIPTION: -* This function prepares the ethernet port to start its activity: -* 1) Completes the ethernet port driver struct initialization toward port -* start routine. -* 2) Resets the device to a quiescent state in case of warm reboot. -* 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. -* 4) Clean MAC tables. The reset status of those tables is unknown. -* 5) Set PHY address. -* Note: Call this routine prior to eth_port_start routine and after setting -* user values in the user fields of Ethernet port control struct (i.e. -* port_phy_addr). -* -* INPUT: -* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct -* -* OUTPUT: -* See description. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl) -{ - int queue; - ETH_WIN_PARAM win_param; - - p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE; - p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE; - p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE; - p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE; - - p_eth_port_ctrl->port_rx_queue_command = 0; - p_eth_port_ctrl->port_tx_queue_command = 0; - - /* Zero out SW structs */ - for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { - CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); - USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); - p_eth_port_ctrl->rx_resource_err[queue] = false; - } - - for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { - CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - p_eth_port_ctrl->tx_resource_err[queue] = false; - } - - eth_port_reset (p_eth_port_ctrl->port_num); - - /* Set access parameters for DRAM bank 0 */ - win_param.win = ETH_WIN0; /* Use Ethernet window 0 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK0); - win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 1 */ - win_param.win = ETH_WIN1; /* Use Ethernet window 1 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK1); - win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 2 */ - win_param.win = ETH_WIN2; /* Use Ethernet window 2 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK2); - win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 3 */ - win_param.win = ETH_WIN3; /* Use Ethernet window 3 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK3); - win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for Internal SRAM */ - win_param.win = ETH_WIN4; /* Use Ethernet window 0 */ - win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */ - win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0; - win_param.high_addr = 0; - win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */ - win_param.size = MV64360_INTERNAL_SRAM_SIZE; /* Get bank size */ - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - eth_port_init_mac_tables (p_eth_port_ctrl->port_num); - - ethernet_phy_set (p_eth_port_ctrl->port_num, - p_eth_port_ctrl->port_phy_addr); - - return; - -} - -/******************************************************************************* -* eth_port_start - Start the Ethernet port activity. -* -* DESCRIPTION: -* This routine prepares the Ethernet port for Rx and Tx activity: -* 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that -* has been initialized a descriptor's ring (using ether_init_tx_desc_ring -* for Tx and ether_init_rx_desc_ring for Rx) -* 2. Initialize and enable the Ethernet configuration port by writing to -* the port's configuration and command registers. -* 3. Initialize and enable the SDMA by writing to the SDMA's -* configuration and command registers. -* After completing these steps, the ethernet port SDMA can starts to -* perform Rx and Tx activities. -* -* Note: Each Rx and Tx queue descriptor's list must be initialized prior -* to calling this function (use ether_init_tx_desc_ring for Tx queues and -* ether_init_rx_desc_ring for Rx queues). -* -* INPUT: -* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct -* -* OUTPUT: -* Ethernet port is ready to receive and transmit. -* -* RETURN: -* false if the port PHY is not up. -* true otherwise. -* -*******************************************************************************/ -static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl) -{ - int queue; - volatile ETH_TX_DESC *p_tx_curr_desc; - volatile ETH_RX_DESC *p_rx_curr_desc; - unsigned int phy_reg_data; - ETH_PORT eth_port_num = p_eth_port_ctrl->port_num; - - - /* Assignment of Tx CTRP of given queue */ - for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { - CURR_TFD_GET (p_tx_curr_desc, queue); - MV_REG_WRITE ((MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0 - (eth_port_num) - + (4 * queue)), - ((unsigned int) p_tx_curr_desc)); - - } - - /* Assignment of Rx CRDP of given queue */ - for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { - CURR_RFD_GET (p_rx_curr_desc, queue); - MV_REG_WRITE ((MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0 - (eth_port_num) - + (4 * queue)), - ((unsigned int) p_rx_curr_desc)); - - if (p_rx_curr_desc != NULL) - /* Add the assigned Ethernet address to the port's address table */ - eth_port_uc_addr_set (p_eth_port_ctrl->port_num, - p_eth_port_ctrl->port_mac_addr, - queue); - } - - /* Assign port configuration and command. */ - MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num), - p_eth_port_ctrl->port_config); - - MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), - p_eth_port_ctrl->port_config_extend); - - MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - p_eth_port_ctrl->port_serial_control); - - MV_SET_REG_BITS (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - ETH_SERIAL_PORT_ENABLE); - - /* Assign port SDMA configuration */ - MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num), - p_eth_port_ctrl->port_sdma_config); - - MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT - (eth_port_num), 0x3fffffff); - MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG - (eth_port_num), 0x03fffcff); - /* Turn off the port/queue bandwidth limitation */ - MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0); - - /* Enable port Rx. */ - MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num), - p_eth_port_ctrl->port_rx_queue_command); - - /* Check if link is up */ - eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); - - if (!(phy_reg_data & 0x20)) - return false; - - return true; -} - -/******************************************************************************* -* eth_port_uc_addr_set - This function Set the port Unicast address. -* -* DESCRIPTION: -* This function Set the port Ethernet MAC address. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* char * p_addr Address to be set -* ETH_QUEUE queue Rx queue number for this MAC address. -* -* OUTPUT: -* Set MAC address low and high registers. also calls eth_port_uc_addr() -* To set the unicast table with the proper information. -* -* RETURN: -* N/A. -* -*******************************************************************************/ -static void eth_port_uc_addr_set (ETH_PORT eth_port_num, - unsigned char *p_addr, ETH_QUEUE queue) -{ - unsigned int mac_h; - unsigned int mac_l; - - mac_l = (p_addr[4] << 8) | (p_addr[5]); - mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | - (p_addr[2] << 8) | (p_addr[3] << 0); - - MV_REG_WRITE (MV64360_ETH_MAC_ADDR_LOW (eth_port_num), mac_l); - MV_REG_WRITE (MV64360_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h); - - /* Accept frames of this address */ - eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR); - - return; -} - -/******************************************************************************* -* eth_port_uc_addr - This function Set the port unicast address table -* -* DESCRIPTION: -* This function locates the proper entry in the Unicast table for the -* specified MAC nibble and sets its properties according to function -* parameters. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char uc_nibble Unicast MAC Address last nibble. -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* This function add/removes MAC addresses from the port unicast address -* table. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_uc_addr (ETH_PORT eth_port_num, - unsigned char uc_nibble, - ETH_QUEUE queue, int option) -{ - unsigned int unicast_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the Unicast table entry */ - uc_nibble = (0xf & uc_nibble); - tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */ - reg_offset = uc_nibble % 4; /* Entry offset within the above register */ - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified unicast DA table entry */ - unicast_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset)); - - unicast_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset), unicast_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at unicast DA filter table entry */ - unicast_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset)); - - unicast_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset), unicast_reg); - - break; - - default: - return false; - } - return true; -} - -#if 0 /* FIXME */ -/******************************************************************************* -* eth_port_mc_addr - Multicast address settings. -* -* DESCRIPTION: -* This API controls the MV device MAC multicast support. -* The MV device supports multicast using two tables: -* 1) Special Multicast Table for MAC addresses of the form -* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). -* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -* Table entries in the DA-Filter table. -* In this case, the function calls eth_port_smc_addr() routine to set the -* Special Multicast Table. -* 2) Other Multicast Table for multicast of another type. A CRC-8bit -* is used as an index to the Other Multicast Table entries in the -* DA-Filter table. -* In this case, the function calculates the CRC-8bit value and calls -* eth_port_omc_addr() routine to set the Other Multicast Table. -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char *p_addr Unicast MAC Address. -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if add_address_table_entry( ) failed. -* -*******************************************************************************/ -static void eth_port_mc_addr (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue, int option) -{ - unsigned int mac_h; - unsigned int mac_l; - unsigned char crc_result = 0; - int mac_array[48]; - int crc[8]; - int i; - - - if ((p_addr[0] == 0x01) && - (p_addr[1] == 0x00) && - (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) - - eth_port_smc_addr (eth_port_num, p_addr[5], queue, option); - else { - /* Calculate CRC-8 out of the given address */ - mac_h = (p_addr[0] << 8) | (p_addr[1]); - mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) | - (p_addr[4] << 8) | (p_addr[5] << 0); - - for (i = 0; i < 32; i++) - mac_array[i] = (mac_l >> i) & 0x1; - for (i = 32; i < 48; i++) - mac_array[i] = (mac_h >> (i - 32)) & 0x1; - - - crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ - mac_array[39] ^ mac_array[35] ^ mac_array[34] ^ - mac_array[31] ^ mac_array[30] ^ mac_array[28] ^ - mac_array[23] ^ mac_array[21] ^ mac_array[19] ^ - mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ - mac_array[12] ^ mac_array[8] ^ mac_array[7] ^ - mac_array[6] ^ mac_array[0]; - - crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[41] ^ mac_array[39] ^ - mac_array[36] ^ mac_array[34] ^ mac_array[32] ^ - mac_array[30] ^ mac_array[29] ^ mac_array[28] ^ - mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ - mac_array[21] ^ mac_array[20] ^ mac_array[18] ^ - mac_array[17] ^ mac_array[16] ^ mac_array[15] ^ - mac_array[14] ^ mac_array[13] ^ mac_array[12] ^ - mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ - mac_array[0]; - - crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[42] ^ mac_array[39] ^ - mac_array[37] ^ mac_array[34] ^ mac_array[33] ^ - mac_array[29] ^ mac_array[28] ^ mac_array[25] ^ - mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ - mac_array[15] ^ mac_array[13] ^ mac_array[12] ^ - mac_array[10] ^ mac_array[8] ^ mac_array[6] ^ - mac_array[2] ^ mac_array[1] ^ mac_array[0]; - - crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[40] ^ mac_array[38] ^ - mac_array[35] ^ mac_array[34] ^ mac_array[30] ^ - mac_array[29] ^ mac_array[26] ^ mac_array[25] ^ - mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ - mac_array[14] ^ mac_array[13] ^ mac_array[11] ^ - mac_array[9] ^ mac_array[7] ^ mac_array[3] ^ - mac_array[2] ^ mac_array[1]; - - crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ - mac_array[35] ^ mac_array[31] ^ mac_array[30] ^ - mac_array[27] ^ mac_array[26] ^ mac_array[24] ^ - mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ - mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ - mac_array[8] ^ mac_array[4] ^ mac_array[3] ^ - mac_array[2]; - - crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ - mac_array[42] ^ mac_array[40] ^ mac_array[37] ^ - mac_array[36] ^ mac_array[32] ^ mac_array[31] ^ - mac_array[28] ^ mac_array[27] ^ mac_array[25] ^ - mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ - mac_array[15] ^ mac_array[13] ^ mac_array[11] ^ - mac_array[9] ^ mac_array[5] ^ mac_array[4] ^ - mac_array[3]; - - crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ - mac_array[41] ^ mac_array[38] ^ mac_array[37] ^ - mac_array[33] ^ mac_array[32] ^ mac_array[29] ^ - mac_array[28] ^ mac_array[26] ^ mac_array[21] ^ - mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ - mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ - mac_array[6] ^ mac_array[5] ^ mac_array[4]; - - crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ - mac_array[39] ^ mac_array[38] ^ mac_array[34] ^ - mac_array[33] ^ mac_array[30] ^ mac_array[29] ^ - mac_array[27] ^ mac_array[22] ^ mac_array[20] ^ - mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ - mac_array[13] ^ mac_array[11] ^ mac_array[7] ^ - mac_array[6] ^ mac_array[5]; - - for (i = 0; i < 8; i++) - crc_result = crc_result | (crc[i] << i); - - eth_port_omc_addr (eth_port_num, crc_result, queue, option); - } - return; -} - -/******************************************************************************* -* eth_port_smc_addr - Special Multicast address settings. -* -* DESCRIPTION: -* This routine controls the MV device special MAC multicast support. -* The Special Multicast Table for MAC addresses supports MAC of the form -* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). -* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -* Table entries in the DA-Filter table. -* This function set the Special Multicast Table appropriate entry -* according to the argument given. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits). -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_smc_addr (ETH_PORT eth_port_num, - unsigned char mc_byte, - ETH_QUEUE queue, int option) -{ - unsigned int smc_table_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the SMC table entry */ - tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */ - reg_offset = mc_byte % 4; /* Entry offset within the above register */ - queue &= 0x7; - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified Special DA table entry */ - smc_table_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - smc_table_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at specified Special DA table entry */ - smc_table_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - smc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); - break; - - default: - return false; - } - return true; -} - -/******************************************************************************* -* eth_port_omc_addr - Multicast address settings. -* -* DESCRIPTION: -* This routine controls the MV device Other MAC multicast support. -* The Other Multicast Table is used for multicast of another type. -* A CRC-8bit is used as an index to the Other Multicast Table entries -* in the DA-Filter table. -* The function gets the CRC-8bit value from the calling routine and -* set the Other Multicast Table appropriate entry according to the -* CRC-8 argument given. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_omc_addr (ETH_PORT eth_port_num, - unsigned char crc8, - ETH_QUEUE queue, int option) -{ - unsigned int omc_table_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the OMC table entry */ - tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ - reg_offset = crc8 % 4; /* Entry offset within the above register */ - queue &= 0x7; - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified Other DA table entry */ - omc_table_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - omc_table_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at specified Other DA table entry */ - omc_table_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - omc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); - break; - - default: - return false; - } - return true; -} -#endif - -/******************************************************************************* -* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables -* -* DESCRIPTION: -* Go through all the DA filter tables (Unicast, Special Multicast & Other -* Multicast) and set each entry to 0. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* Multicast and Unicast packets are rejected. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void eth_port_init_mac_tables (ETH_PORT eth_port_num) -{ - int table_index; - - /* Clear DA filter unicast table (Ex_dFUT) */ - for (table_index = 0; table_index <= 0xC; table_index += 4) - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) + table_index), 0); - - for (table_index = 0; table_index <= 0xFC; table_index += 4) { - /* Clear DA filter special multicast table (Ex_dFSMT) */ - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); - /* Clear DA filter other multicast table (Ex_dFOMT) */ - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); - } -} - -/******************************************************************************* -* eth_clear_mib_counters - Clear all MIB counters -* -* DESCRIPTION: -* This function clears all MIB counters of a specific ethernet port. -* A read from the MIB counter will reset the counter. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* After reading all MIB counters, the counters resets. -* -* RETURN: -* MIB counter value. -* -*******************************************************************************/ -static void eth_clear_mib_counters (ETH_PORT eth_port_num) -{ - int i; - - /* Perform dummy reads from MIB counters */ - for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; - i += 4) - MV_REG_READ((MV64360_ETH_MIB_COUNTERS_BASE(eth_port_num) + i)); - - return; -} - -/******************************************************************************* -* eth_read_mib_counter - Read a MIB counter -* -* DESCRIPTION: -* This function reads a MIB counter of a specific ethernet port. -* NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the -* following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH -* register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and -* ETH_MIB_GOOD_OCTETS_SENT_HIGH -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros). -* -* OUTPUT: -* After reading the MIB counter, the counter resets. -* -* RETURN: -* MIB counter value. -* -*******************************************************************************/ -unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, - unsigned int mib_offset) -{ - return (MV_REG_READ (MV64360_ETH_MIB_COUNTERS_BASE (eth_port_num) - + mib_offset)); -} - -/******************************************************************************* -* ethernet_phy_set - Set the ethernet port PHY address. -* -* DESCRIPTION: -* This routine set the ethernet port PHY address according to given -* parameter. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* Set PHY Address Register with given PHY address parameter. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr) -{ - unsigned int reg_data; - - reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG); - - reg_data &= ~(0x1F << (5 * eth_port_num)); - reg_data |= (phy_addr << (5 * eth_port_num)); - - MV_REG_WRITE (MV64360_ETH_PHY_ADDR_REG, reg_data); - - return; -} - -/******************************************************************************* - * ethernet_phy_get - Get the ethernet port PHY address. - * - * DESCRIPTION: - * This routine returns the given ethernet port PHY address. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * None. - * - * RETURN: - * PHY address. - * - *******************************************************************************/ -static int ethernet_phy_get (ETH_PORT eth_port_num) -{ - unsigned int reg_data; - - reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG); - - return ((reg_data >> (5 * eth_port_num)) & 0x1f); -} - -/******************************************************************************* - * ethernet_phy_reset - Reset Ethernet port PHY. - * - * DESCRIPTION: - * This routine utilize the SMI interface to reset the ethernet port PHY. - * The routine waits until the link is up again or link up is timeout. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * The ethernet port PHY renew its link. - * - * RETURN: - * None. - * -*******************************************************************************/ -static bool ethernet_phy_reset (ETH_PORT eth_port_num) -{ - unsigned int time_out = 50; - unsigned int phy_reg_data; - - /* Reset the PHY */ - eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data); - phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */ - eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data); - - /* Poll on the PHY LINK */ - do { - eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); - - if (time_out-- == 0) - return false; - } - while (!(phy_reg_data & 0x20)); - - return true; -} - -/******************************************************************************* - * eth_port_reset - Reset Ethernet port - * - * DESCRIPTION: - * This routine resets the chip by aborting any SDMA engine activity and - * clearing the MIB counters. The Receiver and the Transmit unit are in - * idle state after this command is performed and the port is disabled. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * Channel activity is halted. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_port_reset (ETH_PORT eth_port_num) -{ - unsigned int reg_data; - - /* Stop Tx port activity. Check port Tx activity. */ - reg_data = - MV_REG_READ (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num)); - - if (reg_data & 0xFF) { - /* Issue stop command for active channels only */ - MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num), (reg_data << 8)); - - /* Wait for all Tx activity to terminate. */ - do { - /* Check port cause register that all Tx queues are stopped */ - reg_data = - MV_REG_READ - (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num)); - } - while (reg_data & 0xFF); - } - - /* Stop Rx port activity. Check port Rx activity. */ - reg_data = - MV_REG_READ (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num)); - - if (reg_data & 0xFF) { - /* Issue stop command for active channels only */ - MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num), (reg_data << 8)); - - /* Wait for all Rx activity to terminate. */ - do { - /* Check port cause register that all Rx queues are stopped */ - reg_data = - MV_REG_READ - (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num)); - } - while (reg_data & 0xFF); - } - - - /* Clear all MIB counters */ - eth_clear_mib_counters (eth_port_num); - - /* Reset the Enable bit in the Configuration Register */ - reg_data = - MV_REG_READ (MV64360_ETH_PORT_SERIAL_CONTROL_REG - (eth_port_num)); - reg_data &= ~ETH_SERIAL_PORT_ENABLE; - MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - reg_data); - - return; -} - -#if 0 /* Not needed here */ -/******************************************************************************* - * ethernet_set_config_reg - Set specified bits in configuration register. - * - * DESCRIPTION: - * This function sets specified bits in the given ethernet - * configuration register. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int value 32 bit value. - * - * OUTPUT: - * The set bits in the value parameter are set in the configuration - * register. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void ethernet_set_config_reg (ETH_PORT eth_port_num, - unsigned int value) -{ - unsigned int eth_config_reg; - - eth_config_reg = - MV_REG_READ (MV64360_ETH_PORT_CONFIG_REG (eth_port_num)); - eth_config_reg |= value; - MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num), - eth_config_reg); - - return; -} -#endif - -#if 0 /* FIXME */ -/******************************************************************************* - * ethernet_reset_config_reg - Reset specified bits in configuration register. - * - * DESCRIPTION: - * This function resets specified bits in the given Ethernet - * configuration register. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int value 32 bit value. - * - * OUTPUT: - * The set bits in the value parameter are reset in the configuration - * register. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void ethernet_reset_config_reg (ETH_PORT eth_port_num, - unsigned int value) -{ - unsigned int eth_config_reg; - - eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG - (eth_port_num)); - eth_config_reg &= ~value; - MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), - eth_config_reg); - - return; -} -#endif - -#if 0 /* Not needed here */ -/******************************************************************************* - * ethernet_get_config_reg - Get the port configuration register - * - * DESCRIPTION: - * This function returns the configuration register value of the given - * ethernet port. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * None. - * - * RETURN: - * Port configuration register value. - * - *******************************************************************************/ -static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num) -{ - unsigned int eth_config_reg; - - eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG - (eth_port_num)); - return eth_config_reg; -} - -#endif - -/******************************************************************************* - * eth_port_read_smi_reg - Read PHY registers - * - * DESCRIPTION: - * This routine utilize the SMI interface to interact with the PHY in - * order to perform PHY register read. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int phy_reg PHY register address offset. - * unsigned int *value Register value buffer. - * - * OUTPUT: - * Write the value of a specified PHY register into given buffer. - * - * RETURN: - * false if the PHY is busy or read data is not in valid state. - * true otherwise. - * - *******************************************************************************/ -static bool eth_port_read_smi_reg (ETH_PORT eth_port_num, - unsigned int phy_reg, unsigned int *value) -{ - unsigned int reg_value; - unsigned int time_out = PHY_BUSY_TIMEOUT; - int phy_addr; - - phy_addr = ethernet_phy_get (eth_port_num); -/* printf(" Phy-Port %d has addess %d \n",eth_port_num, phy_addr );*/ - - /* first check that it is not busy */ - do { - reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while (reg_value & ETH_SMI_BUSY); - - /* not busy */ - - MV_REG_WRITE (MV64360_ETH_SMI_REG, - (phy_addr << 16) | (phy_reg << 21) | - ETH_SMI_OPCODE_READ); - - time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */ - - do { - reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */ - - /* Wait for the data to update in the SMI register */ -#define PHY_UPDATE_TIMEOUT 10000 - for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++); - - reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); - - *value = reg_value & 0xffff; - - return true; -} - -/******************************************************************************* - * eth_port_write_smi_reg - Write to PHY registers - * - * DESCRIPTION: - * This routine utilize the SMI interface to interact with the PHY in - * order to perform writes to PHY registers. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int phy_reg PHY register address offset. - * unsigned int value Register value. - * - * OUTPUT: - * Write the given value to the specified PHY register. - * - * RETURN: - * false if the PHY is busy. - * true otherwise. - * - *******************************************************************************/ -static bool eth_port_write_smi_reg (ETH_PORT eth_port_num, - unsigned int phy_reg, unsigned int value) -{ - unsigned int reg_value; - unsigned int time_out = PHY_BUSY_TIMEOUT; - int phy_addr; - - phy_addr = ethernet_phy_get (eth_port_num); - - /* first check that it is not busy */ - do { - reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while (reg_value & ETH_SMI_BUSY); - - /* not busy */ - MV_REG_WRITE (MV64360_ETH_SMI_REG, - (phy_addr << 16) | (phy_reg << 21) | - ETH_SMI_OPCODE_WRITE | (value & 0xffff)); - return true; -} - -/******************************************************************************* - * eth_set_access_control - Config address decode parameters for Ethernet unit - * - * DESCRIPTION: - * This function configures the address decode parameters for the Gigabit - * Ethernet Controller according the given parameters struct. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * ETH_WIN_PARAM *param Address decode parameter struct. - * - * OUTPUT: - * An access window is opened using the given access parameters. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_set_access_control (ETH_PORT eth_port_num, - ETH_WIN_PARAM * param) -{ - unsigned int access_prot_reg; - - /* Set access control register */ - access_prot_reg = MV_REG_READ (MV64360_ETH_ACCESS_PROTECTION_REG - (eth_port_num)); - access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */ - access_prot_reg |= (param->access_ctrl << (param->win * 2)); - MV_REG_WRITE (MV64360_ETH_ACCESS_PROTECTION_REG (eth_port_num), - access_prot_reg); - - /* Set window Size reg (SR) */ - MV_REG_WRITE ((MV64360_ETH_SIZE_REG_0 + - (ETH_SIZE_REG_GAP * param->win)), - (((param->size / 0x10000) - 1) << 16)); - - /* Set window Base address reg (BA) */ - MV_REG_WRITE ((MV64360_ETH_BAR_0 + (ETH_BAR_GAP * param->win)), - (param->target | param->attributes | param->base_addr)); - /* High address remap reg (HARR) */ - if (param->win < 4) - MV_REG_WRITE ((MV64360_ETH_HIGH_ADDR_REMAP_REG_0 + - (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)), - param->high_addr); - - /* Base address enable reg (BARER) */ - if (param->enable == 1) - MV_RESET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG, - (1 << param->win)); - else - MV_SET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG, - (1 << param->win)); -} - -/******************************************************************************* - * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. - * - * DESCRIPTION: - * This function prepares a Rx chained list of descriptors and packet - * buffers in a form of a ring. The routine must be called after port - * initialization routine and before port start routine. - * The Ethernet SDMA engine uses CPU bus addresses to access the various - * devices in the system (i.e. DRAM). This function uses the ethernet - * struct 'virtual to physical' routine (set by the user) to set the ring - * with physical addresses. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * int rx_desc_num Number of Rx descriptors - * int rx_buff_size Size of Rx buffer - * unsigned int rx_desc_base_addr Rx descriptors memory area base addr. - * unsigned int rx_buff_base_addr Rx buffer memory area base addr. - * - * OUTPUT: - * The routine updates the Ethernet port control struct with information - * regarding the Rx descriptors and buffers. - * - * RETURN: - * false if the given descriptors memory area is not aligned according to - * Ethernet SDMA specifications. - * true otherwise. - * - *******************************************************************************/ -static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE rx_queue, - int rx_desc_num, - int rx_buff_size, - unsigned int rx_desc_base_addr, - unsigned int rx_buff_base_addr) -{ - ETH_RX_DESC *p_rx_desc; - ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */ - unsigned int buffer_addr; - int ix; /* a counter */ - - - p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr; - p_rx_prev_desc = p_rx_desc; - buffer_addr = rx_buff_base_addr; - - /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ - if (rx_buff_base_addr & 0xF) - return false; - - /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */ - if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE)) - return false; - - /* Rx buffers must be 64-bit aligned. */ - if ((rx_buff_base_addr + rx_buff_size) & 0x7) - return false; - - /* initialize the Rx descriptors ring */ - for (ix = 0; ix < rx_desc_num; ix++) { - p_rx_desc->buf_size = rx_buff_size; - p_rx_desc->byte_cnt = 0x0000; - p_rx_desc->cmd_sts = - ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; - p_rx_desc->next_desc_ptr = - ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE; - p_rx_desc->buf_ptr = buffer_addr; - p_rx_desc->return_info = 0x00000000; - D_CACHE_FLUSH_LINE (p_rx_desc, 0); - buffer_addr += rx_buff_size; - p_rx_prev_desc = p_rx_desc; - p_rx_desc = (ETH_RX_DESC *) - ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE); - } - - /* Closing Rx descriptors ring */ - p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr); - D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0); - - /* Save Rx desc pointer to driver struct. */ - CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); - USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); - - p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] = - (ETH_RX_DESC *) rx_desc_base_addr; - p_eth_port_ctrl->rx_desc_area_size[rx_queue] = - rx_desc_num * RX_DESC_ALIGNED_SIZE; - - p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue); - - return true; -} - -/******************************************************************************* - * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. - * - * DESCRIPTION: - * This function prepares a Tx chained list of descriptors and packet - * buffers in a form of a ring. The routine must be called after port - * initialization routine and before port start routine. - * The Ethernet SDMA engine uses CPU bus addresses to access the various - * devices in the system (i.e. DRAM). This function uses the ethernet - * struct 'virtual to physical' routine (set by the user) to set the ring - * with physical addresses. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * int tx_desc_num Number of Tx descriptors - * int tx_buff_size Size of Tx buffer - * unsigned int tx_desc_base_addr Tx descriptors memory area base addr. - * unsigned int tx_buff_base_addr Tx buffer memory area base addr. - * - * OUTPUT: - * The routine updates the Ethernet port control struct with information - * regarding the Tx descriptors and buffers. - * - * RETURN: - * false if the given descriptors memory area is not aligned according to - * Ethernet SDMA specifications. - * true otherwise. - * - *******************************************************************************/ -static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE tx_queue, - int tx_desc_num, - int tx_buff_size, - unsigned int tx_desc_base_addr, - unsigned int tx_buff_base_addr) -{ - - ETH_TX_DESC *p_tx_desc; - ETH_TX_DESC *p_tx_prev_desc; - unsigned int buffer_addr; - int ix; /* a counter */ - - - /* save the first desc pointer to link with the last descriptor */ - p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr; - p_tx_prev_desc = p_tx_desc; - buffer_addr = tx_buff_base_addr; - - /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ - if (tx_buff_base_addr & 0xF) - return false; - - /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */ - if ((tx_buff_size > TX_BUFFER_MAX_SIZE) - || (tx_buff_size < TX_BUFFER_MIN_SIZE)) - return false; - - /* Initialize the Tx descriptors ring */ - for (ix = 0; ix < tx_desc_num; ix++) { - p_tx_desc->byte_cnt = 0x0000; - p_tx_desc->l4i_chk = 0x0000; - p_tx_desc->cmd_sts = 0x00000000; - p_tx_desc->next_desc_ptr = - ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE; - - p_tx_desc->buf_ptr = buffer_addr; - p_tx_desc->return_info = 0x00000000; - D_CACHE_FLUSH_LINE (p_tx_desc, 0); - buffer_addr += tx_buff_size; - p_tx_prev_desc = p_tx_desc; - p_tx_desc = (ETH_TX_DESC *) - ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE); - - } - /* Closing Tx descriptors ring */ - p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr; - D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0); - /* Set Tx desc pointer in driver struct. */ - CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); - USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); - - /* Init Tx ring base and size parameters */ - p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] = - (ETH_TX_DESC *) tx_desc_base_addr; - p_eth_port_ctrl->tx_desc_area_size[tx_queue] = - (tx_desc_num * TX_DESC_ALIGNED_SIZE); - - /* Add the queue to the list of Tx queues of this port */ - p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue); - - return true; -} - -/******************************************************************************* - * eth_port_send - Send an Ethernet packet - * - * DESCRIPTION: - * This routine send a given packet described by p_pktinfo parameter. It - * supports transmitting of a packet spaned over multiple buffers. The - * routine updates 'curr' and 'first' indexes according to the packet - * segment passed to the routine. In case the packet segment is first, - * the 'first' index is update. In any case, the 'curr' index is updated. - * If the routine get into Tx resource error it assigns 'curr' index as - * 'first'. This way the function can abort Tx process of multiple - * descriptors per packet. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Tx ring 'curr' and 'first' indexes are updated. - * - * RETURN: - * ETH_QUEUE_FULL in case of Tx resource error. - * ETH_ERROR in case the routine can not access Tx desc ring. - * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_TX_DESC *p_tx_desc_first; - volatile ETH_TX_DESC *p_tx_desc_curr; - volatile ETH_TX_DESC *p_tx_next_desc_curr; - volatile ETH_TX_DESC *p_tx_desc_used; - unsigned int command_status; - - /* Do not process Tx ring in case of Tx ring resource error */ - if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) - return ETH_QUEUE_FULL; - - /* Get the Tx Desc ring indexes */ - CURR_TFD_GET (p_tx_desc_curr, tx_queue); - USED_TFD_GET (p_tx_desc_used, tx_queue); - - if (p_tx_desc_curr == NULL) - return ETH_ERROR; - - /* The following parameters are used to save readings from memory */ - p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue); - command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC; - - if (command_status & (ETH_TX_FIRST_DESC)) { - /* Update first desc */ - FIRST_TFD_SET (p_tx_desc_curr, tx_queue); - p_tx_desc_first = p_tx_desc_curr; - } else { - FIRST_TFD_GET (p_tx_desc_first, tx_queue); - command_status |= ETH_BUFFER_OWNED_BY_DMA; - } - - /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */ - /* boundary. We use the memory allocated for Tx descriptor. This memory */ - /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */ - if (p_pkt_info->byte_cnt <= 8) { - printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */ - return ETH_ERROR; - - p_tx_desc_curr->buf_ptr = - (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC; - eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr, - p_pkt_info->byte_cnt); - } else - p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr; - - p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt; - p_tx_desc_curr->return_info = p_pkt_info->return_info; - - if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) { - /* Set last desc with DMA ownership and interrupt enable. */ - p_tx_desc_curr->cmd_sts = command_status | - ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT; - - if (p_tx_desc_curr != p_tx_desc_first) - p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA; - - /* Flush CPU pipe */ - - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0); - CPU_PIPE_FLUSH; - - /* Apply send command */ - ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num); - - /* Finish Tx packet. Update first desc in case of Tx resource error */ - p_tx_desc_first = p_tx_next_desc_curr; - FIRST_TFD_SET (p_tx_desc_first, tx_queue); - - } else { - p_tx_desc_curr->cmd_sts = command_status; - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); - } - - /* Check for ring index overlap in the Tx desc ring */ - if (p_tx_next_desc_curr == p_tx_desc_used) { - /* Update the current descriptor */ - CURR_TFD_SET (p_tx_desc_first, tx_queue); - - p_eth_port_ctrl->tx_resource_err[tx_queue] = true; - return ETH_QUEUE_LAST_RESOURCE; - } else { - /* Update the current descriptor */ - CURR_TFD_SET (p_tx_next_desc_curr, tx_queue); - return ETH_OK; - } -} - -/******************************************************************************* - * eth_tx_return_desc - Free all used Tx descriptors - * - * DESCRIPTION: - * This routine returns the transmitted packet information to the caller. - * It uses the 'first' index to support Tx desc return in case a transmit - * of a packet spanned over multiple buffer still in process. - * In case the Tx queue was in "resource error" condition, where there are - * no available Tx resources, the function resets the resource error flag. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Tx ring 'first' and 'used' indexes are updated. - * - * RETURN: - * ETH_ERROR in case the routine can not access Tx desc ring. - * ETH_RETRY in case there is transmission in process. - * ETH_END_OF_JOB if the routine has nothing to release. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO * - p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_TX_DESC *p_tx_desc_used = NULL; - volatile ETH_TX_DESC *p_tx_desc_first = NULL; - unsigned int command_status; - - - /* Get the Tx Desc ring indexes */ - USED_TFD_GET (p_tx_desc_used, tx_queue); - FIRST_TFD_GET (p_tx_desc_first, tx_queue); - - - /* Sanity check */ - if (p_tx_desc_used == NULL) - return ETH_ERROR; - - command_status = p_tx_desc_used->cmd_sts; - - /* Still transmitting... */ - if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - return ETH_RETRY; - } - - /* Stop release. About to overlap the current available Tx descriptor */ - if ((p_tx_desc_used == p_tx_desc_first) && - (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) { - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - return ETH_END_OF_JOB; - } - - /* Pass the packet information to the caller */ - p_pkt_info->cmd_sts = command_status; - p_pkt_info->return_info = p_tx_desc_used->return_info; - p_tx_desc_used->return_info = 0; - - /* Update the next descriptor to release. */ - USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue); - - /* Any Tx return cancels the Tx resource error status */ - if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) - p_eth_port_ctrl->tx_resource_err[tx_queue] = false; - - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - - return ETH_OK; - -} - -/******************************************************************************* - * eth_port_receive - Get received information from Rx ring. - * - * DESCRIPTION: - * This routine returns the received data to the caller. There is no - * data copying during routine operation. All information is returned - * using pointer to packet information struct passed from the caller. - * If the routine exhausts Rx ring resources then the resource error flag - * is set. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Rx ring current and used indexes are updated. - * - * RETURN: - * ETH_ERROR in case the routine can not access Rx desc ring. - * ETH_QUEUE_FULL if Rx ring resources are exhausted. - * ETH_END_OF_JOB if there is no received data. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_RX_DESC *p_rx_curr_desc; - volatile ETH_RX_DESC *p_rx_next_curr_desc; - volatile ETH_RX_DESC *p_rx_used_desc; - unsigned int command_status; - - /* Do not process Rx ring in case of Rx ring resource error */ - if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) { - printf ("\nRx Queue is full ...\n"); - return ETH_QUEUE_FULL; - } - - /* Get the Rx Desc ring 'curr and 'used' indexes */ - CURR_RFD_GET (p_rx_curr_desc, rx_queue); - USED_RFD_GET (p_rx_used_desc, rx_queue); - - /* Sanity check */ - if (p_rx_curr_desc == NULL) - return ETH_ERROR; - - /* The following parameters are used to save readings from memory */ - p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue); - command_status = p_rx_curr_desc->cmd_sts; - - /* Nothing to receive... */ - if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { -/* DP(printf("Rx: command_status: %08x\n", command_status)); */ - D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); -/* DP(printf("\nETH_END_OF_JOB ...\n"));*/ - return ETH_END_OF_JOB; - } - - p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET; - p_pkt_info->cmd_sts = command_status; - p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET; - p_pkt_info->return_info = p_rx_curr_desc->return_info; - p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */ - - /* Clean the return info field to indicate that the packet has been */ - /* moved to the upper layers */ - p_rx_curr_desc->return_info = 0; - - /* Update 'curr' in data structure */ - CURR_RFD_SET (p_rx_next_curr_desc, rx_queue); - - /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */ - if (p_rx_next_curr_desc == p_rx_used_desc) - p_eth_port_ctrl->rx_resource_err[rx_queue] = true; - - D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); - CPU_PIPE_FLUSH; - return ETH_OK; -} - -/******************************************************************************* - * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. - * - * DESCRIPTION: - * This routine returns a Rx buffer back to the Rx ring. It retrieves the - * next 'used' descriptor and attached the returned buffer to it. - * In case the Rx ring was in "resource error" condition, where there are - * no available Rx resources, the function resets the resource error flag. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * PKT_INFO *p_pkt_info Information on the returned buffer. - * - * OUTPUT: - * New available Rx resource in Rx descriptor ring. - * - * RETURN: - * ETH_ERROR in case the routine can not access Rx desc ring. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO * - p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */ - - /* Get 'used' Rx descriptor */ - USED_RFD_GET (p_used_rx_desc, rx_queue); - - /* Sanity check */ - if (p_used_rx_desc == NULL) - return ETH_ERROR; - - p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; - p_used_rx_desc->return_info = p_pkt_info->return_info; - p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt; - p_used_rx_desc->buf_size = MV64360_RX_BUFFER_SIZE; /* Reset Buffer size */ - - /* Flush the write pipe */ - CPU_PIPE_FLUSH; - - /* Return the descriptor to DMA ownership */ - p_used_rx_desc->cmd_sts = - ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; - - /* Flush descriptor and CPU pipe */ - D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0); - CPU_PIPE_FLUSH; - - /* Move the used descriptor pointer to the next descriptor */ - USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue); - - /* Any Rx return cancels the Rx resource error status */ - if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) - p_eth_port_ctrl->rx_resource_err[rx_queue] = false; - - return ETH_OK; -} - -/******************************************************************************* - * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path - * - * DESCRIPTION: - * This routine sets the RX coalescing interrupt mechanism parameter. - * This parameter is a timeout counter, that counts in 64 t_clk - * chunks ; that when timeout event occurs a maskable interrupt - * occurs. - * The parameter is calculated using the tClk of the MV-643xx chip - * , and the required delay of the interrupt in usec. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet port number - * unsigned int t_clk t_clk of the MV-643xx chip in HZ units - * unsigned int delay Delay in usec - * - * OUTPUT: - * Interrupt coalescing mechanism value is set in MV-643xx chip. - * - * RETURN: - * The interrupt coalescing value set in the gigE port. - * - *******************************************************************************/ -#if 0 /* FIXME */ -static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num, - unsigned int t_clk, - unsigned int delay) -{ - unsigned int coal; - - coal = ((t_clk / 1000000) * delay) / 64; - /* Set RX Coalescing mechanism */ - MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num), - ((coal & 0x3fff) << 8) | - (MV_REG_READ - (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num)) - & 0xffc000ff)); - return coal; -} - -#endif -/******************************************************************************* - * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path - * - * DESCRIPTION: - * This routine sets the TX coalescing interrupt mechanism parameter. - * This parameter is a timeout counter, that counts in 64 t_clk - * chunks ; that when timeout event occurs a maskable interrupt - * occurs. - * The parameter is calculated using the t_cLK frequency of the - * MV-643xx chip and the required delay in the interrupt in uSec - * - * INPUT: - * ETH_PORT eth_port_num Ethernet port number - * unsigned int t_clk t_clk of the MV-643xx chip in HZ units - * unsigned int delay Delay in uSeconds - * - * OUTPUT: - * Interrupt coalescing mechanism value is set in MV-643xx chip. - * - * RETURN: - * The interrupt coalescing value set in the gigE port. - * - *******************************************************************************/ -#if 0 /* FIXME */ -static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num, - unsigned int t_clk, - unsigned int delay) -{ - unsigned int coal; - - coal = ((t_clk / 1000000) * delay) / 64; - /* Set TX Coalescing mechanism */ - MV_REG_WRITE (MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num), - coal << 4); - return coal; -} -#endif - -/******************************************************************************* - * eth_b_copy - Copy bytes from source to destination - * - * DESCRIPTION: - * This function supports the eight bytes limitation on Tx buffer size. - * The routine will zero eight bytes starting from the destination address - * followed by copying bytes from the source address to the destination. - * - * INPUT: - * unsigned int src_addr 32 bit source address. - * unsigned int dst_addr 32 bit destination address. - * int byte_count Number of bytes to copy. - * - * OUTPUT: - * See description. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, - int byte_count) -{ - /* Zero the dst_addr area */ - *(unsigned int *) dst_addr = 0x0; - - while (byte_count != 0) { - *(char *) dst_addr = *(char *) src_addr; - dst_addr++; - src_addr++; - byte_count--; - } -} diff --git a/board/Marvell/db64360/mv_eth.h b/board/Marvell/db64360/mv_eth.h deleted file mode 100644 index d960eb4..0000000 --- a/board/Marvell/db64360/mv_eth.h +++ /dev/null @@ -1,818 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus <ingo.assmus@keymile.com> - * - * based on - Driver for MV64360X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mv_eth.h - header file for the polled mode GT ethernet driver - */ - -#ifndef __DB64360_ETH_H__ -#define __DB64360_ETH_H__ - -#include <asm/types.h> -#include <asm/io.h> -#include <asm/byteorder.h> -#include <common.h> -#include <net.h> -#include "mv_regs.h" -#include <asm/errno.h> - -/************************************************************************* -************************************************************************** -************************************************************************** -* The first part is the high level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ -/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */ -#ifndef MAX_SKB_FRAGS -#define MAX_SKB_FRAGS 0 -#endif - -/* Port attributes */ -/*#define MAX_RX_QUEUE_NUM 8*/ -/*#define MAX_TX_QUEUE_NUM 8*/ -#define MAX_RX_QUEUE_NUM 1 -#define MAX_TX_QUEUE_NUM 1 - - -/* Use one TX queue and one RX queue */ -#define MV64360_TX_QUEUE_NUM 1 -#define MV64360_RX_QUEUE_NUM 1 - -/* - * Number of RX / TX descriptors on RX / TX rings. - * Note that allocating RX descriptors is done by allocating the RX - * ring AND a preallocated RX buffers (skb's) for each descriptor. - * The TX descriptors only allocates the TX descriptors ring, - * with no pre allocated TX buffers (skb's are allocated by higher layers. - */ - -/* Default TX ring size is 10 descriptors */ -#ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE -#define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE -#else -#define MV64360_TX_QUEUE_SIZE 4 -#endif - -/* Default RX ring size is 4 descriptors */ -#ifdef CONFIG_MV64360_ETH_RXQUEUE_SIZE -#define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE -#else -#define MV64360_RX_QUEUE_SIZE 4 -#endif - -#ifdef CONFIG_RX_BUFFER_SIZE -#define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE -#else -#define MV64360_RX_BUFFER_SIZE 1600 -#endif - -#ifdef CONFIG_TX_BUFFER_SIZE -#define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE -#else -#define MV64360_TX_BUFFER_SIZE 1600 -#endif - - -/* - * Network device statistics. Akin to the 2.0 ether stats but - * with byte counters. - */ - -struct net_device_stats -{ - unsigned long rx_packets; /* total packets received */ - unsigned long tx_packets; /* total packets transmitted */ - unsigned long rx_bytes; /* total bytes received */ - unsigned long tx_bytes; /* total bytes transmitted */ - unsigned long rx_errors; /* bad packets received */ - unsigned long tx_errors; /* packet transmit problems */ - unsigned long rx_dropped; /* no space in linux buffers */ - unsigned long tx_dropped; /* no space available in linux */ - unsigned long multicast; /* multicast packets received */ - unsigned long collisions; - - /* detailed rx_errors: */ - unsigned long rx_length_errors; - unsigned long rx_over_errors; /* receiver ring buff overflow */ - unsigned long rx_crc_errors; /* recved pkt with crc error */ - unsigned long rx_frame_errors; /* recv'd frame alignment error */ - unsigned long rx_fifo_errors; /* recv'r fifo overrun */ - unsigned long rx_missed_errors; /* receiver missed packet */ - - /* detailed tx_errors */ - unsigned long tx_aborted_errors; - unsigned long tx_carrier_errors; - unsigned long tx_fifo_errors; - unsigned long tx_heartbeat_errors; - unsigned long tx_window_errors; - - /* for cslip etc */ - unsigned long rx_compressed; - unsigned long tx_compressed; -}; - - -/* Private data structure used for ethernet device */ -struct mv64360_eth_priv { - unsigned int port_num; - struct net_device_stats *stats; - -/* to buffer area aligned */ - char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */ - char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */ - - /* Size of Tx Ring per queue */ - unsigned int tx_ring_size [MAX_TX_QUEUE_NUM]; - - - /* Size of Rx Ring per queue */ - unsigned int rx_ring_size [MAX_RX_QUEUE_NUM]; - - /* Magic Number for Ethernet running */ - unsigned int eth_running; - -}; - - -int mv64360_eth_init (struct eth_device *dev); -int mv64360_eth_stop (struct eth_device *dev); -int mv64360_eth_start_xmit(struct eth_device *dev, void *packet, int length); -int mv64360_eth_open (struct eth_device *dev); - - -/************************************************************************* -************************************************************************** -************************************************************************** -* The second part is the low level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ - - -/******************************************************************************** - * Header File for : MV-643xx network interface header - * - * DESCRIPTION: - * This header file contains macros typedefs and function declaration for - * the Marvell Gig Bit Ethernet Controller. - * - * DEPENDENCIES: - * None. - * - *******************************************************************************/ - - -#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY -#ifdef CONFIG_MV64360_SRAM_CACHEABLE -/* In case SRAM is cacheable but not cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) \ -{ \ - __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ -} -#else -/* In case SRAM is cache coherent or non-cacheable */ -#define D_CACHE_FLUSH_LINE(addr, offset) ; -#endif -#else -#ifdef CONFIG_NOT_COHERENT_CACHE -/* In case of descriptors on DDR but not cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) \ -{ \ - __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ -} -#else -/* In case of descriptors on DDR and cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) ; -#endif /* CONFIG_NOT_COHERENT_CACHE */ -#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */ - - -#define CPU_PIPE_FLUSH \ -{ \ - __asm__ __volatile__ ("eieio"); \ -} - - -/* defines */ - -/* Default port configuration value */ -#define PORT_CONFIG_VALUE \ - ETH_UNICAST_NORMAL_MODE | \ - ETH_DEFAULT_RX_QUEUE_0 | \ - ETH_DEFAULT_RX_ARP_QUEUE_0 | \ - ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \ - ETH_RECEIVE_BC_IF_IP | \ - ETH_RECEIVE_BC_IF_ARP | \ - ETH_CAPTURE_TCP_FRAMES_DIS | \ - ETH_CAPTURE_UDP_FRAMES_DIS | \ - ETH_DEFAULT_RX_TCP_QUEUE_0 | \ - ETH_DEFAULT_RX_UDP_QUEUE_0 | \ - ETH_DEFAULT_RX_BPDU_QUEUE_0 - -/* Default port extend configuration value */ -#define PORT_CONFIG_EXTEND_VALUE \ - ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \ - ETH_PARTITION_DISABLE - - -/* Default sdma control value */ -#ifdef CONFIG_NOT_COHERENT_CACHE -#define PORT_SDMA_CONFIG_VALUE \ - ETH_RX_BURST_SIZE_16_64BIT | \ - GT_ETH_IPG_INT_RX(0) | \ - ETH_TX_BURST_SIZE_16_64BIT; -#else -#define PORT_SDMA_CONFIG_VALUE \ - ETH_RX_BURST_SIZE_4_64BIT | \ - GT_ETH_IPG_INT_RX(0) | \ - ETH_TX_BURST_SIZE_4_64BIT; -#endif - -#define GT_ETH_IPG_INT_RX(value) \ - ((value & 0x3fff) << 8) - -/* Default port serial control value */ -#define PORT_SERIAL_CONTROL_VALUE \ - ETH_FORCE_LINK_PASS | \ - ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \ - ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ - ETH_ADV_SYMMETRIC_FLOW_CTRL | \ - ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ - ETH_FORCE_BP_MODE_NO_JAM | \ - BIT9 | \ - ETH_DO_NOT_FORCE_LINK_FAIL | \ - ETH_RETRANSMIT_16_ETTEMPTS | \ - ETH_ENABLE_AUTO_NEG_SPEED_GMII | \ - ETH_DTE_ADV_0 | \ - ETH_DISABLE_AUTO_NEG_BYPASS | \ - ETH_AUTO_NEG_NO_CHANGE | \ - ETH_MAX_RX_PACKET_1552BYTE | \ - ETH_CLR_EXT_LOOPBACK | \ - ETH_SET_FULL_DUPLEX_MODE | \ - ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX; - -#define RX_BUFFER_MAX_SIZE 0xFFFF -#define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */ - -#define RX_BUFFER_MIN_SIZE 0x8 -#define TX_BUFFER_MIN_SIZE 0x8 - -/* Tx WRR confoguration macros */ -#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */ -#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */ -#define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */ - -/* MAC accepet/reject macros */ -#define ACCEPT_MAC_ADDR 0 -#define REJECT_MAC_ADDR 1 - -/* Size of a Tx/Rx descriptor used in chain list data structure */ -#define RX_DESC_ALIGNED_SIZE 0x20 -#define TX_DESC_ALIGNED_SIZE 0x20 - -/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */ -#define TX_BUF_OFFSET_IN_DESC 0x18 -/* Buffer offset from buffer pointer */ -#define RX_BUF_OFFSET 0x2 - -/* Gap define */ -#define ETH_BAR_GAP 0x8 -#define ETH_SIZE_REG_GAP 0x8 -#define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4 -#define ETH_PORT_ACCESS_CTRL_GAP 0x4 - -/* Gigabit Ethernet Unit Global Registers */ - -/* MIB Counters register definitions */ -#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0 -#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4 -#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8 -#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc -#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10 -#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14 -#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18 -#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c -#define ETH_MIB_FRAMES_64_OCTETS 0x20 -#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24 -#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28 -#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c -#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30 -#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 -#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38 -#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c -#define ETH_MIB_GOOD_FRAMES_SENT 0x40 -#define ETH_MIB_EXCESSIVE_COLLISION 0x44 -#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48 -#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c -#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50 -#define ETH_MIB_FC_SENT 0x54 -#define ETH_MIB_GOOD_FC_RECEIVED 0x58 -#define ETH_MIB_BAD_FC_RECEIVED 0x5c -#define ETH_MIB_UNDERSIZE_RECEIVED 0x60 -#define ETH_MIB_FRAGMENTS_RECEIVED 0x64 -#define ETH_MIB_OVERSIZE_RECEIVED 0x68 -#define ETH_MIB_JABBER_RECEIVED 0x6c -#define ETH_MIB_MAC_RECEIVE_ERROR 0x70 -#define ETH_MIB_BAD_CRC_EVENT 0x74 -#define ETH_MIB_COLLISION 0x78 -#define ETH_MIB_LATE_COLLISION 0x7c - -/* Port serial status reg (PSR) */ -#define ETH_INTERFACE_GMII_MII 0 -#define ETH_INTERFACE_PCM BIT0 -#define ETH_LINK_IS_DOWN 0 -#define ETH_LINK_IS_UP BIT1 -#define ETH_PORT_AT_HALF_DUPLEX 0 -#define ETH_PORT_AT_FULL_DUPLEX BIT2 -#define ETH_RX_FLOW_CTRL_DISABLED 0 -#define ETH_RX_FLOW_CTRL_ENBALED BIT3 -#define ETH_GMII_SPEED_100_10 0 -#define ETH_GMII_SPEED_1000 BIT4 -#define ETH_MII_SPEED_10 0 -#define ETH_MII_SPEED_100 BIT5 -#define ETH_NO_TX 0 -#define ETH_TX_IN_PROGRESS BIT7 -#define ETH_BYPASS_NO_ACTIVE 0 -#define ETH_BYPASS_ACTIVE BIT8 -#define ETH_PORT_NOT_AT_PARTITION_STATE 0 -#define ETH_PORT_AT_PARTITION_STATE BIT9 -#define ETH_PORT_TX_FIFO_NOT_EMPTY 0 -#define ETH_PORT_TX_FIFO_EMPTY BIT10 - - -/* These macros describes the Port configuration reg (Px_cR) bits */ -#define ETH_UNICAST_NORMAL_MODE 0 -#define ETH_UNICAST_PROMISCUOUS_MODE BIT0 -#define ETH_DEFAULT_RX_QUEUE_0 0 -#define ETH_DEFAULT_RX_QUEUE_1 BIT1 -#define ETH_DEFAULT_RX_QUEUE_2 BIT2 -#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1) -#define ETH_DEFAULT_RX_QUEUE_4 BIT3 -#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1) -#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2) -#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1) -#define ETH_DEFAULT_RX_ARP_QUEUE_0 0 -#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4 -#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5 -#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4) -#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6 -#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4) -#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5) -#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4) -#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0 -#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7 -#define ETH_RECEIVE_BC_IF_IP 0 -#define ETH_REJECT_BC_IF_IP BIT8 -#define ETH_RECEIVE_BC_IF_ARP 0 -#define ETH_REJECT_BC_IF_ARP BIT9 -#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12 -#define ETH_CAPTURE_TCP_FRAMES_DIS 0 -#define ETH_CAPTURE_TCP_FRAMES_EN BIT14 -#define ETH_CAPTURE_UDP_FRAMES_DIS 0 -#define ETH_CAPTURE_UDP_FRAMES_EN BIT15 -#define ETH_DEFAULT_RX_TCP_QUEUE_0 0 -#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16 -#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17 -#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16) -#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18 -#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16) -#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17) -#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16) -#define ETH_DEFAULT_RX_UDP_QUEUE_0 0 -#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19 -#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20 -#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19) -#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21 -#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19) -#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20) -#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19) -#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0 -#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22 -#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23 -#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22) -#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24 -#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22) -#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23) -#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22) - - -/* These macros describes the Port configuration extend reg (Px_cXR) bits*/ -#define ETH_CLASSIFY_EN BIT0 -#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0 -#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1 -#define ETH_PARTITION_DISABLE 0 -#define ETH_PARTITION_ENABLE BIT2 - - -/* Tx/Rx queue command reg (RQCR/TQCR)*/ -#define ETH_QUEUE_0_ENABLE BIT0 -#define ETH_QUEUE_1_ENABLE BIT1 -#define ETH_QUEUE_2_ENABLE BIT2 -#define ETH_QUEUE_3_ENABLE BIT3 -#define ETH_QUEUE_4_ENABLE BIT4 -#define ETH_QUEUE_5_ENABLE BIT5 -#define ETH_QUEUE_6_ENABLE BIT6 -#define ETH_QUEUE_7_ENABLE BIT7 -#define ETH_QUEUE_0_DISABLE BIT8 -#define ETH_QUEUE_1_DISABLE BIT9 -#define ETH_QUEUE_2_DISABLE BIT10 -#define ETH_QUEUE_3_DISABLE BIT11 -#define ETH_QUEUE_4_DISABLE BIT12 -#define ETH_QUEUE_5_DISABLE BIT13 -#define ETH_QUEUE_6_DISABLE BIT14 -#define ETH_QUEUE_7_DISABLE BIT15 - - -/* These macros describes the Port Sdma configuration reg (SDCR) bits */ -#define ETH_RIFB BIT0 -#define ETH_RX_BURST_SIZE_1_64BIT 0 -#define ETH_RX_BURST_SIZE_2_64BIT BIT1 -#define ETH_RX_BURST_SIZE_4_64BIT BIT2 -#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1) -#define ETH_RX_BURST_SIZE_16_64BIT BIT3 -#define ETH_BLM_RX_NO_SWAP BIT4 -#define ETH_BLM_RX_BYTE_SWAP 0 -#define ETH_BLM_TX_NO_SWAP BIT5 -#define ETH_BLM_TX_BYTE_SWAP 0 -#define ETH_DESCRIPTORS_BYTE_SWAP BIT6 -#define ETH_DESCRIPTORS_NO_SWAP 0 -#define ETH_TX_BURST_SIZE_1_64BIT 0 -#define ETH_TX_BURST_SIZE_2_64BIT BIT22 -#define ETH_TX_BURST_SIZE_4_64BIT BIT23 -#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22) -#define ETH_TX_BURST_SIZE_16_64BIT BIT24 - - -/* These macros describes the Port serial control reg (PSCR) bits */ -#define ETH_SERIAL_PORT_DISABLE 0 -#define ETH_SERIAL_PORT_ENABLE BIT0 -#define ETH_FORCE_LINK_PASS BIT1 -#define ETH_DO_NOT_FORCE_LINK_PASS 0 -#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0 -#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2 -#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0 -#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3 -#define ETH_ADV_NO_FLOW_CTRL 0 -#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4 -#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0 -#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5 -#define ETH_FORCE_BP_MODE_NO_JAM 0 -#define ETH_FORCE_BP_MODE_JAM_TX BIT7 -#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8 -#define ETH_FORCE_LINK_FAIL 0 -#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10 -#define ETH_RETRANSMIT_16_ETTEMPTS 0 -#define ETH_RETRANSMIT_FOREVER BIT11 -#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13 -#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0 -#define ETH_DTE_ADV_0 0 -#define ETH_DTE_ADV_1 BIT14 -#define ETH_DISABLE_AUTO_NEG_BYPASS 0 -#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15 -#define ETH_AUTO_NEG_NO_CHANGE 0 -#define ETH_RESTART_AUTO_NEG BIT16 -#define ETH_MAX_RX_PACKET_1518BYTE 0 -#define ETH_MAX_RX_PACKET_1522BYTE BIT17 -#define ETH_MAX_RX_PACKET_1552BYTE BIT18 -#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17) -#define ETH_MAX_RX_PACKET_9192BYTE BIT19 -#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17) -#define ETH_SET_EXT_LOOPBACK BIT20 -#define ETH_CLR_EXT_LOOPBACK 0 -#define ETH_SET_FULL_DUPLEX_MODE BIT21 -#define ETH_SET_HALF_DUPLEX_MODE 0 -#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22 -#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0 -#define ETH_SET_GMII_SPEED_TO_10_100 0 -#define ETH_SET_GMII_SPEED_TO_1000 BIT23 -#define ETH_SET_MII_SPEED_TO_10 0 -#define ETH_SET_MII_SPEED_TO_100 BIT24 - - -/* SMI reg */ -#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */ -#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */ -#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */ -#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */ - -/* SDMA command status fields macros */ - -/* Tx & Rx descriptors status */ -#define ETH_ERROR_SUMMARY (BIT0) - -/* Tx & Rx descriptors command */ -#define ETH_BUFFER_OWNED_BY_DMA (BIT31) - -/* Tx descriptors status */ -#define ETH_LC_ERROR (0 ) -#define ETH_UR_ERROR (BIT1 ) -#define ETH_RL_ERROR (BIT2 ) -#define ETH_LLC_SNAP_FORMAT (BIT9 ) - -/* Rx descriptors status */ -#define ETH_CRC_ERROR (0 ) -#define ETH_OVERRUN_ERROR (BIT1 ) -#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 ) -#define ETH_RESOURCE_ERROR ((BIT2 | BIT1)) -#define ETH_VLAN_TAGGED (BIT19) -#define ETH_BPDU_FRAME (BIT20) -#define ETH_TCP_FRAME_OVER_IP_V_4 (0 ) -#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21) -#define ETH_OTHER_FRAME_TYPE (BIT22) -#define ETH_LAYER_2_IS_ETH_V_2 (BIT23) -#define ETH_FRAME_TYPE_IP_V_4 (BIT24) -#define ETH_FRAME_HEADER_OK (BIT25) -#define ETH_RX_LAST_DESC (BIT26) -#define ETH_RX_FIRST_DESC (BIT27) -#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28) -#define ETH_RX_ENABLE_INTERRUPT (BIT29) -#define ETH_LAYER_4_CHECKSUM_OK (BIT30) - -/* Rx descriptors byte count */ -#define ETH_FRAME_FRAGMENTED (BIT2) - -/* Tx descriptors command */ -#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10) -#define ETH_FRAME_SET_TO_VLAN (BIT15) -#define ETH_TCP_FRAME (0 ) -#define ETH_UDP_FRAME (BIT16) -#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17) -#define ETH_GEN_IP_V_4_CHECKSUM (BIT18) -#define ETH_ZERO_PADDING (BIT19) -#define ETH_TX_LAST_DESC (BIT20) -#define ETH_TX_FIRST_DESC (BIT21) -#define ETH_GEN_CRC (BIT22) -#define ETH_TX_ENABLE_INTERRUPT (BIT23) -#define ETH_AUTO_MODE (BIT30) - -/* Address decode parameters */ -/* Ethernet Base Address Register bits */ -#define EBAR_TARGET_DRAM 0x00000000 -#define EBAR_TARGET_DEVICE 0x00000001 -#define EBAR_TARGET_CBS 0x00000002 -#define EBAR_TARGET_PCI0 0x00000003 -#define EBAR_TARGET_PCI1 0x00000004 -#define EBAR_TARGET_CUNIT 0x00000005 -#define EBAR_TARGET_AUNIT 0x00000006 -#define EBAR_TARGET_GUNIT 0x00000007 - -/* Window attributes */ -#define EBAR_ATTR_DRAM_CS0 0x00000E00 -#define EBAR_ATTR_DRAM_CS1 0x00000D00 -#define EBAR_ATTR_DRAM_CS2 0x00000B00 -#define EBAR_ATTR_DRAM_CS3 0x00000700 - -/* DRAM Target interface */ -#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000 -#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000 -#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000 - -/* Device Bus Target interface */ -#define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00 -#define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00 -#define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00 -#define EBAR_ATTR_DEVICE_DEVCS3 0x00001700 -#define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00 - -/* PCI Target interface */ -#define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000 -#define EBAR_ATTR_PCI_NO_SWAP 0x00000100 -#define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200 -#define EBAR_ATTR_PCI_WORD_SWAP 0x00000300 -#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000 -#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400 -#define EBAR_ATTR_PCI_IO_SPACE 0x00000000 -#define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800 -#define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000 -#define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000 - -/* CPU 60x bus or internal SRAM interface */ -#define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000 -#define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100 -#define EBAR_ATTR_CBS_SRAM 0x00000000 -#define EBAR_ATTR_CBS_CPU_BUS 0x00000800 - -/* Window access control */ -#define EWIN_ACCESS_NOT_ALLOWED 0 -#define EWIN_ACCESS_READ_ONLY BIT0 -#define EWIN_ACCESS_FULL (BIT1 | BIT0) -#define EWIN0_ACCESS_MASK 0x0003 -#define EWIN1_ACCESS_MASK 0x000C -#define EWIN2_ACCESS_MASK 0x0030 -#define EWIN3_ACCESS_MASK 0x00C0 - -/* typedefs */ - -typedef enum _eth_port -{ - ETH_0 = 0, - ETH_1 = 1, - ETH_2 = 2 -}ETH_PORT; - -typedef enum _eth_func_ret_status -{ - ETH_OK, /* Returned as expected. */ - ETH_ERROR, /* Fundamental error. */ - ETH_RETRY, /* Could not process request. Try later. */ - ETH_END_OF_JOB, /* Ring has nothing to process. */ - ETH_QUEUE_FULL, /* Ring resource error. */ - ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */ -}ETH_FUNC_RET_STATUS; - -typedef enum _eth_queue -{ - ETH_Q0 = 0, - ETH_Q1 = 1, - ETH_Q2 = 2, - ETH_Q3 = 3, - ETH_Q4 = 4, - ETH_Q5 = 5, - ETH_Q6 = 6, - ETH_Q7 = 7 -} ETH_QUEUE; - -typedef enum _addr_win -{ - ETH_WIN0, - ETH_WIN1, - ETH_WIN2, - ETH_WIN3, - ETH_WIN4, - ETH_WIN5 -} ETH_ADDR_WIN; - -typedef enum _eth_target -{ - ETH_TARGET_DRAM , - ETH_TARGET_DEVICE, - ETH_TARGET_CBS , - ETH_TARGET_PCI0 , - ETH_TARGET_PCI1 -}ETH_TARGET; - -typedef struct _eth_rx_desc -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short buf_size ; /* Buffer size */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int next_desc_ptr; /* Next descriptor pointer */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} ETH_RX_DESC; - - -typedef struct _eth_tx_desc -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short l4i_chk ; /* CPU provided TCP Checksum */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int next_desc_ptr; /* Next descriptor pointer */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} ETH_TX_DESC; - -/* Unified struct for Rx and Tx operations. The user is not required to */ -/* be familier with neither Tx nor Rx descriptors. */ -typedef struct _pkt_info -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} PKT_INFO; - - -typedef struct _eth_win_param -{ - ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */ - ETH_TARGET target; /* System targets. See ETH_TARGET enum */ - unsigned short attributes; /* BAR attributes. See above macros. */ - unsigned int base_addr; /* Window base address in unsigned int form */ - unsigned int high_addr; /* Window high address in unsigned int form */ - unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */ - bool enable; /* Enable/disable access to the window. */ - unsigned short access_ctrl; /* Access ctrl register. see above macros */ -} ETH_WIN_PARAM; - - -/* Ethernet port specific infomation */ - -typedef struct _eth_port_ctrl -{ - ETH_PORT port_num; /* User Ethernet port number */ - int port_phy_addr; /* User phy address of Ethrnet port */ - unsigned char port_mac_addr[6]; /* User defined port MAC address. */ - unsigned int port_config; /* User port configuration value */ - unsigned int port_config_extend; /* User port config extend value */ - unsigned int port_sdma_config; /* User port SDMA config value */ - unsigned int port_serial_control; /* User port serial control value */ - unsigned int port_tx_queue_command; /* Port active Tx queues summary */ - unsigned int port_rx_queue_command; /* Port active Rx queues summary */ - - /* User function to cast virtual address to CPU bus address */ - unsigned int (*port_virt_to_phys)(unsigned int addr); - /* User scratch pad for user specific data structures */ - void *port_private; - - bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */ - bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */ - - /* Tx/Rx rings managment indexes fields. For driver use */ - - /* Next available Rx resource */ - volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM]; - /* Returning Rx resource */ - volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM]; - - /* Next available Tx resource */ - volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM]; - /* Returning Tx resource */ - volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM]; - /* An extra Tx index to support transmit of multiple buffers per packet */ - volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM]; - - /* Tx/Rx rings size and base variables fields. For driver use */ - - volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM]; - unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM]; - char *p_rx_buffer_base[MAX_RX_QUEUE_NUM]; - - volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM]; - unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM]; - char *p_tx_buffer_base[MAX_TX_QUEUE_NUM]; - -} ETH_PORT_INFO; - - -/* ethernet.h API list */ - -/* Port operation control routines */ -static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl); -static void eth_port_reset(ETH_PORT eth_port_num); -static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl); - - -/* Port MAC address routines */ -static void eth_port_uc_addr_set (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue); -#if 0 /* FIXME */ -static void eth_port_mc_addr (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue, - int option); -#endif - -/* PHY and MIB routines */ -static bool ethernet_phy_reset(ETH_PORT eth_port_num); - -static bool eth_port_write_smi_reg(ETH_PORT eth_port_num, - unsigned int phy_reg, - unsigned int value); - -static bool eth_port_read_smi_reg(ETH_PORT eth_port_num, - unsigned int phy_reg, - unsigned int* value); - -static void eth_clear_mib_counters(ETH_PORT eth_port_num); - -/* Port data flow control routines */ -static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO *p_pkt_info); - - -static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - int tx_desc_num, - int tx_buff_size, - unsigned int tx_desc_base_addr, - unsigned int tx_buff_base_addr); - -static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - int rx_desc_num, - int rx_buff_size, - unsigned int rx_desc_base_addr, - unsigned int rx_buff_base_addr); - -#endif /* MV64360_ETH_ */ diff --git a/board/Marvell/db64360/mv_regs.h b/board/Marvell/db64360/mv_regs.h deleted file mode 100644 index 9a54a97..0000000 --- a/board/Marvell/db64360/mv_regs.h +++ /dev/null @@ -1,1108 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus <ingo.assmus@keymile.com> - * - * based on - Driver for MV64360X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/******************************************************************************** -* gt64360r.h - GT-64360 Internal registers definition file. -* -* DESCRIPTION: -* None. -* -* DEPENDENCIES: -* None. -* -*******************************************************************************/ - -#ifndef __INCmv_regsh -#define __INCmv_regsh - -#define MV64360 - -/* Supported by the Atlantis */ -#define MV64360_INCLUDE_PCI_1 -#define MV64360_INCLUDE_PCI_0_ARBITER -#define MV64360_INCLUDE_PCI_1_ARBITER -#define MV64360_INCLUDE_SNOOP_SUPPORT -#define MV64360_INCLUDE_P2P -#define MV64360_INCLUDE_ETH_PORT_2 -#define MV64360_INCLUDE_CPU_MAPPING -#define MV64360_INCLUDE_MPSC - -/* Not supported features */ -#undef INCLUDE_CNTMR_4_7 -#undef INCLUDE_DMA_4_7 - -/****************************************/ -/* Processor Address Space */ -/****************************************/ - -/* DDR SDRAM BAR and size registers */ - -#define MV64360_CS_0_BASE_ADDR 0x008 -#define MV64360_CS_0_SIZE 0x010 -#define MV64360_CS_1_BASE_ADDR 0x208 -#define MV64360_CS_1_SIZE 0x210 -#define MV64360_CS_2_BASE_ADDR 0x018 -#define MV64360_CS_2_SIZE 0x020 -#define MV64360_CS_3_BASE_ADDR 0x218 -#define MV64360_CS_3_SIZE 0x220 - -/* Devices BAR and size registers */ - -#define MV64360_DEV_CS0_BASE_ADDR 0x028 -#define MV64360_DEV_CS0_SIZE 0x030 -#define MV64360_DEV_CS1_BASE_ADDR 0x228 -#define MV64360_DEV_CS1_SIZE 0x230 -#define MV64360_DEV_CS2_BASE_ADDR 0x248 -#define MV64360_DEV_CS2_SIZE 0x250 -#define MV64360_DEV_CS3_BASE_ADDR 0x038 -#define MV64360_DEV_CS3_SIZE 0x040 -#define MV64360_BOOTCS_BASE_ADDR 0x238 -#define MV64360_BOOTCS_SIZE 0x240 - -/* PCI 0 BAR and size registers */ - -#define MV64360_PCI_0_IO_BASE_ADDR 0x048 -#define MV64360_PCI_0_IO_SIZE 0x050 -#define MV64360_PCI_0_MEMORY0_BASE_ADDR 0x058 -#define MV64360_PCI_0_MEMORY0_SIZE 0x060 -#define MV64360_PCI_0_MEMORY1_BASE_ADDR 0x080 -#define MV64360_PCI_0_MEMORY1_SIZE 0x088 -#define MV64360_PCI_0_MEMORY2_BASE_ADDR 0x258 -#define MV64360_PCI_0_MEMORY2_SIZE 0x260 -#define MV64360_PCI_0_MEMORY3_BASE_ADDR 0x280 -#define MV64360_PCI_0_MEMORY3_SIZE 0x288 - -/* PCI 1 BAR and size registers */ -#define MV64360_PCI_1_IO_BASE_ADDR 0x090 -#define MV64360_PCI_1_IO_SIZE 0x098 -#define MV64360_PCI_1_MEMORY0_BASE_ADDR 0x0a0 -#define MV64360_PCI_1_MEMORY0_SIZE 0x0a8 -#define MV64360_PCI_1_MEMORY1_BASE_ADDR 0x0b0 -#define MV64360_PCI_1_MEMORY1_SIZE 0x0b8 -#define MV64360_PCI_1_MEMORY2_BASE_ADDR 0x2a0 -#define MV64360_PCI_1_MEMORY2_SIZE 0x2a8 -#define MV64360_PCI_1_MEMORY3_BASE_ADDR 0x2b0 -#define MV64360_PCI_1_MEMORY3_SIZE 0x2b8 - -/* SRAM base address */ -#define MV64360_INTEGRATED_SRAM_BASE_ADDR 0x268 - -/* internal registers space base address */ -#define MV64360_INTERNAL_SPACE_BASE_ADDR 0x068 - -/* Enables the CS , DEV_CS , PCI 0 and PCI 1 - windows above */ -#define MV64360_BASE_ADDR_ENABLE 0x278 - -/****************************************/ -/* PCI remap registers */ -/****************************************/ - /* PCI 0 */ -#define MV64360_PCI_0_IO_ADDR_REMAP 0x0f0 -#define MV64360_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8 -#define MV64360_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320 -#define MV64360_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100 -#define MV64360_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328 -#define MV64360_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8 -#define MV64360_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330 -#define MV64360_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300 -#define MV64360_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338 - /* PCI 1 */ -#define MV64360_PCI_1_IO_ADDR_REMAP 0x108 -#define MV64360_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110 -#define MV64360_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340 -#define MV64360_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118 -#define MV64360_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348 -#define MV64360_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310 -#define MV64360_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350 -#define MV64360_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318 -#define MV64360_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358 - -#define MV64360_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0 -#define MV64360_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8 -#define MV64360_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0 -#define MV64360_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8 -#define MV64360_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0 -#define MV64360_CPU_GE_HEADERS_RETARGET_BASE 0x3d8 -#define MV64360_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0 -#define MV64360_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8 - -/****************************************/ -/* CPU Control Registers */ -/****************************************/ - -#define MV64360_CPU_CONFIG 0x000 -#define MV64360_CPU_MODE 0x120 -#define MV64360_CPU_MASTER_CONTROL 0x160 -#define MV64360_CPU_CROSS_BAR_CONTROL_LOW 0x150 -#define MV64360_CPU_CROSS_BAR_CONTROL_HIGH 0x158 -#define MV64360_CPU_CROSS_BAR_TIMEOUT 0x168 - -/****************************************/ -/* SMP RegisterS */ -/****************************************/ - -#define MV64360_SMP_WHO_AM_I 0x200 -#define MV64360_SMP_CPU0_DOORBELL 0x214 -#define MV64360_SMP_CPU0_DOORBELL_CLEAR 0x21C -#define MV64360_SMP_CPU1_DOORBELL 0x224 -#define MV64360_SMP_CPU1_DOORBELL_CLEAR 0x22C -#define MV64360_SMP_CPU0_DOORBELL_MASK 0x234 -#define MV64360_SMP_CPU1_DOORBELL_MASK 0x23C -#define MV64360_SMP_SEMAPHOR0 0x244 -#define MV64360_SMP_SEMAPHOR1 0x24c -#define MV64360_SMP_SEMAPHOR2 0x254 -#define MV64360_SMP_SEMAPHOR3 0x25c -#define MV64360_SMP_SEMAPHOR4 0x264 -#define MV64360_SMP_SEMAPHOR5 0x26c -#define MV64360_SMP_SEMAPHOR6 0x274 -#define MV64360_SMP_SEMAPHOR7 0x27c - -/****************************************/ -/* CPU Sync Barrier Register */ -/****************************************/ - -#define MV64360_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0 -#define MV64360_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8 -#define MV64360_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0 -#define MV64360_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8 - -/****************************************/ -/* CPU Access Protect */ -/****************************************/ - -#define MV64360_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180 -#define MV64360_CPU_PROTECT_WINDOW_0_SIZE 0x188 -#define MV64360_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190 -#define MV64360_CPU_PROTECT_WINDOW_1_SIZE 0x198 -#define MV64360_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0 -#define MV64360_CPU_PROTECT_WINDOW_2_SIZE 0x1a8 -#define MV64360_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0 -#define MV64360_CPU_PROTECT_WINDOW_3_SIZE 0x1b8 - - -/****************************************/ -/* CPU Error Report */ -/****************************************/ - -#define MV64360_CPU_ERROR_ADDR_LOW 0x070 -#define MV64360_CPU_ERROR_ADDR_HIGH 0x078 -#define MV64360_CPU_ERROR_DATA_LOW 0x128 -#define MV64360_CPU_ERROR_DATA_HIGH 0x130 -#define MV64360_CPU_ERROR_PARITY 0x138 -#define MV64360_CPU_ERROR_CAUSE 0x140 -#define MV64360_CPU_ERROR_MASK 0x148 - -/****************************************/ -/* CPU Interface Debug Registers */ -/****************************************/ - -#define MV64360_PUNIT_SLAVE_DEBUG_LOW 0x360 -#define MV64360_PUNIT_SLAVE_DEBUG_HIGH 0x368 -#define MV64360_PUNIT_MASTER_DEBUG_LOW 0x370 -#define MV64360_PUNIT_MASTER_DEBUG_HIGH 0x378 -#define MV64360_PUNIT_MMASK 0x3e4 - -/****************************************/ -/* Integrated SRAM Registers */ -/****************************************/ - -#define MV64360_SRAM_CONFIG 0x380 -#define MV64360_SRAM_TEST_MODE 0X3F4 -#define MV64360_SRAM_ERROR_CAUSE 0x388 -#define MV64360_SRAM_ERROR_ADDR 0x390 -#define MV64360_SRAM_ERROR_ADDR_HIGH 0X3F8 -#define MV64360_SRAM_ERROR_DATA_LOW 0x398 -#define MV64360_SRAM_ERROR_DATA_HIGH 0x3a0 -#define MV64360_SRAM_ERROR_DATA_PARITY 0x3a8 - -/****************************************/ -/* SDRAM Configuration */ -/****************************************/ - -#define MV64360_SDRAM_CONFIG 0x1400 -#define MV64360_D_UNIT_CONTROL_LOW 0x1404 -#define MV64360_D_UNIT_CONTROL_HIGH 0x1424 -#define MV64360_SDRAM_TIMING_CONTROL_LOW 0x1408 -#define MV64360_SDRAM_TIMING_CONTROL_HIGH 0x140c -#define MV64360_SDRAM_ADDR_CONTROL 0x1410 -#define MV64360_SDRAM_OPEN_PAGES_CONTROL 0x1414 -#define MV64360_SDRAM_OPERATION 0x1418 -#define MV64360_SDRAM_MODE 0x141c -#define MV64360_EXTENDED_DRAM_MODE 0x1420 -#define MV64360_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430 -#define MV64360_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434 -#define MV64360_SDRAM_CROSS_BAR_TIMEOUT 0x1438 -#define MV64360_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0 -#define MV64360_SDRAM_DATA_PADS_CALIBRATION 0x14c4 - -/****************************************/ -/* SDRAM Error Report */ -/****************************************/ - -#define MV64360_SDRAM_ERROR_DATA_LOW 0x1444 -#define MV64360_SDRAM_ERROR_DATA_HIGH 0x1440 -#define MV64360_SDRAM_ERROR_ADDR 0x1450 -#define MV64360_SDRAM_RECEIVED_ECC 0x1448 -#define MV64360_SDRAM_CALCULATED_ECC 0x144c -#define MV64360_SDRAM_ECC_CONTROL 0x1454 -#define MV64360_SDRAM_ECC_ERROR_COUNTER 0x1458 - -/******************************************/ -/* Controlled Delay Line (CDL) Registers */ -/******************************************/ - -#define MV64360_DFCDL_CONFIG0 0x1480 -#define MV64360_DFCDL_CONFIG1 0x1484 -#define MV64360_DLL_WRITE 0x1488 -#define MV64360_DLL_READ 0x148c -#define MV64360_SRAM_ADDR 0x1490 -#define MV64360_SRAM_DATA0 0x1494 -#define MV64360_SRAM_DATA1 0x1498 -#define MV64360_SRAM_DATA2 0x149c -#define MV64360_DFCL_PROBE 0x14a0 - -/******************************************/ -/* Debug Registers */ -/******************************************/ - -#define MV64360_DUNIT_DEBUG_LOW 0x1460 -#define MV64360_DUNIT_DEBUG_HIGH 0x1464 -#define MV64360_DUNIT_MMASK 0X1b40 - -/****************************************/ -/* Device Parameters */ -/****************************************/ - -#define MV64360_DEVICE_BANK0_PARAMETERS 0x45c -#define MV64360_DEVICE_BANK1_PARAMETERS 0x460 -#define MV64360_DEVICE_BANK2_PARAMETERS 0x464 -#define MV64360_DEVICE_BANK3_PARAMETERS 0x468 -#define MV64360_DEVICE_BOOT_BANK_PARAMETERS 0x46c -#define MV64360_DEVICE_INTERFACE_CONTROL 0x4c0 -#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8 -#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc -#define MV64360_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4 - -/****************************************/ -/* Device interrupt registers */ -/****************************************/ - -#define MV64360_DEVICE_INTERRUPT_CAUSE 0x4d0 -#define MV64360_DEVICE_INTERRUPT_MASK 0x4d4 -#define MV64360_DEVICE_ERROR_ADDR 0x4d8 -#define MV64360_DEVICE_ERROR_DATA 0x4dc -#define MV64360_DEVICE_ERROR_PARITY 0x4e0 - -/****************************************/ -/* Device debug registers */ -/****************************************/ - -#define MV64360_DEVICE_DEBUG_LOW 0x4e4 -#define MV64360_DEVICE_DEBUG_HIGH 0x4e8 -#define MV64360_RUNIT_MMASK 0x4f0 - -/****************************************/ -/* PCI Slave Address Decoding registers */ -/****************************************/ - -#define MV64360_PCI_0_CS_0_BANK_SIZE 0xc08 -#define MV64360_PCI_1_CS_0_BANK_SIZE 0xc88 -#define MV64360_PCI_0_CS_1_BANK_SIZE 0xd08 -#define MV64360_PCI_1_CS_1_BANK_SIZE 0xd88 -#define MV64360_PCI_0_CS_2_BANK_SIZE 0xc0c -#define MV64360_PCI_1_CS_2_BANK_SIZE 0xc8c -#define MV64360_PCI_0_CS_3_BANK_SIZE 0xd0c -#define MV64360_PCI_1_CS_3_BANK_SIZE 0xd8c -#define MV64360_PCI_0_DEVCS_0_BANK_SIZE 0xc10 -#define MV64360_PCI_1_DEVCS_0_BANK_SIZE 0xc90 -#define MV64360_PCI_0_DEVCS_1_BANK_SIZE 0xd10 -#define MV64360_PCI_1_DEVCS_1_BANK_SIZE 0xd90 -#define MV64360_PCI_0_DEVCS_2_BANK_SIZE 0xd18 -#define MV64360_PCI_1_DEVCS_2_BANK_SIZE 0xd98 -#define MV64360_PCI_0_DEVCS_3_BANK_SIZE 0xc14 -#define MV64360_PCI_1_DEVCS_3_BANK_SIZE 0xc94 -#define MV64360_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14 -#define MV64360_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94 -#define MV64360_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c -#define MV64360_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c -#define MV64360_PCI_0_P2P_MEM1_BAR_SIZE 0xd20 -#define MV64360_PCI_1_P2P_MEM1_BAR_SIZE 0xda0 -#define MV64360_PCI_0_P2P_I_O_BAR_SIZE 0xd24 -#define MV64360_PCI_1_P2P_I_O_BAR_SIZE 0xda4 -#define MV64360_PCI_0_CPU_BAR_SIZE 0xd28 -#define MV64360_PCI_1_CPU_BAR_SIZE 0xda8 -#define MV64360_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00 -#define MV64360_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80 -#define MV64360_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c -#define MV64360_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c -#define MV64360_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c -#define MV64360_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc -#define MV64360_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48 -#define MV64360_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8 -#define MV64360_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48 -#define MV64360_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8 -#define MV64360_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c -#define MV64360_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc -#define MV64360_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c -#define MV64360_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc -#define MV64360_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04 -#define MV64360_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84 -#define MV64360_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08 -#define MV64360_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88 -#define MV64360_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C -#define MV64360_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C -#define MV64360_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10 -#define MV64360_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90 -#define MV64360_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50 -#define MV64360_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0 -#define MV64360_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50 -#define MV64360_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0 -#define MV64360_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58 -#define MV64360_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8 -#define MV64360_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54 -#define MV64360_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4 -#define MV64360_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54 -#define MV64360_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4 -#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c -#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc -#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60 -#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0 -#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64 -#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4 -#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68 -#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8 -#define MV64360_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c -#define MV64360_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec -#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70 -#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0 -#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74 -#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4 -#define MV64360_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00 -#define MV64360_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80 -#define MV64360_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38 -#define MV64360_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8 -#define MV64360_PCI_0_ADDR_DECODE_CONTROL 0xd3c -#define MV64360_PCI_1_ADDR_DECODE_CONTROL 0xdbc -#define MV64360_PCI_0_HEADERS_RETARGET_CONTROL 0xF40 -#define MV64360_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0 -#define MV64360_PCI_0_HEADERS_RETARGET_BASE 0xF44 -#define MV64360_PCI_1_HEADERS_RETARGET_BASE 0xFc4 -#define MV64360_PCI_0_HEADERS_RETARGET_HIGH 0xF48 -#define MV64360_PCI_1_HEADERS_RETARGET_HIGH 0xFc8 - -/***********************************/ -/* PCI Control Register Map */ -/***********************************/ - -#define MV64360_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20 -#define MV64360_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0 -#define MV64360_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C -#define MV64360_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C -#define MV64360_PCI_0_COMMAND 0xc00 -#define MV64360_PCI_1_COMMAND 0xc80 -#define MV64360_PCI_0_MODE 0xd00 -#define MV64360_PCI_1_MODE 0xd80 -#define MV64360_PCI_0_RETRY 0xc04 -#define MV64360_PCI_1_RETRY 0xc84 -#define MV64360_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04 -#define MV64360_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84 -#define MV64360_PCI_0_MSI_TRIGGER_TIMER 0xc38 -#define MV64360_PCI_1_MSI_TRIGGER_TIMER 0xcb8 -#define MV64360_PCI_0_ARBITER_CONTROL 0x1d00 -#define MV64360_PCI_1_ARBITER_CONTROL 0x1d80 -#define MV64360_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08 -#define MV64360_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88 -#define MV64360_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c -#define MV64360_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c -#define MV64360_PCI_0_CROSS_BAR_TIMEOUT 0x1d04 -#define MV64360_PCI_1_CROSS_BAR_TIMEOUT 0x1d84 -#define MV64360_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18 -#define MV64360_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98 -#define MV64360_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10 -#define MV64360_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90 -#define MV64360_PCI_0_P2P_CONFIG 0x1d14 -#define MV64360_PCI_1_P2P_CONFIG 0x1d94 - -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58 - -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8 - -/****************************************/ -/* PCI Configuration Access Registers */ -/****************************************/ - -#define MV64360_PCI_0_CONFIG_ADDR 0xcf8 -#define MV64360_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc -#define MV64360_PCI_1_CONFIG_ADDR 0xc78 -#define MV64360_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c -#define MV64360_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34 -#define MV64360_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4 - -/****************************************/ -/* PCI Error Report Registers */ -/****************************************/ - -#define MV64360_PCI_0_SERR_MASK 0xc28 -#define MV64360_PCI_1_SERR_MASK 0xca8 -#define MV64360_PCI_0_ERROR_ADDR_LOW 0x1d40 -#define MV64360_PCI_1_ERROR_ADDR_LOW 0x1dc0 -#define MV64360_PCI_0_ERROR_ADDR_HIGH 0x1d44 -#define MV64360_PCI_1_ERROR_ADDR_HIGH 0x1dc4 -#define MV64360_PCI_0_ERROR_ATTRIBUTE 0x1d48 -#define MV64360_PCI_1_ERROR_ATTRIBUTE 0x1dc8 -#define MV64360_PCI_0_ERROR_COMMAND 0x1d50 -#define MV64360_PCI_1_ERROR_COMMAND 0x1dd0 -#define MV64360_PCI_0_ERROR_CAUSE 0x1d58 -#define MV64360_PCI_1_ERROR_CAUSE 0x1dd8 -#define MV64360_PCI_0_ERROR_MASK 0x1d5c -#define MV64360_PCI_1_ERROR_MASK 0x1ddc - -/****************************************/ -/* PCI Debug Registers */ -/****************************************/ - -#define MV64360_PCI_0_MMASK 0X1D24 -#define MV64360_PCI_1_MMASK 0X1DA4 - -/*********************************************/ -/* PCI Configuration, Function 0, Registers */ -/*********************************************/ - -#define MV64360_PCI_DEVICE_AND_VENDOR_ID 0x000 -#define MV64360_PCI_STATUS_AND_COMMAND 0x004 -#define MV64360_PCI_CLASS_CODE_AND_REVISION_ID 0x008 -#define MV64360_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C - -#define MV64360_PCI_SCS_0_BASE_ADDR_LOW 0x010 -#define MV64360_PCI_SCS_0_BASE_ADDR_HIGH 0x014 -#define MV64360_PCI_SCS_1_BASE_ADDR_LOW 0x018 -#define MV64360_PCI_SCS_1_BASE_ADDR_HIGH 0x01C -#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020 -#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024 -#define MV64360_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c -#define MV64360_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 -#define MV64360_PCI_CAPABILTY_LIST_POINTER 0x034 -#define MV64360_PCI_INTERRUPT_PIN_AND_LINE 0x03C - /* capability list */ -#define MV64360_PCI_POWER_MANAGEMENT_CAPABILITY 0x040 -#define MV64360_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 -#define MV64360_PCI_VPD_ADDR 0x048 -#define MV64360_PCI_VPD_DATA 0x04c -#define MV64360_PCI_MSI_MESSAGE_CONTROL 0x050 -#define MV64360_PCI_MSI_MESSAGE_ADDR 0x054 -#define MV64360_PCI_MSI_MESSAGE_UPPER_ADDR 0x058 -#define MV64360_PCI_MSI_MESSAGE_DATA 0x05c -#define MV64360_PCI_X_COMMAND 0x060 -#define MV64360_PCI_X_STATUS 0x064 -#define MV64360_PCI_COMPACT_PCI_HOT_SWAP 0x068 - -/***********************************************/ -/* PCI Configuration, Function 1, Registers */ -/***********************************************/ - -#define MV64360_PCI_SCS_2_BASE_ADDR_LOW 0x110 -#define MV64360_PCI_SCS_2_BASE_ADDR_HIGH 0x114 -#define MV64360_PCI_SCS_3_BASE_ADDR_LOW 0x118 -#define MV64360_PCI_SCS_3_BASE_ADDR_HIGH 0x11c -#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120 -#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124 - -/***********************************************/ -/* PCI Configuration, Function 2, Registers */ -/***********************************************/ - -#define MV64360_PCI_DEVCS_0_BASE_ADDR_LOW 0x210 -#define MV64360_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214 -#define MV64360_PCI_DEVCS_1_BASE_ADDR_LOW 0x218 -#define MV64360_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c -#define MV64360_PCI_DEVCS_2_BASE_ADDR_LOW 0x220 -#define MV64360_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224 - -/***********************************************/ -/* PCI Configuration, Function 3, Registers */ -/***********************************************/ - -#define MV64360_PCI_DEVCS_3_BASE_ADDR_LOW 0x310 -#define MV64360_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314 -#define MV64360_PCI_BOOT_CS_BASE_ADDR_LOW 0x318 -#define MV64360_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c -#define MV64360_PCI_CPU_BASE_ADDR_LOW 0x220 -#define MV64360_PCI_CPU_BASE_ADDR_HIGH 0x224 - -/***********************************************/ -/* PCI Configuration, Function 4, Registers */ -/***********************************************/ - -#define MV64360_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410 -#define MV64360_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414 -#define MV64360_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418 -#define MV64360_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c -#define MV64360_PCI_P2P_I_O_BASE_ADDR 0x420 -#define MV64360_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424 - -/****************************************/ -/* Messaging Unit Registers (I20) */ -/****************************************/ - -#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010 -#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C -#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020 -#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024 -#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028 -#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C -#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030 -#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034 -#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040 -#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044 -#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050 -#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054 -#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060 -#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064 -#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068 -#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C -#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070 -#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074 -#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8 -#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC - -#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090 -#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C -#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0 -#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4 -#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8 -#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC -#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0 -#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4 -#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0 -#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4 -#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0 -#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4 -#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0 -#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4 -#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8 -#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC -#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0 -#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4 -#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078 -#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C - -#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10 -#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C -#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20 -#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24 -#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28 -#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C -#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30 -#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34 -#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40 -#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44 -#define MV64360_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50 -#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54 -#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60 -#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64 -#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68 -#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C -#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70 -#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74 -#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8 -#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC -#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90 -#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C -#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0 -#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4 -#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8 -#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC -#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0 -#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4 -#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0 -#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4 -#define MV64360_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0 -#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4 -#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0 -#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4 -#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8 -#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC -#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0 -#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4 -#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78 -#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C - -/****************************************/ -/* Ethernet Unit Registers */ -/****************************************/ - -#define MV64360_ETH_PHY_ADDR_REG 0x2000 -#define MV64360_ETH_SMI_REG 0x2004 -#define MV64360_ETH_UNIT_DEFAULT_ADDR_REG 0x2008 -#define MV64360_ETH_UNIT_DEFAULTID_REG 0x200c -#define MV64360_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080 -#define MV64360_ETH_UNIT_INTERRUPT_MASK_REG 0x2084 -#define MV64360_ETH_UNIT_INTERNAL_USE_REG 0x24fc -#define MV64360_ETH_UNIT_ERROR_ADDR_REG 0x2094 -#define MV64360_ETH_BAR_0 0x2200 -#define MV64360_ETH_BAR_1 0x2208 -#define MV64360_ETH_BAR_2 0x2210 -#define MV64360_ETH_BAR_3 0x2218 -#define MV64360_ETH_BAR_4 0x2220 -#define MV64360_ETH_BAR_5 0x2228 -#define MV64360_ETH_SIZE_REG_0 0x2204 -#define MV64360_ETH_SIZE_REG_1 0x220c -#define MV64360_ETH_SIZE_REG_2 0x2214 -#define MV64360_ETH_SIZE_REG_3 0x221c -#define MV64360_ETH_SIZE_REG_4 0x2224 -#define MV64360_ETH_SIZE_REG_5 0x222c -#define MV64360_ETH_HEADERS_RETARGET_BASE_REG 0x2230 -#define MV64360_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234 -#define MV64360_ETH_HIGH_ADDR_REMAP_REG_0 0x2280 -#define MV64360_ETH_HIGH_ADDR_REMAP_REG_1 0x2284 -#define MV64360_ETH_HIGH_ADDR_REMAP_REG_2 0x2288 -#define MV64360_ETH_HIGH_ADDR_REMAP_REG_3 0x228c -#define MV64360_ETH_BASE_ADDR_ENABLE_REG 0x2290 -#define MV64360_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2)) -#define MV64360_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7)) -#define MV64360_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10)) -#define MV64360_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10)) -#define MV64360_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10)) -#define MV64360_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10)) -#define MV64360_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10)) -#define MV64360_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10)) -#define MV64360_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10)) -#define MV64360_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10)) -#define MV64360_ETH_DSCP_0(port) (0x2420 + (port<<10)) -#define MV64360_ETH_DSCP_1(port) (0x2424 + (port<<10)) -#define MV64360_ETH_DSCP_2(port) (0x2428 + (port<<10)) -#define MV64360_ETH_DSCP_3(port) (0x242c + (port<<10)) -#define MV64360_ETH_DSCP_4(port) (0x2430 + (port<<10)) -#define MV64360_ETH_DSCP_5(port) (0x2434 + (port<<10)) -#define MV64360_ETH_DSCP_6(port) (0x2438 + (port<<10)) -#define MV64360_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10)) -#define MV64360_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10)) -#define MV64360_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10)) -#define MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10)) -#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10)) -#define MV64360_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10)) -#define MV64360_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10)) -#define MV64360_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10)) -#define MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10)) -#define MV64360_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10)) -#define MV64360_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10)) -#define MV64360_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10)) -#define MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10)) -#define MV64360_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10)) -#define MV64360_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10) -#define MV64360_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10)) -#define MV64360_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10)) -#define MV64360_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10)) -#define MV64360_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10)) -#define MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10)) -#define MV64360_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10)) -#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10)) -#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10)) -#define MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10)) -#define MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10)) -#define MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10)) - -/*******************************************/ -/* CUNIT Registers */ -/*******************************************/ - - /* Address Decoding Register Map */ - -#define MV64360_CUNIT_BASE_ADDR_REG0 0xf200 -#define MV64360_CUNIT_BASE_ADDR_REG1 0xf208 -#define MV64360_CUNIT_BASE_ADDR_REG2 0xf210 -#define MV64360_CUNIT_BASE_ADDR_REG3 0xf218 -#define MV64360_CUNIT_SIZE0 0xf204 -#define MV64360_CUNIT_SIZE1 0xf20c -#define MV64360_CUNIT_SIZE2 0xf214 -#define MV64360_CUNIT_SIZE3 0xf21c -#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240 -#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244 -#define MV64360_CUNIT_BASE_ADDR_ENABLE_REG 0xf250 -#define MV64360_MPSC0_ACCESS_PROTECTION_REG 0xf254 -#define MV64360_MPSC1_ACCESS_PROTECTION_REG 0xf258 -#define MV64360_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C - - /* Error Report Registers */ - -#define MV64360_CUNIT_INTERRUPT_CAUSE_REG 0xf310 -#define MV64360_CUNIT_INTERRUPT_MASK_REG 0xf314 -#define MV64360_CUNIT_ERROR_ADDR 0xf318 - - /* Cunit Control Registers */ - -#define MV64360_CUNIT_ARBITER_CONTROL_REG 0xf300 -#define MV64360_CUNIT_CONFIG_REG 0xb40c -#define MV64360_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304 - - /* Cunit Debug Registers */ - -#define MV64360_CUNIT_DEBUG_LOW 0xf340 -#define MV64360_CUNIT_DEBUG_HIGH 0xf344 -#define MV64360_CUNIT_MMASK 0xf380 - - /* Cunit Base Address Enable Window Bits*/ -#define MV64360_CUNIT_BASE_ADDR_WIN_0_BIT 0x0 -#define MV64360_CUNIT_BASE_ADDR_WIN_1_BIT 0x1 -#define MV64360_CUNIT_BASE_ADDR_WIN_2_BIT 0x2 -#define MV64360_CUNIT_BASE_ADDR_WIN_3_BIT 0x3 - - /* MPSCs Clocks Routing Registers */ - -#define MV64360_MPSC_ROUTING_REG 0xb400 -#define MV64360_MPSC_RX_CLOCK_ROUTING_REG 0xb404 -#define MV64360_MPSC_TX_CLOCK_ROUTING_REG 0xb408 - - /* MPSCs Interrupts Registers */ - -#define MV64360_MPSC_CAUSE_REG(port) (0xb804 + (port<<3)) -#define MV64360_MPSC_MASK_REG(port) (0xb884 + (port<<3)) - -#define MV64360_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12)) -#define MV64360_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12)) -#define MV64360_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG1(port) (0x800c + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG5(port) (0x801c + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG9(port) (0x802c + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12)) - - /* MPSC0 Registers */ - - -/***************************************/ -/* SDMA Registers */ -/***************************************/ - -#define MV64360_SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13)) -#define MV64360_SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13)) -#define MV64360_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13)) -#define MV64360_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13)) -#define MV64360_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13)) - -#define MV64360_SDMA_CAUSE_REG 0xb800 -#define MV64360_SDMA_MASK_REG 0xb880 - - -/****************************************/ -/* SDMA Address Space Targets */ -/****************************************/ - -#define MV64360_SDMA_DRAM_CS_0_TARGET 0x0e00 -#define MV64360_SDMA_DRAM_CS_1_TARGET 0x0d00 -#define MV64360_SDMA_DRAM_CS_2_TARGET 0x0b00 -#define MV64360_SDMA_DRAM_CS_3_TARGET 0x0700 - -#define MV64360_SDMA_DEV_CS_0_TARGET 0x1e01 -#define MV64360_SDMA_DEV_CS_1_TARGET 0x1d01 -#define MV64360_SDMA_DEV_CS_2_TARGET 0x1b01 -#define MV64360_SDMA_DEV_CS_3_TARGET 0x1701 - -#define MV64360_SDMA_BOOT_CS_TARGET 0x0f00 - -#define MV64360_SDMA_SRAM_TARGET 0x0003 -#define MV64360_SDMA_60X_BUS_TARGET 0x4003 - -#define MV64360_PCI_0_TARGET 0x0003 -#define MV64360_PCI_1_TARGET 0x0004 - - -/* Devices BAR and size registers */ - -#define MV64360_DEV_CS0_BASE_ADDR 0x028 -#define MV64360_DEV_CS0_SIZE 0x030 -#define MV64360_DEV_CS1_BASE_ADDR 0x228 -#define MV64360_DEV_CS1_SIZE 0x230 -#define MV64360_DEV_CS2_BASE_ADDR 0x248 -#define MV64360_DEV_CS2_SIZE 0x250 -#define MV64360_DEV_CS3_BASE_ADDR 0x038 -#define MV64360_DEV_CS3_SIZE 0x040 -#define MV64360_BOOTCS_BASE_ADDR 0x238 -#define MV64360_BOOTCS_SIZE 0x240 - -/* SDMA Window access protection */ -#define MV64360_SDMA_WIN_ACCESS_NOT_ALLOWED 0 -#define MV64360_SDMA_WIN_ACCESS_READ_ONLY 1 -#define MV64360_SDMA_WIN_ACCESS_FULL 2 - -/* BRG Interrupts */ - -#define MV64360_BRG_CONFIG_REG(brg) (0xb200 + (brg<<3)) -#define MV64360_BRG_BAUDE_TUNING_REG(brg) (0xb204 + (brg<<3)) -#define MV64360_BRG_CAUSE_REG 0xb834 -#define MV64360_BRG_MASK_REG 0xb8b4 - -/****************************************/ -/* DMA Channel Control */ -/****************************************/ - -#define MV64360_DMA_CHANNEL0_CONTROL 0x840 -#define MV64360_DMA_CHANNEL0_CONTROL_HIGH 0x880 -#define MV64360_DMA_CHANNEL1_CONTROL 0x844 -#define MV64360_DMA_CHANNEL1_CONTROL_HIGH 0x884 -#define MV64360_DMA_CHANNEL2_CONTROL 0x848 -#define MV64360_DMA_CHANNEL2_CONTROL_HIGH 0x888 -#define MV64360_DMA_CHANNEL3_CONTROL 0x84C -#define MV64360_DMA_CHANNEL3_CONTROL_HIGH 0x88C - - -/****************************************/ -/* IDMA Registers */ -/****************************************/ - -#define MV64360_DMA_CHANNEL0_BYTE_COUNT 0x800 -#define MV64360_DMA_CHANNEL1_BYTE_COUNT 0x804 -#define MV64360_DMA_CHANNEL2_BYTE_COUNT 0x808 -#define MV64360_DMA_CHANNEL3_BYTE_COUNT 0x80C -#define MV64360_DMA_CHANNEL0_SOURCE_ADDR 0x810 -#define MV64360_DMA_CHANNEL1_SOURCE_ADDR 0x814 -#define MV64360_DMA_CHANNEL2_SOURCE_ADDR 0x818 -#define MV64360_DMA_CHANNEL3_SOURCE_ADDR 0x81c -#define MV64360_DMA_CHANNEL0_DESTINATION_ADDR 0x820 -#define MV64360_DMA_CHANNEL1_DESTINATION_ADDR 0x824 -#define MV64360_DMA_CHANNEL2_DESTINATION_ADDR 0x828 -#define MV64360_DMA_CHANNEL3_DESTINATION_ADDR 0x82C -#define MV64360_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830 -#define MV64360_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834 -#define MV64360_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838 -#define MV64360_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C -#define MV64360_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870 -#define MV64360_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874 -#define MV64360_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878 -#define MV64360_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C - - /* IDMA Address Decoding Base Address Registers */ - -#define MV64360_DMA_BASE_ADDR_REG0 0xa00 -#define MV64360_DMA_BASE_ADDR_REG1 0xa08 -#define MV64360_DMA_BASE_ADDR_REG2 0xa10 -#define MV64360_DMA_BASE_ADDR_REG3 0xa18 -#define MV64360_DMA_BASE_ADDR_REG4 0xa20 -#define MV64360_DMA_BASE_ADDR_REG5 0xa28 -#define MV64360_DMA_BASE_ADDR_REG6 0xa30 -#define MV64360_DMA_BASE_ADDR_REG7 0xa38 - - /* IDMA Address Decoding Size Address Register */ - -#define MV64360_DMA_SIZE_REG0 0xa04 -#define MV64360_DMA_SIZE_REG1 0xa0c -#define MV64360_DMA_SIZE_REG2 0xa14 -#define MV64360_DMA_SIZE_REG3 0xa1c -#define MV64360_DMA_SIZE_REG4 0xa24 -#define MV64360_DMA_SIZE_REG5 0xa2c -#define MV64360_DMA_SIZE_REG6 0xa34 -#define MV64360_DMA_SIZE_REG7 0xa3C - - /* IDMA Address Decoding High Address Remap and Access - Protection Registers */ - -#define MV64360_DMA_HIGH_ADDR_REMAP_REG0 0xa60 -#define MV64360_DMA_HIGH_ADDR_REMAP_REG1 0xa64 -#define MV64360_DMA_HIGH_ADDR_REMAP_REG2 0xa68 -#define MV64360_DMA_HIGH_ADDR_REMAP_REG3 0xa6C -#define MV64360_DMA_BASE_ADDR_ENABLE_REG 0xa80 -#define MV64360_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70 -#define MV64360_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74 -#define MV64360_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78 -#define MV64360_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c -#define MV64360_DMA_ARBITER_CONTROL 0x860 -#define MV64360_DMA_CROSS_BAR_TIMEOUT 0x8d0 - - /* IDMA Headers Retarget Registers */ - -#define MV64360_DMA_HEADERS_RETARGET_CONTROL 0xa84 -#define MV64360_DMA_HEADERS_RETARGET_BASE 0xa88 - - /* IDMA Interrupt Register */ - -#define MV64360_DMA_INTERRUPT_CAUSE_REG 0x8c0 -#define MV64360_DMA_INTERRUPT_CAUSE_MASK 0x8c4 -#define MV64360_DMA_ERROR_ADDR 0x8c8 -#define MV64360_DMA_ERROR_SELECT 0x8cc - - /* IDMA Debug Register ( for internal use ) */ - -#define MV64360_DMA_DEBUG_LOW 0x8e0 -#define MV64360_DMA_DEBUG_HIGH 0x8e4 -#define MV64360_DMA_SPARE 0xA8C - -/****************************************/ -/* Timer_Counter */ -/****************************************/ - -#define MV64360_TIMER_COUNTER0 0x850 -#define MV64360_TIMER_COUNTER1 0x854 -#define MV64360_TIMER_COUNTER2 0x858 -#define MV64360_TIMER_COUNTER3 0x85C -#define MV64360_TIMER_COUNTER_0_3_CONTROL 0x864 -#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 -#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c - -/****************************************/ -/* Watchdog registers */ -/****************************************/ - -#define MV64360_WATCHDOG_CONFIG_REG 0xb410 -#define MV64360_WATCHDOG_VALUE_REG 0xb414 - -/****************************************/ -/* I2C Registers */ -/****************************************/ - -#define MV64360_I2C_SLAVE_ADDR 0xc000 -#define MV64360_I2C_EXTENDED_SLAVE_ADDR 0xc010 -#define MV64360_I2C_DATA 0xc004 -#define MV64360_I2C_CONTROL 0xc008 -#define MV64360_I2C_STATUS_BAUDE_RATE 0xc00C -#define MV64360_I2C_SOFT_RESET 0xc01c - -/****************************************/ -/* GPP Interface Registers */ -/****************************************/ - -#define MV64360_GPP_IO_CONTROL 0xf100 -#define MV64360_GPP_LEVEL_CONTROL 0xf110 -#define MV64360_GPP_VALUE 0xf104 -#define MV64360_GPP_INTERRUPT_CAUSE 0xf108 -#define MV64360_GPP_INTERRUPT_MASK0 0xf10c -#define MV64360_GPP_INTERRUPT_MASK1 0xf114 -#define MV64360_GPP_VALUE_SET 0xf118 -#define MV64360_GPP_VALUE_CLEAR 0xf11c - -/****************************************/ -/* Interrupt Controller Registers */ -/****************************************/ - -/****************************************/ -/* Interrupts */ -/****************************************/ - -#define MV64360_MAIN_INTERRUPT_CAUSE_LOW 0x004 -#define MV64360_MAIN_INTERRUPT_CAUSE_HIGH 0x00c -#define MV64360_CPU_INTERRUPT0_MASK_LOW 0x014 -#define MV64360_CPU_INTERRUPT0_MASK_HIGH 0x01c -#define MV64360_CPU_INTERRUPT0_SELECT_CAUSE 0x024 -#define MV64360_CPU_INTERRUPT1_MASK_LOW 0x034 -#define MV64360_CPU_INTERRUPT1_MASK_HIGH 0x03c -#define MV64360_CPU_INTERRUPT1_SELECT_CAUSE 0x044 -#define MV64360_INTERRUPT0_MASK_0_LOW 0x054 -#define MV64360_INTERRUPT0_MASK_0_HIGH 0x05c -#define MV64360_INTERRUPT0_SELECT_CAUSE 0x064 -#define MV64360_INTERRUPT1_MASK_0_LOW 0x074 -#define MV64360_INTERRUPT1_MASK_0_HIGH 0x07c -#define MV64360_INTERRUPT1_SELECT_CAUSE 0x084 - -/****************************************/ -/* MPP Interface Registers */ -/****************************************/ - -#define MV64360_MPP_CONTROL0 0xf000 -#define MV64360_MPP_CONTROL1 0xf004 -#define MV64360_MPP_CONTROL2 0xf008 -#define MV64360_MPP_CONTROL3 0xf00c - -/****************************************/ -/* Serial Initialization registers */ -/****************************************/ - -#define MV64360_SERIAL_INIT_LAST_DATA 0xf324 -#define MV64360_SERIAL_INIT_CONTROL 0xf328 -#define MV64360_SERIAL_INIT_STATUS 0xf32c - - -#endif /* __INCgt64360rh */ diff --git a/board/Marvell/db64360/pci.c b/board/Marvell/db64360/pci.c deleted file mode 100644 index 8c25198..0000000 --- a/board/Marvell/db64360/pci.c +++ /dev/null @@ -1,923 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* PCI.c - PCI functions */ - - -#include <common.h> -#include <pci.h> - -#include "../include/pci.h" - -#undef DEBUG -#undef IDE_SET_NATIVE_MODE -static unsigned int local_buses[] = { 0, 0 }; - -static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = { - {0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 }, - {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 }, -}; - - -#ifdef DEBUG -static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE }; -static void gt_pci_bus_mode_display (PCI_HOST host) -{ - unsigned int mode; - - - mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4; - switch (mode) { - case 0: - printf ("PCI %d bus mode: Conventional PCI\n", host); - break; - case 1: - printf ("PCI %d bus mode: 66 MHz PCIX\n", host); - break; - case 2: - printf ("PCI %d bus mode: 100 MHz PCIX\n", host); - break; - case 3: - printf ("PCI %d bus mode: 133 MHz PCIX\n", host); - break; - default: - printf ("Unknown BUS %d\n", mode); - } -} -#endif - -static const unsigned int pci_p2p_configuration_reg[] = { - PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION -}; - -static const unsigned int pci_configuration_address[] = { - PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS -}; - -static const unsigned int pci_configuration_data[] = { - PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, - PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER -}; - -static const unsigned int pci_error_cause_reg[] = { - PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE -}; - -static const unsigned int pci_arbiter_control[] = { - PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL -}; - -static const unsigned int pci_address_space_en[] = { - PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE -}; - -static const unsigned int pci_snoop_control_base_0_low[] = { - PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW -}; -static const unsigned int pci_snoop_control_top_0[] = { - PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0 -}; - -static const unsigned int pci_access_control_base_0_low[] = { - PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW -}; -static const unsigned int pci_access_control_top_0[] = { - PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0 -}; - -static const unsigned int pci_scs_bank_size[2][4] = { - {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE, - PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE}, - {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE, - PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE} -}; - -static const unsigned int pci_p2p_configuration[] = { - PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION -}; - - -/******************************************************************** -* pciWriteConfigReg - Write to a PCI configuration register -* - Make sure the GT is configured as a master before writing -* to another device on the PCI. -* - The function takes care of Big/Little endian conversion. -* -* -* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec -* (or any other PCI device spec) -* pciDevNum: The device number needs to be addressed. -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum, unsigned int data) -{ - volatile unsigned int DataForAddrReg; - unsigned int functionNum; - unsigned int busNum = 0; - unsigned int addr; - - if (pciDevNum > 32) /* illegal device Number */ - return; - if (pciDevNum == SELF) { /* configure our configuration space. */ - pciDevNum = - (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & - 0x1f; - busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & - 0xff0000; - } - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xfc; - DataForAddrReg = - (regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); - GT_REG_READ (pci_configuration_address[host], &addr); - if (addr != DataForAddrReg) - return; - GT_REG_WRITE (pci_configuration_data[host], data); -} - -/******************************************************************** -* pciReadConfigReg - Read from a PCI0 configuration register -* - Make sure the GT is configured as a master before reading -* from another device on the PCI. -* - The function takes care of Big/Little endian conversion. -* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec) -* pciDevNum: The device number needs to be addressed. -* RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum) -{ - volatile unsigned int DataForAddrReg; - unsigned int data; - unsigned int functionNum; - unsigned int busNum = 0; - - if (pciDevNum > 32) /* illegal device Number */ - return 0xffffffff; - if (pciDevNum == SELF) { /* configure our configuration space. */ - pciDevNum = - (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & - 0x1f; - busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & - 0xff0000; - } - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xfc; - DataForAddrReg = - (regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); - GT_REG_READ (pci_configuration_address[host], &data); - if (data != DataForAddrReg) - return 0xffffffff; - GT_REG_READ (pci_configuration_data[host], &data); - return data; -} - -/******************************************************************** -* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where -* the agent is placed on another Bus. For more -* information read P2P in the PCI spec. -* -* Inputs: unsigned int regOffset - The register offset as it apears in the -* GT spec (or any other PCI device spec). -* unsigned int pciDevNum - The device number needs to be addressed. -* unsigned int busNum - On which bus does the Target agent connect -* to. -* unsigned int data - data to be written. -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -* The configuration Address is configure as type-I (bits[1:0] = '01') due to -* PCI spec referring to P2P. -* -*********************************************************************/ -void pciOverBridgeWriteConfigReg (PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum, unsigned int data) -{ - unsigned int DataForReg; - unsigned int functionNum; - - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - busNum = busNum << 16; - if (pciDevNum == SELF) { /* This board */ - DataForReg = (regOffset | pciDevNum | functionNum) | BIT0; - } else { - DataForReg = (regOffset | pciDevNum | functionNum | busNum) | - BIT31 | BIT0; - } - GT_REG_WRITE (pci_configuration_address[host], DataForReg); - GT_REG_WRITE (pci_configuration_data[host], data); -} - - -/******************************************************************** -* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where -* the agent target locate on another PCI bus. -* - Make sure the GT is configured as a master -* before reading from another device on the PCI. -* - The function takes care of Big/Little endian -* conversion. -* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec). (configuration register offset.) -* pciDevNum: The device number needs to be addressed. -* busNum: the Bus number where the agent is place. -* RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -unsigned int pciOverBridgeReadConfigReg (PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum) -{ - unsigned int DataForReg; - unsigned int data; - unsigned int functionNum; - - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - busNum = busNum << 16; - if (pciDevNum == SELF) { /* This board */ - DataForReg = (regOffset | pciDevNum | functionNum) | BIT31; - } else { /* agent on another bus */ - - DataForReg = (regOffset | pciDevNum | functionNum | busNum) | - BIT0 | BIT31; - } - GT_REG_WRITE (pci_configuration_address[host], DataForReg); - GT_REG_READ (pci_configuration_data[host], &data); - return data; -} - - -/******************************************************************** -* pciGetRegOffset - Gets the register offset for this region config. -* -* INPUT: Bus, Region - The bus and region we ask for its base address. -* OUTPUT: N/A -* RETURNS: PCI register base address -*********************************************************************/ -static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region) -{ - switch (host) { - case PCI_HOST0: - switch (region) { - case PCI_IO: - return PCI_0I_O_LOW_DECODE_ADDRESS; - case PCI_REGION0: - return PCI_0MEMORY0_LOW_DECODE_ADDRESS; - case PCI_REGION1: - return PCI_0MEMORY1_LOW_DECODE_ADDRESS; - case PCI_REGION2: - return PCI_0MEMORY2_LOW_DECODE_ADDRESS; - case PCI_REGION3: - return PCI_0MEMORY3_LOW_DECODE_ADDRESS; - } - case PCI_HOST1: - switch (region) { - case PCI_IO: - return PCI_1I_O_LOW_DECODE_ADDRESS; - case PCI_REGION0: - return PCI_1MEMORY0_LOW_DECODE_ADDRESS; - case PCI_REGION1: - return PCI_1MEMORY1_LOW_DECODE_ADDRESS; - case PCI_REGION2: - return PCI_1MEMORY2_LOW_DECODE_ADDRESS; - case PCI_REGION3: - return PCI_1MEMORY3_LOW_DECODE_ADDRESS; - } - } - return PCI_0MEMORY0_LOW_DECODE_ADDRESS; -} - -static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region) -{ - switch (host) { - case PCI_HOST0: - switch (region) { - case PCI_IO: - return PCI_0I_O_ADDRESS_REMAP; - case PCI_REGION0: - return PCI_0MEMORY0_ADDRESS_REMAP; - case PCI_REGION1: - return PCI_0MEMORY1_ADDRESS_REMAP; - case PCI_REGION2: - return PCI_0MEMORY2_ADDRESS_REMAP; - case PCI_REGION3: - return PCI_0MEMORY3_ADDRESS_REMAP; - } - case PCI_HOST1: - switch (region) { - case PCI_IO: - return PCI_1I_O_ADDRESS_REMAP; - case PCI_REGION0: - return PCI_1MEMORY0_ADDRESS_REMAP; - case PCI_REGION1: - return PCI_1MEMORY1_ADDRESS_REMAP; - case PCI_REGION2: - return PCI_1MEMORY2_ADDRESS_REMAP; - case PCI_REGION3: - return PCI_1MEMORY3_ADDRESS_REMAP; - } - } - return PCI_0MEMORY0_ADDRESS_REMAP; -} - -/******************************************************************** -* pciGetBaseAddress - Gets the base address of a PCI. -* - If the PCI size is 0 then this base address has no meaning!!! -* -* -* INPUT: Bus, Region - The bus and region we ask for its base address. -* OUTPUT: N/A -* RETURNS: PCI base address. -*********************************************************************/ -unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region) -{ - unsigned int regBase; - unsigned int regEnd; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, ®Base); - GT_REG_READ (regOffset + 8, ®End); - - if (regEnd <= regBase) - return 0xffffffff; /* ERROR !!! */ - - regBase = regBase << 16; - return regBase; -} - -bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase, - unsigned int bankBase, unsigned int bankLength) -{ - unsigned int low = 0xfff; - unsigned int high = 0x0; - unsigned int regOffset = pciGetRegOffset (host, region); - unsigned int remapOffset = pciGetRemapOffset (host, region); - - if (bankLength != 0) { - low = (bankBase >> 16) & 0xffff; - high = ((bankBase + bankLength) >> 16) - 1; - } - - GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */ - GT_REG_WRITE (regOffset + 8, high); - - if (bankLength != 0) { /* must do AFTER writing maps */ - GT_REG_WRITE (remapOffset, remapBase >> 16); /* sorry, 32 bits only. - dont support upper 32 - in this driver */ - } - return true; -} - -unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region) -{ - unsigned int low; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, &low); - return (low & 0xffff) << 16; -} - -unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region) -{ - unsigned int low, high; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, &low); - GT_REG_READ (regOffset + 8, &high); - return ((high & 0xffff) + 1) << 16; -} - - -/* ronen - 7/Dec/03*/ -/******************************************************************** -* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS. -* Inputs: one of the PCI BAR -*********************************************************************/ -void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR) -{ - RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR); -} - -void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR) -{ - SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR); -} - -/******************************************************************** -* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave. -* -* Inputs: base and size of PCI SCS -*********************************************************************/ -void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank, - unsigned int pciDramBase, unsigned int pciDramSize) -{ - /*ronen different function for 3rd bank. */ - unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8; - - pciDramBase = pciDramBase & 0xfffff000; - pciDramBase = pciDramBase | (pciReadConfigReg (host, - PCI_SCS_0_BASE_ADDRESS - + offset, - SELF) & 0x00000fff); - pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF, - pciDramBase); - if (pciDramSize == 0) - pciDramSize++; - GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1); - gtPciEnableInternalBAR (host, bank); -} - -/******************************************************************** -* pciSetRegionFeatures - This function modifys one of the 8 regions with -* feature bits given as an input. -* - Be advised to check the spec before modifying them. -* Inputs: PCI_PROTECT_REGION region - one of the eight regions. -* unsigned int features - See file: pci.h there are defintion for those -* region features. -* unsigned int baseAddress - The region base Address. -* unsigned int topAddress - The region top Address. -* Returns: false if one of the parameters is erroneous true otherwise. -*********************************************************************/ -bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region, - unsigned int features, unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int accessLow; - unsigned int accessHigh; - unsigned int accessTop = baseAddress + regionLength; - - if (regionLength == 0) { /* close the region. */ - pciDisableAccessRegion (host, region); - return true; - } - /* base Address is store is bits [11:0] */ - accessLow = (baseAddress & 0xfff00000) >> 20; - /* All the features are update according to the defines in pci.h (to be on - the safe side we disable bits: [11:0] */ - accessLow = accessLow | (features & 0xfffff000); - /* write to the Low Access Region register */ - GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, - accessLow); - - accessHigh = (accessTop & 0xfff00000) >> 20; - - /* write to the High Access Region register */ - GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, - accessHigh - 1); - return true; -} - -/******************************************************************** -* pciDisableAccessRegion - Disable The given Region by writing MAX size -* to its low Address and MIN size to its high Address. -* -* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled. -* Returns: N/A. -*********************************************************************/ -void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region) -{ - /* writing back the registers default values. */ - GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, - 0x01001fff); - GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0); -} - -/******************************************************************** -* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism. -* -* Inputs: N/A -* Returns: true. -*********************************************************************/ -bool pciArbiterEnable (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31); - return true; -} - -/******************************************************************** -* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism. -* -* Inputs: N/A -* Returns: true -*********************************************************************/ -bool pciArbiterDisable (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff); - return true; -} - -/******************************************************************** -* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low) -* -* Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent. -* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent. -* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent. -* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent. -* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent. -* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent. -* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent. -* Returns: true -*********************************************************************/ -bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent, - PCI_AGENT_PRIO externalAgent0, - PCI_AGENT_PRIO externalAgent1, - PCI_AGENT_PRIO externalAgent2, - PCI_AGENT_PRIO externalAgent3, - PCI_AGENT_PRIO externalAgent4, - PCI_AGENT_PRIO externalAgent5) -{ - unsigned int regData; - unsigned int writeData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - writeData = (internalAgent << 7) + (externalAgent0 << 8) + - (externalAgent1 << 9) + (externalAgent2 << 10) + - (externalAgent3 << 11) + (externalAgent4 << 12) + - (externalAgent5 << 13); - regData = (regData & 0xffffc07f) | writeData; - GT_REG_WRITE (pci_arbiter_control[host], regData & regData); - return true; -} - -/******************************************************************** -* pciParkingDisable - Park on last option disable, with this function you can -* disable the park on last mechanism for each agent. -* disabling this option for all agents results parking -* on the internal master. -* -* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent. -* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. -* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. -* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. -* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. -* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. -* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. -* Returns: true -*********************************************************************/ -bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent, - PCI_AGENT_PARK externalAgent0, - PCI_AGENT_PARK externalAgent1, - PCI_AGENT_PARK externalAgent2, - PCI_AGENT_PARK externalAgent3, - PCI_AGENT_PARK externalAgent4, - PCI_AGENT_PARK externalAgent5) -{ - unsigned int regData; - unsigned int writeData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - writeData = (internalAgent << 14) + (externalAgent0 << 15) + - (externalAgent1 << 16) + (externalAgent2 << 17) + - (externalAgent3 << 18) + (externalAgent4 << 19) + - (externalAgent5 << 20); - regData = (regData & ~(0x7f << 14)) | writeData; - GT_REG_WRITE (pci_arbiter_control[host], regData); - return true; -} - -/******************************************************************** -* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to -* respond to grant assertion within a window specified in -* the input value: 'brokenValue'. -* -* Inputs: unsigned char brokenValue - A value which limits the Master to hold the -* grant without asserting frame. -* Returns: Error for illegal broken value otherwise true. -*********************************************************************/ -bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue) -{ - unsigned int data; - unsigned int regData; - - if (brokenValue > 0xf) - return false; /* brokenValue must be 4 bit */ - data = brokenValue << 3; - GT_REG_READ (pci_arbiter_control[host], ®Data); - regData = (regData & 0xffffff87) | data; - GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1); - return true; -} - -/******************************************************************** -* pciDisableBrokenAgentDetection - This function disable the Broken agent -* Detection mechanism. -* NOTE: This operation may cause a dead lock on the -* pci0 arbitration. -* -* Inputs: N/A -* Returns: true. -*********************************************************************/ -bool pciDisableBrokenAgentDetection (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - regData = regData & 0xfffffffd; - GT_REG_WRITE (pci_arbiter_control[host], regData); - return true; -} - -/******************************************************************** -* pciP2PConfig - This function set the PCI_n P2P configurate. -* For more information on the P2P read PCI spec. -* -* Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower -* Boundry. -* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper -* Boundry. -* unsigned int busNum - The CPI bus number to which the PCI interface -* is connected. -* unsigned int devNum - The PCI interface's device number. -* -* Returns: true. -*********************************************************************/ -bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow, - unsigned int SecondBusHigh, - unsigned int busNum, unsigned int devNum) -{ - unsigned int regData; - - regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) | - ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24); - GT_REG_WRITE (pci_p2p_configuration[host], regData); - return true; -} - -/******************************************************************** -* pciSetRegionSnoopMode - This function modifys one of the 4 regions which -* supports Cache Coherency in the PCI_n interface. -* Inputs: region - One of the four regions. -* snoopType - There is four optional Types: -* 1. No Snoop. -* 2. Snoop to WT region. -* 3. Snoop to WB region. -* 4. Snoop & Invalidate to WB region. -* baseAddress - Base Address of this region. -* regionLength - Region length. -* Returns: false if one of the parameters is wrong otherwise return true. -*********************************************************************/ -bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region, - PCI_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int snoopXbaseAddress; - unsigned int snoopXtopAddress; - unsigned int data; - unsigned int snoopHigh = baseAddress + regionLength; - - if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB)) - return false; - snoopXbaseAddress = - pci_snoop_control_base_0_low[host] + 0x10 * region; - snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region; - if (regionLength == 0) { /* closing the region */ - GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff); - GT_REG_WRITE (snoopXtopAddress, 0); - return true; - } - baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ - data = (baseAddress >> 20) | snoopType << 12; - GT_REG_WRITE (snoopXbaseAddress, data); - snoopHigh = (snoopHigh & 0xfff00000) >> 20; - GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1); - return true; -} - -static int gt_read_config_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, u32 * value) -{ - int bus = PCI_BUS (dev); - - if ((bus == local_buses[0]) || (bus == local_buses[1])) { - *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset, - PCI_DEV (dev)); - } else { - *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose-> - cfg_addr, offset, - PCI_DEV (dev), bus); - } - - return 0; -} - -static int gt_write_config_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, u32 value) -{ - int bus = PCI_BUS (dev); - - if ((bus == local_buses[0]) || (bus == local_buses[1])) { - pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset, - PCI_DEV (dev), value); - } else { - pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr, - offset, PCI_DEV (dev), bus, - value); - } - return 0; -} - - -static void gt_setup_ide (struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *entry) -{ - static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 }; - u32 bar_response, bar_value; - int bar; - - for (bar = 0; bar < 6; bar++) { - /*ronen different function for 3rd bank. */ - unsigned int offset = - (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8; - - pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset, - 0x0); - pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset, - &bar_response); - - pciauto_region_allocate (bar_response & - PCI_BASE_ADDRESS_SPACE_IO ? hose-> - pci_io : hose->pci_mem, ide_bar[bar], - &bar_value); - - pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4, - bar_value); - } -} - - -/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */ -/* and is curently not called *. */ -#if 0 -static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char pin, irq; - - pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin); - - if (pin == 1) { /* only allow INT A */ - irq = pci_irq_swizzle[(PCI_HOST) hose-> - cfg_addr][PCI_DEV (dev)]; - if (irq) - pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq); - } -} -#endif - -struct pci_config_table gt_config_table[] = { - {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide}, - - {} -}; - -struct pci_controller pci0_hose = { -/* fixup_irq: gt_fixup_irq, */ - config_table:gt_config_table, -}; - -struct pci_controller pci1_hose = { -/* fixup_irq: gt_fixup_irq, */ - config_table:gt_config_table, -}; - -void pci_init_board (void) -{ - unsigned int command; - -#ifdef DEBUG - gt_pci_bus_mode_display (PCI_HOST0); -#endif - - pci0_hose.first_busno = 0; - pci0_hose.last_busno = 0xff; - local_buses[0] = pci0_hose.first_busno; - - /* PCI memory space */ - pci_set_region (pci0_hose.regions + 0, - CONFIG_SYS_PCI0_0_MEM_SPACE, - CONFIG_SYS_PCI0_0_MEM_SPACE, - CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (pci0_hose.regions + 1, - CONFIG_SYS_PCI0_IO_SPACE_PCI, - CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO); - - pci_set_ops (&pci0_hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - gt_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - gt_write_config_dword); - pci0_hose.region_count = 2; - - pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0; - - pci_register_hose (&pci0_hose); - pciArbiterEnable (PCI_HOST0); - pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1); - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - - pci0_hose.last_busno = pci_hose_scan (&pci0_hose); - -#ifdef DEBUG - gt_pci_bus_mode_display (PCI_HOST1); -#endif - pci1_hose.first_busno = pci0_hose.last_busno + 1; - pci1_hose.last_busno = 0xff; - pci1_hose.current_busno = pci1_hose.first_busno; - local_buses[1] = pci1_hose.first_busno; - - /* PCI memory space */ - pci_set_region (pci1_hose.regions + 0, - CONFIG_SYS_PCI1_0_MEM_SPACE, - CONFIG_SYS_PCI1_0_MEM_SPACE, - CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (pci1_hose.regions + 1, - CONFIG_SYS_PCI1_IO_SPACE_PCI, - CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); - - pci_set_ops (&pci1_hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - gt_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - gt_write_config_dword); - - pci1_hose.region_count = 2; - - pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1; - - pci_register_hose (&pci1_hose); - - pciArbiterEnable (PCI_HOST1); - pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1); - - command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); - - pci1_hose.last_busno = pci_hose_scan (&pci1_hose); - - command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); - -} diff --git a/board/Marvell/db64360/sdram_init.c b/board/Marvell/db64360/sdram_init.c deleted file mode 100644 index 5954b4c..0000000 --- a/board/Marvell/db64360/sdram_init.c +++ /dev/null @@ -1,1945 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * adaption for the Marvell DB64360 Board - * Ingo Assmus (ingo.assmus@keymile.com) - ************************************************************************/ - - -/* sdram_init.c - automatic memory sizing */ - -#include <common.h> -#include <74xx_7xx.h> -#include "../include/memory.h" -#include "../include/pci.h" -#include "../include/mv_gen_reg.h" -#include <net.h> - -#include "eth.h" -#include "mpsc.h" -#include "../common/i2c.h" -#include "64360.h" -#include "mv_regs.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define MAP_PCI - -int set_dfcdlInit (void); /* setup delay line of Mv64360 */ -int mvDmaIsChannelActive (int); -int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong); -int mvDmaTransfer (int, ulong, ulong, ulong, ulong); - -/* ------------------------------------------------------------------------- */ - -int -memory_map_bank (unsigned int bankNo, - unsigned int bankBase, unsigned int bankLength) -{ -#ifdef MAP_PCI - PCI_HOST host; -#endif - - -#ifdef DEBUG - if (bankLength > 0) { - printf ("mapping bank %d at %08x - %08x\n", - bankNo, bankBase, bankBase + bankLength - 1); - } else { - printf ("unmapping bank %d\n", bankNo); - } -#endif - - memoryMapBank (bankNo, bankBase, bankLength); - -#ifdef MAP_PCI - for (host = PCI_HOST0; host <= PCI_HOST1; host++) { - const int features = - PREFETCH_ENABLE | - DELAYED_READ_ENABLE | - AGGRESSIVE_PREFETCH | - READ_LINE_AGGRESSIVE_PREFETCH | - READ_MULTI_AGGRESSIVE_PREFETCH | - MAX_BURST_4 | PCI_NO_SWAP; - - pciMapMemoryBank (host, bankNo, bankBase, bankLength); - - pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase, - bankLength); - - pciSetRegionFeatures (host, bankNo, features, bankBase, - bankLength); - } -#endif - return 0; -} - -#define GB (1 << 30) - -/* much of this code is based on (or is) the code in the pip405 port */ -/* thanks go to the authors of said port - Josh */ - -/* structure to store the relevant information about an sdram bank */ -typedef struct sdram_info { - uchar drb_size; - uchar registered, ecc; - uchar tpar; - uchar tras_clocks; - uchar burst_len; - uchar banks, slot; -} sdram_info_t; - -/* Typedefs for 'gtAuxilGetDIMMinfo' function */ - -typedef enum _memoryType { SDRAM, DDR } MEMORY_TYPE; - -typedef enum _voltageInterface { TTL_5V_TOLERANT, LVTTL, HSTL_1_5V, - SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN, -} VOLTAGE_INTERFACE; - -typedef enum _max_CL_supported_DDR { DDR_CL_1 = 1, DDR_CL_1_5 = 2, DDR_CL_2 = - 4, DDR_CL_2_5 = 8, DDR_CL_3 = 16, DDR_CL_3_5 = - 32, DDR_CL_FAULT } MAX_CL_SUPPORTED_DDR; -typedef enum _max_CL_supported_SD { SD_CL_1 = - 1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7, - SD_FAULT } MAX_CL_SUPPORTED_SD; - - -/* SDRAM/DDR information struct */ -typedef struct _gtMemoryDimmInfo { - MEMORY_TYPE memoryType; - unsigned int numOfRowAddresses; - unsigned int numOfColAddresses; - unsigned int numOfModuleBanks; - unsigned int dataWidth; - VOLTAGE_INTERFACE voltageInterface; - unsigned int errorCheckType; /* ECC , PARITY.. */ - unsigned int sdramWidth; /* 4,8,16 or 32 */ ; - unsigned int errorCheckDataWidth; /* 0 - no, 1 - Yes */ - unsigned int minClkDelay; - unsigned int burstLengthSupported; - unsigned int numOfBanksOnEachDevice; - unsigned int suportedCasLatencies; - unsigned int RefreshInterval; - unsigned int maxCASlatencySupported_LoP; /* LoP left of point (measured in ns) */ - unsigned int maxCASlatencySupported_RoP; /* RoP right of point (measured in ns) */ - MAX_CL_SUPPORTED_DDR maxClSupported_DDR; - MAX_CL_SUPPORTED_SD maxClSupported_SD; - unsigned int moduleBankDensity; - /* module attributes (true for yes) */ - bool bufferedAddrAndControlInputs; - bool registeredAddrAndControlInputs; - bool onCardPLL; - bool bufferedDQMBinputs; - bool registeredDQMBinputs; - bool differentialClockInput; - bool redundantRowAddressing; - - /* module general attributes */ - bool suportedAutoPreCharge; - bool suportedPreChargeAll; - bool suportedEarlyRasPreCharge; - bool suportedWrite1ReadBurst; - bool suported5PercentLowVCC; - bool suported5PercentUpperVCC; - /* module timing parameters */ - unsigned int minRasToCasDelay; - unsigned int minRowActiveRowActiveDelay; - unsigned int minRasPulseWidth; - unsigned int minRowPrechargeTime; /* measured in ns */ - - int addrAndCommandHoldTime; /* LoP left of point (measured in ns) */ - int addrAndCommandSetupTime; /* (measured in ns/100) */ - int dataInputSetupTime; /* LoP left of point (measured in ns) */ - int dataInputHoldTime; /* LoP left of point (measured in ns) */ -/* tAC times for highest 2nd and 3rd highest CAS Latency values */ - unsigned int clockToDataOut_LoP; /* LoP left of point (measured in ns) */ - unsigned int clockToDataOut_RoP; /* RoP right of point (measured in ns) */ - unsigned int clockToDataOutMinus1_LoP; /* LoP left of point (measured in ns) */ - unsigned int clockToDataOutMinus1_RoP; /* RoP right of point (measured in ns) */ - unsigned int clockToDataOutMinus2_LoP; /* LoP left of point (measured in ns) */ - unsigned int clockToDataOutMinus2_RoP; /* RoP right of point (measured in ns) */ - - unsigned int minimumCycleTimeAtMaxCasLatancy_LoP; /* LoP left of point (measured in ns) */ - unsigned int minimumCycleTimeAtMaxCasLatancy_RoP; /* RoP right of point (measured in ns) */ - - unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */ - unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns) */ - - unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */ - unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns) */ - - /* Parameters calculated from - the extracted DIMM information */ - unsigned int size; - unsigned int deviceDensity; /* 16,64,128,256 or 512 Mbit */ - unsigned int numberOfDevices; - uchar drb_size; /* DRAM size in n*64Mbit */ - uchar slot; /* Slot Number this module is inserted in */ - uchar spd_raw_data[128]; /* Content of SPD-EEPROM copied 1:1 */ -#ifdef DEBUG - uchar manufactura[8]; /* Content of SPD-EEPROM Byte 64-71 */ - uchar modul_id[18]; /* Content of SPD-EEPROM Byte 73-90 */ - uchar vendor_data[27]; /* Content of SPD-EEPROM Byte 99-125 */ - unsigned long modul_serial_no; /* Content of SPD-EEPROM Byte 95-98 */ - unsigned int manufac_date; /* Content of SPD-EEPROM Byte 93-94 */ - unsigned int modul_revision; /* Content of SPD-EEPROM Byte 91-92 */ - uchar manufac_place; /* Content of SPD-EEPROM Byte 72 */ - -#endif -} AUX_MEM_DIMM_INFO; - - -/* - * translate ns.ns/10 coding of SPD timing values - * into 10 ps unit values - */ -static inline unsigned short NS10to10PS (unsigned char spd_byte) -{ - unsigned short ns, ns10; - - /* isolate upper nibble */ - ns = (spd_byte >> 4) & 0x0F; - /* isolate lower nibble */ - ns10 = (spd_byte & 0x0F); - - return (ns * 100 + ns10 * 10); -} - -/* - * translate ns coding of SPD timing values - * into 10 ps unit values - */ -static inline unsigned short NSto10PS (unsigned char spd_byte) -{ - return (spd_byte * 100); -} - -/* This code reads the SPD chip on the sdram and populates - * the array which is passed in with the relevant information */ -/* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */ -static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) -{ - unsigned long spd_checksum; - -#ifdef ZUMA_NTL - /* zero all the values */ - memset (info, 0, sizeof (*info)); - -/* - if (!slot) { - info->slot = 0; - info->banks = 1; - info->registered = 0; - info->drb_size = 16;*/ /* 16 - 256MBit, 32 - 512MBit */ -/* info->tpar = 3; - info->tras_clocks = 5; - info->burst_len = 4; -*/ -#ifdef CONFIG_MV64360_ECC - /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */ - dimmInfo->errorCheckType = 2; -/* info->ecc = 2;*/ -#endif -} - -return 0; - -#else - uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; - int ret; - unsigned int i, j, density = 1; - -#ifdef DEBUG - unsigned int k; -#endif - unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp; - int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint; - uchar supp_cal, cal_val; - ulong memclk, tmemclk; - ulong tmp; - uchar trp_clocks = 0, tras_clocks; - uchar data[128]; - - memclk = gd->bus_clk; - tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ - - debug("before i2c read\n"); - - ret = i2c_read (addr, 0, 1, data, 128); - - debug("after i2c read\n"); - - /* zero all the values */ - memset (dimmInfo, 0, sizeof (*dimmInfo)); - - /* copy the SPD content 1:1 into the dimmInfo structure */ - for (i = 0; i <= 127; i++) { - dimmInfo->spd_raw_data[i] = data[i]; - } - - if (ret) { - debug("No DIMM in slot %d [err = %x]\n", slot, ret); - return 0; - } else - dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */ - -#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT - - for (i = 0; i <= 127; i++) { - printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i], - data[i]); - } - -#endif -#ifdef DEBUG -/* find Manufactura of Dimm Module */ - for (i = 0; i < sizeof (dimmInfo->manufactura); i++) { - dimmInfo->manufactura[i] = data[64 + i]; - } - printf ("\nThis RAM-Module is produced by: %s\n", - dimmInfo->manufactura); - -/* find Manul-ID of Dimm Module */ - for (i = 0; i < sizeof (dimmInfo->modul_id); i++) { - dimmInfo->modul_id[i] = data[73 + i]; - } - printf ("The Module-ID of this RAM-Module is: %s\n", - dimmInfo->modul_id); - -/* find Vendor-Data of Dimm Module */ - for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) { - dimmInfo->vendor_data[i] = data[99 + i]; - } - printf ("Vendor Data of this RAM-Module is: %s\n", - dimmInfo->vendor_data); - -/* find modul_serial_no of Dimm Module */ - dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95]))); - printf ("Serial No. of this RAM-Module is: %ld (%lx)\n", - dimmInfo->modul_serial_no, dimmInfo->modul_serial_no); - -/* find Manufac-Data of Dimm Module */ - dimmInfo->manufac_date = (*((unsigned int *) (&data[93]))); - printf ("Manufactoring Date of this RAM-Module is: %d.%d\n", data[93], data[94]); /*dimmInfo->manufac_date */ - -/* find modul_revision of Dimm Module */ - dimmInfo->modul_revision = (*((unsigned int *) (&data[91]))); - printf ("Module Revision of this RAM-Module is: %d.%d\n", data[91], data[92]); /* dimmInfo->modul_revision */ - -/* find manufac_place of Dimm Module */ - dimmInfo->manufac_place = (*((unsigned char *) (&data[72]))); - printf ("manufac_place of this RAM-Module is: %d\n", - dimmInfo->manufac_place); - -#endif - -/*------------------------------------------------------------------------------------------------------------------------------*/ -/* calculate SPD checksum */ -/*------------------------------------------------------------------------------------------------------------------------------*/ - spd_checksum = 0; - - for (i = 0; i <= 62; i++) { - spd_checksum += data[i]; - } - - if ((spd_checksum & 0xff) != data[63]) { - printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]); - hang (); - } - - else - printf ("SPD Checksum ok!\n"); - - -/*------------------------------------------------------------------------------------------------------------------------------*/ - for (i = 2; i <= 35; i++) { - switch (i) { - case 2: /* Memory type (DDR / SDRAM) */ - dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM; - if (dimmInfo->memoryType == 0) - debug - ("Dram_type in slot %d is: SDRAM\n", - dimmInfo->slot); - if (dimmInfo->memoryType == 1) - debug - ("Dram_type in slot %d is: DDRAM\n", - dimmInfo->slot); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 3: /* Number Of Row Addresses */ - dimmInfo->numOfRowAddresses = data[i]; - debug - ("Module Number of row addresses: %d\n", - dimmInfo->numOfRowAddresses); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 4: /* Number Of Column Addresses */ - dimmInfo->numOfColAddresses = data[i]; - debug - ("Module Number of col addresses: %d\n", - dimmInfo->numOfColAddresses); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 5: /* Number Of Module Banks */ - dimmInfo->numOfModuleBanks = data[i]; - debug - ("Number of Banks on Mod. : %d\n", - dimmInfo->numOfModuleBanks); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 6: /* Data Width */ - dimmInfo->dataWidth = data[i]; - debug - ("Module Data Width: %d\n", - dimmInfo->dataWidth); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 8: /* Voltage Interface */ - switch (data[i]) { - case 0x0: - dimmInfo->voltageInterface = TTL_5V_TOLERANT; - debug - ("Module is TTL_5V_TOLERANT\n"); - break; - case 0x1: - dimmInfo->voltageInterface = LVTTL; - debug - ("Module is LVTTL\n"); - break; - case 0x2: - dimmInfo->voltageInterface = HSTL_1_5V; - debug - ("Module is TTL_5V_TOLERANT\n"); - break; - case 0x3: - dimmInfo->voltageInterface = SSTL_3_3V; - debug - ("Module is HSTL_1_5V\n"); - break; - case 0x4: - dimmInfo->voltageInterface = SSTL_2_5V; - debug - ("Module is SSTL_2_5V\n"); - break; - default: - dimmInfo->voltageInterface = VOLTAGE_UNKNOWN; - debug - ("Module is VOLTAGE_UNKNOWN\n"); - break; - } - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 9: /* Minimum Cycle Time At Max CasLatancy */ - shift = (dimmInfo->memoryType == DDR) ? 4 : 2; - mult = (dimmInfo->memoryType == DDR) ? 10 : 25; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf : 0x03; - leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; - rightOfPoint = (data[i] & maskRightOfPoint) * mult; - dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP = - leftOfPoint; - dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP = - rightOfPoint; - debug - ("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n", - leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 10: /* Clock To Data Out */ - div = (dimmInfo->memoryType == DDR) ? 100 : 10; - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - dimmInfo->clockToDataOut_LoP = leftOfPoint; - dimmInfo->clockToDataOut_RoP = rightOfPoint; - debug("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->clockToDataOut */ - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - -/*#ifdef CONFIG_ECC */ - case 11: /* Error Check Type */ - dimmInfo->errorCheckType = data[i]; - debug - ("Error Check Type (0=NONE): %d\n", - dimmInfo->errorCheckType); - break; -/* #endif */ -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 12: /* Refresh Interval */ - dimmInfo->RefreshInterval = data[i]; - debug - ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n", - dimmInfo->RefreshInterval); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 13: /* Sdram Width */ - dimmInfo->sdramWidth = data[i]; - debug - ("Sdram Width: %d\n", - dimmInfo->sdramWidth); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 14: /* Error Check Data Width */ - dimmInfo->errorCheckDataWidth = data[i]; - debug - ("Error Check Data Width: %d\n", - dimmInfo->errorCheckDataWidth); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 15: /* Minimum Clock Delay */ - dimmInfo->minClkDelay = data[i]; - debug - ("Minimum Clock Delay: %d\n", - dimmInfo->minClkDelay); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 16: /* Burst Length Supported */ - /******-******-******-******* - * bit3 | bit2 | bit1 | bit0 * - *******-******-******-******* - burst length = * 8 | 4 | 2 | 1 * - ***************************** - - If for example bit0 and bit2 are set, the burst - length supported are 1 and 4. */ - - dimmInfo->burstLengthSupported = data[i]; -#ifdef DEBUG - debug - ("Burst Length Supported: "); - if (dimmInfo->burstLengthSupported & 0x01) - debug("1, "); - if (dimmInfo->burstLengthSupported & 0x02) - debug("2, "); - if (dimmInfo->burstLengthSupported & 0x04) - debug("4, "); - if (dimmInfo->burstLengthSupported & 0x08) - debug("8, "); - debug(" Bit \n"); -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 17: /* Number Of Banks On Each Device */ - dimmInfo->numOfBanksOnEachDevice = data[i]; - debug - ("Number Of Banks On Each Chip: %d\n", - dimmInfo->numOfBanksOnEachDevice); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 18: /* Suported Cas Latencies */ - - /* DDR: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | TBD | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * - ********************************************************* - SDRAM: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * - ********************************************************/ - dimmInfo->suportedCasLatencies = data[i]; -#ifdef DEBUG - debug - ("Suported Cas Latencies: (CL) "); - if (dimmInfo->memoryType == 0) { /* SDRAM */ - for (k = 0; k <= 7; k++) { - if (dimmInfo-> - suportedCasLatencies & (1 << k)) - debug - ("%d, ", - k + 1); - } - - } else { /* DDR-RAM */ - - if (dimmInfo->suportedCasLatencies & 1) - debug("1, "); - if (dimmInfo->suportedCasLatencies & 2) - debug("1.5, "); - if (dimmInfo->suportedCasLatencies & 4) - debug("2, "); - if (dimmInfo->suportedCasLatencies & 8) - debug("2.5, "); - if (dimmInfo->suportedCasLatencies & 16) - debug("3, "); - if (dimmInfo->suportedCasLatencies & 32) - debug("3.5, "); - - } - debug("\n"); -#endif - /* Calculating MAX CAS latency */ - for (j = 7; j > 0; j--) { - if (((dimmInfo-> - suportedCasLatencies >> j) & 0x1) == - 1) { - switch (dimmInfo->memoryType) { - case DDR: - /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */ - switch (j) { - case 7: - debug - ("Max. Cas Latencies (DDR): ERROR !!!\n"); - dimmInfo-> - maxClSupported_DDR - = - DDR_CL_FAULT; - hang (); - break; - case 6: - debug - ("Max. Cas Latencies (DDR): ERROR !!!\n"); - dimmInfo-> - maxClSupported_DDR - = - DDR_CL_FAULT; - hang (); - break; - case 5: - debug - ("Max. Cas Latencies (DDR): 3.5 clk's\n"); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_3_5; - break; - case 4: - debug - ("Max. Cas Latencies (DDR): 3 clk's \n"); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_3; - break; - case 3: - debug - ("Max. Cas Latencies (DDR): 2.5 clk's \n"); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_2_5; - break; - case 2: - debug - ("Max. Cas Latencies (DDR): 2 clk's \n"); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_2; - break; - case 1: - debug - ("Max. Cas Latencies (DDR): 1.5 clk's \n"); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_1_5; - break; - } - - /* ronen - in case we have a DIMM with minimumCycleTimeAtMaxCasLatancy - lower then our SDRAM cycle count, we won't be able to support this CAL - and we will have to use lower CAL. (minus - means from 3.0 to 2.5) */ - if ((dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_LoP - < - CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) - || - ((dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_LoP - == - CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) - && (dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_RoP - < - CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP))) - { - dimmInfo-> - maxClSupported_DDR - = - dimmInfo-> - maxClSupported_DDR - >> 1; - debug - ("*** Change actual Cas Latencies cause of minimumCycleTime n"); - } - /* ronen - checkif the Dimm frequency compared to the Sysclock. */ - if ((dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_LoP - > - CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) - || - ((dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_LoP - == - CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) - && (dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_RoP - > - CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP))) - { - printf ("*********************************************************\n"); - printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n"); - printf ("*********************************************************\n"); - hang (); - } - - dimmInfo-> - maxCASlatencySupported_LoP - = - 1 + - (int) (5 * j / 10); - if (((5 * j) % 10) != 0) - dimmInfo-> - maxCASlatencySupported_RoP - = 5; - else - dimmInfo-> - maxCASlatencySupported_RoP - = 0; - debug - ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", - dimmInfo-> - maxCASlatencySupported_LoP, - dimmInfo-> - maxCASlatencySupported_RoP); - break; - case SDRAM: - /* CAS latency 1, 2, 3, 4, 5, 6, 7 */ - dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */ - debug - ("Max. Cas Latencies (SD): %d\n", - dimmInfo-> - maxClSupported_SD); - dimmInfo-> - maxCASlatencySupported_LoP - = j; - dimmInfo-> - maxCASlatencySupported_RoP - = 0; - debug - ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", - dimmInfo-> - maxCASlatencySupported_LoP, - dimmInfo-> - maxCASlatencySupported_RoP); - break; - } - break; - } - } - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 21: /* Buffered Address And Control Inputs */ - debug("\nModul Attributes (SPD Byte 21): \n"); - dimmInfo->bufferedAddrAndControlInputs = - data[i] & BIT0; - dimmInfo->registeredAddrAndControlInputs = - (data[i] & BIT1) >> 1; - dimmInfo->onCardPLL = (data[i] & BIT2) >> 2; - dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3; - dimmInfo->registeredDQMBinputs = - (data[i] & BIT4) >> 4; - dimmInfo->differentialClockInput = - (data[i] & BIT5) >> 5; - dimmInfo->redundantRowAddressing = - (data[i] & BIT6) >> 6; -#ifdef DEBUG - if (dimmInfo->bufferedAddrAndControlInputs == 1) - debug - (" - Buffered Address/Control Input: Yes \n"); - else - debug - (" - Buffered Address/Control Input: No \n"); - - if (dimmInfo->registeredAddrAndControlInputs == 1) - debug - (" - Registered Address/Control Input: Yes \n"); - else - debug - (" - Registered Address/Control Input: No \n"); - - if (dimmInfo->onCardPLL == 1) - debug - (" - On-Card PLL (clock): Yes \n"); - else - debug - (" - On-Card PLL (clock): No \n"); - - if (dimmInfo->bufferedDQMBinputs == 1) - debug - (" - Bufferd DQMB Inputs: Yes \n"); - else - debug - (" - Bufferd DQMB Inputs: No \n"); - - if (dimmInfo->registeredDQMBinputs == 1) - debug - (" - Registered DQMB Inputs: Yes \n"); - else - debug - (" - Registered DQMB Inputs: No \n"); - - if (dimmInfo->differentialClockInput == 1) - debug - (" - Differential Clock Input: Yes \n"); - else - debug - (" - Differential Clock Input: No \n"); - - if (dimmInfo->redundantRowAddressing == 1) - debug - (" - redundant Row Addressing: Yes \n"); - else - debug - (" - redundant Row Addressing: No \n"); - -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 22: /* Suported AutoPreCharge */ - debug("\nModul Attributes (SPD Byte 22): \n"); - dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0; - dimmInfo->suportedAutoPreCharge = - (data[i] & BIT1) >> 1; - dimmInfo->suportedPreChargeAll = - (data[i] & BIT2) >> 2; - dimmInfo->suportedWrite1ReadBurst = - (data[i] & BIT3) >> 3; - dimmInfo->suported5PercentLowVCC = - (data[i] & BIT4) >> 4; - dimmInfo->suported5PercentUpperVCC = - (data[i] & BIT5) >> 5; -#ifdef DEBUG - if (dimmInfo->suportedEarlyRasPreCharge == 1) - debug - (" - Early Ras Precharge: Yes \n"); - else - debug - (" - Early Ras Precharge: No \n"); - - if (dimmInfo->suportedAutoPreCharge == 1) - debug - (" - AutoPreCharge: Yes \n"); - else - debug - (" - AutoPreCharge: No \n"); - - if (dimmInfo->suportedPreChargeAll == 1) - debug - (" - Precharge All: Yes \n"); - else - debug - (" - Precharge All: No \n"); - - if (dimmInfo->suportedWrite1ReadBurst == 1) - debug - (" - Write 1/ReadBurst: Yes \n"); - else - debug - (" - Write 1/ReadBurst: No \n"); - - if (dimmInfo->suported5PercentLowVCC == 1) - debug - (" - lower VCC tolerance: 5 Percent \n"); - else - debug - (" - lower VCC tolerance: 10 Percent \n"); - - if (dimmInfo->suported5PercentUpperVCC == 1) - debug - (" - upper VCC tolerance: 5 Percent \n"); - else - debug - (" - upper VCC tolerance: 10 Percent \n"); - -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 23: /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ - shift = (dimmInfo->memoryType == DDR) ? 4 : 2; - mult = (dimmInfo->memoryType == DDR) ? 10 : 25; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf : 0x03; - leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; - rightOfPoint = (data[i] & maskRightOfPoint) * mult; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP = - leftOfPoint; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP = - rightOfPoint; - debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 24: /* Clock To Data Out 2nd highest Cas Latency Value */ - div = (dimmInfo->memoryType == DDR) ? 100 : 10; - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint; - dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint; - debug - ("Clock To Data Out (2nd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 25: /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ - shift = (dimmInfo->memoryType == DDR) ? 4 : 2; - mult = (dimmInfo->memoryType == DDR) ? 10 : 25; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf : 0x03; - leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; - rightOfPoint = (data[i] & maskRightOfPoint) * mult; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP = - leftOfPoint; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP = - rightOfPoint; - debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 26: /* Clock To Data Out 3rd highest Cas Latency Value */ - div = (dimmInfo->memoryType == DDR) ? 100 : 10; - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint; - dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint; - debug - ("Clock To Data Out (3rd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 27: /* Minimum Row Precharge Time */ - shift = (dimmInfo->memoryType == DDR) ? 2 : 0; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; - leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (data[i] & maskRightOfPoint) * 25; - - dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint); /* measured in n times 10ps Intervals */ - trp_clocks = - (dimmInfo->minRowPrechargeTime + - (tmemclk - 1)) / tmemclk; - debug - ("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n", - tmemclk, tmemclk / 100, tmemclk % 100); - debug - ("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 28: /* Minimum Row Active to Row Active Time */ - shift = (dimmInfo->memoryType == DDR) ? 2 : 0; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; - leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (data[i] & maskRightOfPoint) * 25; - - dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - debug - ("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 29: /* Minimum Ras-To-Cas Delay */ - shift = (dimmInfo->memoryType == DDR) ? 2 : 0; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; - leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (data[i] & maskRightOfPoint) * 25; - - dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - debug - ("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 30: /* Minimum Ras Pulse Width */ - dimmInfo->minRasPulseWidth = data[i]; - tras_clocks = - (NSto10PS (data[i]) + - (tmemclk - 1)) / tmemclk; - debug - ("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n", - dimmInfo->minRasPulseWidth, tras_clocks); - - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 31: /* Module Bank Density */ - dimmInfo->moduleBankDensity = data[i]; - debug - ("Module Bank Density: %d\n", - dimmInfo->moduleBankDensity); -#ifdef DEBUG - debug - ("*** Offered Densities (more than 1 = Multisize-Module): "); - { - if (dimmInfo->moduleBankDensity & 1) - debug("4MB, "); - if (dimmInfo->moduleBankDensity & 2) - debug("8MB, "); - if (dimmInfo->moduleBankDensity & 4) - debug("16MB, "); - if (dimmInfo->moduleBankDensity & 8) - debug("32MB, "); - if (dimmInfo->moduleBankDensity & 16) - debug("64MB, "); - if (dimmInfo->moduleBankDensity & 32) - debug("128MB, "); - if ((dimmInfo->moduleBankDensity & 64) - || (dimmInfo->moduleBankDensity & 128)) { - debug("ERROR, "); - hang (); - } - } - debug("\n"); -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 32: /* Address And Command Setup Time (measured in ns/1000) */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->addrAndCommandSetupTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - debug - ("Address And Command Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 33: /* Address And Command Hold Time */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->addrAndCommandHoldTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - debug - ("Address And Command Hold Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 34: /* Data Input Setup Time */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->dataInputSetupTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - debug - ("Data Input Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 35: /* Data Input Hold Time */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->dataInputHoldTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - debug - ("Data Input Hold Time [ns]: %d.%d\n\n", - sign * leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - } - } - /* calculating the sdram density */ - for (i = 0; - i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses; - i++) { - density = density * 2; - } - dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice * - dimmInfo->sdramWidth; - dimmInfo->numberOfDevices = - (dimmInfo->dataWidth / dimmInfo->sdramWidth) * - dimmInfo->numOfModuleBanks; - if ((dimmInfo->errorCheckType == 0x1) - || (dimmInfo->errorCheckType == 0x2) - || (dimmInfo->errorCheckType == 0x3)) { - dimmInfo->size = - (dimmInfo->deviceDensity / 8) * - (dimmInfo->numberOfDevices - - /* ronen on the 1G dimm we get wrong value. (was devicesForErrCheck) */ - dimmInfo->numberOfDevices / 8); - } else { - dimmInfo->size = - (dimmInfo->deviceDensity / 8) * - dimmInfo->numberOfDevices; - } - - /* compute the module DRB size */ - tmp = (1 << - (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses)); - tmp *= dimmInfo->numOfModuleBanks; - tmp *= dimmInfo->sdramWidth; - tmp = tmp >> 24; /* div by 0x4000000 (64M) */ - dimmInfo->drb_size = (uchar) tmp; - debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size); - - /* try a CAS latency of 3 first... */ - - /* bit 1 is CL2, bit 2 is CL3 */ - supp_cal = (dimmInfo->suportedCasLatencies & 0x6) >> 1; - - cal_val = 0; - if (supp_cal & 3) { - if (NS10to10PS (data[9]) <= tmemclk) - cal_val = 3; - } - - /* then 2... */ - if (supp_cal & 2) { - if (NS10to10PS (data[23]) <= tmemclk) - cal_val = 2; - } - - debug("cal_val = %d\n", cal_val); - - /* bummer, did't work... */ - if (cal_val == 0) { - debug("Couldn't find a good CAS latency\n"); - hang (); - return 0; - } - - return true; - -#endif -} - -/* sets up the GT properly with information passed in */ -int setup_sdram (AUX_MEM_DIMM_INFO * info) -{ - ulong tmp, check; - ulong tmp_sdram_mode = 0; /* 0x141c */ - ulong tmp_dunit_control_low = 0; /* 0x1404 */ - int i; - - /* added 8/21/2003 P. Marchese */ - unsigned int sdram_config_reg; - - /* added 10/10/2003 P. Marchese */ - ulong sdram_chip_size; - - /* sanity checking */ - if (!info->numOfModuleBanks) { - printf ("setup_sdram called with 0 banks\n"); - return 1; - } - - /* delay line */ - set_dfcdlInit (); /* may be its not needed */ - debug("Delay line set done\n"); - - /* set SDRAM mode NOP */ /* To_do check it */ - GT_REG_WRITE (SDRAM_OPERATION, 0x5); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - debug - ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"); - } - - /* SDRAM configuration */ -/* added 8/21/2003 P. Marchese */ -/* code allows usage of registered DIMMS */ - - /* figure out the memory refresh internal */ - switch (info->RefreshInterval) { - case 0x0: - case 0x80: /* refresh period is 15.625 usec */ - sdram_config_reg = - (unsigned int) (((float) 15.625 * (float) CONFIG_SYS_BUS_CLK) - / (float) 1000000.0); - break; - case 0x1: - case 0x81: /* refresh period is 3.9 usec */ - sdram_config_reg = - (unsigned int) (((float) 3.9 * (float) CONFIG_SYS_BUS_CLK) / - (float) 1000000.0); - break; - case 0x2: - case 0x82: /* refresh period is 7.8 usec */ - sdram_config_reg = - (unsigned int) (((float) 7.8 * (float) CONFIG_SYS_BUS_CLK) / - (float) 1000000.0); - break; - case 0x3: - case 0x83: /* refresh period is 31.3 usec */ - sdram_config_reg = - (unsigned int) (((float) 31.3 * (float) CONFIG_SYS_BUS_CLK) / - (float) 1000000.0); - break; - case 0x4: - case 0x84: /* refresh period is 62.5 usec */ - sdram_config_reg = - (unsigned int) (((float) 62.5 * (float) CONFIG_SYS_BUS_CLK) / - (float) 1000000.0); - break; - case 0x5: - case 0x85: /* refresh period is 125 usec */ - sdram_config_reg = - (unsigned int) (((float) 125 * (float) CONFIG_SYS_BUS_CLK) / - (float) 1000000.0); - break; - default: /* refresh period undefined */ - printf ("DRAM refresh period is unknown!\n"); - printf ("Aborting DRAM setup with an error\n"); - hang (); - break; - } - debug("calculated refresh interval %0x\n", sdram_config_reg); - - /* make sure the refresh value is only 14 bits */ - if (sdram_config_reg > 0x1fff) - sdram_config_reg = 0x1fff; - debug("adjusted refresh interval %0x\n", sdram_config_reg); - - /* we want physical bank interleaving and */ - /* virtual bank interleaving enabled so do nothing */ - /* since these bits need to be zero to enable the interleaving */ - - /* registered DRAM ? */ - if (info->registeredAddrAndControlInputs == 1) { - /* it's registered DRAM, so set the reg. DRAM bit */ - sdram_config_reg = sdram_config_reg | BIT17; - debug("Enabling registered DRAM bit\n"); - } - /* turn on DRAM ECC? */ -#ifdef CONFIG_MV64360_ECC - if (info->errorCheckType == 0x2) { - /* DRAM has ECC, so turn it on */ - sdram_config_reg = sdram_config_reg | BIT18; - debug("Enabling ECC\n"); - } -#endif - /* set the data DQS pin configuration */ - switch (info->sdramWidth) { - case 0x4: /* memory is x4 */ - sdram_config_reg = sdram_config_reg | BIT20 | BIT21; - debug("Data DQS pins set for 16 pins\n"); - break; - case 0x8: /* memory is x8 or x16 */ - case 0x10: - sdram_config_reg = sdram_config_reg | BIT21; - debug("Data DQS pins set for 8 pins\n"); - break; - case 0x20: /* memory is x32 */ - /* both bits are cleared for x32 so nothing to do */ - debug("Data DQS pins set for 2 pins\n"); - break; - default: /* memory width unsupported */ - printf ("DRAM chip width is unknown!\n"); - printf ("Aborting DRAM setup with an error\n"); - hang (); - break; - } - - /* perform read buffer assignments */ - /* we are going to use the Power-up defaults */ - /* bit 26 = CPU = buffer 1 */ - /* bit 27 = PCI bus #0 = buffer 0 */ - /* bit 28 = PCI bus #1 = buffer 0 */ - /* bit 29 = MPSC = buffer 0 */ - /* bit 30 = IDMA = buffer 0 */ - /* bit 31 = Gigabit = buffer 0 */ - sdram_config_reg = sdram_config_reg | BIT26; - /* sdram_config_reg = sdram_config_reg | 0x58000000; */ - /* sdram_config_reg = sdram_config_reg & 0xffffff00; */ - - /* write the value into the SDRAM configuration register */ - GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg); - debug - ("OOOOOOOOO sdram_conf 0x1400: %08x\n", - GTREGREAD (SDRAM_CONFIG)); - - /* SDRAM open pages control keep open as much as I can */ - GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0); - debug - ("sdram_open_pages_controll 0x1414: %08x\n", - GTREGREAD (SDRAM_OPEN_PAGES_CONTROL)); - - /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ - tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */ - if (tmp == 0) - debug("Core Signals are sync (by HW-Setting)!!!\n"); - else - debug - ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"); - - /* SDRAM set CAS Latency according to SPD information */ - switch (info->memoryType) { - case SDRAM: - printf ("### SD-RAM not supported !!!\n"); - printf ("Aborting!!!\n"); - hang (); - /* ToDo fill SD-RAM if needed !!!!! */ - break; - /* Calculate the settings for SDRAM mode and Dunit control low registers */ - /* Values set according to technical bulletin TB-92 rev. c */ - case DDR: - debug("### SET-CL for DDR-RAM\n"); - switch (info->maxClSupported_DDR) { - case DDR_CL_3: - tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */ - if (tmp == 1) { /* clocks sync */ - if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0x05110051; - else - tmp_dunit_control_low = 0x24110051; - debug - ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } else { /* clk sync. bypassed */ - - if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0x2C1107F2; - else - tmp_dunit_control_low = 0x3C1107d2; - debug - ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } - break; - case DDR_CL_2_5: - tmp_sdram_mode = 0x62; /* CL=2.5 Burstlength = 4 */ - if (tmp == 1) { /* clocks sync */ - if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0x25110051; - else - tmp_dunit_control_low = 0x24110051; - debug - ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } else { /* clk sync. bypassed */ - - if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ - printf ("CL = 2.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n"); - printf ("Aborting!!!\n"); - hang (); - } else - tmp_dunit_control_low = 0x1B1107d2; - debug - ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } - break; - case DDR_CL_2: - tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */ - if (tmp == 1) { /* clocks sync */ - if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0x04110051; - else - tmp_dunit_control_low = 0x03110051; - debug - ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } else { /* clk sync. bypassed */ - - if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ - printf ("CL = 2, Clock Unsync'ed, Dunit Control Low register setting undefined\n"); - printf ("Aborting!!!\n"); - hang (); - } else - tmp_dunit_control_low = 0x3B1107d2; - debug - ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } - break; - case DDR_CL_1_5: - tmp_sdram_mode = 0x52; /* CL=1.5 Burstlength = 4 */ - if (tmp == 1) { /* clocks sync */ - if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0x24110051; - else - tmp_dunit_control_low = 0x23110051; - debug - ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } else { /* clk sync. bypassed */ - - if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ - printf ("CL = 1.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n"); - printf ("Aborting!!!\n"); - hang (); - } else - tmp_dunit_control_low = 0x1A1107d2; - debug - ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } - break; - - default: - printf ("Max. CL is out of range %d\n", - info->maxClSupported_DDR); - hang (); - break; - } /* end DDR switch */ - break; - } /* end CL switch */ - - /* Write results of CL detection procedure */ - /* set SDRAM mode reg. 0x141c */ - GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode); - - /* set SDRAM mode SetCommand 0x1418 */ - GT_REG_WRITE (SDRAM_OPERATION, 0x3); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - debug - ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); - } - - /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ - GT_REG_WRITE (D_UNIT_CONTROL_LOW, tmp_dunit_control_low); - - /* set SDRAM mode SetCommand 0x1418 */ - GT_REG_WRITE (SDRAM_OPERATION, 0x3); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - debug - ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"); - } - -/*------------------------------------------------------------------------------ */ - - /* bank parameters */ - /* SDRAM address decode register 0x1410 */ - /* program this with the default value */ - tmp = 0x02; /* power-up default address select decoding value */ - - debug("drb_size (n*64Mbit): %d\n", info->drb_size); -/* figure out the DRAM chip size */ - sdram_chip_size = - (1 << (info->numOfRowAddresses + info->numOfColAddresses)); - sdram_chip_size *= info->sdramWidth; - sdram_chip_size *= 4; - debug("computed sdram chip size is %#lx\n", sdram_chip_size); - /* divide sdram chip size by 64 Mbits */ - sdram_chip_size = sdram_chip_size / 0x4000000; - switch (sdram_chip_size) { - case 1: /* 64 Mbit */ - case 2: /* 128 Mbit */ - debug("RAM-Device_size 64Mbit or 128Mbit)\n"); - tmp |= (0x00 << 4); - break; - case 4: /* 256 Mbit */ - case 8: /* 512 Mbit */ - debug("RAM-Device_size 256Mbit or 512Mbit)\n"); - tmp |= (0x01 << 4); - break; - case 16: /* 1 Gbit */ - case 32: /* 2 Gbit */ - debug("RAM-Device_size 1Gbit or 2Gbit)\n"); - tmp |= (0x02 << 4); - break; - default: - printf ("Error in dram size calculation\n"); - printf ("RAM-Device_size is unsupported\n"); - hang (); - } - - /* SDRAM address control */ - GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp); - debug - ("setting up sdram address control (0x1410) with: %08lx \n", - tmp); - -/* ------------------------------------------------------------------------------ */ -/* same settings for registerd & non-registerd DDR SDRAM */ - debug - ("setting up sdram_timing_control_low (0x1408) with: %08x \n", - 0x11511220); - GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220); - - -/* ------------------------------------------------------------------------------ */ - - /* SDRAM configuration */ - tmp = GTREGREAD (SDRAM_CONFIG); - - if (info->registeredAddrAndControlInputs - || info->registeredDQMBinputs) { - tmp |= (1 << 17); - debug - ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n", - info->registeredAddrAndControlInputs, - info->registeredDQMBinputs); - } - - /* Use buffer 1 to return read data to the CPU - * Page 426 MV64360 */ - tmp |= (1 << 26); - debug - ("Before Buffer assignment - sdram_conf (0x1400): %08x\n", - GTREGREAD (SDRAM_CONFIG)); - debug - ("After Buffer assignment - sdram_conf (0x1400): %08x\n", - GTREGREAD (SDRAM_CONFIG)); - - /* SDRAM timing To_do: */ -/* ------------------------------------------------------------------------------ */ - - debug - ("setting up sdram_timing_control_high (0x140c) with: %08x \n", - 0x9); - GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0x9); - - debug - ("setting up sdram address pads control (0x14c0) with: %08x \n", - 0x7d5014a); - GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a); - - debug - ("setting up sdram data pads control (0x14c4) with: %08x \n", - 0x7d5014a); - GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a); - -/* ------------------------------------------------------------------------------ */ - - /* set the SDRAM configuration for each bank */ - -/* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */ - { - i = info->slot; - debug - ("\n*** Running a MRS cycle for bank %d ***\n", i); - - /* map the bank */ - memory_map_bank (i, 0, GB / 4); - - /* set SDRAM mode */ /* To_do check it */ - GT_REG_WRITE (SDRAM_OPERATION, 0x3); - check = GTREGREAD (SDRAM_OPERATION); - debug - ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", - check); - - - /* switch back to normal operation mode */ - GT_REG_WRITE (SDRAM_OPERATION, 0); - check = GTREGREAD (SDRAM_OPERATION); - debug - ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", - check); - - /* unmap the bank */ - memory_map_bank (i, 0, 0); - } - - return 0; - -} - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ -long int dram_size (long int *base, long int maxsize) -{ - volatile long int *addr, *b = base; - long int cnt, val, save1, save2; - -#define STARTVAL (1<<20) /* start test at 1M */ - for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long); - cnt <<= 1) { - addr = base + cnt; /* pointer arith! */ - - save1 = *addr; /* save contents of addr */ - save2 = *b; /* save contents of base */ - - *addr = cnt; /* write cnt to addr */ - *b = 0; /* put null at base */ - - /* check at base address */ - if ((*b) != 0) { - *addr = save1; /* restore *addr */ - *b = save2; /* restore *b */ - return (0); - } - val = *addr; /* read *addr */ - val = *addr; /* read *addr */ - - *addr = save1; - *b = save2; - - if (val != cnt) { - debug - ("Found %08x at Address %08x (failure)\n", - (unsigned int) val, (unsigned int) addr); - /* fix boundary condition.. STARTVAL means zero */ - if (cnt == STARTVAL / sizeof (long)) - cnt = 0; - return (cnt * sizeof (long)); - } - } - return maxsize; -} - -/* ------------------------------------------------------------------------- */ - -/* ppcboot interface function to SDRAM init - this is where all the - * controlling logic happens */ -phys_size_t initdram (int board_type) -{ - int checkbank[4] = {[0 ... 3] = 0 }; - ulong realsize, total; - AUX_MEM_DIMM_INFO dimmInfo1; - AUX_MEM_DIMM_INFO dimmInfo2; - int nhr, bank_no; - ulong dest, memSpaceAttr; - - /* first, use the SPD to get info about the SDRAM/ DDRRAM */ - - /* check the NHR bit and skip mem init if it's already done */ - nhr = get_hid0 () & (1 << 16); - - if (nhr) { - printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n"); - } else { - /* DIMM0 */ - check_dimm (0, &dimmInfo1); - - /* DIMM1 */ - check_dimm (1, &dimmInfo2); - - memory_map_bank (0, 0, 0); - memory_map_bank (1, 0, 0); - memory_map_bank (2, 0, 0); - memory_map_bank (3, 0, 0); - - /* ronen check correct set of DIMMS */ - if (dimmInfo1.numOfModuleBanks && dimmInfo2.numOfModuleBanks) { - if (dimmInfo1.errorCheckType != - dimmInfo2.errorCheckType) - printf ("***WARNNING***!!!! different ECC support of the DIMMS\n"); - if (dimmInfo1.maxClSupported_DDR != - dimmInfo2.maxClSupported_DDR) - printf ("***WARNNING***!!!! different CAL setting of the DIMMS\n"); - if (dimmInfo1.registeredAddrAndControlInputs != - dimmInfo2.registeredAddrAndControlInputs) - printf ("***WARNNING***!!!! different Registration setting of the DIMMS\n"); - } - - if (dimmInfo1.numOfModuleBanks && setup_sdram (&dimmInfo1)) { - printf ("Setup for DIMM1 failed.\n"); - } - - if (dimmInfo2.numOfModuleBanks && setup_sdram (&dimmInfo2)) { - printf ("Setup for DIMM2 failed.\n"); - } - - /* set the NHR bit */ - set_hid0 (get_hid0 () | (1 << 16)); - } - /* next, size the SDRAM banks */ - - realsize = total = 0; - if (dimmInfo1.numOfModuleBanks > 0) { - checkbank[0] = 1; - } - if (dimmInfo1.numOfModuleBanks > 1) { - checkbank[1] = 1; - } - if (dimmInfo1.numOfModuleBanks > 2) - printf ("Error, SPD claims DIMM1 has >2 banks\n"); - - printf ("-- DIMM1 has %d banks\n", dimmInfo1.numOfModuleBanks); - - if (dimmInfo2.numOfModuleBanks > 0) { - checkbank[2] = 1; - } - if (dimmInfo2.numOfModuleBanks > 1) { - checkbank[3] = 1; - } - if (dimmInfo2.numOfModuleBanks > 2) - printf ("Error, SPD claims DIMM2 has >2 banks\n"); - - printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks); - - for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) { - /* skip over banks that are not populated */ - if (!checkbank[bank_no]) - continue; - - /* ronen - realsize = dram_size((long int *)total, check); */ - if (bank_no == 0 || bank_no == 1) { - if (checkbank[1] == 1) - realsize = dimmInfo1.size / 2; - else - realsize = dimmInfo1.size; - } - if (bank_no == 2 || bank_no == 3) { - if (checkbank[3] == 1) - realsize = dimmInfo2.size / 2; - else - realsize = dimmInfo2.size; - } - memory_map_bank (bank_no, total, realsize); - - /* ronen - initialize the DRAM for ECC */ -#ifdef CONFIG_MV64360_ECC - if ((dimmInfo1.errorCheckType != 0) && - ((dimmInfo2.errorCheckType != 0) - || (dimmInfo2.numOfModuleBanks == 0))) { - printf ("ECC Initialization of Bank %d:", bank_no); - memSpaceAttr = ((~(BIT0 << bank_no)) & 0xf) << 8; - mvDmaSetMemorySpace (0, 0, memSpaceAttr, total, - realsize); - for (dest = total; dest < total + realsize; - dest += _8M) { - mvDmaTransfer (0, total, dest, _8M, - BIT8 /*DMA_DTL_128BYTES */ | - BIT3 /*DMA_HOLD_SOURCE_ADDR */ - | - BIT11 - /*DMA_BLOCK_TRANSFER_MODE */ ); - while (mvDmaIsChannelActive (0)); - } - printf (" PASS\n"); - } -#endif - - total += realsize; - } - - /* ronen- add DRAM conf prints */ - switch ((GTREGREAD (0x141c) >> 4) & 0x7) { - case 0x2: - printf ("CAS Latency = 2"); - break; - case 0x3: - printf ("CAS Latency = 3"); - break; - case 0x5: - printf ("CAS Latency = 1.5"); - break; - case 0x6: - printf ("CAS Latency = 2.5"); - break; - } - printf (" tRP = %d tRAS = %d tRCD=%d\n", - ((GTREGREAD (0x1408) >> 8) & 0xf) + 1, - ((GTREGREAD (0x1408) >> 20) & 0xf) + 1, - ((GTREGREAD (0x1408) >> 4) & 0xf) + 1); - -/* Setup Ethernet DMA Adress window to DRAM Area */ - if (total > _256M) - printf ("*** ONLY the first 256MB DRAM memory are used out of the "); - else - printf ("Total SDRAM memory is "); - /* (cause all the 4 BATS are taken) */ - return (total); -} - - -/* ronen- add Idma functions for usage of the ecc dram init. */ -/******************************************************************************* -* mvDmaIsChannelActive - Checks if a engine is busy. -********************************************************************************/ -int mvDmaIsChannelActive (int engine) -{ - ulong data; - - data = GTREGREAD (MV64360_DMA_CHANNEL0_CONTROL + 4 * engine); - if (data & BIT14 /*activity status */ ) { - return 1; - } - return 0; -} - -/******************************************************************************* -* mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding -* map. -*******************************************************************************/ -int mvDmaSetMemorySpace (ulong memSpace, - ulong memSpaceTarget, - ulong memSpaceAttr, ulong baseAddress, ulong size) -{ - ulong temp; - - /* The base address must be aligned to the size. */ - if (baseAddress % size != 0) { - return 0; - } - if (size >= 0x10000 /*64K */ ) { - size &= 0xffff0000; - baseAddress = (baseAddress & 0xffff0000); - /* Set the new attributes */ - GT_REG_WRITE (MV64360_DMA_BASE_ADDR_REG0 + memSpace * 8, - (baseAddress | memSpaceTarget | memSpaceAttr)); - GT_REG_WRITE ((MV64360_DMA_SIZE_REG0 + memSpace * 8), - (size - 1) & 0xffff0000); - temp = GTREGREAD (MV64360_DMA_BASE_ADDR_ENABLE_REG); - GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG, - (temp & ~(BIT0 << memSpace))); - return 1; - } - return 0; -} - - -/******************************************************************************* -* mvDmaTransfer - Transfer data from sourceAddr to destAddr on one of the 4 -* DMA channels. -********************************************************************************/ -int mvDmaTransfer (int engine, ulong sourceAddr, - ulong destAddr, ulong numOfBytes, ulong command) -{ - ulong engOffReg = 0; /* Engine Offset Register */ - - if (numOfBytes > 0xffff) { - command = command | BIT31 /*DMA_16M_DESCRIPTOR_MODE */ ; - } - command = command | ((command >> 6) & 0x7); - engOffReg = engine * 4; - GT_REG_WRITE (MV64360_DMA_CHANNEL0_BYTE_COUNT + engOffReg, - numOfBytes); - GT_REG_WRITE (MV64360_DMA_CHANNEL0_SOURCE_ADDR + engOffReg, - sourceAddr); - GT_REG_WRITE (MV64360_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg, - destAddr); - command = - command | BIT12 /*DMA_CHANNEL_ENABLE */ | BIT9 - /*DMA_NON_CHAIN_MODE */ ; - /* Activate DMA engine By writting to mvDmaControlRegister */ - GT_REG_WRITE (MV64360_DMA_CHANNEL0_CONTROL + engOffReg, command); - return 1; -} - -/**************************************************************************************** - * SDRAM INIT * - * This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb * - * This procedure fits only the Atlantis * - * * - ***************************************************************************************/ - - -/**************************************************************************************** - * DFCDL initialize MV643xx Design Considerations * - * * - ***************************************************************************************/ -int set_dfcdlInit (void) -{ - int i; - unsigned int dfcdl_word = 0x391; /* 0x14f; ronen new dfcdl */ - - for (i = 0; i < 64; i++) { - GT_REG_WRITE (SRAM_DATA0, dfcdl_word); -/* dfcdl_word += 0x41; - ronen new dfcdl */ - } - GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000); /* enable dynamic delay line updating */ - - return (0); -} diff --git a/board/Marvell/db64460/64460.h b/board/Marvell/db64460/64460.h deleted file mode 100644 index 9cf7fee..0000000 --- a/board/Marvell/db64460/64460.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus <ingo.assmus@keymile.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * main board support/init for the Galileo Eval board DB64460. - */ - -#ifndef __64460_H__ -#define __64460_H__ - -/* CPU Configuration bits */ -#define CPU_CONF_ADDR_MISS_EN (1 << 8) -#define CPU_CONF_SINGLE_CPU (1 << 11) -#define CPU_CONF_ENDIANESS (1 << 12) -#define CPU_CONF_PIPELINE (1 << 13) -#define CPU_CONF_STOP_RETRY (1 << 17) -#define CPU_CONF_MULTI_DECODE (1 << 18) -#define CPU_CONF_DP_VALID (1 << 19) -#define CPU_CONF_PERR_PROP (1 << 22) -#define CPU_CONF_AACK_DELAY_2 (1 << 25) -#define CPU_CONF_AP_VALID (1 << 26) -#define CPU_CONF_REMAP_WR_DIS (1 << 27) - -/* CPU Master Control bits */ -#define CPU_MAST_CTL_ARB_EN (1 << 8) -#define CPU_MAST_CTL_MASK_BR_1 (1 << 9) -#define CPU_MAST_CTL_M_WR_TRIG (1 << 10) -#define CPU_MAST_CTL_M_RD_TRIG (1 << 11) -#define CPU_MAST_CTL_CLEAN_BLK (1 << 12) -#define CPU_MAST_CTL_FLUSH_BLK (1 << 13) - -#endif /* __64460_H__ */ diff --git a/board/Marvell/db64460/Kconfig b/board/Marvell/db64460/Kconfig deleted file mode 100644 index f53e3a9..0000000 --- a/board/Marvell/db64460/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_DB64460 - -config SYS_BOARD - default "db64460" - -config SYS_VENDOR - default "Marvell" - -config SYS_CONFIG_NAME - default "DB64460" - -endif diff --git a/board/Marvell/db64460/MAINTAINERS b/board/Marvell/db64460/MAINTAINERS deleted file mode 100644 index a30c51c..0000000 --- a/board/Marvell/db64460/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -DB64460 BOARD -#M: - -S: Maintained -F: board/Marvell/db64460/ -F: include/configs/DB64460.h -F: configs/DB64460_defconfig diff --git a/board/Marvell/db64460/Makefile b/board/Marvell/db64460/Makefile deleted file mode 100644 index a970f9a..0000000 --- a/board/Marvell/db64460/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2001 -# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += db64460.o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \ - mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \ - sdram_init.o ../common/intel_flash.o ../common/misc.o diff --git a/board/Marvell/db64460/README b/board/Marvell/db64460/README deleted file mode 100644 index c6e01fe..0000000 --- a/board/Marvell/db64460/README +++ /dev/null @@ -1,105 +0,0 @@ -This file contains status information for the port of the U-Boot to the Marvell Development Board DB64460. - -Author: Ronen Shitrit <rshitrit@il.marvell.com> - - -Supported CPU Types : -+++++++++++++++++++++ -IBM750Gx Rev 1.0 -MPC7457 Rev 1.1 - -Supported CPU Cache Library: -++++++++++++++++++++++++++++ - L1 and L2 only. - -CPU Control: -++++++++++++ - Marvell optimized CPU control settings: - Big Endian - Enable CPU pipeline - Data and address parity checking - AACK# assert after 2 cycles - -U-Boot I/O Interface Support: -+++++++++++++++++++++++++++++ -- Serial Interface (UART) - This version of U-Boot supports the SIO U-Boot interface driver, with a PC standard baud rate up to 115200 BPS on the ST16C2552 DUART device located on DB-64360-BP device module. -- Network Interface - This LSP supports the following network devices: - o MV64360 Gigabit Ethernet Controller device - o Intel 82559 PCI NIC device -- PCI Interface - This LSP supports the following capabilities over the Marvell(r) device PCI0/1 units: - o Local PCI configuration header control. - o External PCI configuration header control (for other agents on the bus). - o PCI configuration application. Scans and configures the PCI agents on the bus. - o PCI Internal Arbiter activation and configuration. - -Memory Interface Support: -+++++++++++++++++++++++++ -- DDR - o DDR auto-detection and configuration. Enables access up to 256 MB, due to the limitations of using only four Base Address Translations (BATs). - o Enable DDR ECC in case both DIMM support ECC, and initialize the entire DDR memory by using the idma. - -- Devices - o Initializes the MV64360 device's chip-selects 0-3 to enable access to the boot flash, main flash, real time clock (RTC), and external SRAM. - o JFFS2 - JFFS2 is a crash/power down safe file system for disk-less embedded devices. - This version of U-Boot supports scanning a JFFS2 file system on the large flash and loading files from it. - -Unsupported Features: -+++++++++++++++++++++ - Messaging unit - No support for MV64360 Messaging unit. - Watchdog Timer - No support for MV64360 Watchdog unit. - L3 cache - No support for L3 cache on MPC7455 - Dual PCU - No support for Dual CPU - PCI-X was never tested - IDMA driver - No support for MV64360 IDMA unit. - XOR Engine - No support for MV64460 XOR Engine - -BSP Special Considerations: -+++++++++++++++++++++++++++ -- DDR DIMM location: Due to PCI specifications, place the larger DIMM module in the MAIN DIMM slot, in order to have full access from the PCI to the DDR while using both DDR slots. -- DDR DIMM types: Due to architectural and software limitations, the registration, CAS Latency, and ECC of both DIMMS should be identical. - -Test Cases: -########### -UART: -+++++ -Check that the UART baud rate is configured to 57600 and 115200, and check: - Transmit (to the hyper terminal) and Receive (using the keyboard) using Linux minicom. - Load S-Record file over the UART using Windows HyperTerminal. - -Network: -++++++++ -Use TFTP application to load a debugged executable and execute it. -Insert Intel PCI NIC 82557 rev 08 to PCI slots 0-3 Check correct detection of the PCI NIC, correct configuration of the NIC BARs , and load files by using tftp through the PCI NIC. - -Memory: -+++++++ -Test DDR DIMMs on DB-64360-BP. See that Uboot report their correct parameters: -o 128MB DIMM consist of 16 x 64Mbit devices -o 128MB DIMM consist of 09 x 128Mbit devices @ 266MHz. -o 256MB DIMM consist of 16 x 128Mbit devices @ 266MHz. -o 256MB DIMM consist of 09 x 256Mbit devices @ 400MHz. -o 512MB DIMM consist of 16 x 256Mbit devices @ 333MHz. -o 512MB DIMM consist of 18 x 256Mbit devices @ 266MHz. -o GigaB DIMM consist of 36 x 256Mbit devices @ 266MHz registered - -For each chip select device perform data access to verify its accessibility. - -Create a JFFS2 on the large flash through the Linux holding few files, few dirs and a uImage. -Load the U-Boot and: -use the ls command to check correct scan of the JFFS2 on the large flash. -Use the floads command to copy the uImage from the JFFS2 on the large flash to the DIMM SDRAM, and boot the uImage. - -PCI: -++++ -1)Insert different PCI cards: -Galileo 64120A rev 10 and 12, Intel Nic 82557 rev 08 and Real Tech NIC 8139 rev10 -on different slots (0-3) of the PCI and check: -o Correct detection of the PCI devices. -o Correct address mapping of the PCI devices. -2)Insert Galileo 64120A rev 10 on different slots (0-3) of the PCI and check writing and reading pci configuration register through the U-Boot. - -Booting Linux through the U-Boot (use the bootargs of the U-Boot as a bootcmd to the kernal) diff --git a/board/Marvell/db64460/db64460.c b/board/Marvell/db64460/db64460.c deleted file mode 100644 index 9baaaac..0000000 --- a/board/Marvell/db64460/db64460.c +++ /dev/null @@ -1,922 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * modifications for the DB64460 eval board based by Ingo.Assmus@keymile.com - */ - -/* - * db64460.c - main board support/init for the Galileo Eval board. - */ - -#include <common.h> -#include <74xx_7xx.h> -#include "../include/memory.h" -#include "../include/pci.h" -#include "../include/mv_gen_reg.h" -#include <net.h> -#include <netdev.h> -#include <linux/compiler.h> - -#include "eth.h" -#include "mpsc.h" -#include "i2c.h" -#include "64460.h" -#include "mv_regs.h" - -#undef DEBUG -/*#define DEBUG */ - -#define MAP_PCI - -#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -/* ------------------------------------------------------------------------- */ - -/* this is the current GT register space location */ -/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */ - -/* Unfortunately, we cant change it while we are in flash, so we initialize it - * to the "final" value. This means that any debug_led calls before - * board_early_init_f wont work right (like in cpu_init_f). - * See also my_remap_gt_regs below. (NTL) - */ - -void board_prebootm_init (void); -unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS; -int display_mem_map (void); - -/* ------------------------------------------------------------------------- */ - -/* - * This is a version of the GT register space remapping function that - * doesn't touch globals (meaning, it's ok to run from flash.) - * - * Unfortunately, this has the side effect that a writable - * INTERNAL_REG_BASE_ADDR is impossible. Oh well. - */ - -void my_remap_gt_regs (u32 cur_loc, u32 new_loc) -{ - u32 temp; - - /* check and see if it's already moved */ - -/* original ppcboot 1.1.6 source - - temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 20) - return; - - temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 20); - - out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp); - - while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp); -original ppcboot 1.1.6 source end */ - - temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 16) - return; - - temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 16); - - out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp); - - while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp); -} - -#ifdef CONFIG_PCI - -static void gt_pci_config (void) -{ - unsigned int stat; - unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */ - - /* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's - * config registers by writing ones to the bus and device. - * We then update the Virtual register with the correct value for the bus and device. - */ - if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ - GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); - - GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat); - - GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); - GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); - - } - if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ - GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); - GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat); - - GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); - GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); - } - - /* Enable master */ - PCI_MASTER_ENABLE (0, SELF); - PCI_MASTER_ENABLE (1, SELF); - - /* Enable PCI0/1 Mem0 and IO 0 disable all others */ - GT_REG_READ (BASE_ADDR_ENABLE, &stat); - stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1 - << - 18); - stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15)); - GT_REG_WRITE (BASE_ADDR_ENABLE, stat); - - /* ronen- add write to pci remap registers for 64460. - in 64360 when writing to pci base go and overide remap automaticaly, - in 64460 it doesn't */ - GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_BASE >> 16); - GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_BASE >> 16); - GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_BASE >> 16); - GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_BASE >> 16); - GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16); - - /* PCI interface settings */ - /* Timeout set to retry forever */ - GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0); - GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0); - - /* ronen - enable only CS0 and Internal reg!! */ - GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); - GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); - -/*ronen update the pci internal registers base address.*/ -#ifdef MAP_PCI - for (stat = 0; stat <= PCI_HOST1; stat++) - pciWriteConfigReg (stat, - PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, - SELF, CONFIG_SYS_GT_REGS); -#endif - -} -#endif - -/* Setup CPU interface paramaters */ -static void gt_cpu_config (void) -{ - cpu_t cpu = get_cpu_type (); - ulong tmp; - - /* cpu configuration register */ - tmp = GTREGREAD (CPU_CONFIGURATION); - - /* set the SINGLE_CPU bit see MV64460 P.399 */ -#ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ - tmp |= CPU_CONF_SINGLE_CPU; -#endif - - tmp &= ~CPU_CONF_AACK_DELAY_2; - - tmp |= CPU_CONF_DP_VALID; - tmp |= CPU_CONF_AP_VALID; - - tmp |= CPU_CONF_PIPELINE; - - GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */ - - /* CPU master control register */ - tmp = GTREGREAD (CPU_MASTER_CONTROL); - - tmp |= CPU_MAST_CTL_ARB_EN; - - if ((cpu == CPU_7400) || - (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) { - - tmp |= CPU_MAST_CTL_CLEAN_BLK; - tmp |= CPU_MAST_CTL_FLUSH_BLK; - - } else { - /* cleanblock must be cleared for CPUs - * that do not support this command (603e, 750) - * see Res#1 */ - tmp &= ~CPU_MAST_CTL_CLEAN_BLK; - tmp &= ~CPU_MAST_CTL_FLUSH_BLK; - } - GT_REG_WRITE (CPU_MASTER_CONTROL, tmp); -} - -/* - * board_early_init_f. - * - * set up gal. device mappings, etc. - */ -int board_early_init_f (void) -{ - uchar sram_boot = 0; - - /* - * set up the GT the way the kernel wants it - * the call to move the GT register space will obviously - * fail if it has already been done, but we're going to assume - * that if it's not at the power-on location, it's where we put - * it last time. (huber) - */ - - my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS); - - /* No PCI in first release of Port To_do: enable it. */ -#ifdef CONFIG_PCI - gt_pci_config (); -#endif - /* mask all external interrupt sources */ - GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0); - /* new in MV6446x */ - GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0); - /* --------------------- */ - GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); - GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); - /* does not exist in MV6446x - GT_REG_WRITE(CPU_INT_0_MASK, 0); - GT_REG_WRITE(CPU_INT_1_MASK, 0); - GT_REG_WRITE(CPU_INT_2_MASK, 0); - GT_REG_WRITE(CPU_INT_3_MASK, 0); - --------------------- */ - - - /* ----- DEVICE BUS SETTINGS ------ */ - - /* - * EVB - * 0 - SRAM ???? - * 1 - RTC ???? - * 2 - UART ???? - * 3 - Flash checked 32Bit Intel Strata - * boot - BootCS checked 8Bit 29LV040B - * - * Zuma - * 0 - Flash - * boot - BootCS - */ - - /* - * the dual 7450 module requires burst access to the boot - * device, so the serial rom copies the boot device to the - * on-board sram on the eval board, and updates the correct - * registers to boot from the sram. (device0) - */ - if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) - sram_boot = 1; - if (!sram_boot) - memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE); - - memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE); - memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE); - memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE); - - - /* configure device timing */ -#ifdef CONFIG_SYS_DEV0_PAR /* set port parameters for SRAM device module access */ - if (!sram_boot) - GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR); -#endif - -#ifdef CONFIG_SYS_DEV1_PAR /* set port parameters for RTC device module access */ - GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR); -#endif -#ifdef CONFIG_SYS_DEV2_PAR /* set port parameters for DUART device module access */ - GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR); -#endif - -#ifdef CONFIG_SYS_32BIT_BOOT_PAR /* set port parameters for Flash device module access */ - /* detect if we are booting from the 32 bit flash */ - if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) { - /* 32 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); - GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, - CONFIG_SYS_32BIT_BOOT_PAR); - } else { - /* 8 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR); - GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); - } -#else - /* 8 bit boot flash only */ -/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/ -#endif - - - gt_cpu_config (); - - /* MPP setup */ - GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0); - GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1); - GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2); - GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3); - - GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL); - DEBUG_LED0_ON (); - DEBUG_LED1_ON (); - DEBUG_LED2_ON (); - - return 0; -} - -/* various things to do after relocation */ - -int misc_init_r () -{ - icache_enable (); -#ifdef CONFIG_SYS_L2 - l2cache_enable (); -#endif -#ifdef CONFIG_MPSC - - mpsc_sdma_init (); - mpsc_init2 (); -#endif - -#if 0 - /* disable the dcache and MMU */ - dcache_lock (); -#endif - return 0; -} - -void after_reloc (ulong dest_addr, gd_t * gd) -{ - /* check to see if we booted from the sram. If so, move things - * back to the way they should be. (we're running from main - * memory at this point now */ - if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) { - memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE); - memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_DFL_BOOTCS_BASE, _8M); - } - display_mem_map (); - /* now, jump to the main ppcboot board init code */ - board_init_r (gd, dest_addr); - /* NOTREACHED */ -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - * - * right now, assume borad type. (there is just one...after all) - */ - -int checkboard (void) -{ - int l_type = 0; - - printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME); - return (l_type); -} - -/* utility functions */ -void debug_led (int led, int mode) -{ - volatile int *addr = 0; - __maybe_unused int dummy; - - if (mode == 1) { - switch (led) { - case 0: - addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | - 0x08000); - break; - - case 1: - addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | - 0x0c000); - break; - - case 2: - addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | - 0x10000); - break; - } - } else if (mode == 0) { - switch (led) { - case 0: - addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | - 0x14000); - break; - - case 1: - addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | - 0x18000); - break; - - case 2: - addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | - 0x1c000); - break; - } - } - - dummy = *addr; -} - -int display_mem_map (void) -{ - int i, j; - unsigned int base, size, width; - - /* SDRAM */ - printf ("SD (DDR) RAM\n"); - for (i = 0; i <= BANK3; i++) { - base = memoryGetBankBaseAddress (i); - size = memoryGetBankSize (i); - if (size != 0) { - printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n", - i, base, size >> 20); - } - } - - /* CPU's PCI windows */ - for (i = 0; i <= PCI_HOST1; i++) { - printf ("\nCPU's PCI %d windows\n", i); - base = pciGetSpaceBase (i, PCI_IO); - size = pciGetSpaceSize (i, PCI_IO); - printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base, - size >> 20); - for (j = 0; - j <= - PCI_REGION0 - /*ronen currently only first PCI MEM is used 3 */ ; - j++) { - base = pciGetSpaceBase (i, j); - size = pciGetSpaceSize (i, j); - printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20); - } - } - - /* Devices */ - printf ("\nDEVICES\n"); - for (i = 0; i <= DEVICE3; i++) { - base = memoryGetDeviceBaseAddress (i); - size = memoryGetDeviceSize (i); - width = memoryGetDeviceWidth (i) * 8; - printf ("DEV %d: base - 0x%08x size - %dM bytes\twidth - %d bits", i, base, size >> 20, width); - if (i == 0) - printf ("\t- EXT SRAM (actual - 1M)\n"); - else if (i == 1) - printf ("\t- RTC\n"); - else if (i == 2) - printf ("\t- UART\n"); - else - printf ("\t- LARGE FLASH\n"); - } - - /* Bootrom */ - base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */ - size = memoryGetDeviceSize (BOOT_DEVICE); - width = memoryGetDeviceWidth (BOOT_DEVICE) * 8; - printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\n", - base, size >> 20, width); - return (0); -} - -/* DRAM check routines copied from gw8260 */ - -#if defined (CONFIG_SYS_DRAM_TEST) - -/*********************************************************************/ -/* NAME: move64() - moves a double word (64-bit) */ -/* */ -/* DESCRIPTION: */ -/* this function performs a double word move from the data at */ -/* the source pointer to the location at the destination pointer. */ -/* */ -/* INPUTS: */ -/* unsigned long long *src - pointer to data to move */ -/* */ -/* OUTPUTS: */ -/* unsigned long long *dest - pointer to locate to move data */ -/* */ -/* RETURNS: */ -/* None */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* May cloober fr0. */ -/* */ -/*********************************************************************/ -static void move64 (unsigned long long *src, unsigned long long *dest) -{ - asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ - "stfd 0, 0(4)" /* *dest = fpr0 */ - : : : "fr0"); /* Clobbers fr0 */ - return; -} - - -#if defined (CONFIG_SYS_DRAM_TEST_DATA) - -unsigned long long pattern[] = { - 0xaaaaaaaaaaaaaaaaULL, - 0xccccccccccccccccULL, - 0xf0f0f0f0f0f0f0f0ULL, - 0xff00ff00ff00ff00ULL, - 0xffff0000ffff0000ULL, - 0xffffffff00000000ULL, - 0x00000000ffffffffULL, - 0x0000ffff0000ffffULL, - 0x00ff00ff00ff00ffULL, - 0x0f0f0f0f0f0f0f0fULL, - 0x3333333333333333ULL, - 0x5555555555555555ULL, -}; - -/*********************************************************************/ -/* NAME: mem_test_data() - test data lines for shorts and opens */ -/* */ -/* DESCRIPTION: */ -/* Tests data lines for shorts and opens by forcing adjacent data */ -/* to opposite states. Because the data lines could be routed in */ -/* an arbitrary manner the must ensure test patterns ensure that */ -/* every case is tested. By using the following series of binary */ -/* patterns every combination of adjacent bits is test regardless */ -/* of routing. */ -/* */ -/* ...101010101010101010101010 */ -/* ...110011001100110011001100 */ -/* ...111100001111000011110000 */ -/* ...111111110000000011111111 */ -/* */ -/* Carrying this out, gives us six hex patterns as follows: */ -/* */ -/* 0xaaaaaaaaaaaaaaaa */ -/* 0xcccccccccccccccc */ -/* 0xf0f0f0f0f0f0f0f0 */ -/* 0xff00ff00ff00ff00 */ -/* 0xffff0000ffff0000 */ -/* 0xffffffff00000000 */ -/* */ -/* The number test patterns will always be given by: */ -/* */ -/* log(base 2)(number data bits) = log2 (64) = 6 */ -/* */ -/* To test for short and opens to other signals on our boards. we */ -/* simply */ -/* test with the 1's complemnt of the paterns as well. */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* Assumes only one one SDRAM bank */ -/* */ -/*********************************************************************/ -int mem_test_data (void) -{ - unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START; - unsigned long long temp64 = 0; - int num_patterns = sizeof (pattern) / sizeof (pattern[0]); - int i; - unsigned int hi, lo; - - for (i = 0; i < num_patterns; i++) { - move64 (&(pattern[i]), pmem); - move64 (pmem, &temp64); - - /* hi = (temp64>>32) & 0xffffffff; */ - /* lo = temp64 & 0xffffffff; */ - /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */ - - hi = (pattern[i] >> 32) & 0xffffffff; - lo = pattern[i] & 0xffffffff; - /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */ - - if (temp64 != pattern[i]) { - printf ("\n Data Test Failed, pattern 0x%08x%08x", - hi, lo); - return 1; - } - } - - return 0; -} -#endif /* CONFIG_SYS_DRAM_TEST_DATA */ - -#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS) -/*********************************************************************/ -/* NAME: mem_test_address() - test address lines */ -/* */ -/* DESCRIPTION: */ -/* This function performs a test to verify that each word im */ -/* memory is uniquly addressable. The test sequence is as follows: */ -/* */ -/* 1) write the address of each word to each word. */ -/* 2) verify that each location equals its address */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern and address */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_test_address (void) -{ - volatile unsigned int *pmem = - (volatile unsigned int *) CONFIG_SYS_MEMTEST_START; - const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4; - unsigned int i; - - /* write address to each location */ - for (i = 0; i < size; i++) { - pmem[i] = i; - } - - /* verify each loaction */ - for (i = 0; i < size; i++) { - if (pmem[i] != i) { - printf ("\n Address Test Failed at 0x%x", i); - return 1; - } - } - return 0; -} -#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */ - -#if defined (CONFIG_SYS_DRAM_TEST_WALK) -/*********************************************************************/ -/* NAME: mem_march() - memory march */ -/* */ -/* DESCRIPTION: */ -/* Marches up through memory. At each location verifies rmask if */ -/* read = 1. At each location write wmask if write = 1. Displays */ -/* failing address and pattern. */ -/* */ -/* INPUTS: */ -/* volatile unsigned long long * base - start address of test */ -/* unsigned int size - number of dwords(64-bit) to test */ -/* unsigned long long rmask - read verify mask */ -/* unsigned long long wmask - wrtie verify mask */ -/* short read - verifies rmask if read = 1 */ -/* short write - writes wmask if write = 1 */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern and address */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_march (volatile unsigned long long *base, - unsigned int size, - unsigned long long rmask, - unsigned long long wmask, short read, short write) -{ - unsigned int i; - unsigned long long temp = 0; - unsigned int hitemp, lotemp, himask, lomask; - - for (i = 0; i < size; i++) { - if (read != 0) { - /* temp = base[i]; */ - move64 ((unsigned long long *) &(base[i]), &temp); - if (rmask != temp) { - hitemp = (temp >> 32) & 0xffffffff; - lotemp = temp & 0xffffffff; - himask = (rmask >> 32) & 0xffffffff; - lomask = rmask & 0xffffffff; - - printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp); - return 1; - } - } - if (write != 0) { - /* base[i] = wmask; */ - move64 (&wmask, (unsigned long long *) &(base[i])); - } - } - return 0; -} -#endif /* CONFIG_SYS_DRAM_TEST_WALK */ - -/*********************************************************************/ -/* NAME: mem_test_walk() - a simple walking ones test */ -/* */ -/* DESCRIPTION: */ -/* Performs a walking ones through entire physical memory. The */ -/* test uses as series of memory marches, mem_march(), to verify */ -/* and write the test patterns to memory. The test sequence is as */ -/* follows: */ -/* 1) march writing 0000...0001 */ -/* 2) march verifying 0000...0001 , writing 0000...0010 */ -/* 3) repeat step 2 shifting masks left 1 bit each time unitl */ -/* the write mask equals 1000...0000 */ -/* 4) march verifying 1000...0000 */ -/* The test fails if any of the memory marches return a failure. */ -/* */ -/* OUTPUTS: */ -/* Displays which pass on the memory test is executing */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_test_walk (void) -{ - unsigned long long mask; - volatile unsigned long long *pmem = - (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START; - const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8; - - unsigned int i; - - mask = 0x01; - - printf ("Initial Pass"); - mem_march (pmem, size, 0x0, 0x1, 0, 1); - - printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); - printf (" "); - printf (" "); - printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); - - for (i = 0; i < 63; i++) { - printf ("Pass %2d", i + 2); - if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) { - /*printf("mask: 0x%x, pass: %d, ", mask, i); */ - return 1; - } - mask = mask << 1; - printf ("\b\b\b\b\b\b\b"); - } - - printf ("Last Pass"); - if (mem_march (pmem, size, 0, mask, 0, 1) != 0) { - /* printf("mask: 0x%x", mask); */ - return 1; - } - printf ("\b\b\b\b\b\b\b\b\b"); - printf (" "); - printf ("\b\b\b\b\b\b\b\b\b"); - - return 0; -} - -/*********************************************************************/ -/* NAME: testdram() - calls any enabled memory tests */ -/* */ -/* DESCRIPTION: */ -/* Runs memory tests if the environment test variables are set to */ -/* 'y'. */ -/* */ -/* INPUTS: */ -/* testdramdata - If set to 'y', data test is run. */ -/* testdramaddress - If set to 'y', address test is run. */ -/* testdramwalk - If set to 'y', walking ones test is run */ -/* */ -/* OUTPUTS: */ -/* None */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int testdram (void) -{ - int rundata, runaddress, runwalk; - - rundata = getenv_yesno("testdramdata") == 1; - runaddress = getenv_yesno("testdramaddress") == 1; - runwalk = getenv_yesno("testdramwalk") == 1; - -/* rundata = 1; */ -/* runaddress = 0; */ -/* runwalk = 0; */ - - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END); - } -#ifdef CONFIG_SYS_DRAM_TEST_DATA - if (rundata == 1) { - printf ("Test DATA ... "); - if (mem_test_data () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif -#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS - if (runaddress == 1) { - printf ("Test ADDRESS ... "); - if (mem_test_address () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif -#ifdef CONFIG_SYS_DRAM_TEST_WALK - if (runwalk == 1) { - printf ("Test WALKING ONEs ... "); - if (mem_test_walk () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("passed\n"); - } - return 0; - -} -#endif /* CONFIG_SYS_DRAM_TEST */ - -/* ronen - the below functions are used by the bootm function */ -/* - we map the base register to fbe00000 (same mapping as in the LSP) */ -/* - we turn off the RX gig dmas - to prevent the dma from overunning */ -/* the kernel data areas. */ -/* - we diable and invalidate the icache and dcache. */ -void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc) -{ - u32 temp; - - temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 16) - return; - - temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 16); - - out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp); - - while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE | - new_loc | - (INTERNAL_SPACE_DECODE))))) - != temp); - -} - -void board_prebootm_init () -{ - -/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */ - GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16); - -/* Stop GigE Rx DMA engines */ - GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00); - GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00); - GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00); - -/* Relocate MV64460 internal regs */ - my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, BRIDGE_REG_BASE_BOOTM); - - icache_disable (); - dcache_disable (); -} - -int board_eth_init(bd_t *bis) -{ - int ret; - ret = pci_eth_init(bis); - if (!ret) - ret = mv6446x_eth_initialize(bis); - return ret; -} diff --git a/board/Marvell/db64460/eth.h b/board/Marvell/db64460/eth.h deleted file mode 100644 index c2067a4..0000000 --- a/board/Marvell/db64460/eth.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * eth.h - header file for the polled mode GT ethernet driver - */ - -#ifndef __EVB64460_ETH_H__ -#define __EVB64460_ETH_H__ - -#include <asm/types.h> -#include <asm/io.h> -#include <asm/byteorder.h> -#include <common.h> - -int db64460_eth0_poll(void); -int db64460_eth0_transmit(unsigned int s, volatile char *p); -void db64460_eth0_disable(void); -bool network_start(bd_t *bis); - -int mv6446x_eth_initialize(bd_t *); - -#endif /* __EVB64460_ETH_H__ */ diff --git a/board/Marvell/db64460/mpsc.c b/board/Marvell/db64460/mpsc.c deleted file mode 100644 index 9fbbae8..0000000 --- a/board/Marvell/db64460/mpsc.c +++ /dev/null @@ -1,1001 +0,0 @@ -/* - * (C) Copyright 2001 - * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * changes for Marvell DB64460 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com> - * - ************************************************************************/ - -/* - * mpsc.c - driver for console over the MPSC. - */ - - -#include <common.h> -#include <config.h> -#include <asm/cache.h> - -#include <malloc.h> -#include "mpsc.h" - -#include "mv_regs.h" - -#include "../include/memory.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* Define this if you wish to use the MPSC as a register based UART. - * This will force the serial port to not use the SDMA engine at all. - */ -#undef CONFIG_MPSC_DEBUG_PORT - - -int (*mpsc_putchar) (char ch) = mpsc_putchar_early; -char (*mpsc_getchar) (void) = mpsc_getchar_debug; -int (*mpsc_test_char) (void) = mpsc_test_char_debug; - - -static volatile unsigned int *rx_desc_base = NULL; -static unsigned int rx_desc_index = 0; -static volatile unsigned int *tx_desc_base = NULL; -static unsigned int tx_desc_index = 0; - -/* local function declarations */ -static int galmpsc_connect (int channel, int connect); -static int galmpsc_route_rx_clock (int channel, int brg); -static int galmpsc_route_tx_clock (int channel, int brg); -static int galmpsc_write_config_regs (int mpsc, int mode); -static int galmpsc_config_channel_regs (int mpsc); -static int galmpsc_set_char_length (int mpsc, int value); -static int galmpsc_set_stop_bit_length (int mpsc, int value); -static int galmpsc_set_parity (int mpsc, int value); -static int galmpsc_enter_hunt (int mpsc); -static int galmpsc_set_brkcnt (int mpsc, int value); -static int galmpsc_set_tcschar (int mpsc, int value); -static int galmpsc_set_snoop (int mpsc, int value); -static int galmpsc_shutdown (int mpsc); - -static int galsdma_set_RFT (int channel); -static int galsdma_set_SFM (int channel); -static int galsdma_set_rxle (int channel); -static int galsdma_set_txle (int channel); -static int galsdma_set_burstsize (int channel, unsigned int value); -static int galsdma_set_RC (int channel, unsigned int value); - -static int galbrg_set_CDV (int channel, int value); -static int galbrg_enable (int channel); -static int galbrg_disable (int channel); -static int galbrg_set_clksrc (int channel, int value); -static int galbrg_set_CUV (int channel, int value); - -static void galsdma_enable_rx (void); -static int galsdma_set_mem_space (unsigned int memSpace, - unsigned int memSpaceTarget, - unsigned int memSpaceAttr, - unsigned int baseAddress, - unsigned int size); - - -#define SOFTWARE_CACHE_MANAGEMENT - -#ifdef SOFTWARE_CACHE_MANAGEMENT -#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));} -#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));} -#else -#define FLUSH_DCACHE(a,b) -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) -#define INVALIDATE_DCACHE(a,b) -#endif - -#ifdef CONFIG_MPSC_DEBUG_PORT -static void mpsc_debug_init (void) -{ - - volatile unsigned int temp; - - /* Clear the CFR (CHR4) */ - /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */ - temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP)); - temp &= 0xffffff00; - temp |= BIT29; - GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP), - temp); - - /* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */ - temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP)); - temp |= (BIT12 | BIT15); - GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP), - temp); - - /* Set int mask */ - temp = GTREGREAD (GALMPSC_0_INT_MASK); - temp |= BIT6; - GT_REG_WRITE (GALMPSC_0_INT_MASK, temp); -} -#endif - -char mpsc_getchar_debug (void) -{ - volatile int temp; - volatile unsigned int cause; - - cause = GTREGREAD (GALMPSC_0_INT_CAUSE); - while ((cause & BIT6) == 0) { - cause = GTREGREAD (GALMPSC_0_INT_CAUSE); - } - - temp = GTREGREAD (GALMPSC_CHANNELREG_10 + - (CHANNEL * GALMPSC_REG_GAP)); - /* By writing 1's to the set bits, the register is cleared */ - GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP), - temp); - GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6); - return (temp >> 16) & 0xff; -} - -/* special function for running out of flash. doesn't modify any - * global variables [josh] */ -int mpsc_putchar_early (char ch) -{ - int mpsc = CHANNEL; - int temp = - GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - galmpsc_set_tcschar (mpsc, ch); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), - temp | 0x200); - -#define MAGIC_FACTOR (10*1000000) - - udelay (MAGIC_FACTOR / gd->baudrate); - return 0; -} - -/* This is used after relocation, see serial.c and mpsc_init2 */ -static int mpsc_putchar_sdma (char ch) -{ - volatile unsigned int *p; - unsigned int temp; - - - /* align the descriptor */ - p = tx_desc_base; - memset ((void *) p, 0, 8 * sizeof (unsigned int)); - - /* fill one 64 bit buffer */ - /* word swap, pad with 0 */ - p[4] = 0; /* x */ - p[5] = (unsigned int) ch; /* x */ - - /* CHANGED completely according to GT64260A dox - NTL */ - p[0] = 0x00010001; /* 0 */ - p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* 4 */ - p[2] = 0; /* 8 */ - p[3] = (unsigned int) &p[4]; /* c */ - -#if 0 - p[9] = DESC_FIRST | DESC_LAST; - p[10] = (unsigned int) &p[0]; - p[11] = (unsigned int) &p[12]; -#endif - - FLUSH_DCACHE (&p[0], &p[8]); - - GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &p[0]); - GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &p[0]); - - temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF)); - temp |= (TX_DEMAND | TX_STOP); - GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp); - - INVALIDATE_DCACHE (&p[1], &p[2]); - - while (p[1] & DESC_OWNER_BIT) { - udelay (100); - INVALIDATE_DCACHE (&p[1], &p[2]); - } - return 0; -} - -char mpsc_getchar_sdma (void) -{ - static unsigned int done = 0; - volatile char ch; - unsigned int len = 0, idx = 0, temp; - - volatile unsigned int *p; - - - do { - p = &rx_desc_base[rx_desc_index * 8]; - - INVALIDATE_DCACHE (&p[0], &p[1]); - /* Wait for character */ - while (p[1] & DESC_OWNER_BIT) { - udelay (100); - INVALIDATE_DCACHE (&p[0], &p[1]); - } - - /* Handle error case */ - if (p[1] & (1 << 15)) { - printf ("oops, error: %08x\n", p[1]); - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + - (CHANNEL * GALMPSC_REG_GAP)); - temp |= (1 << 23); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + - (CHANNEL * GALMPSC_REG_GAP), temp); - - /* Can't poll on abort bit, so we just wait. */ - udelay (100); - - galsdma_enable_rx (); - } - - /* Number of bytes left in this descriptor */ - len = p[0] & 0xffff; - - if (len) { - /* Where to look */ - idx = 5; - if (done > 3) - idx = 4; - if (done > 7) - idx = 7; - if (done > 11) - idx = 6; - - INVALIDATE_DCACHE (&p[idx], &p[idx + 1]); - ch = p[idx] & 0xff; - done++; - } - - if (done < len) { - /* this descriptor has more bytes still - * shift down the char we just read, and leave the - * buffer in place for the next time around - */ - p[idx] = p[idx] >> 8; - FLUSH_DCACHE (&p[idx], &p[idx + 1]); - } - - if (done == len) { - /* nothing left in this descriptor. - * go to next one - */ - p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; - p[0] = 0x00100000; - FLUSH_DCACHE (&p[0], &p[1]); - /* Next descriptor */ - rx_desc_index = (rx_desc_index + 1) % RX_DESC; - done = 0; - } - } while (len == 0); /* galileo bug.. len might be zero */ - - return ch; -} - - -int mpsc_test_char_debug (void) -{ - if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0) - return 0; - else { - return 1; - } -} - - -int mpsc_test_char_sdma (void) -{ - volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8]; - - INVALIDATE_DCACHE (&p[1], &p[2]); - - if (p[1] & DESC_OWNER_BIT) - return 0; - else - return 1; -} - -int mpsc_init (int baud) -{ - /* BRG CONFIG */ - galbrg_set_baudrate (CHANNEL, baud); - galbrg_set_clksrc (CHANNEL, 8); /* set source=Tclk */ - galbrg_set_CUV (CHANNEL, 0); /* set up CountUpValue */ - galbrg_enable (CHANNEL); /* Enable BRG */ - - /* Set up clock routing */ - galmpsc_connect (CHANNEL, GALMPSC_CONNECT); /* connect it */ - - galmpsc_route_rx_clock (CHANNEL, CHANNEL); /* chosse BRG0 for Rx */ - galmpsc_route_tx_clock (CHANNEL, CHANNEL); /* chose BRG0 for Tx */ - - /* reset MPSC state */ - galmpsc_shutdown (CHANNEL); - - /* SDMA CONFIG */ - galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8); /* in 64 bit words (8 bytes) */ - galsdma_set_txle (CHANNEL); - galsdma_set_rxle (CHANNEL); - galsdma_set_RC (CHANNEL, 0xf); - galsdma_set_SFM (CHANNEL); - galsdma_set_RFT (CHANNEL); - - /* MPSC CONFIG */ - galmpsc_write_config_regs (CHANNEL, GALMPSC_UART); - galmpsc_config_channel_regs (CHANNEL); - galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8); /* 8 */ - galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE); /* N */ - galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */ - -#ifdef CONFIG_MPSC_DEBUG_PORT - mpsc_debug_init (); -#endif - - /* COMM_MPSC CONFIG */ -#ifdef SOFTWARE_CACHE_MANAGEMENT - galmpsc_set_snoop (CHANNEL, 0); /* disable snoop */ -#else - galmpsc_set_snoop (CHANNEL, 1); /* enable snoop */ -#endif - - return 0; -} - - -void mpsc_sdma_init (void) -{ -/* Setup SDMA channel0 SDMA_CONFIG_REG*/ - GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff); - -/* Enable MPSC-Window0 for DRAM Bank0 */ - if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT, - MV64460_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_0_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK0)) != true) - printf ("%s: SDMA_Window0 memory setup failed !!! \n", - __FUNCTION__); - - -/* Disable MPSC-Window1 */ - if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_1_BIT, - MV64460_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_1_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK3)) != true) - printf ("%s: SDMA_Window1 memory setup failed !!! \n", - __FUNCTION__); - - -/* Disable MPSC-Window2 */ - if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_2_BIT, - MV64460_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_2_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK3)) != true) - printf ("%s: SDMA_Window2 memory setup failed !!! \n", - __FUNCTION__); - - -/* Disable MPSC-Window3 */ - if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_3_BIT, - MV64460_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_3_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK3)) != true) - printf ("%s: SDMA_Window3 memory setup failed !!! \n", - __FUNCTION__); - -/* Setup MPSC0 access mode Window0 full access */ - GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG, - (MV64460_SDMA_WIN_ACCESS_FULL << - (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); - -/* Setup MPSC1 access mode Window1 full access */ - GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG, - (MV64460_SDMA_WIN_ACCESS_FULL << - (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); - -/* Setup MPSC internal address space base address */ - GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS); - -/* no high address remap*/ - GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00); - GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00); - -/* clear interrupt cause register for MPSC (fault register)*/ - GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00); -} - - -void mpsc_init2 (void) -{ - int i; - -#ifndef CONFIG_MPSC_DEBUG_PORT - mpsc_putchar = mpsc_putchar_sdma; - mpsc_getchar = mpsc_getchar_sdma; - mpsc_test_char = mpsc_test_char_sdma; -#endif - /* RX descriptors */ - rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) * - sizeof (unsigned int)); - - /* align descriptors */ - rx_desc_base = (unsigned int *) - (((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0); - - rx_desc_index = 0; - - memset ((void *) rx_desc_base, 0, - (RX_DESC * 8) * sizeof (unsigned int)); - - for (i = 0; i < RX_DESC; i++) { - rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4]; /* Buffer */ - rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8]; /* Next descriptor */ - rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* Command & control */ - rx_desc_base[i * 8] = 0x00100000; - } - rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0]; - - FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]); - GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &rx_desc_base[0]); - - /* TX descriptors */ - tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) * - sizeof (unsigned int)); - - /* align descriptors */ - tx_desc_base = (unsigned int *) - (((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0); - - tx_desc_index = -1; - - memset ((void *) tx_desc_base, 0, - (TX_DESC * 8) * sizeof (unsigned int)); - - for (i = 0; i < TX_DESC; i++) { - tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323; - tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323; - tx_desc_base[i * 8 + 3] = - (unsigned int) &tx_desc_base[i * 8 + 4]; - tx_desc_base[i * 8 + 2] = - (unsigned int) &tx_desc_base[(i + 1) * 8]; - tx_desc_base[i * 8 + 1] = - DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; - - /* set sbytecnt and shadow byte cnt to 1 */ - tx_desc_base[i * 8] = 0x00010001; - } - tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0]; - - FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]); - - udelay (100); - - galsdma_enable_rx (); - - return; -} - -int galbrg_set_baudrate (int channel, int rate) -{ - int clock; - - galbrg_disable (channel); /*ok */ - -#ifdef ZUMA_NTL - /* from tclk */ - clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; -#else - clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; -#endif - - galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */ - - galbrg_enable (channel); - - gd->baudrate = rate; - - return 0; -} - -/* ------------------------------------------------------------------ */ - -/* Below are all the private functions that no one else needs */ - -static int galbrg_set_CDV (int channel, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFFF0000; - temp |= (value & 0x0000FFFF); - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_enable (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp |= 0x00010000; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_disable (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFFEFFFF; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_set_clksrc (int channel, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFC3FFFF; /* Bit 18 - 21 (MV 64260 18-22) */ - temp |= (value << 18); - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - return 0; -} - -static int galbrg_set_CUV (int channel, int value) -{ - /* set CountUpValue */ - GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value); - - return 0; -} - -#if 0 -static int galbrg_reset (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp |= 0x20000; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} -#endif - -static int galsdma_set_RFT (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000001; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_SFM (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000002; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_rxle (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000040; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_txle (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000080; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_RC (int channel, unsigned int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp &= ~0x0000003c; - temp |= (value << 2); - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_burstsize (int channel, unsigned int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp &= 0xFFFFCFFF; - switch (value) { - case 8: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x3 << 12))); - break; - - case 4: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x2 << 12))); - break; - - case 2: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x1 << 12))); - break; - - case 1: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x0 << 12))); - break; - - default: - return -1; - break; - } - - return 0; -} - -static int galmpsc_connect (int channel, int connect) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_ROUTING_REGISTER); - - if ((channel == 0) && connect) - temp &= ~0x00000007; - else if ((channel == 1) && connect) - temp &= ~(0x00000007 << 6); - else if ((channel == 0) && !connect) - temp |= 0x00000007; - else - temp |= (0x00000007 << 6); - - /* Just in case... */ - temp &= 0x3fffffff; - - GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp); - - return 0; -} - -static int galmpsc_route_rx_clock (int channel, int brg) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_RxC_ROUTE); - - if (channel == 0) { - temp &= ~0x0000000F; - temp |= brg; - } else { - temp &= ~0x00000F00; - temp |= (brg << 8); - } - - GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp); - - return 0; -} - -static int galmpsc_route_tx_clock (int channel, int brg) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_TxC_ROUTE); - - if (channel == 0) { - temp &= ~0x0000000F; - temp |= brg; - } else { - temp &= ~0x00000F00; - temp |= (brg << 8); - } - - GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp); - - return 0; -} - -static int galmpsc_write_config_regs (int mpsc, int mode) -{ - if (mode == GALMPSC_UART) { - /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */ - GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP), - 0x000004c4); - - /* Main config reg High (32x Rx/Tx clock mode, width=8bits */ - GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP), - 0x024003f8); - /* 22 2222 1111 */ - /* 54 3210 9876 */ - /* 0000 0010 0000 0000 */ - /* 1 */ - /* 098 7654 3210 */ - /* 0000 0011 1111 1000 */ - } else - return -1; - - return 0; -} - -static int galmpsc_config_channel_regs (int mpsc) -{ - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1); - GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0); - - galmpsc_set_brkcnt (mpsc, 0x3); - galmpsc_set_tcschar (mpsc, 0xab); - - return 0; -} - -static int galmpsc_set_brkcnt (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP)); - temp &= 0x0000FFFF; - temp |= (value << 16); - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_tcschar (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFF0000; - temp |= value; - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_char_length (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFFCFFF; - temp |= (value << 12); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_stop_bit_length (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFFBFFF; - temp |= (value << 14); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_parity (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - if (value != -1) { - temp &= 0xFFF3FFF3; - temp |= ((value << 18) | (value << 2)); - temp |= ((value << 17) | (value << 1)); - } else { - temp &= 0xFFF1FFF1; - } - - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_enter_hunt (int mpsc) -{ - int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - temp |= 0x80000000; - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) & - MPSC_ENTER_HUNT) { - udelay (1); - } - return 0; -} - - -static int galmpsc_shutdown (int mpsc) -{ - unsigned int temp; - - /* cause RX abort (clears RX) */ - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - temp |= MPSC_RX_ABORT | MPSC_TX_ABORT; - temp &= ~MPSC_ENTER_HUNT; - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - GT_REG_WRITE (GALSDMA_0_COM_REG, 0); - GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT); - - /* shut down the MPSC */ - GT_REG_WRITE (GALMPSC_MCONF_LOW, 0); - GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0); - - udelay (100); - - /* shut down the sdma engines. */ - /* reset config to default */ - GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc); - - udelay (100); - - /* clear the SDMA current and first TX and RX pointers */ - GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0); - GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0); - GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0); - - udelay (100); - - return 0; -} - -static void galsdma_enable_rx (void) -{ - int temp; - - /* Enable RX processing */ - temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF)); - temp |= RX_ENABLE; - GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp); - - galmpsc_enter_hunt (CHANNEL); -} - -static int galmpsc_set_snoop (int mpsc, int value) -{ - int reg = - mpsc ? MPSC_1_ADDRESS_CONTROL_LOW : - MPSC_0_ADDRESS_CONTROL_LOW; - int temp = GTREGREAD (reg); - - if (value) - temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30); - else - temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30)); - GT_REG_WRITE (reg, temp); - return 0; -} - -/******************************************************************************* -* galsdma_set_mem_space - Set MV64460 IDMA memory decoding map. -* -* DESCRIPTION: -* the MV64460 SDMA has its own address decoding map that is de-coupled -* from the CPU interface address decoding windows. The SDMA channels -* share four address windows. Each region can be individually configured -* by this function by associating it to a target interface and setting -* base and size values. -* -* NOTE!!! -* The size must be in 64Kbyte granularity. -* The base address must be aligned to the size. -* The size must be a series of 1s followed by a series of zeros -* -* OUTPUT: -* None. -* -* RETURN: -* true for success, false otherwise. -* -*******************************************************************************/ - -static int galsdma_set_mem_space (unsigned int memSpace, - unsigned int memSpaceTarget, - unsigned int memSpaceAttr, - unsigned int baseAddress, unsigned int size) -{ - unsigned int temp; - - if (size == 0) { - GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG, - 1 << memSpace); - return true; - } - - /* The base address must be aligned to the size. */ - if (baseAddress % size != 0) { - return false; - } - if (size < 0x10000) { - return false; - } - - /* Align size and base to 64K */ - baseAddress &= 0xffff0000; - size &= 0xffff0000; - temp = size >> 16; - - /* Checking that the size is a sequence of '1' followed by a - sequence of '0' starting from LSB to MSB. */ - while ((temp > 0) && (temp & 0x1)) { - temp = temp >> 1; - } - - if (temp != 0) { - GT_REG_WRITE (MV64460_CUNIT_BASE_ADDR_REG0 + memSpace * 8, - (baseAddress | memSpaceTarget | memSpaceAttr)); - GT_REG_WRITE ((MV64460_CUNIT_SIZE0 + memSpace * 8), - (size - 1) & 0xffff0000); - GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG, - 1 << memSpace); - } else { - /* An invalid size was specified */ - return false; - } - return true; -} diff --git a/board/Marvell/db64460/mpsc.h b/board/Marvell/db64460/mpsc.h deleted file mode 100644 index 9e65e67..0000000 --- a/board/Marvell/db64460/mpsc.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * (C) Copyright 2001 - * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * changes for Marvell DB64460 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com> - * - ************************************************************************/ - - -/* - * mpsc.h - header file for MPSC in uart mode (console driver) - */ - -#ifndef __MPSC_H__ -#define __MPSC_H__ - -/* include actual Galileo defines */ -#include "../include/mv_gen_reg.h" - -/* driver related defines */ - -int mpsc_init(int baud); -void mpsc_sdma_init(void); -void mpsc_init2(void); -int galbrg_set_baudrate(int channel, int rate); - -int mpsc_putchar_early(char ch); -char mpsc_getchar_debug(void); -int mpsc_test_char_debug(void); - -int mpsc_test_char_sdma(void); - -extern int (*mpsc_putchar)(char ch); -extern char (*mpsc_getchar)(void); -extern int (*mpsc_test_char)(void); - -#define CHANNEL CONFIG_MPSC_PORT - -#define TX_DESC 5 -#define RX_DESC 20 - -#define DESC_FIRST 0x00010000 -#define DESC_LAST 0x00020000 -#define DESC_OWNER_BIT 0x80000000 - -#define TX_DEMAND 0x00800000 -#define TX_STOP 0x00010000 -#define RX_ENABLE 0x00000080 - -#define SDMA_RX_ABORT (1 << 15) -#define SDMA_TX_ABORT (1 << 31) -#define MPSC_TX_ABORT (1 << 7) -#define MPSC_RX_ABORT (1 << 23) -#define MPSC_ENTER_HUNT (1 << 31) - -/* MPSC defines */ - -#define GALMPSC_CONNECT 0x1 -#define GALMPSC_DISCONNECT 0x0 - -#define GALMPSC_UART 0x1 - -#define GALMPSC_STOP_BITS_1 0x0 -#define GALMPSC_STOP_BITS_2 0x1 -#define GALMPSC_CHAR_LENGTH_8 0x3 -#define GALMPSC_CHAR_LENGTH_7 0x2 - -#define GALMPSC_PARITY_ODD 0x0 -#define GALMPSC_PARITY_EVEN 0x2 -#define GALMPSC_PARITY_MARK 0x3 -#define GALMPSC_PARITY_SPACE 0x1 -#define GALMPSC_PARITY_NONE -1 - -#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */ -#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */ -#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */ -#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */ -#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */ -#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */ -#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */ - -#define GALMPSC_REG_GAP 0x1000 - -#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */ -#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */ -#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */ -#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */ -#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */ -#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */ -#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */ -#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */ -#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */ -#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */ -#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */ -#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */ - -#define GALSDMA_COMMAND_FIRST (1 << 16) -#define GALSDMA_COMMAND_LAST (1 << 17) -#define GALSDMA_COMMAND_ENABLEINT (1 << 23) -#define GALSDMA_COMMAND_AUTO (1 << 30) -#define GALSDMA_COMMAND_OWNER (1 << 31) - -#define GALSDMA_RX 0 -#define GALSDMA_TX 1 - -/* CHANNEL2 should be CHANNEL1, according to documentation, - * but to work with the current GTREGS file... - */ -#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */ -#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */ -#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */ -#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */ -#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */ -#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */ -#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */ -#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */ -#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */ -#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */ -#define GALSDMA_REG_DIFF 0x2000 - -/* WRONG in gt64260R.h */ -#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */ -#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */ -#define GALMPSC_0_INT_CAUSE 0xb804 -#define GALMPSC_0_INT_MASK 0xb884 - -#define GALSDMA_MODE_UART 0 -#define GALSDMA_MODE_BISYNC 1 -#define GALSDMA_MODE_HDLC 2 -#define GALSDMA_MODE_TRANSPARENT 3 - -#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */ -#define GALBRG_REG_GAP 0x0008 -#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */ - -#endif /* __MPSC_H__ */ diff --git a/board/Marvell/db64460/mv_eth.c b/board/Marvell/db64460/mv_eth.c deleted file mode 100644 index 82fcadf..0000000 --- a/board/Marvell/db64460/mv_eth.c +++ /dev/null @@ -1,3127 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus <ingo.assmus@keymile.com> - * - * based on - Driver for MV64460X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mv_eth.c - header file for the polled mode GT ethernet driver - */ -#include <common.h> -#include <net.h> -#include <malloc.h> - -#include "mv_eth.h" - -/* enable Debug outputs */ - -#undef DEBUG_MV_ETH - -#ifdef DEBUG_MV_ETH -#define DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -#undef MV64460_CHECKSUM_OFFLOAD -/************************************************************************* -************************************************************************** -************************************************************************** -* The first part is the high level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ - -/* Definition for configuring driver */ -/* #define UPDATE_STATS_BY_SOFTWARE */ -#undef MV64460_RX_QUEUE_FILL_ON_TASK - - -/* Constants */ -#define MAGIC_ETH_RUNNING 8031971 -#define MV64460_INTERNAL_SRAM_SIZE _256K -#define EXTRA_BYTES 32 -#define WRAP ETH_HLEN + 2 + 4 + 16 -#define BUFFER_MTU dev->mtu + WRAP -#define INT_CAUSE_UNMASK_ALL 0x0007ffff -#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff -#ifdef MV64460_RX_FILL_ON_TASK -#define INT_CAUSE_MASK_ALL 0x00000000 -#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL -#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT -#endif - -/* Read/Write to/from MV64460 internal registers */ -#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset)) -#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data) -#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits))) -#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits))) - -/* Static function declarations */ -static int mv64460_eth_real_open (struct eth_device *eth); -static int mv64460_eth_real_stop (struct eth_device *eth); -static struct net_device_stats *mv64460_eth_get_stats (struct eth_device - *dev); -static void eth_port_init_mac_tables (ETH_PORT eth_port_num); -static void mv64460_eth_update_stat (struct eth_device *dev); -bool db64460_eth_start (struct eth_device *eth); -unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, - unsigned int mib_offset); -int mv64460_eth_receive (struct eth_device *dev); - -int mv64460_eth_xmit (struct eth_device *, volatile void *packet, int length); - -#ifndef UPDATE_STATS_BY_SOFTWARE -static void mv64460_eth_print_stat (struct eth_device *dev); -#endif - -extern unsigned int INTERNAL_REG_BASE_ADDR; - -/************************************************* - *Helper functions - used inside the driver only * - *************************************************/ -#ifdef DEBUG_MV_ETH -void print_globals (struct eth_device *dev) -{ - printf ("Ethernet PRINT_Globals-Debug function\n"); - printf ("Base Address for ETH_PORT_INFO: %08x\n", - (unsigned int) dev->priv); - printf ("Base Address for mv64460_eth_priv: %08x\n", - (unsigned int) &(((ETH_PORT_INFO *) dev->priv)-> - port_private)); - - printf ("GT Internal Base Address: %08x\n", - INTERNAL_REG_BASE_ADDR); - printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64460_TX_QUEUE_SIZE); - printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64460_RX_QUEUE_SIZE); - printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n", - (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> - p_rx_buffer_base[0], - (MV64460_RX_QUEUE_SIZE * MV64460_RX_BUFFER_SIZE) + 32); - printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n", - (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> - p_tx_buffer_base[0], - (MV64460_TX_QUEUE_SIZE * MV64460_TX_BUFFER_SIZE) + 32); -} -#endif - -#define my_cpu_to_le32(x) my_le32_to_cpu((x)) - -unsigned long my_le32_to_cpu (unsigned long x) -{ - return (((x & 0x000000ffU) << 24) | - ((x & 0x0000ff00U) << 8) | - ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24)); -} - - -/********************************************************************** - * mv64460_eth_print_phy_status - * - * Prints gigabit ethenret phy status - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64460_eth_print_phy_status (struct eth_device *dev) -{ - struct mv64460_eth_priv *port_private; - unsigned int port_num; - ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv; - unsigned int port_status, phy_reg_data; - - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Check Link status on phy */ - eth_port_read_smi_reg (port_num, 1, &phy_reg_data); - if (!(phy_reg_data & 0x20)) { - printf ("Ethernet port changed link status to DOWN\n"); - } else { - port_status = - MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num)); - printf ("Ethernet status port %d: Link up", port_num); - printf (", %s", - (port_status & BIT2) ? "Full Duplex" : "Half Duplex"); - if (port_status & BIT4) - printf (", Speed 1 Gbps"); - else - printf (", %s", - (port_status & BIT5) ? "Speed 100 Mbps" : - "Speed 10 Mbps"); - printf ("\n"); - } -} - -/********************************************************************** - * u-boot entry functions for mv64460_eth - * - **********************************************************************/ -int db64460_eth_probe (struct eth_device *dev) -{ - return ((int) db64460_eth_start (dev)); -} - -int db64460_eth_poll (struct eth_device *dev) -{ - return mv64460_eth_receive (dev); -} - -int db64460_eth_transmit(struct eth_device *dev, void *packet, int length) -{ - mv64460_eth_xmit (dev, packet, length); - return 0; -} - -void db64460_eth_disable (struct eth_device *dev) -{ - mv64460_eth_stop (dev); -} - - -void mv6446x_eth_initialize (bd_t * bis) -{ - struct eth_device *dev; - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - int devnum, x, temp; - char *s, *e, buf[64]; - - for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) { - dev = calloc (sizeof (*dev), 1); - if (!dev) { - printf ("%s: mv_enet%d allocation failure, %s\n", - __FUNCTION__, devnum, "eth_device structure"); - return; - } - - /* must be less than sizeof(dev->name) */ - sprintf (dev->name, "mv_enet%d", devnum); - -#ifdef DEBUG - printf ("Initializing %s\n", dev->name); -#endif - - /* Extract the MAC address from the environment */ - switch (devnum) { - case 0: - s = "ethaddr"; - break; - - case 1: - s = "eth1addr"; - break; - - case 2: - s = "eth2addr"; - break; - - default: /* this should never happen */ - printf ("%s: Invalid device number %d\n", - __FUNCTION__, devnum); - return; - } - - temp = getenv_f(s, buf, sizeof (buf)); - s = (temp > 0) ? buf : NULL; - -#ifdef DEBUG - printf ("Setting MAC %d to %s\n", devnum, s); -#endif - for (x = 0; x < 6; ++x) { - dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - /* ronen - set the MAC addr in the HW */ - eth_port_uc_addr_set (devnum, dev->enetaddr, 0); - - dev->init = (void *) db64460_eth_probe; - dev->halt = (void *) ethernet_phy_reset; - dev->send = (void *) db64460_eth_transmit; - dev->recv = (void *) db64460_eth_poll; - - ethernet_private = calloc (sizeof (*ethernet_private), 1); - dev->priv = (void *)ethernet_private; - if (!ethernet_private) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Private Device Structure"); - free (dev); - return; - } - /* start with an zeroed ETH_PORT_INFO */ - memset (ethernet_private, 0, sizeof (ETH_PORT_INFO)); - memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); - - /* set pointer to memory for stats data structure etc... */ - port_private = calloc (sizeof (*ethernet_private), 1); - ethernet_private->port_private = (void *)port_private; - if (!port_private) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Port Private Device Structure"); - - free (ethernet_private); - free (dev); - return; - } - - port_private->stats = - calloc (sizeof (struct net_device_stats), 1); - if (!port_private->stats) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Net stat Structure"); - - free (port_private); - free (ethernet_private); - free (dev); - return; - } - memset (ethernet_private->port_private, 0, - sizeof (struct mv64460_eth_priv)); - switch (devnum) { - case 0: - ethernet_private->port_num = ETH_0; - break; - case 1: - ethernet_private->port_num = ETH_1; - break; - case 2: - ethernet_private->port_num = ETH_2; - break; - default: - printf ("Invalid device number %d\n", devnum); - break; - }; - - port_private->port_num = devnum; - /* - * Read MIB counter on the GT in order to reset them, - * then zero all the stats fields in memory - */ - mv64460_eth_update_stat (dev); - memset (port_private->stats, 0, - sizeof (struct net_device_stats)); - /* Extract the MAC address from the environment */ - switch (devnum) { - case 0: - s = "ethaddr"; - break; - - case 1: - s = "eth1addr"; - break; - - case 2: - s = "eth2addr"; - break; - - default: /* this should never happen */ - printf ("%s: Invalid device number %d\n", - __FUNCTION__, devnum); - return; - } - - temp = getenv_f(s, buf, sizeof (buf)); - s = (temp > 0) ? buf : NULL; - -#ifdef DEBUG - printf ("Setting MAC %d to %s\n", devnum, s); -#endif - for (x = 0; x < 6; ++x) { - dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - - DP (printf ("Allocating descriptor and buffer rings\n")); - - ethernet_private->p_rx_desc_area_base[0] = - (ETH_RX_DESC *) memalign (16, - RX_DESC_ALIGNED_SIZE * - MV64460_RX_QUEUE_SIZE + 1); - ethernet_private->p_tx_desc_area_base[0] = - (ETH_TX_DESC *) memalign (16, - TX_DESC_ALIGNED_SIZE * - MV64460_TX_QUEUE_SIZE + 1); - - ethernet_private->p_rx_buffer_base[0] = - (char *) memalign (16, - MV64460_RX_QUEUE_SIZE * - MV64460_TX_BUFFER_SIZE + 1); - ethernet_private->p_tx_buffer_base[0] = - (char *) memalign (16, - MV64460_RX_QUEUE_SIZE * - MV64460_TX_BUFFER_SIZE + 1); - -#ifdef DEBUG_MV_ETH - /* DEBUG OUTPUT prints adresses of globals */ - print_globals (dev); -#endif - eth_register (dev); - - } - DP (printf ("%s: exit\n", __FUNCTION__)); - -} - -/********************************************************************** - * mv64460_eth_open - * - * This function is called when openning the network device. The function - * should initialize all the hardware, initialize cyclic Rx/Tx - * descriptors chain and buffers and allocate an IRQ to the network - * device. - * - * Input : a pointer to the network device structure - * / / ronen - changed the output to match net/eth.c needs - * Output : nonzero of success , zero if fails. - * under construction - **********************************************************************/ - -int mv64460_eth_open (struct eth_device *dev) -{ - return (mv64460_eth_real_open (dev)); -} - -/* Helper function for mv64460_eth_open */ -static int mv64460_eth_real_open (struct eth_device *dev) -{ - - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - unsigned int port_num; - u32 phy_reg_data; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - /* ronen - when we update the MAC env params we only update dev->enetaddr - see ./net/eth.c eth_set_enetaddr() */ - memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); - - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Stop RX Queues */ - MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Clear the ethernet port interrupts */ - MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0); - MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); - - /* Unmask RX buffer and TX end interrupt */ - MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num), - INT_CAUSE_UNMASK_ALL); - - /* Unmask phy and link status changes interrupts */ - MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), - INT_CAUSE_UNMASK_ALL_EXT); - - /* Set phy address of the port */ - ethernet_private->port_phy_addr = 0x8 + port_num; - - /* Activate the DMA channels etc */ - eth_port_init (ethernet_private); - - - /* "Allocate" setup TX rings */ - - for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) { - unsigned int size; - - port_private->tx_ring_size[queue] = MV64460_TX_QUEUE_SIZE; - size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */ - ethernet_private->tx_desc_area_size[queue] = size; - - /* first clear desc area completely */ - memset ((void *) ethernet_private->p_tx_desc_area_base[queue], - 0, ethernet_private->tx_desc_area_size[queue]); - - /* initialize tx desc ring with low level driver */ - if (ether_init_tx_desc_ring - (ethernet_private, ETH_Q0, - port_private->tx_ring_size[queue], - MV64460_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , - (unsigned int) ethernet_private-> - p_tx_desc_area_base[queue], - (unsigned int) ethernet_private-> - p_tx_buffer_base[queue]) == false) - printf ("### Error initializing TX Ring\n"); - } - - /* "Allocate" setup RX rings */ - for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) { - unsigned int size; - - /* Meantime RX Ring are fixed - but must be configurable by user */ - port_private->rx_ring_size[queue] = MV64460_RX_QUEUE_SIZE; - size = (port_private->rx_ring_size[queue] * - RX_DESC_ALIGNED_SIZE); - ethernet_private->rx_desc_area_size[queue] = size; - - /* first clear desc area completely */ - memset ((void *) ethernet_private->p_rx_desc_area_base[queue], - 0, ethernet_private->rx_desc_area_size[queue]); - if ((ether_init_rx_desc_ring - (ethernet_private, ETH_Q0, - port_private->rx_ring_size[queue], - MV64460_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , - (unsigned int) ethernet_private-> - p_rx_desc_area_base[queue], - (unsigned int) ethernet_private-> - p_rx_buffer_base[queue])) == false) - printf ("### Error initializing RX Ring\n"); - } - - eth_port_start (ethernet_private); - - /* Set maximum receive buffer to 9700 bytes */ - MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num), - (0x5 << 17) | - (MV_REG_READ - (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num)) - & 0xfff1ffff)); - - /* - * Set ethernet MTU for leaky bucket mechanism to 0 - this will - * disable the leaky bucket mechanism . - */ - - MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0); - MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num)); - - /* Check Link status on phy */ - eth_port_read_smi_reg (port_num, 1, &phy_reg_data); - if (!(phy_reg_data & 0x20)) { - /* Reset PHY */ - if ((ethernet_phy_reset (port_num)) != true) { - printf ("$$ Warnning: No link on port %d \n", - port_num); - return 0; - } else { - eth_port_read_smi_reg (port_num, 1, &phy_reg_data); - if (!(phy_reg_data & 0x20)) { - printf ("### Error: Phy is not active\n"); - return 0; - } - } - } else { - mv64460_eth_print_phy_status (dev); - } - port_private->eth_running = MAGIC_ETH_RUNNING; - return 1; -} - - -static int mv64460_eth_free_tx_rings (struct eth_device *dev) -{ - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - unsigned int port_num; - volatile ETH_TX_DESC *p_tx_curr_desc; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Stop Tx Queues */ - MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Free TX rings */ - DP (printf ("Clearing previously allocated TX queues... ")); - for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) { - /* Free on TX rings */ - for (p_tx_curr_desc = - ethernet_private->p_tx_desc_area_base[queue]; - ((unsigned int) p_tx_curr_desc <= (unsigned int) - ethernet_private->p_tx_desc_area_base[queue] + - ethernet_private->tx_desc_area_size[queue]); - p_tx_curr_desc = - (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc + - TX_DESC_ALIGNED_SIZE)) { - /* this is inside for loop */ - if (p_tx_curr_desc->return_info != 0) { - p_tx_curr_desc->return_info = 0; - DP (printf ("freed\n")); - } - } - DP (printf ("Done\n")); - } - return 0; -} - -static int mv64460_eth_free_rx_rings (struct eth_device *dev) -{ - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - unsigned int port_num; - volatile ETH_RX_DESC *p_rx_curr_desc; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - - /* Stop RX Queues */ - MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Free RX rings */ - DP (printf ("Clearing previously allocated RX queues... ")); - for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) { - /* Free preallocated skb's on RX rings */ - for (p_rx_curr_desc = - ethernet_private->p_rx_desc_area_base[queue]; - (((unsigned int) p_rx_curr_desc < - ((unsigned int) ethernet_private-> - p_rx_desc_area_base[queue] + - ethernet_private->rx_desc_area_size[queue]))); - p_rx_curr_desc = - (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc + - RX_DESC_ALIGNED_SIZE)) { - if (p_rx_curr_desc->return_info != 0) { - p_rx_curr_desc->return_info = 0; - DP (printf ("freed\n")); - } - } - DP (printf ("Done\n")); - } - return 0; -} - -/********************************************************************** - * mv64460_eth_stop - * - * This function is used when closing the network device. - * It updates the hardware, - * release all memory that holds buffers and descriptors and release the IRQ. - * Input : a pointer to the device structure - * Output : zero if success , nonzero if fails - *********************************************************************/ - -int mv64460_eth_stop (struct eth_device *dev) -{ - /* Disable all gigE address decoder */ - MV_REG_WRITE (MV64460_ETH_BASE_ADDR_ENABLE_REG, 0x3f); - DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__)); - mv64460_eth_real_stop (dev); - - return 0; -}; - -/* Helper function for mv64460_eth_stop */ - -static int mv64460_eth_real_stop (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - unsigned int port_num; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - - mv64460_eth_free_tx_rings (dev); - mv64460_eth_free_rx_rings (dev); - - eth_port_reset (ethernet_private->port_num); - /* Disable ethernet port interrupts */ - MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0); - MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); - /* Mask RX buffer and TX end interrupt */ - MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num), 0); - /* Mask phy and link status changes interrupts */ - MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0); - MV_RESET_REG_BITS (MV64460_CPU_INTERRUPT0_MASK_HIGH, - BIT0 << port_num); - /* Print Network statistics */ -#ifndef UPDATE_STATS_BY_SOFTWARE - /* - * Print statistics (only if ethernet is running), - * then zero all the stats fields in memory - */ - if (port_private->eth_running == MAGIC_ETH_RUNNING) { - port_private->eth_running = 0; - mv64460_eth_print_stat (dev); - } - memset (port_private->stats, 0, sizeof (struct net_device_stats)); -#endif - DP (printf ("\nEthernet stopped ... \n")); - return 0; -} - - -/********************************************************************** - * mv64460_eth_start_xmit - * - * This function is queues a packet in the Tx descriptor for - * required port. - * - * Input : skb - a pointer to socket buffer - * dev - a pointer to the required port - * - * Output : zero upon success - **********************************************************************/ - -int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr, - int dataSize) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - PKT_INFO pkt_info; - ETH_FUNC_RET_STATUS status; - struct net_device_stats *stats; - ETH_FUNC_RET_STATUS release_result; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - - stats = port_private->stats; - - /* Update packet info data structure */ - pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */ - pkt_info.byte_cnt = dataSize; - pkt_info.buf_ptr = (unsigned int) dataPtr; - pkt_info.return_info = 0; - - status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info); - if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) { - printf ("Error on transmitting packet .."); - if (status == ETH_QUEUE_FULL) - printf ("ETH Queue is full. \n"); - if (status == ETH_QUEUE_LAST_RESOURCE) - printf ("ETH Queue: using last available resource. \n"); - goto error; - } - - /* Update statistics and start of transmittion time */ - stats->tx_bytes += dataSize; - stats->tx_packets++; - - /* Check if packet(s) is(are) transmitted correctly (release everything) */ - do { - release_result = - eth_tx_return_desc (ethernet_private, ETH_Q0, - &pkt_info); - switch (release_result) { - case ETH_OK: - DP (printf ("descriptor released\n")); - if (pkt_info.cmd_sts & BIT0) { - printf ("Error in TX\n"); - stats->tx_errors++; - - } - break; - case ETH_RETRY: - DP (printf ("transmission still in process\n")); - break; - - case ETH_ERROR: - printf ("routine can not access Tx desc ring\n"); - break; - - case ETH_END_OF_JOB: - DP (printf ("the routine has nothing to release\n")); - break; - default: /* should not happen */ - break; - } - } while (release_result == ETH_OK); - - - return 0; /* success */ - error: - return 1; /* Failed - higher layers will free the skb */ -} - -/********************************************************************** - * mv64460_eth_receive - * - * This function is forward packets that are received from the port's - * queues toward kernel core or FastRoute them to another interface. - * - * Input : dev - a pointer to the required interface - * max - maximum number to receive (0 means unlimted) - * - * Output : number of served packets - **********************************************************************/ - -int mv64460_eth_receive (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - PKT_INFO pkt_info; - struct net_device_stats *stats; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - stats = port_private->stats; - - while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) == - ETH_OK)) { - -#ifdef DEBUG_MV_ETH - if (pkt_info.byte_cnt != 0) { - printf ("%s: Received %d byte Packet @ 0x%x\n", - __FUNCTION__, pkt_info.byte_cnt, - pkt_info.buf_ptr); - } -#endif - /* Update statistics. Note byte count includes 4 byte CRC count */ - stats->rx_packets++; - stats->rx_bytes += pkt_info.byte_cnt; - - /* - * In case received a packet without first / last bits on OR the error - * summary bit is on, the packets needs to be dropeed. - */ - if (((pkt_info. - cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != - (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) - || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) { - stats->rx_dropped++; - - printf ("Received packet spread on multiple descriptors\n"); - - /* Is this caused by an error ? */ - if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) { - stats->rx_errors++; - } - - /* free these descriptors again without forwarding them to the higher layers */ - pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ - pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ - - if (eth_rx_return_buff - (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { - printf ("Error while returning the RX Desc to Ring\n"); - } else { - DP (printf ("RX Desc returned to Ring\n")); - } - /* /free these descriptors again */ - } else { - -/* !!! call higher layer processing */ -#ifdef DEBUG_MV_ETH - printf ("\nNow send it to upper layer protocols (NetReceive) ...\n"); -#endif - /* let the upper layer handle the packet */ - NetReceive ((uchar *) pkt_info.buf_ptr, - (int) pkt_info.byte_cnt); - -/* **************************************************************** */ -/* free descriptor */ - pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ - pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ - DP (printf - ("RX: pkt_info.buf_ptr = %x\n", - pkt_info.buf_ptr)); - if (eth_rx_return_buff - (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { - printf ("Error while returning the RX Desc to Ring\n"); - } else { - DP (printf ("RX Desc returned to Ring\n")); - } - -/* **************************************************************** */ - - } - } - mv64460_eth_get_stats (dev); /* update statistics */ - return 1; -} - -/********************************************************************** - * mv64460_eth_get_stats - * - * Returns a pointer to the interface statistics. - * - * Input : dev - a pointer to the required interface - * - * Output : a pointer to the interface's statistics - **********************************************************************/ - -static struct net_device_stats *mv64460_eth_get_stats (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - - mv64460_eth_update_stat (dev); - - return port_private->stats; -} - - -/********************************************************************** - * mv64460_eth_update_stat - * - * Update the statistics structure in the private data structure - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64460_eth_update_stat (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - struct net_device_stats *stats; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - stats = port_private->stats; - - /* These are false updates */ - stats->rx_packets += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_FRAMES_RECEIVED); - stats->tx_packets += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_FRAMES_SENT); - stats->rx_bytes += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_RECEIVED_LOW); - /* - * Ideally this should be as follows - - * - * stats->rx_bytes += stats->rx_bytes + - * ((unsigned long) ethReadMibCounter (ethernet_private->port_num , - * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32); - * - * But the unsigned long in PowerPC and MIPS are 32bit. So the next read - * is just a dummy read for proper work of the GigE port - */ - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH); - stats->tx_bytes += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_SENT_LOW); - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_SENT_HIGH); - stats->rx_errors += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_MAC_RECEIVE_ERROR); - - /* Rx dropped is for received packet with CRC error */ - stats->rx_dropped += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_BAD_CRC_EVENT); - stats->multicast += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_MULTICAST_FRAMES_RECEIVED); - stats->collisions += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_COLLISION) + - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_LATE_COLLISION); - /* detailed rx errors */ - stats->rx_length_errors += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_UNDERSIZE_RECEIVED) - + - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_OVERSIZE_RECEIVED); - /* detailed tx errors */ -} - -#ifndef UPDATE_STATS_BY_SOFTWARE -/********************************************************************** - * mv64460_eth_print_stat - * - * Update the statistics structure in the private data structure - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64460_eth_print_stat (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - struct net_device_stats *stats; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - stats = port_private->stats; - - /* These are false updates */ - printf ("\n### Network statistics: ###\n"); - printf ("--------------------------\n"); - printf (" Packets received: %ld\n", stats->rx_packets); - printf (" Packets send: %ld\n", stats->tx_packets); - printf (" Received bytes: %ld\n", stats->rx_bytes); - printf (" Send bytes: %ld\n", stats->tx_bytes); - if (stats->rx_errors != 0) - printf (" Rx Errors: %ld\n", - stats->rx_errors); - if (stats->rx_dropped != 0) - printf (" Rx dropped (CRC Errors): %ld\n", - stats->rx_dropped); - if (stats->multicast != 0) - printf (" Rx mulicast frames: %ld\n", - stats->multicast); - if (stats->collisions != 0) - printf (" No. of collisions: %ld\n", - stats->collisions); - if (stats->rx_length_errors != 0) - printf (" Rx length errors: %ld\n", - stats->rx_length_errors); -} -#endif - -/************************************************************************** - *network_start - Network Kick Off Routine UBoot - *Inputs : - *Outputs : - **************************************************************************/ - -bool db64460_eth_start (struct eth_device *dev) -{ - return (mv64460_eth_open (dev)); /* calls real open */ -} - -/************************************************************************* -************************************************************************** -************************************************************************** -* The second part is the low level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ -/* - * based on Linux code - * arch/powerpc/galileo/EVB64460/mv64460_eth.c - Driver for MV64460X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * SPDX-License-Identifier: GPL-2.0+ - */ - -/******************************************************************************** - * Marvell's Gigabit Ethernet controller low level driver - * - * DESCRIPTION: - * This file introduce low level API to Marvell's Gigabit Ethernet - * controller. This Gigabit Ethernet Controller driver API controls - * 1) Operations (i.e. port init, start, reset etc'). - * 2) Data flow (i.e. port send, receive etc'). - * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO - * struct. - * This struct includes user configuration information as well as - * driver internal data needed for its operations. - * - * Supported Features: - * - This low level driver is OS independent. Allocating memory for - * the descriptor rings and buffers are not within the scope of - * this driver. - * - The user is free from Rx/Tx queue managing. - * - This low level driver introduce functionality API that enable - * the to operate Marvell's Gigabit Ethernet Controller in a - * convenient way. - * - Simple Gigabit Ethernet port operation API. - * - Simple Gigabit Ethernet port data flow API. - * - Data flow and operation API support per queue functionality. - * - Support cached descriptors for better performance. - * - Enable access to all four DRAM banks and internal SRAM memory - * spaces. - * - PHY access and control API. - * - Port control register configuration API. - * - Full control over Unicast and Multicast MAC configurations. - * - * Operation flow: - * - * Initialization phase - * This phase complete the initialization of the ETH_PORT_INFO - * struct. - * User information regarding port configuration has to be set - * prior to calling the port initialization routine. For example, - * the user has to assign the port_phy_addr field which is board - * depended parameter. - * In this phase any port Tx/Rx activity is halted, MIB counters - * are cleared, PHY address is set according to user parameter and - * access to DRAM and internal SRAM memory spaces. - * - * Driver ring initialization - * Allocating memory for the descriptor rings and buffers is not - * within the scope of this driver. Thus, the user is required to - * allocate memory for the descriptors ring and buffers. Those - * memory parameters are used by the Rx and Tx ring initialization - * routines in order to curve the descriptor linked list in a form - * of a ring. - * Note: Pay special attention to alignment issues when using - * cached descriptors/buffers. In this phase the driver store - * information in the ETH_PORT_INFO struct regarding each queue - * ring. - * - * Driver start - * This phase prepares the Ethernet port for Rx and Tx activity. - * It uses the information stored in the ETH_PORT_INFO struct to - * initialize the various port registers. - * - * Data flow: - * All packet references to/from the driver are done using PKT_INFO - * struct. - * This struct is a unified struct used with Rx and Tx operations. - * This way the user is not required to be familiar with neither - * Tx nor Rx descriptors structures. - * The driver's descriptors rings are management by indexes. - * Those indexes controls the ring resources and used to indicate - * a SW resource error: - * 'current' - * This index points to the current available resource for use. For - * example in Rx process this index will point to the descriptor - * that will be passed to the user upon calling the receive routine. - * In Tx process, this index will point to the descriptor - * that will be assigned with the user packet info and transmitted. - * 'used' - * This index points to the descriptor that need to restore its - * resources. For example in Rx process, using the Rx buffer return - * API will attach the buffer returned in packet info to the - * descriptor pointed by 'used'. In Tx process, using the Tx - * descriptor return will merely return the user packet info with - * the command status of the transmitted buffer pointed by the - * 'used' index. Nevertheless, it is essential to use this routine - * to update the 'used' index. - * 'first' - * This index supports Tx Scatter-Gather. It points to the first - * descriptor of a packet assembled of multiple buffers. For example - * when in middle of Such packet we have a Tx resource error the - * 'curr' index get the value of 'first' to indicate that the ring - * returned to its state before trying to transmit this packet. - * - * Receive operation: - * The eth_port_receive API set the packet information struct, - * passed by the caller, with received information from the - * 'current' SDMA descriptor. - * It is the user responsibility to return this resource back - * to the Rx descriptor ring to enable the reuse of this source. - * Return Rx resource is done using the eth_rx_return_buff API. - * - * Transmit operation: - * The eth_port_send API supports Scatter-Gather which enables to - * send a packet spanned over multiple buffers. This means that - * for each packet info structure given by the user and put into - * the Tx descriptors ring, will be transmitted only if the 'LAST' - * bit will be set in the packet info command status field. This - * API also consider restriction regarding buffer alignments and - * sizes. - * The user must return a Tx resource after ensuring the buffer - * has been transmitted to enable the Tx ring indexes to update. - * - * BOARD LAYOUT - * This device is on-board. No jumper diagram is necessary. - * - * EXTERNAL INTERFACE - * - * Prior to calling the initialization routine eth_port_init() the user - * must set the following fields under ETH_PORT_INFO struct: - * port_num User Ethernet port number. - * port_phy_addr User PHY address of Ethernet port. - * port_mac_addr[6] User defined port MAC address. - * port_config User port configuration value. - * port_config_extend User port config extend value. - * port_sdma_config User port SDMA config value. - * port_serial_control User port serial control value. - * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr. - * *port_private User scratch pad for user specific data structures. - * - * This driver introduce a set of default values: - * PORT_CONFIG_VALUE Default port configuration value - * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value - * PORT_SDMA_CONFIG_VALUE Default sdma control value - * PORT_SERIAL_CONTROL_VALUE Default port serial control value - * - * This driver data flow is done using the PKT_INFO struct which is - * a unified struct for Rx and Tx operations: - * byte_cnt Tx/Rx descriptor buffer byte count. - * l4i_chk CPU provided TCP Checksum. For Tx operation only. - * cmd_sts Tx/Rx descriptor command status. - * buf_ptr Tx/Rx descriptor buffer pointer. - * return_info Tx/Rx user resource return information. - * - * - * EXTERNAL SUPPORT REQUIREMENTS - * - * This driver requires the following external support: - * - * D_CACHE_FLUSH_LINE (address, address offset) - * - * This macro applies assembly code to flush and invalidate cache - * line. - * address - address base. - * address offset - address offset - * - * - * CPU_PIPE_FLUSH - * - * This macro applies assembly code to flush the CPU pipeline. - * - *******************************************************************************/ -/* includes */ - -/* defines */ -/* SDMA command macros */ -#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \ - MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue)) - -#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \ - MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\ - (1 << (8 + tx_queue))) - -#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \ -MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue)) - -#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \ -MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue))) - -#define CURR_RFD_GET(p_curr_desc, queue) \ - ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue]) - -#define CURR_RFD_SET(p_curr_desc, queue) \ - (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc)) - -#define USED_RFD_GET(p_used_desc, queue) \ - ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue]) - -#define USED_RFD_SET(p_used_desc, queue)\ -(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc)) - - -#define CURR_TFD_GET(p_curr_desc, queue) \ - ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue]) - -#define CURR_TFD_SET(p_curr_desc, queue) \ - (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc)) - -#define USED_TFD_GET(p_used_desc, queue) \ - ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue]) - -#define USED_TFD_SET(p_used_desc, queue) \ - (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc)) - -#define FIRST_TFD_GET(p_first_desc, queue) \ - ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue]) - -#define FIRST_TFD_SET(p_first_desc, queue) \ - (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc)) - - -/* Macros that save access to desc in order to find next desc pointer */ -#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) - -#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) - -#define LINK_UP_TIMEOUT 100000 -#define PHY_BUSY_TIMEOUT 10000000 - -/* locals */ - -/* PHY routines */ -static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr); -static int ethernet_phy_get (ETH_PORT eth_port_num); - -/* Ethernet Port routines */ -static void eth_set_access_control (ETH_PORT eth_port_num, - ETH_WIN_PARAM * param); -static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble, - ETH_QUEUE queue, int option); -#if 0 /* FIXME */ -static bool eth_port_smc_addr (ETH_PORT eth_port_num, - unsigned char mc_byte, - ETH_QUEUE queue, int option); -static bool eth_port_omc_addr (ETH_PORT eth_port_num, - unsigned char crc8, - ETH_QUEUE queue, int option); -#endif - -static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, - int byte_count); - -void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl); - - -typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK; -u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank) -{ - u32 result = 0; - u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE); - - if (enable & (1 << bank)) - return 0; - if (bank == BANK0) - result = MV_REG_READ (MV64460_CS_0_BASE_ADDR); - if (bank == BANK1) - result = MV_REG_READ (MV64460_CS_1_BASE_ADDR); - if (bank == BANK2) - result = MV_REG_READ (MV64460_CS_2_BASE_ADDR); - if (bank == BANK3) - result = MV_REG_READ (MV64460_CS_3_BASE_ADDR); - result &= 0x0000ffff; - result = result << 16; - return result; -} - -u32 mv_get_dram_bank_size (MEMORY_BANK bank) -{ - u32 result = 0; - u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE); - - if (enable & (1 << bank)) - return 0; - if (bank == BANK0) - result = MV_REG_READ (MV64460_CS_0_SIZE); - if (bank == BANK1) - result = MV_REG_READ (MV64460_CS_1_SIZE); - if (bank == BANK2) - result = MV_REG_READ (MV64460_CS_2_SIZE); - if (bank == BANK3) - result = MV_REG_READ (MV64460_CS_3_SIZE); - result += 1; - result &= 0x0000ffff; - result = result << 16; - return result; -} - -u32 mv_get_internal_sram_base (void) -{ - u32 result; - - result = MV_REG_READ (MV64460_INTEGRATED_SRAM_BASE_ADDR); - result &= 0x0000ffff; - result = result << 16; - return result; -} - -/******************************************************************************* -* eth_port_init - Initialize the Ethernet port driver -* -* DESCRIPTION: -* This function prepares the ethernet port to start its activity: -* 1) Completes the ethernet port driver struct initialization toward port -* start routine. -* 2) Resets the device to a quiescent state in case of warm reboot. -* 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. -* 4) Clean MAC tables. The reset status of those tables is unknown. -* 5) Set PHY address. -* Note: Call this routine prior to eth_port_start routine and after setting -* user values in the user fields of Ethernet port control struct (i.e. -* port_phy_addr). -* -* INPUT: -* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct -* -* OUTPUT: -* See description. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl) -{ - int queue; - ETH_WIN_PARAM win_param; - - p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE; - p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE; - p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE; - p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE; - - p_eth_port_ctrl->port_rx_queue_command = 0; - p_eth_port_ctrl->port_tx_queue_command = 0; - - /* Zero out SW structs */ - for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { - CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); - USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); - p_eth_port_ctrl->rx_resource_err[queue] = false; - } - - for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { - CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - p_eth_port_ctrl->tx_resource_err[queue] = false; - } - - eth_port_reset (p_eth_port_ctrl->port_num); - - /* Set access parameters for DRAM bank 0 */ - win_param.win = ETH_WIN0; /* Use Ethernet window 0 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK0); - win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 1 */ - win_param.win = ETH_WIN1; /* Use Ethernet window 1 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK1); - win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 2 */ - win_param.win = ETH_WIN2; /* Use Ethernet window 2 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK2); - win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 3 */ - win_param.win = ETH_WIN3; /* Use Ethernet window 3 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK3); - win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for Internal SRAM */ - win_param.win = ETH_WIN4; /* Use Ethernet window 0 */ - win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */ - win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0; - win_param.high_addr = 0; - win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */ - win_param.size = MV64460_INTERNAL_SRAM_SIZE; /* Get bank size */ - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - eth_port_init_mac_tables (p_eth_port_ctrl->port_num); - - ethernet_phy_set (p_eth_port_ctrl->port_num, - p_eth_port_ctrl->port_phy_addr); - - return; - -} - -/******************************************************************************* -* eth_port_start - Start the Ethernet port activity. -* -* DESCRIPTION: -* This routine prepares the Ethernet port for Rx and Tx activity: -* 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that -* has been initialized a descriptor's ring (using ether_init_tx_desc_ring -* for Tx and ether_init_rx_desc_ring for Rx) -* 2. Initialize and enable the Ethernet configuration port by writing to -* the port's configuration and command registers. -* 3. Initialize and enable the SDMA by writing to the SDMA's -* configuration and command registers. -* After completing these steps, the ethernet port SDMA can starts to -* perform Rx and Tx activities. -* -* Note: Each Rx and Tx queue descriptor's list must be initialized prior -* to calling this function (use ether_init_tx_desc_ring for Tx queues and -* ether_init_rx_desc_ring for Rx queues). -* -* INPUT: -* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct -* -* OUTPUT: -* Ethernet port is ready to receive and transmit. -* -* RETURN: -* false if the port PHY is not up. -* true otherwise. -* -*******************************************************************************/ -static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl) -{ - int queue; - volatile ETH_TX_DESC *p_tx_curr_desc; - volatile ETH_RX_DESC *p_rx_curr_desc; - unsigned int phy_reg_data; - ETH_PORT eth_port_num = p_eth_port_ctrl->port_num; - - - /* Assignment of Tx CTRP of given queue */ - for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { - CURR_TFD_GET (p_tx_curr_desc, queue); - MV_REG_WRITE ((MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0 - (eth_port_num) - + (4 * queue)), - ((unsigned int) p_tx_curr_desc)); - - } - - /* Assignment of Rx CRDP of given queue */ - for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { - CURR_RFD_GET (p_rx_curr_desc, queue); - MV_REG_WRITE ((MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0 - (eth_port_num) - + (4 * queue)), - ((unsigned int) p_rx_curr_desc)); - - if (p_rx_curr_desc != NULL) - /* Add the assigned Ethernet address to the port's address table */ - eth_port_uc_addr_set (p_eth_port_ctrl->port_num, - p_eth_port_ctrl->port_mac_addr, - queue); - } - - /* Assign port configuration and command. */ - MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num), - p_eth_port_ctrl->port_config); - - MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), - p_eth_port_ctrl->port_config_extend); - - MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - p_eth_port_ctrl->port_serial_control); - - MV_SET_REG_BITS (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - ETH_SERIAL_PORT_ENABLE); - - /* Assign port SDMA configuration */ - MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num), - p_eth_port_ctrl->port_sdma_config); - - MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT - (eth_port_num), 0x3fffffff); - MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG - (eth_port_num), 0x03fffcff); - /* Turn off the port/queue bandwidth limitation */ - MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0); - - /* Enable port Rx. */ - MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num), - p_eth_port_ctrl->port_rx_queue_command); - - /* Check if link is up */ - eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); - - if (!(phy_reg_data & 0x20)) - return false; - - return true; -} - -/******************************************************************************* -* eth_port_uc_addr_set - This function Set the port Unicast address. -* -* DESCRIPTION: -* This function Set the port Ethernet MAC address. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* char * p_addr Address to be set -* ETH_QUEUE queue Rx queue number for this MAC address. -* -* OUTPUT: -* Set MAC address low and high registers. also calls eth_port_uc_addr() -* To set the unicast table with the proper information. -* -* RETURN: -* N/A. -* -*******************************************************************************/ -static void eth_port_uc_addr_set (ETH_PORT eth_port_num, - unsigned char *p_addr, ETH_QUEUE queue) -{ - unsigned int mac_h; - unsigned int mac_l; - - mac_l = (p_addr[4] << 8) | (p_addr[5]); - mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | - (p_addr[2] << 8) | (p_addr[3] << 0); - - MV_REG_WRITE (MV64460_ETH_MAC_ADDR_LOW (eth_port_num), mac_l); - MV_REG_WRITE (MV64460_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h); - - /* Accept frames of this address */ - eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR); - - return; -} - -/******************************************************************************* -* eth_port_uc_addr - This function Set the port unicast address table -* -* DESCRIPTION: -* This function locates the proper entry in the Unicast table for the -* specified MAC nibble and sets its properties according to function -* parameters. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char uc_nibble Unicast MAC Address last nibble. -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* This function add/removes MAC addresses from the port unicast address -* table. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_uc_addr (ETH_PORT eth_port_num, - unsigned char uc_nibble, - ETH_QUEUE queue, int option) -{ - unsigned int unicast_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the Unicast table entry */ - uc_nibble = (0xf & uc_nibble); - tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */ - reg_offset = uc_nibble % 4; /* Entry offset within the above register */ - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified unicast DA table entry */ - unicast_reg = - MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset)); - - unicast_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset), unicast_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at unicast DA filter table entry */ - unicast_reg = - MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset)); - - unicast_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset), unicast_reg); - - break; - - default: - return false; - } - return true; -} - -#if 0 /* FIXME */ -/******************************************************************************* -* eth_port_mc_addr - Multicast address settings. -* -* DESCRIPTION: -* This API controls the MV device MAC multicast support. -* The MV device supports multicast using two tables: -* 1) Special Multicast Table for MAC addresses of the form -* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). -* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -* Table entries in the DA-Filter table. -* In this case, the function calls eth_port_smc_addr() routine to set the -* Special Multicast Table. -* 2) Other Multicast Table for multicast of another type. A CRC-8bit -* is used as an index to the Other Multicast Table entries in the -* DA-Filter table. -* In this case, the function calculates the CRC-8bit value and calls -* eth_port_omc_addr() routine to set the Other Multicast Table. -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char *p_addr Unicast MAC Address. -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if add_address_table_entry( ) failed. -* -*******************************************************************************/ -static void eth_port_mc_addr (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue, int option) -{ - unsigned int mac_h; - unsigned int mac_l; - unsigned char crc_result = 0; - int mac_array[48]; - int crc[8]; - int i; - - - if ((p_addr[0] == 0x01) && - (p_addr[1] == 0x00) && - (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) - - eth_port_smc_addr (eth_port_num, p_addr[5], queue, option); - else { - /* Calculate CRC-8 out of the given address */ - mac_h = (p_addr[0] << 8) | (p_addr[1]); - mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) | - (p_addr[4] << 8) | (p_addr[5] << 0); - - for (i = 0; i < 32; i++) - mac_array[i] = (mac_l >> i) & 0x1; - for (i = 32; i < 48; i++) - mac_array[i] = (mac_h >> (i - 32)) & 0x1; - - - crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ - mac_array[39] ^ mac_array[35] ^ mac_array[34] ^ - mac_array[31] ^ mac_array[30] ^ mac_array[28] ^ - mac_array[23] ^ mac_array[21] ^ mac_array[19] ^ - mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ - mac_array[12] ^ mac_array[8] ^ mac_array[7] ^ - mac_array[6] ^ mac_array[0]; - - crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[41] ^ mac_array[39] ^ - mac_array[36] ^ mac_array[34] ^ mac_array[32] ^ - mac_array[30] ^ mac_array[29] ^ mac_array[28] ^ - mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ - mac_array[21] ^ mac_array[20] ^ mac_array[18] ^ - mac_array[17] ^ mac_array[16] ^ mac_array[15] ^ - mac_array[14] ^ mac_array[13] ^ mac_array[12] ^ - mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ - mac_array[0]; - - crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[42] ^ mac_array[39] ^ - mac_array[37] ^ mac_array[34] ^ mac_array[33] ^ - mac_array[29] ^ mac_array[28] ^ mac_array[25] ^ - mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ - mac_array[15] ^ mac_array[13] ^ mac_array[12] ^ - mac_array[10] ^ mac_array[8] ^ mac_array[6] ^ - mac_array[2] ^ mac_array[1] ^ mac_array[0]; - - crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[40] ^ mac_array[38] ^ - mac_array[35] ^ mac_array[34] ^ mac_array[30] ^ - mac_array[29] ^ mac_array[26] ^ mac_array[25] ^ - mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ - mac_array[14] ^ mac_array[13] ^ mac_array[11] ^ - mac_array[9] ^ mac_array[7] ^ mac_array[3] ^ - mac_array[2] ^ mac_array[1]; - - crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ - mac_array[35] ^ mac_array[31] ^ mac_array[30] ^ - mac_array[27] ^ mac_array[26] ^ mac_array[24] ^ - mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ - mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ - mac_array[8] ^ mac_array[4] ^ mac_array[3] ^ - mac_array[2]; - - crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ - mac_array[42] ^ mac_array[40] ^ mac_array[37] ^ - mac_array[36] ^ mac_array[32] ^ mac_array[31] ^ - mac_array[28] ^ mac_array[27] ^ mac_array[25] ^ - mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ - mac_array[15] ^ mac_array[13] ^ mac_array[11] ^ - mac_array[9] ^ mac_array[5] ^ mac_array[4] ^ - mac_array[3]; - - crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ - mac_array[41] ^ mac_array[38] ^ mac_array[37] ^ - mac_array[33] ^ mac_array[32] ^ mac_array[29] ^ - mac_array[28] ^ mac_array[26] ^ mac_array[21] ^ - mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ - mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ - mac_array[6] ^ mac_array[5] ^ mac_array[4]; - - crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ - mac_array[39] ^ mac_array[38] ^ mac_array[34] ^ - mac_array[33] ^ mac_array[30] ^ mac_array[29] ^ - mac_array[27] ^ mac_array[22] ^ mac_array[20] ^ - mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ - mac_array[13] ^ mac_array[11] ^ mac_array[7] ^ - mac_array[6] ^ mac_array[5]; - - for (i = 0; i < 8; i++) - crc_result = crc_result | (crc[i] << i); - - eth_port_omc_addr (eth_port_num, crc_result, queue, option); - } - return; -} - -/******************************************************************************* -* eth_port_smc_addr - Special Multicast address settings. -* -* DESCRIPTION: -* This routine controls the MV device special MAC multicast support. -* The Special Multicast Table for MAC addresses supports MAC of the form -* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). -* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -* Table entries in the DA-Filter table. -* This function set the Special Multicast Table appropriate entry -* according to the argument given. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits). -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_smc_addr (ETH_PORT eth_port_num, - unsigned char mc_byte, - ETH_QUEUE queue, int option) -{ - unsigned int smc_table_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the SMC table entry */ - tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */ - reg_offset = mc_byte % 4; /* Entry offset within the above register */ - queue &= 0x7; - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified Special DA table entry */ - smc_table_reg = - MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - smc_table_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at specified Special DA table entry */ - smc_table_reg = - MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - smc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); - break; - - default: - return false; - } - return true; -} - -/******************************************************************************* -* eth_port_omc_addr - Multicast address settings. -* -* DESCRIPTION: -* This routine controls the MV device Other MAC multicast support. -* The Other Multicast Table is used for multicast of another type. -* A CRC-8bit is used as an index to the Other Multicast Table entries -* in the DA-Filter table. -* The function gets the CRC-8bit value from the calling routine and -* set the Other Multicast Table appropriate entry according to the -* CRC-8 argument given. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_omc_addr (ETH_PORT eth_port_num, - unsigned char crc8, - ETH_QUEUE queue, int option) -{ - unsigned int omc_table_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the OMC table entry */ - tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ - reg_offset = crc8 % 4; /* Entry offset within the above register */ - queue &= 0x7; - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified Other DA table entry */ - omc_table_reg = - MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - omc_table_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at specified Other DA table entry */ - omc_table_reg = - MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - omc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); - break; - - default: - return false; - } - return true; -} -#endif - -/******************************************************************************* -* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables -* -* DESCRIPTION: -* Go through all the DA filter tables (Unicast, Special Multicast & Other -* Multicast) and set each entry to 0. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* Multicast and Unicast packets are rejected. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void eth_port_init_mac_tables (ETH_PORT eth_port_num) -{ - int table_index; - - /* Clear DA filter unicast table (Ex_dFUT) */ - for (table_index = 0; table_index <= 0xC; table_index += 4) - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) + table_index), 0); - - for (table_index = 0; table_index <= 0xFC; table_index += 4) { - /* Clear DA filter special multicast table (Ex_dFSMT) */ - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); - /* Clear DA filter other multicast table (Ex_dFOMT) */ - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); - } -} - -/******************************************************************************* -* eth_clear_mib_counters - Clear all MIB counters -* -* DESCRIPTION: -* This function clears all MIB counters of a specific ethernet port. -* A read from the MIB counter will reset the counter. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* After reading all MIB counters, the counters resets. -* -* RETURN: -* MIB counter value. -* -*******************************************************************************/ -static void eth_clear_mib_counters (ETH_PORT eth_port_num) -{ - int i; - - /* Perform dummy reads from MIB counters */ - for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; - i += 4) - MV_REG_READ((MV64460_ETH_MIB_COUNTERS_BASE(eth_port_num) + i)); - - return; -} - -/******************************************************************************* -* eth_read_mib_counter - Read a MIB counter -* -* DESCRIPTION: -* This function reads a MIB counter of a specific ethernet port. -* NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the -* following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH -* register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and -* ETH_MIB_GOOD_OCTETS_SENT_HIGH -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros). -* -* OUTPUT: -* After reading the MIB counter, the counter resets. -* -* RETURN: -* MIB counter value. -* -*******************************************************************************/ -unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, - unsigned int mib_offset) -{ - return (MV_REG_READ (MV64460_ETH_MIB_COUNTERS_BASE (eth_port_num) - + mib_offset)); -} - -/******************************************************************************* -* ethernet_phy_set - Set the ethernet port PHY address. -* -* DESCRIPTION: -* This routine set the ethernet port PHY address according to given -* parameter. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* Set PHY Address Register with given PHY address parameter. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr) -{ - unsigned int reg_data; - - reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG); - - reg_data &= ~(0x1F << (5 * eth_port_num)); - reg_data |= (phy_addr << (5 * eth_port_num)); - - MV_REG_WRITE (MV64460_ETH_PHY_ADDR_REG, reg_data); - - return; -} - -/******************************************************************************* - * ethernet_phy_get - Get the ethernet port PHY address. - * - * DESCRIPTION: - * This routine returns the given ethernet port PHY address. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * None. - * - * RETURN: - * PHY address. - * - *******************************************************************************/ -static int ethernet_phy_get (ETH_PORT eth_port_num) -{ - unsigned int reg_data; - - reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG); - - return ((reg_data >> (5 * eth_port_num)) & 0x1f); -} - -/******************************************************************************* - * ethernet_phy_reset - Reset Ethernet port PHY. - * - * DESCRIPTION: - * This routine utilize the SMI interface to reset the ethernet port PHY. - * The routine waits until the link is up again or link up is timeout. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * The ethernet port PHY renew its link. - * - * RETURN: - * None. - * -*******************************************************************************/ -static bool ethernet_phy_reset (ETH_PORT eth_port_num) -{ - unsigned int time_out = 50; - unsigned int phy_reg_data; - - /* Reset the PHY */ - eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data); - phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */ - eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data); - - /* Poll on the PHY LINK */ - do { - eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); - - if (time_out-- == 0) - return false; - } - while (!(phy_reg_data & 0x20)); - - return true; -} - -/******************************************************************************* - * eth_port_reset - Reset Ethernet port - * - * DESCRIPTION: - * This routine resets the chip by aborting any SDMA engine activity and - * clearing the MIB counters. The Receiver and the Transmit unit are in - * idle state after this command is performed and the port is disabled. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * Channel activity is halted. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_port_reset (ETH_PORT eth_port_num) -{ - unsigned int reg_data; - - /* Stop Tx port activity. Check port Tx activity. */ - reg_data = - MV_REG_READ (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num)); - - if (reg_data & 0xFF) { - /* Issue stop command for active channels only */ - MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num), (reg_data << 8)); - - /* Wait for all Tx activity to terminate. */ - do { - /* Check port cause register that all Tx queues are stopped */ - reg_data = - MV_REG_READ - (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num)); - } - while (reg_data & 0xFF); - } - - /* Stop Rx port activity. Check port Rx activity. */ - reg_data = - MV_REG_READ (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num)); - - if (reg_data & 0xFF) { - /* Issue stop command for active channels only */ - MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num), (reg_data << 8)); - - /* Wait for all Rx activity to terminate. */ - do { - /* Check port cause register that all Rx queues are stopped */ - reg_data = - MV_REG_READ - (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num)); - } - while (reg_data & 0xFF); - } - - - /* Clear all MIB counters */ - eth_clear_mib_counters (eth_port_num); - - /* Reset the Enable bit in the Configuration Register */ - reg_data = - MV_REG_READ (MV64460_ETH_PORT_SERIAL_CONTROL_REG - (eth_port_num)); - reg_data &= ~ETH_SERIAL_PORT_ENABLE; - MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - reg_data); - - return; -} - -#if 0 /* Not needed here */ -/******************************************************************************* - * ethernet_set_config_reg - Set specified bits in configuration register. - * - * DESCRIPTION: - * This function sets specified bits in the given ethernet - * configuration register. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int value 32 bit value. - * - * OUTPUT: - * The set bits in the value parameter are set in the configuration - * register. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void ethernet_set_config_reg (ETH_PORT eth_port_num, - unsigned int value) -{ - unsigned int eth_config_reg; - - eth_config_reg = - MV_REG_READ (MV64460_ETH_PORT_CONFIG_REG (eth_port_num)); - eth_config_reg |= value; - MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num), - eth_config_reg); - - return; -} -#endif - -#if 0 /* FIXME */ -/******************************************************************************* - * ethernet_reset_config_reg - Reset specified bits in configuration register. - * - * DESCRIPTION: - * This function resets specified bits in the given Ethernet - * configuration register. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int value 32 bit value. - * - * OUTPUT: - * The set bits in the value parameter are reset in the configuration - * register. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void ethernet_reset_config_reg (ETH_PORT eth_port_num, - unsigned int value) -{ - unsigned int eth_config_reg; - - eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG - (eth_port_num)); - eth_config_reg &= ~value; - MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), - eth_config_reg); - - return; -} -#endif - -#if 0 /* Not needed here */ -/******************************************************************************* - * ethernet_get_config_reg - Get the port configuration register - * - * DESCRIPTION: - * This function returns the configuration register value of the given - * ethernet port. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * None. - * - * RETURN: - * Port configuration register value. - * - *******************************************************************************/ -static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num) -{ - unsigned int eth_config_reg; - - eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG - (eth_port_num)); - return eth_config_reg; -} - -#endif - -/******************************************************************************* - * eth_port_read_smi_reg - Read PHY registers - * - * DESCRIPTION: - * This routine utilize the SMI interface to interact with the PHY in - * order to perform PHY register read. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int phy_reg PHY register address offset. - * unsigned int *value Register value buffer. - * - * OUTPUT: - * Write the value of a specified PHY register into given buffer. - * - * RETURN: - * false if the PHY is busy or read data is not in valid state. - * true otherwise. - * - *******************************************************************************/ -static bool eth_port_read_smi_reg (ETH_PORT eth_port_num, - unsigned int phy_reg, unsigned int *value) -{ - unsigned int reg_value; - unsigned int time_out = PHY_BUSY_TIMEOUT; - int phy_addr; - - phy_addr = ethernet_phy_get (eth_port_num); -/* printf(" Phy-Port %d has addess %d \n",eth_port_num, phy_addr );*/ - - /* first check that it is not busy */ - do { - reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while (reg_value & ETH_SMI_BUSY); - - /* not busy */ - - MV_REG_WRITE (MV64460_ETH_SMI_REG, - (phy_addr << 16) | (phy_reg << 21) | - ETH_SMI_OPCODE_READ); - - time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */ - - do { - reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */ - - /* Wait for the data to update in the SMI register */ -#define PHY_UPDATE_TIMEOUT 10000 - for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++); - - reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); - - *value = reg_value & 0xffff; - - return true; -} - -/******************************************************************************* - * eth_port_write_smi_reg - Write to PHY registers - * - * DESCRIPTION: - * This routine utilize the SMI interface to interact with the PHY in - * order to perform writes to PHY registers. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int phy_reg PHY register address offset. - * unsigned int value Register value. - * - * OUTPUT: - * Write the given value to the specified PHY register. - * - * RETURN: - * false if the PHY is busy. - * true otherwise. - * - *******************************************************************************/ -static bool eth_port_write_smi_reg (ETH_PORT eth_port_num, - unsigned int phy_reg, unsigned int value) -{ - unsigned int reg_value; - unsigned int time_out = PHY_BUSY_TIMEOUT; - int phy_addr; - - phy_addr = ethernet_phy_get (eth_port_num); - - /* first check that it is not busy */ - do { - reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while (reg_value & ETH_SMI_BUSY); - - /* not busy */ - MV_REG_WRITE (MV64460_ETH_SMI_REG, - (phy_addr << 16) | (phy_reg << 21) | - ETH_SMI_OPCODE_WRITE | (value & 0xffff)); - return true; -} - -/******************************************************************************* - * eth_set_access_control - Config address decode parameters for Ethernet unit - * - * DESCRIPTION: - * This function configures the address decode parameters for the Gigabit - * Ethernet Controller according the given parameters struct. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * ETH_WIN_PARAM *param Address decode parameter struct. - * - * OUTPUT: - * An access window is opened using the given access parameters. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_set_access_control (ETH_PORT eth_port_num, - ETH_WIN_PARAM * param) -{ - unsigned int access_prot_reg; - - /* Set access control register */ - access_prot_reg = MV_REG_READ (MV64460_ETH_ACCESS_PROTECTION_REG - (eth_port_num)); - access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */ - access_prot_reg |= (param->access_ctrl << (param->win * 2)); - MV_REG_WRITE (MV64460_ETH_ACCESS_PROTECTION_REG (eth_port_num), - access_prot_reg); - - /* Set window Size reg (SR) */ - MV_REG_WRITE ((MV64460_ETH_SIZE_REG_0 + - (ETH_SIZE_REG_GAP * param->win)), - (((param->size / 0x10000) - 1) << 16)); - - /* Set window Base address reg (BA) */ - MV_REG_WRITE ((MV64460_ETH_BAR_0 + (ETH_BAR_GAP * param->win)), - (param->target | param->attributes | param->base_addr)); - /* High address remap reg (HARR) */ - if (param->win < 4) - MV_REG_WRITE ((MV64460_ETH_HIGH_ADDR_REMAP_REG_0 + - (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)), - param->high_addr); - - /* Base address enable reg (BARER) */ - if (param->enable == 1) - MV_RESET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG, - (1 << param->win)); - else - MV_SET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG, - (1 << param->win)); -} - -/******************************************************************************* - * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. - * - * DESCRIPTION: - * This function prepares a Rx chained list of descriptors and packet - * buffers in a form of a ring. The routine must be called after port - * initialization routine and before port start routine. - * The Ethernet SDMA engine uses CPU bus addresses to access the various - * devices in the system (i.e. DRAM). This function uses the ethernet - * struct 'virtual to physical' routine (set by the user) to set the ring - * with physical addresses. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * int rx_desc_num Number of Rx descriptors - * int rx_buff_size Size of Rx buffer - * unsigned int rx_desc_base_addr Rx descriptors memory area base addr. - * unsigned int rx_buff_base_addr Rx buffer memory area base addr. - * - * OUTPUT: - * The routine updates the Ethernet port control struct with information - * regarding the Rx descriptors and buffers. - * - * RETURN: - * false if the given descriptors memory area is not aligned according to - * Ethernet SDMA specifications. - * true otherwise. - * - *******************************************************************************/ -static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE rx_queue, - int rx_desc_num, - int rx_buff_size, - unsigned int rx_desc_base_addr, - unsigned int rx_buff_base_addr) -{ - ETH_RX_DESC *p_rx_desc; - ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */ - unsigned int buffer_addr; - int ix; /* a counter */ - - - p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr; - p_rx_prev_desc = p_rx_desc; - buffer_addr = rx_buff_base_addr; - - /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ - if (rx_buff_base_addr & 0xF) - return false; - - /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */ - if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE)) - return false; - - /* Rx buffers must be 64-bit aligned. */ - if ((rx_buff_base_addr + rx_buff_size) & 0x7) - return false; - - /* initialize the Rx descriptors ring */ - for (ix = 0; ix < rx_desc_num; ix++) { - p_rx_desc->buf_size = rx_buff_size; - p_rx_desc->byte_cnt = 0x0000; - p_rx_desc->cmd_sts = - ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; - p_rx_desc->next_desc_ptr = - ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE; - p_rx_desc->buf_ptr = buffer_addr; - p_rx_desc->return_info = 0x00000000; - D_CACHE_FLUSH_LINE (p_rx_desc, 0); - buffer_addr += rx_buff_size; - p_rx_prev_desc = p_rx_desc; - p_rx_desc = (ETH_RX_DESC *) - ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE); - } - - /* Closing Rx descriptors ring */ - p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr); - D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0); - - /* Save Rx desc pointer to driver struct. */ - CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); - USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); - - p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] = - (ETH_RX_DESC *) rx_desc_base_addr; - p_eth_port_ctrl->rx_desc_area_size[rx_queue] = - rx_desc_num * RX_DESC_ALIGNED_SIZE; - - p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue); - - return true; -} - -/******************************************************************************* - * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. - * - * DESCRIPTION: - * This function prepares a Tx chained list of descriptors and packet - * buffers in a form of a ring. The routine must be called after port - * initialization routine and before port start routine. - * The Ethernet SDMA engine uses CPU bus addresses to access the various - * devices in the system (i.e. DRAM). This function uses the ethernet - * struct 'virtual to physical' routine (set by the user) to set the ring - * with physical addresses. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * int tx_desc_num Number of Tx descriptors - * int tx_buff_size Size of Tx buffer - * unsigned int tx_desc_base_addr Tx descriptors memory area base addr. - * unsigned int tx_buff_base_addr Tx buffer memory area base addr. - * - * OUTPUT: - * The routine updates the Ethernet port control struct with information - * regarding the Tx descriptors and buffers. - * - * RETURN: - * false if the given descriptors memory area is not aligned according to - * Ethernet SDMA specifications. - * true otherwise. - * - *******************************************************************************/ -static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE tx_queue, - int tx_desc_num, - int tx_buff_size, - unsigned int tx_desc_base_addr, - unsigned int tx_buff_base_addr) -{ - - ETH_TX_DESC *p_tx_desc; - ETH_TX_DESC *p_tx_prev_desc; - unsigned int buffer_addr; - int ix; /* a counter */ - - - /* save the first desc pointer to link with the last descriptor */ - p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr; - p_tx_prev_desc = p_tx_desc; - buffer_addr = tx_buff_base_addr; - - /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ - if (tx_buff_base_addr & 0xF) - return false; - - /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */ - if ((tx_buff_size > TX_BUFFER_MAX_SIZE) - || (tx_buff_size < TX_BUFFER_MIN_SIZE)) - return false; - - /* Initialize the Tx descriptors ring */ - for (ix = 0; ix < tx_desc_num; ix++) { - p_tx_desc->byte_cnt = 0x0000; - p_tx_desc->l4i_chk = 0x0000; - p_tx_desc->cmd_sts = 0x00000000; - p_tx_desc->next_desc_ptr = - ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE; - - p_tx_desc->buf_ptr = buffer_addr; - p_tx_desc->return_info = 0x00000000; - D_CACHE_FLUSH_LINE (p_tx_desc, 0); - buffer_addr += tx_buff_size; - p_tx_prev_desc = p_tx_desc; - p_tx_desc = (ETH_TX_DESC *) - ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE); - - } - /* Closing Tx descriptors ring */ - p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr; - D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0); - /* Set Tx desc pointer in driver struct. */ - CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); - USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); - - /* Init Tx ring base and size parameters */ - p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] = - (ETH_TX_DESC *) tx_desc_base_addr; - p_eth_port_ctrl->tx_desc_area_size[tx_queue] = - (tx_desc_num * TX_DESC_ALIGNED_SIZE); - - /* Add the queue to the list of Tx queues of this port */ - p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue); - - return true; -} - -/******************************************************************************* - * eth_port_send - Send an Ethernet packet - * - * DESCRIPTION: - * This routine send a given packet described by p_pktinfo parameter. It - * supports transmitting of a packet spaned over multiple buffers. The - * routine updates 'curr' and 'first' indexes according to the packet - * segment passed to the routine. In case the packet segment is first, - * the 'first' index is update. In any case, the 'curr' index is updated. - * If the routine get into Tx resource error it assigns 'curr' index as - * 'first'. This way the function can abort Tx process of multiple - * descriptors per packet. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Tx ring 'curr' and 'first' indexes are updated. - * - * RETURN: - * ETH_QUEUE_FULL in case of Tx resource error. - * ETH_ERROR in case the routine can not access Tx desc ring. - * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_TX_DESC *p_tx_desc_first; - volatile ETH_TX_DESC *p_tx_desc_curr; - volatile ETH_TX_DESC *p_tx_next_desc_curr; - volatile ETH_TX_DESC *p_tx_desc_used; - unsigned int command_status; - - /* Do not process Tx ring in case of Tx ring resource error */ - if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) - return ETH_QUEUE_FULL; - - /* Get the Tx Desc ring indexes */ - CURR_TFD_GET (p_tx_desc_curr, tx_queue); - USED_TFD_GET (p_tx_desc_used, tx_queue); - - if (p_tx_desc_curr == NULL) - return ETH_ERROR; - - /* The following parameters are used to save readings from memory */ - p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue); - command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC; - - if (command_status & (ETH_TX_FIRST_DESC)) { - /* Update first desc */ - FIRST_TFD_SET (p_tx_desc_curr, tx_queue); - p_tx_desc_first = p_tx_desc_curr; - } else { - FIRST_TFD_GET (p_tx_desc_first, tx_queue); - command_status |= ETH_BUFFER_OWNED_BY_DMA; - } - - /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */ - /* boundary. We use the memory allocated for Tx descriptor. This memory */ - /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */ - if (p_pkt_info->byte_cnt <= 8) { - printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */ - return ETH_ERROR; - - p_tx_desc_curr->buf_ptr = - (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC; - eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr, - p_pkt_info->byte_cnt); - } else - p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr; - - p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt; - p_tx_desc_curr->return_info = p_pkt_info->return_info; - - if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) { - /* Set last desc with DMA ownership and interrupt enable. */ - p_tx_desc_curr->cmd_sts = command_status | - ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT; - - if (p_tx_desc_curr != p_tx_desc_first) - p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA; - - /* Flush CPU pipe */ - - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0); - CPU_PIPE_FLUSH; - - /* Apply send command */ - ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num); - - /* Finish Tx packet. Update first desc in case of Tx resource error */ - p_tx_desc_first = p_tx_next_desc_curr; - FIRST_TFD_SET (p_tx_desc_first, tx_queue); - - } else { - p_tx_desc_curr->cmd_sts = command_status; - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); - } - - /* Check for ring index overlap in the Tx desc ring */ - if (p_tx_next_desc_curr == p_tx_desc_used) { - /* Update the current descriptor */ - CURR_TFD_SET (p_tx_desc_first, tx_queue); - - p_eth_port_ctrl->tx_resource_err[tx_queue] = true; - return ETH_QUEUE_LAST_RESOURCE; - } else { - /* Update the current descriptor */ - CURR_TFD_SET (p_tx_next_desc_curr, tx_queue); - return ETH_OK; - } -} - -/******************************************************************************* - * eth_tx_return_desc - Free all used Tx descriptors - * - * DESCRIPTION: - * This routine returns the transmitted packet information to the caller. - * It uses the 'first' index to support Tx desc return in case a transmit - * of a packet spanned over multiple buffer still in process. - * In case the Tx queue was in "resource error" condition, where there are - * no available Tx resources, the function resets the resource error flag. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Tx ring 'first' and 'used' indexes are updated. - * - * RETURN: - * ETH_ERROR in case the routine can not access Tx desc ring. - * ETH_RETRY in case there is transmission in process. - * ETH_END_OF_JOB if the routine has nothing to release. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO * - p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_TX_DESC *p_tx_desc_used = NULL; - volatile ETH_TX_DESC *p_tx_desc_first = NULL; - unsigned int command_status; - - - /* Get the Tx Desc ring indexes */ - USED_TFD_GET (p_tx_desc_used, tx_queue); - FIRST_TFD_GET (p_tx_desc_first, tx_queue); - - - /* Sanity check */ - if (p_tx_desc_used == NULL) - return ETH_ERROR; - - command_status = p_tx_desc_used->cmd_sts; - - /* Still transmitting... */ - if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - return ETH_RETRY; - } - - /* Stop release. About to overlap the current available Tx descriptor */ - if ((p_tx_desc_used == p_tx_desc_first) && - (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) { - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - return ETH_END_OF_JOB; - } - - /* Pass the packet information to the caller */ - p_pkt_info->cmd_sts = command_status; - p_pkt_info->return_info = p_tx_desc_used->return_info; - p_tx_desc_used->return_info = 0; - - /* Update the next descriptor to release. */ - USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue); - - /* Any Tx return cancels the Tx resource error status */ - if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) - p_eth_port_ctrl->tx_resource_err[tx_queue] = false; - - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - - return ETH_OK; - -} - -/******************************************************************************* - * eth_port_receive - Get received information from Rx ring. - * - * DESCRIPTION: - * This routine returns the received data to the caller. There is no - * data copying during routine operation. All information is returned - * using pointer to packet information struct passed from the caller. - * If the routine exhausts Rx ring resources then the resource error flag - * is set. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Rx ring current and used indexes are updated. - * - * RETURN: - * ETH_ERROR in case the routine can not access Rx desc ring. - * ETH_QUEUE_FULL if Rx ring resources are exhausted. - * ETH_END_OF_JOB if there is no received data. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_RX_DESC *p_rx_curr_desc; - volatile ETH_RX_DESC *p_rx_next_curr_desc; - volatile ETH_RX_DESC *p_rx_used_desc; - unsigned int command_status; - - /* Do not process Rx ring in case of Rx ring resource error */ - if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) { - printf ("\nRx Queue is full ...\n"); - return ETH_QUEUE_FULL; - } - - /* Get the Rx Desc ring 'curr and 'used' indexes */ - CURR_RFD_GET (p_rx_curr_desc, rx_queue); - USED_RFD_GET (p_rx_used_desc, rx_queue); - - /* Sanity check */ - if (p_rx_curr_desc == NULL) - return ETH_ERROR; - - /* The following parameters are used to save readings from memory */ - p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue); - command_status = p_rx_curr_desc->cmd_sts; - - /* Nothing to receive... */ - if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { -/* DP(printf("Rx: command_status: %08x\n", command_status)); */ - D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); -/* DP(printf("\nETH_END_OF_JOB ...\n"));*/ - return ETH_END_OF_JOB; - } - - p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET; - p_pkt_info->cmd_sts = command_status; - p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET; - p_pkt_info->return_info = p_rx_curr_desc->return_info; - p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */ - - /* Clean the return info field to indicate that the packet has been */ - /* moved to the upper layers */ - p_rx_curr_desc->return_info = 0; - - /* Update 'curr' in data structure */ - CURR_RFD_SET (p_rx_next_curr_desc, rx_queue); - - /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */ - if (p_rx_next_curr_desc == p_rx_used_desc) - p_eth_port_ctrl->rx_resource_err[rx_queue] = true; - - D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); - CPU_PIPE_FLUSH; - return ETH_OK; -} - -/******************************************************************************* - * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. - * - * DESCRIPTION: - * This routine returns a Rx buffer back to the Rx ring. It retrieves the - * next 'used' descriptor and attached the returned buffer to it. - * In case the Rx ring was in "resource error" condition, where there are - * no available Rx resources, the function resets the resource error flag. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * PKT_INFO *p_pkt_info Information on the returned buffer. - * - * OUTPUT: - * New available Rx resource in Rx descriptor ring. - * - * RETURN: - * ETH_ERROR in case the routine can not access Rx desc ring. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO * - p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */ - - /* Get 'used' Rx descriptor */ - USED_RFD_GET (p_used_rx_desc, rx_queue); - - /* Sanity check */ - if (p_used_rx_desc == NULL) - return ETH_ERROR; - - p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; - p_used_rx_desc->return_info = p_pkt_info->return_info; - p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt; - p_used_rx_desc->buf_size = MV64460_RX_BUFFER_SIZE; /* Reset Buffer size */ - - /* Flush the write pipe */ - CPU_PIPE_FLUSH; - - /* Return the descriptor to DMA ownership */ - p_used_rx_desc->cmd_sts = - ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; - - /* Flush descriptor and CPU pipe */ - D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0); - CPU_PIPE_FLUSH; - - /* Move the used descriptor pointer to the next descriptor */ - USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue); - - /* Any Rx return cancels the Rx resource error status */ - if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) - p_eth_port_ctrl->rx_resource_err[rx_queue] = false; - - return ETH_OK; -} - -/******************************************************************************* - * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path - * - * DESCRIPTION: - * This routine sets the RX coalescing interrupt mechanism parameter. - * This parameter is a timeout counter, that counts in 64 t_clk - * chunks ; that when timeout event occurs a maskable interrupt - * occurs. - * The parameter is calculated using the tClk of the MV-643xx chip - * , and the required delay of the interrupt in usec. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet port number - * unsigned int t_clk t_clk of the MV-643xx chip in HZ units - * unsigned int delay Delay in usec - * - * OUTPUT: - * Interrupt coalescing mechanism value is set in MV-643xx chip. - * - * RETURN: - * The interrupt coalescing value set in the gigE port. - * - *******************************************************************************/ -#if 0 /* FIXME */ -static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num, - unsigned int t_clk, - unsigned int delay) -{ - unsigned int coal; - - coal = ((t_clk / 1000000) * delay) / 64; - /* Set RX Coalescing mechanism */ - MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num), - ((coal & 0x3fff) << 8) | - (MV_REG_READ - (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num)) - & 0xffc000ff)); - return coal; -} - -#endif -/******************************************************************************* - * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path - * - * DESCRIPTION: - * This routine sets the TX coalescing interrupt mechanism parameter. - * This parameter is a timeout counter, that counts in 64 t_clk - * chunks ; that when timeout event occurs a maskable interrupt - * occurs. - * The parameter is calculated using the t_cLK frequency of the - * MV-643xx chip and the required delay in the interrupt in uSec - * - * INPUT: - * ETH_PORT eth_port_num Ethernet port number - * unsigned int t_clk t_clk of the MV-643xx chip in HZ units - * unsigned int delay Delay in uSeconds - * - * OUTPUT: - * Interrupt coalescing mechanism value is set in MV-643xx chip. - * - * RETURN: - * The interrupt coalescing value set in the gigE port. - * - *******************************************************************************/ -#if 0 /* FIXME */ -static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num, - unsigned int t_clk, - unsigned int delay) -{ - unsigned int coal; - - coal = ((t_clk / 1000000) * delay) / 64; - /* Set TX Coalescing mechanism */ - MV_REG_WRITE (MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num), - coal << 4); - return coal; -} -#endif - -/******************************************************************************* - * eth_b_copy - Copy bytes from source to destination - * - * DESCRIPTION: - * This function supports the eight bytes limitation on Tx buffer size. - * The routine will zero eight bytes starting from the destination address - * followed by copying bytes from the source address to the destination. - * - * INPUT: - * unsigned int src_addr 32 bit source address. - * unsigned int dst_addr 32 bit destination address. - * int byte_count Number of bytes to copy. - * - * OUTPUT: - * See description. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, - int byte_count) -{ - /* Zero the dst_addr area */ - *(unsigned int *) dst_addr = 0x0; - - while (byte_count != 0) { - *(char *) dst_addr = *(char *) src_addr; - dst_addr++; - src_addr++; - byte_count--; - } -} diff --git a/board/Marvell/db64460/mv_eth.h b/board/Marvell/db64460/mv_eth.h deleted file mode 100644 index 4c95e3e..0000000 --- a/board/Marvell/db64460/mv_eth.h +++ /dev/null @@ -1,815 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus <ingo.assmus@keymile.com> - * - * based on - Driver for MV64460X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mv_eth.h - header file for the polled mode GT ethernet driver - */ - -#ifndef __DB64460_ETH_H__ -#define __DB64460_ETH_H__ - -#include <asm/types.h> -#include <asm/io.h> -#include <asm/byteorder.h> -#include <common.h> -#include <net.h> -#include "mv_regs.h" -#include <asm/errno.h> - - -/************************************************************************* -************************************************************************** -************************************************************************** -* The first part is the high level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ -/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */ -#ifndef MAX_SKB_FRAGS -#define MAX_SKB_FRAGS 0 -#endif - -/* Port attributes */ -/*#define MAX_RX_QUEUE_NUM 8*/ -/*#define MAX_TX_QUEUE_NUM 8*/ -#define MAX_RX_QUEUE_NUM 1 -#define MAX_TX_QUEUE_NUM 1 - - -/* Use one TX queue and one RX queue */ -#define MV64460_TX_QUEUE_NUM 1 -#define MV64460_RX_QUEUE_NUM 1 - -/* - * Number of RX / TX descriptors on RX / TX rings. - * Note that allocating RX descriptors is done by allocating the RX - * ring AND a preallocated RX buffers (skb's) for each descriptor. - * The TX descriptors only allocates the TX descriptors ring, - * with no pre allocated TX buffers (skb's are allocated by higher layers. - */ - -/* Default TX ring size is 10 descriptors */ -#ifdef CONFIG_MV64460_ETH_TXQUEUE_SIZE -#define MV64460_TX_QUEUE_SIZE CONFIG_MV64460_ETH_TXQUEUE_SIZE -#else -#define MV64460_TX_QUEUE_SIZE 4 -#endif - -/* Default RX ring size is 4 descriptors */ -#ifdef CONFIG_MV64460_ETH_RXQUEUE_SIZE -#define MV64460_RX_QUEUE_SIZE CONFIG_MV64460_ETH_RXQUEUE_SIZE -#else -#define MV64460_RX_QUEUE_SIZE 4 -#endif - -#ifdef CONFIG_RX_BUFFER_SIZE -#define MV64460_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE -#else -#define MV64460_RX_BUFFER_SIZE 1600 -#endif - -#ifdef CONFIG_TX_BUFFER_SIZE -#define MV64460_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE -#else -#define MV64460_TX_BUFFER_SIZE 1600 -#endif - -/* - * Network device statistics. Akin to the 2.0 ether stats but - * with byte counters. - */ - -struct net_device_stats -{ - unsigned long rx_packets; /* total packets received */ - unsigned long tx_packets; /* total packets transmitted */ - unsigned long rx_bytes; /* total bytes received */ - unsigned long tx_bytes; /* total bytes transmitted */ - unsigned long rx_errors; /* bad packets received */ - unsigned long tx_errors; /* packet transmit problems */ - unsigned long rx_dropped; /* no space in linux buffers */ - unsigned long tx_dropped; /* no space available in linux */ - unsigned long multicast; /* multicast packets received */ - unsigned long collisions; - - /* detailed rx_errors: */ - unsigned long rx_length_errors; - unsigned long rx_over_errors; /* receiver ring buff overflow */ - unsigned long rx_crc_errors; /* recved pkt with crc error */ - unsigned long rx_frame_errors; /* recv'd frame alignment error */ - unsigned long rx_fifo_errors; /* recv'r fifo overrun */ - unsigned long rx_missed_errors; /* receiver missed packet */ - - /* detailed tx_errors */ - unsigned long tx_aborted_errors; - unsigned long tx_carrier_errors; - unsigned long tx_fifo_errors; - unsigned long tx_heartbeat_errors; - unsigned long tx_window_errors; - - /* for cslip etc */ - unsigned long rx_compressed; - unsigned long tx_compressed; -}; - - -/* Private data structure used for ethernet device */ -struct mv64460_eth_priv { - unsigned int port_num; - struct net_device_stats *stats; - -/* to buffer area aligned */ - char * p_eth_tx_buffer[MV64460_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */ - char * p_eth_rx_buffer[MV64460_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */ - - /* Size of Tx Ring per queue */ - unsigned int tx_ring_size [MAX_TX_QUEUE_NUM]; - - - /* Size of Rx Ring per queue */ - unsigned int rx_ring_size [MAX_RX_QUEUE_NUM]; - - /* Magic Number for Ethernet running */ - unsigned int eth_running; - -}; - -int mv64460_eth_init (struct eth_device *dev); -int mv64460_eth_stop (struct eth_device *dev); -int mv64460_eth_start_xmit(struct eth_device *dev, void *packet, int length); -int mv64460_eth_open (struct eth_device *dev); - - -/************************************************************************* -************************************************************************** -************************************************************************** -* The second part is the low level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ - - -/******************************************************************************** - * Header File for : MV-643xx network interface header - * - * DESCRIPTION: - * This header file contains macros typedefs and function declaration for - * the Marvell Gig Bit Ethernet Controller. - * - * DEPENDENCIES: - * None. - * - *******************************************************************************/ - - -#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY -#ifdef CONFIG_MV64460_SRAM_CACHEABLE -/* In case SRAM is cacheable but not cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) \ -{ \ - __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ -} -#else -/* In case SRAM is cache coherent or non-cacheable */ -#define D_CACHE_FLUSH_LINE(addr, offset) ; -#endif -#else -#ifdef CONFIG_NOT_COHERENT_CACHE -/* In case of descriptors on DDR but not cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) \ -{ \ - __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ -} -#else -/* In case of descriptors on DDR and cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) ; -#endif /* CONFIG_NOT_COHERENT_CACHE */ -#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */ - - -#define CPU_PIPE_FLUSH \ -{ \ - __asm__ __volatile__ ("eieio"); \ -} - - -/* defines */ - -/* Default port configuration value */ -#define PORT_CONFIG_VALUE \ - ETH_UNICAST_NORMAL_MODE | \ - ETH_DEFAULT_RX_QUEUE_0 | \ - ETH_DEFAULT_RX_ARP_QUEUE_0 | \ - ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \ - ETH_RECEIVE_BC_IF_IP | \ - ETH_RECEIVE_BC_IF_ARP | \ - ETH_CAPTURE_TCP_FRAMES_DIS | \ - ETH_CAPTURE_UDP_FRAMES_DIS | \ - ETH_DEFAULT_RX_TCP_QUEUE_0 | \ - ETH_DEFAULT_RX_UDP_QUEUE_0 | \ - ETH_DEFAULT_RX_BPDU_QUEUE_0 - -/* Default port extend configuration value */ -#define PORT_CONFIG_EXTEND_VALUE \ - ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \ - ETH_PARTITION_DISABLE - - -/* Default sdma control value */ -#ifdef CONFIG_NOT_COHERENT_CACHE -#define PORT_SDMA_CONFIG_VALUE \ - ETH_RX_BURST_SIZE_16_64BIT | \ - GT_ETH_IPG_INT_RX(0) | \ - ETH_TX_BURST_SIZE_16_64BIT; -#else -#define PORT_SDMA_CONFIG_VALUE \ - ETH_RX_BURST_SIZE_4_64BIT | \ - GT_ETH_IPG_INT_RX(0) | \ - ETH_TX_BURST_SIZE_4_64BIT; -#endif - -#define GT_ETH_IPG_INT_RX(value) \ - ((value & 0x3fff) << 8) - -/* Default port serial control value */ -#define PORT_SERIAL_CONTROL_VALUE \ - ETH_FORCE_LINK_PASS | \ - ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \ - ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ - ETH_ADV_SYMMETRIC_FLOW_CTRL | \ - ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ - ETH_FORCE_BP_MODE_NO_JAM | \ - BIT9 | \ - ETH_DO_NOT_FORCE_LINK_FAIL | \ - ETH_RETRANSMIT_16_ETTEMPTS | \ - ETH_ENABLE_AUTO_NEG_SPEED_GMII | \ - ETH_DTE_ADV_0 | \ - ETH_DISABLE_AUTO_NEG_BYPASS | \ - ETH_AUTO_NEG_NO_CHANGE | \ - ETH_MAX_RX_PACKET_1552BYTE | \ - ETH_CLR_EXT_LOOPBACK | \ - ETH_SET_FULL_DUPLEX_MODE | \ - ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX; - -#define RX_BUFFER_MAX_SIZE 0xFFFF -#define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */ - -#define RX_BUFFER_MIN_SIZE 0x8 -#define TX_BUFFER_MIN_SIZE 0x8 - -/* Tx WRR confoguration macros */ -#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */ -#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */ -#define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */ - -/* MAC accepet/reject macros */ -#define ACCEPT_MAC_ADDR 0 -#define REJECT_MAC_ADDR 1 - -/* Size of a Tx/Rx descriptor used in chain list data structure */ -#define RX_DESC_ALIGNED_SIZE 0x20 -#define TX_DESC_ALIGNED_SIZE 0x20 - -/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */ -#define TX_BUF_OFFSET_IN_DESC 0x18 -/* Buffer offset from buffer pointer */ -#define RX_BUF_OFFSET 0x2 - -/* Gap define */ -#define ETH_BAR_GAP 0x8 -#define ETH_SIZE_REG_GAP 0x8 -#define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4 -#define ETH_PORT_ACCESS_CTRL_GAP 0x4 - -/* Gigabit Ethernet Unit Global Registers */ - -/* MIB Counters register definitions */ -#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0 -#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4 -#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8 -#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc -#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10 -#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14 -#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18 -#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c -#define ETH_MIB_FRAMES_64_OCTETS 0x20 -#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24 -#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28 -#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c -#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30 -#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 -#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38 -#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c -#define ETH_MIB_GOOD_FRAMES_SENT 0x40 -#define ETH_MIB_EXCESSIVE_COLLISION 0x44 -#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48 -#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c -#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50 -#define ETH_MIB_FC_SENT 0x54 -#define ETH_MIB_GOOD_FC_RECEIVED 0x58 -#define ETH_MIB_BAD_FC_RECEIVED 0x5c -#define ETH_MIB_UNDERSIZE_RECEIVED 0x60 -#define ETH_MIB_FRAGMENTS_RECEIVED 0x64 -#define ETH_MIB_OVERSIZE_RECEIVED 0x68 -#define ETH_MIB_JABBER_RECEIVED 0x6c -#define ETH_MIB_MAC_RECEIVE_ERROR 0x70 -#define ETH_MIB_BAD_CRC_EVENT 0x74 -#define ETH_MIB_COLLISION 0x78 -#define ETH_MIB_LATE_COLLISION 0x7c - -/* Port serial status reg (PSR) */ -#define ETH_INTERFACE_GMII_MII 0 -#define ETH_INTERFACE_PCM BIT0 -#define ETH_LINK_IS_DOWN 0 -#define ETH_LINK_IS_UP BIT1 -#define ETH_PORT_AT_HALF_DUPLEX 0 -#define ETH_PORT_AT_FULL_DUPLEX BIT2 -#define ETH_RX_FLOW_CTRL_DISABLED 0 -#define ETH_RX_FLOW_CTRL_ENBALED BIT3 -#define ETH_GMII_SPEED_100_10 0 -#define ETH_GMII_SPEED_1000 BIT4 -#define ETH_MII_SPEED_10 0 -#define ETH_MII_SPEED_100 BIT5 -#define ETH_NO_TX 0 -#define ETH_TX_IN_PROGRESS BIT7 -#define ETH_BYPASS_NO_ACTIVE 0 -#define ETH_BYPASS_ACTIVE BIT8 -#define ETH_PORT_NOT_AT_PARTITION_STATE 0 -#define ETH_PORT_AT_PARTITION_STATE BIT9 -#define ETH_PORT_TX_FIFO_NOT_EMPTY 0 -#define ETH_PORT_TX_FIFO_EMPTY BIT10 - - -/* These macros describes the Port configuration reg (Px_cR) bits */ -#define ETH_UNICAST_NORMAL_MODE 0 -#define ETH_UNICAST_PROMISCUOUS_MODE BIT0 -#define ETH_DEFAULT_RX_QUEUE_0 0 -#define ETH_DEFAULT_RX_QUEUE_1 BIT1 -#define ETH_DEFAULT_RX_QUEUE_2 BIT2 -#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1) -#define ETH_DEFAULT_RX_QUEUE_4 BIT3 -#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1) -#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2) -#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1) -#define ETH_DEFAULT_RX_ARP_QUEUE_0 0 -#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4 -#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5 -#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4) -#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6 -#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4) -#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5) -#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4) -#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0 -#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7 -#define ETH_RECEIVE_BC_IF_IP 0 -#define ETH_REJECT_BC_IF_IP BIT8 -#define ETH_RECEIVE_BC_IF_ARP 0 -#define ETH_REJECT_BC_IF_ARP BIT9 -#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12 -#define ETH_CAPTURE_TCP_FRAMES_DIS 0 -#define ETH_CAPTURE_TCP_FRAMES_EN BIT14 -#define ETH_CAPTURE_UDP_FRAMES_DIS 0 -#define ETH_CAPTURE_UDP_FRAMES_EN BIT15 -#define ETH_DEFAULT_RX_TCP_QUEUE_0 0 -#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16 -#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17 -#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16) -#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18 -#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16) -#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17) -#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16) -#define ETH_DEFAULT_RX_UDP_QUEUE_0 0 -#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19 -#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20 -#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19) -#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21 -#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19) -#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20) -#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19) -#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0 -#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22 -#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23 -#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22) -#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24 -#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22) -#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23) -#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22) - - -/* These macros describes the Port configuration extend reg (Px_cXR) bits*/ -#define ETH_CLASSIFY_EN BIT0 -#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0 -#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1 -#define ETH_PARTITION_DISABLE 0 -#define ETH_PARTITION_ENABLE BIT2 - - -/* Tx/Rx queue command reg (RQCR/TQCR)*/ -#define ETH_QUEUE_0_ENABLE BIT0 -#define ETH_QUEUE_1_ENABLE BIT1 -#define ETH_QUEUE_2_ENABLE BIT2 -#define ETH_QUEUE_3_ENABLE BIT3 -#define ETH_QUEUE_4_ENABLE BIT4 -#define ETH_QUEUE_5_ENABLE BIT5 -#define ETH_QUEUE_6_ENABLE BIT6 -#define ETH_QUEUE_7_ENABLE BIT7 -#define ETH_QUEUE_0_DISABLE BIT8 -#define ETH_QUEUE_1_DISABLE BIT9 -#define ETH_QUEUE_2_DISABLE BIT10 -#define ETH_QUEUE_3_DISABLE BIT11 -#define ETH_QUEUE_4_DISABLE BIT12 -#define ETH_QUEUE_5_DISABLE BIT13 -#define ETH_QUEUE_6_DISABLE BIT14 -#define ETH_QUEUE_7_DISABLE BIT15 - -/* These macros describes the Port Sdma configuration reg (SDCR) bits */ -#define ETH_RIFB BIT0 -#define ETH_RX_BURST_SIZE_1_64BIT 0 -#define ETH_RX_BURST_SIZE_2_64BIT BIT1 -#define ETH_RX_BURST_SIZE_4_64BIT BIT2 -#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1) -#define ETH_RX_BURST_SIZE_16_64BIT BIT3 -#define ETH_BLM_RX_NO_SWAP BIT4 -#define ETH_BLM_RX_BYTE_SWAP 0 -#define ETH_BLM_TX_NO_SWAP BIT5 -#define ETH_BLM_TX_BYTE_SWAP 0 -#define ETH_DESCRIPTORS_BYTE_SWAP BIT6 -#define ETH_DESCRIPTORS_NO_SWAP 0 -#define ETH_TX_BURST_SIZE_1_64BIT 0 -#define ETH_TX_BURST_SIZE_2_64BIT BIT22 -#define ETH_TX_BURST_SIZE_4_64BIT BIT23 -#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22) -#define ETH_TX_BURST_SIZE_16_64BIT BIT24 - -/* These macros describes the Port serial control reg (PSCR) bits */ -#define ETH_SERIAL_PORT_DISABLE 0 -#define ETH_SERIAL_PORT_ENABLE BIT0 -#define ETH_FORCE_LINK_PASS BIT1 -#define ETH_DO_NOT_FORCE_LINK_PASS 0 -#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0 -#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2 -#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0 -#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3 -#define ETH_ADV_NO_FLOW_CTRL 0 -#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4 -#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0 -#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5 -#define ETH_FORCE_BP_MODE_NO_JAM 0 -#define ETH_FORCE_BP_MODE_JAM_TX BIT7 -#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8 -#define ETH_FORCE_LINK_FAIL 0 -#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10 -#define ETH_RETRANSMIT_16_ETTEMPTS 0 -#define ETH_RETRANSMIT_FOREVER BIT11 -#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13 -#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0 -#define ETH_DTE_ADV_0 0 -#define ETH_DTE_ADV_1 BIT14 -#define ETH_DISABLE_AUTO_NEG_BYPASS 0 -#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15 -#define ETH_AUTO_NEG_NO_CHANGE 0 -#define ETH_RESTART_AUTO_NEG BIT16 -#define ETH_MAX_RX_PACKET_1518BYTE 0 -#define ETH_MAX_RX_PACKET_1522BYTE BIT17 -#define ETH_MAX_RX_PACKET_1552BYTE BIT18 -#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17) -#define ETH_MAX_RX_PACKET_9192BYTE BIT19 -#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17) -#define ETH_SET_EXT_LOOPBACK BIT20 -#define ETH_CLR_EXT_LOOPBACK 0 -#define ETH_SET_FULL_DUPLEX_MODE BIT21 -#define ETH_SET_HALF_DUPLEX_MODE 0 -#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22 -#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0 -#define ETH_SET_GMII_SPEED_TO_10_100 0 -#define ETH_SET_GMII_SPEED_TO_1000 BIT23 -#define ETH_SET_MII_SPEED_TO_10 0 -#define ETH_SET_MII_SPEED_TO_100 BIT24 - - -/* SMI reg */ -#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */ -#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */ -#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */ -#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */ - -/* SDMA command status fields macros */ - -/* Tx & Rx descriptors status */ -#define ETH_ERROR_SUMMARY (BIT0) - -/* Tx & Rx descriptors command */ -#define ETH_BUFFER_OWNED_BY_DMA (BIT31) - -/* Tx descriptors status */ -#define ETH_LC_ERROR (0 ) -#define ETH_UR_ERROR (BIT1 ) -#define ETH_RL_ERROR (BIT2 ) -#define ETH_LLC_SNAP_FORMAT (BIT9 ) - -/* Rx descriptors status */ -#define ETH_CRC_ERROR (0 ) -#define ETH_OVERRUN_ERROR (BIT1 ) -#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 ) -#define ETH_RESOURCE_ERROR ((BIT2 | BIT1)) -#define ETH_VLAN_TAGGED (BIT19) -#define ETH_BPDU_FRAME (BIT20) -#define ETH_TCP_FRAME_OVER_IP_V_4 (0 ) -#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21) -#define ETH_OTHER_FRAME_TYPE (BIT22) -#define ETH_LAYER_2_IS_ETH_V_2 (BIT23) -#define ETH_FRAME_TYPE_IP_V_4 (BIT24) -#define ETH_FRAME_HEADER_OK (BIT25) -#define ETH_RX_LAST_DESC (BIT26) -#define ETH_RX_FIRST_DESC (BIT27) -#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28) -#define ETH_RX_ENABLE_INTERRUPT (BIT29) -#define ETH_LAYER_4_CHECKSUM_OK (BIT30) - -/* Rx descriptors byte count */ -#define ETH_FRAME_FRAGMENTED (BIT2) - -/* Tx descriptors command */ -#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10) -#define ETH_FRAME_SET_TO_VLAN (BIT15) -#define ETH_TCP_FRAME (0 ) -#define ETH_UDP_FRAME (BIT16) -#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17) -#define ETH_GEN_IP_V_4_CHECKSUM (BIT18) -#define ETH_ZERO_PADDING (BIT19) -#define ETH_TX_LAST_DESC (BIT20) -#define ETH_TX_FIRST_DESC (BIT21) -#define ETH_GEN_CRC (BIT22) -#define ETH_TX_ENABLE_INTERRUPT (BIT23) -#define ETH_AUTO_MODE (BIT30) - -/* Address decode parameters */ -/* Ethernet Base Address Register bits */ -#define EBAR_TARGET_DRAM 0x00000000 -#define EBAR_TARGET_DEVICE 0x00000001 -#define EBAR_TARGET_CBS 0x00000002 -#define EBAR_TARGET_PCI0 0x00000003 -#define EBAR_TARGET_PCI1 0x00000004 -#define EBAR_TARGET_CUNIT 0x00000005 -#define EBAR_TARGET_AUNIT 0x00000006 -#define EBAR_TARGET_GUNIT 0x00000007 - -/* Window attributes */ -#define EBAR_ATTR_DRAM_CS0 0x00000E00 -#define EBAR_ATTR_DRAM_CS1 0x00000D00 -#define EBAR_ATTR_DRAM_CS2 0x00000B00 -#define EBAR_ATTR_DRAM_CS3 0x00000700 - -/* DRAM Target interface */ -#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000 -#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000 -#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000 - -/* Device Bus Target interface */ -#define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00 -#define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00 -#define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00 -#define EBAR_ATTR_DEVICE_DEVCS3 0x00001700 -#define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00 - -/* PCI Target interface */ -#define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000 -#define EBAR_ATTR_PCI_NO_SWAP 0x00000100 -#define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200 -#define EBAR_ATTR_PCI_WORD_SWAP 0x00000300 -#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000 -#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400 -#define EBAR_ATTR_PCI_IO_SPACE 0x00000000 -#define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800 -#define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000 -#define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000 - -/* CPU 60x bus or internal SRAM interface */ -#define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000 -#define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100 -#define EBAR_ATTR_CBS_SRAM 0x00000000 -#define EBAR_ATTR_CBS_CPU_BUS 0x00000800 - -/* Window access control */ -#define EWIN_ACCESS_NOT_ALLOWED 0 -#define EWIN_ACCESS_READ_ONLY BIT0 -#define EWIN_ACCESS_FULL (BIT1 | BIT0) -#define EWIN0_ACCESS_MASK 0x0003 -#define EWIN1_ACCESS_MASK 0x000C -#define EWIN2_ACCESS_MASK 0x0030 -#define EWIN3_ACCESS_MASK 0x00C0 - -/* typedefs */ - -typedef enum _eth_port -{ - ETH_0 = 0, - ETH_1 = 1, - ETH_2 = 2 -}ETH_PORT; - -typedef enum _eth_func_ret_status -{ - ETH_OK, /* Returned as expected. */ - ETH_ERROR, /* Fundamental error. */ - ETH_RETRY, /* Could not process request. Try later. */ - ETH_END_OF_JOB, /* Ring has nothing to process. */ - ETH_QUEUE_FULL, /* Ring resource error. */ - ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */ -}ETH_FUNC_RET_STATUS; - -typedef enum _eth_queue -{ - ETH_Q0 = 0, - ETH_Q1 = 1, - ETH_Q2 = 2, - ETH_Q3 = 3, - ETH_Q4 = 4, - ETH_Q5 = 5, - ETH_Q6 = 6, - ETH_Q7 = 7 -} ETH_QUEUE; - -typedef enum _addr_win -{ - ETH_WIN0, - ETH_WIN1, - ETH_WIN2, - ETH_WIN3, - ETH_WIN4, - ETH_WIN5 -} ETH_ADDR_WIN; - -typedef enum _eth_target -{ - ETH_TARGET_DRAM , - ETH_TARGET_DEVICE, - ETH_TARGET_CBS , - ETH_TARGET_PCI0 , - ETH_TARGET_PCI1 -}ETH_TARGET; - -typedef struct _eth_rx_desc -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short buf_size ; /* Buffer size */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int next_desc_ptr; /* Next descriptor pointer */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} ETH_RX_DESC; - - -typedef struct _eth_tx_desc -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short l4i_chk ; /* CPU provided TCP Checksum */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int next_desc_ptr; /* Next descriptor pointer */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} ETH_TX_DESC; - -/* Unified struct for Rx and Tx operations. The user is not required to */ -/* be familier with neither Tx nor Rx descriptors. */ -typedef struct _pkt_info -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} PKT_INFO; - - -typedef struct _eth_win_param -{ - ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */ - ETH_TARGET target; /* System targets. See ETH_TARGET enum */ - unsigned short attributes; /* BAR attributes. See above macros. */ - unsigned int base_addr; /* Window base address in unsigned int form */ - unsigned int high_addr; /* Window high address in unsigned int form */ - unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */ - bool enable; /* Enable/disable access to the window. */ - unsigned short access_ctrl; /* Access ctrl register. see above macros */ -} ETH_WIN_PARAM; - - -/* Ethernet port specific infomation */ - -typedef struct _eth_port_ctrl -{ - ETH_PORT port_num; /* User Ethernet port number */ - int port_phy_addr; /* User phy address of Ethrnet port */ - unsigned char port_mac_addr[6]; /* User defined port MAC address. */ - unsigned int port_config; /* User port configuration value */ - unsigned int port_config_extend; /* User port config extend value */ - unsigned int port_sdma_config; /* User port SDMA config value */ - unsigned int port_serial_control; /* User port serial control value */ - unsigned int port_tx_queue_command; /* Port active Tx queues summary */ - unsigned int port_rx_queue_command; /* Port active Rx queues summary */ - - /* User function to cast virtual address to CPU bus address */ - unsigned int (*port_virt_to_phys)(unsigned int addr); - /* User scratch pad for user specific data structures */ - void *port_private; - - bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */ - bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */ - - /* Tx/Rx rings managment indexes fields. For driver use */ - - /* Next available Rx resource */ - volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM]; - /* Returning Rx resource */ - volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM]; - - /* Next available Tx resource */ - volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM]; - /* Returning Tx resource */ - volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM]; - /* An extra Tx index to support transmit of multiple buffers per packet */ - volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM]; - - /* Tx/Rx rings size and base variables fields. For driver use */ - - volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM]; - unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM]; - char *p_rx_buffer_base[MAX_RX_QUEUE_NUM]; - - volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM]; - unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM]; - char *p_tx_buffer_base[MAX_TX_QUEUE_NUM]; - -} ETH_PORT_INFO; - - -/* ethernet.h API list */ - -/* Port operation control routines */ -static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl); -static void eth_port_reset(ETH_PORT eth_port_num); -static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl); - - -/* Port MAC address routines */ -static void eth_port_uc_addr_set (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue); -#if 0 /* FIXME */ -static void eth_port_mc_addr (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue, - int option); -#endif - -/* PHY and MIB routines */ -static bool ethernet_phy_reset(ETH_PORT eth_port_num); - -static bool eth_port_write_smi_reg(ETH_PORT eth_port_num, - unsigned int phy_reg, - unsigned int value); - -static bool eth_port_read_smi_reg(ETH_PORT eth_port_num, - unsigned int phy_reg, - unsigned int* value); - -static void eth_clear_mib_counters(ETH_PORT eth_port_num); - -/* Port data flow control routines */ -static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO *p_pkt_info); - - -static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - int tx_desc_num, - int tx_buff_size, - unsigned int tx_desc_base_addr, - unsigned int tx_buff_base_addr); - -static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - int rx_desc_num, - int rx_buff_size, - unsigned int rx_desc_base_addr, - unsigned int rx_buff_base_addr); - -#endif /* MV64460_ETH_ */ diff --git a/board/Marvell/db64460/mv_regs.h b/board/Marvell/db64460/mv_regs.h deleted file mode 100644 index 70b6d2e..0000000 --- a/board/Marvell/db64460/mv_regs.h +++ /dev/null @@ -1,1108 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus <ingo.assmus@keymile.com> - * - * based on - Driver for MV64460X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/******************************************************************************** -* gt64460r.h - GT-64460 Internal registers definition file. -* -* DESCRIPTION: -* None. -* -* DEPENDENCIES: -* None. -* -*******************************************************************************/ - -#ifndef __INCmv_regsh -#define __INCmv_regsh - -#define MV64460 - -/* Supported by the Atlantis */ -#define MV64460_INCLUDE_PCI_1 -#define MV64460_INCLUDE_PCI_0_ARBITER -#define MV64460_INCLUDE_PCI_1_ARBITER -#define MV64460_INCLUDE_SNOOP_SUPPORT -#define MV64460_INCLUDE_P2P -#define MV64460_INCLUDE_ETH_PORT_2 -#define MV64460_INCLUDE_CPU_MAPPING -#define MV64460_INCLUDE_MPSC - -/* Not supported features */ -#undef INCLUDE_CNTMR_4_7 -#undef INCLUDE_DMA_4_7 - -/****************************************/ -/* Processor Address Space */ -/****************************************/ - -/* DDR SDRAM BAR and size registers */ - -#define MV64460_CS_0_BASE_ADDR 0x008 -#define MV64460_CS_0_SIZE 0x010 -#define MV64460_CS_1_BASE_ADDR 0x208 -#define MV64460_CS_1_SIZE 0x210 -#define MV64460_CS_2_BASE_ADDR 0x018 -#define MV64460_CS_2_SIZE 0x020 -#define MV64460_CS_3_BASE_ADDR 0x218 -#define MV64460_CS_3_SIZE 0x220 - -/* Devices BAR and size registers */ - -#define MV64460_DEV_CS0_BASE_ADDR 0x028 -#define MV64460_DEV_CS0_SIZE 0x030 -#define MV64460_DEV_CS1_BASE_ADDR 0x228 -#define MV64460_DEV_CS1_SIZE 0x230 -#define MV64460_DEV_CS2_BASE_ADDR 0x248 -#define MV64460_DEV_CS2_SIZE 0x250 -#define MV64460_DEV_CS3_BASE_ADDR 0x038 -#define MV64460_DEV_CS3_SIZE 0x040 -#define MV64460_BOOTCS_BASE_ADDR 0x238 -#define MV64460_BOOTCS_SIZE 0x240 - -/* PCI 0 BAR and size registers */ - -#define MV64460_PCI_0_IO_BASE_ADDR 0x048 -#define MV64460_PCI_0_IO_SIZE 0x050 -#define MV64460_PCI_0_MEMORY0_BASE_ADDR 0x058 -#define MV64460_PCI_0_MEMORY0_SIZE 0x060 -#define MV64460_PCI_0_MEMORY1_BASE_ADDR 0x080 -#define MV64460_PCI_0_MEMORY1_SIZE 0x088 -#define MV64460_PCI_0_MEMORY2_BASE_ADDR 0x258 -#define MV64460_PCI_0_MEMORY2_SIZE 0x260 -#define MV64460_PCI_0_MEMORY3_BASE_ADDR 0x280 -#define MV64460_PCI_0_MEMORY3_SIZE 0x288 - -/* PCI 1 BAR and size registers */ -#define MV64460_PCI_1_IO_BASE_ADDR 0x090 -#define MV64460_PCI_1_IO_SIZE 0x098 -#define MV64460_PCI_1_MEMORY0_BASE_ADDR 0x0a0 -#define MV64460_PCI_1_MEMORY0_SIZE 0x0a8 -#define MV64460_PCI_1_MEMORY1_BASE_ADDR 0x0b0 -#define MV64460_PCI_1_MEMORY1_SIZE 0x0b8 -#define MV64460_PCI_1_MEMORY2_BASE_ADDR 0x2a0 -#define MV64460_PCI_1_MEMORY2_SIZE 0x2a8 -#define MV64460_PCI_1_MEMORY3_BASE_ADDR 0x2b0 -#define MV64460_PCI_1_MEMORY3_SIZE 0x2b8 - -/* SRAM base address */ -#define MV64460_INTEGRATED_SRAM_BASE_ADDR 0x268 - -/* internal registers space base address */ -#define MV64460_INTERNAL_SPACE_BASE_ADDR 0x068 - -/* Enables the CS , DEV_CS , PCI 0 and PCI 1 - windows above */ -#define MV64460_BASE_ADDR_ENABLE 0x278 - -/****************************************/ -/* PCI remap registers */ -/****************************************/ - /* PCI 0 */ -#define MV64460_PCI_0_IO_ADDR_REMAP 0x0f0 -#define MV64460_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8 -#define MV64460_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320 -#define MV64460_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100 -#define MV64460_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328 -#define MV64460_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8 -#define MV64460_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330 -#define MV64460_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300 -#define MV64460_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338 - /* PCI 1 */ -#define MV64460_PCI_1_IO_ADDR_REMAP 0x108 -#define MV64460_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110 -#define MV64460_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340 -#define MV64460_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118 -#define MV64460_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348 -#define MV64460_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310 -#define MV64460_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350 -#define MV64460_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318 -#define MV64460_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358 - -#define MV64460_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0 -#define MV64460_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8 -#define MV64460_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0 -#define MV64460_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8 -#define MV64460_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0 -#define MV64460_CPU_GE_HEADERS_RETARGET_BASE 0x3d8 -#define MV64460_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0 -#define MV64460_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8 - -/****************************************/ -/* CPU Control Registers */ -/****************************************/ - -#define MV64460_CPU_CONFIG 0x000 -#define MV64460_CPU_MODE 0x120 -#define MV64460_CPU_MASTER_CONTROL 0x160 -#define MV64460_CPU_CROSS_BAR_CONTROL_LOW 0x150 -#define MV64460_CPU_CROSS_BAR_CONTROL_HIGH 0x158 -#define MV64460_CPU_CROSS_BAR_TIMEOUT 0x168 - -/****************************************/ -/* SMP RegisterS */ -/****************************************/ - -#define MV64460_SMP_WHO_AM_I 0x200 -#define MV64460_SMP_CPU0_DOORBELL 0x214 -#define MV64460_SMP_CPU0_DOORBELL_CLEAR 0x21C -#define MV64460_SMP_CPU1_DOORBELL 0x224 -#define MV64460_SMP_CPU1_DOORBELL_CLEAR 0x22C -#define MV64460_SMP_CPU0_DOORBELL_MASK 0x234 -#define MV64460_SMP_CPU1_DOORBELL_MASK 0x23C -#define MV64460_SMP_SEMAPHOR0 0x244 -#define MV64460_SMP_SEMAPHOR1 0x24c -#define MV64460_SMP_SEMAPHOR2 0x254 -#define MV64460_SMP_SEMAPHOR3 0x25c -#define MV64460_SMP_SEMAPHOR4 0x264 -#define MV64460_SMP_SEMAPHOR5 0x26c -#define MV64460_SMP_SEMAPHOR6 0x274 -#define MV64460_SMP_SEMAPHOR7 0x27c - -/****************************************/ -/* CPU Sync Barrier Register */ -/****************************************/ - -#define MV64460_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0 -#define MV64460_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8 -#define MV64460_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0 -#define MV64460_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8 - -/****************************************/ -/* CPU Access Protect */ -/****************************************/ - -#define MV64460_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180 -#define MV64460_CPU_PROTECT_WINDOW_0_SIZE 0x188 -#define MV64460_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190 -#define MV64460_CPU_PROTECT_WINDOW_1_SIZE 0x198 -#define MV64460_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0 -#define MV64460_CPU_PROTECT_WINDOW_2_SIZE 0x1a8 -#define MV64460_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0 -#define MV64460_CPU_PROTECT_WINDOW_3_SIZE 0x1b8 - - -/****************************************/ -/* CPU Error Report */ -/****************************************/ - -#define MV64460_CPU_ERROR_ADDR_LOW 0x070 -#define MV64460_CPU_ERROR_ADDR_HIGH 0x078 -#define MV64460_CPU_ERROR_DATA_LOW 0x128 -#define MV64460_CPU_ERROR_DATA_HIGH 0x130 -#define MV64460_CPU_ERROR_PARITY 0x138 -#define MV64460_CPU_ERROR_CAUSE 0x140 -#define MV64460_CPU_ERROR_MASK 0x148 - -/****************************************/ -/* CPU Interface Debug Registers */ -/****************************************/ - -#define MV64460_PUNIT_SLAVE_DEBUG_LOW 0x360 -#define MV64460_PUNIT_SLAVE_DEBUG_HIGH 0x368 -#define MV64460_PUNIT_MASTER_DEBUG_LOW 0x370 -#define MV64460_PUNIT_MASTER_DEBUG_HIGH 0x378 -#define MV64460_PUNIT_MMASK 0x3e4 - -/****************************************/ -/* Integrated SRAM Registers */ -/****************************************/ - -#define MV64460_SRAM_CONFIG 0x380 -#define MV64460_SRAM_TEST_MODE 0X3F4 -#define MV64460_SRAM_ERROR_CAUSE 0x388 -#define MV64460_SRAM_ERROR_ADDR 0x390 -#define MV64460_SRAM_ERROR_ADDR_HIGH 0X3F8 -#define MV64460_SRAM_ERROR_DATA_LOW 0x398 -#define MV64460_SRAM_ERROR_DATA_HIGH 0x3a0 -#define MV64460_SRAM_ERROR_DATA_PARITY 0x3a8 - -/****************************************/ -/* SDRAM Configuration */ -/****************************************/ - -#define MV64460_SDRAM_CONFIG 0x1400 -#define MV64460_D_UNIT_CONTROL_LOW 0x1404 -#define MV64460_D_UNIT_CONTROL_HIGH 0x1424 -#define MV64460_SDRAM_TIMING_CONTROL_LOW 0x1408 -#define MV64460_SDRAM_TIMING_CONTROL_HIGH 0x140c -#define MV64460_SDRAM_ADDR_CONTROL 0x1410 -#define MV64460_SDRAM_OPEN_PAGES_CONTROL 0x1414 -#define MV64460_SDRAM_OPERATION 0x1418 -#define MV64460_SDRAM_MODE 0x141c -#define MV64460_EXTENDED_DRAM_MODE 0x1420 -#define MV64460_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430 -#define MV64460_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434 -#define MV64460_SDRAM_CROSS_BAR_TIMEOUT 0x1438 -#define MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0 -#define MV64460_SDRAM_DATA_PADS_CALIBRATION 0x14c4 - -/****************************************/ -/* SDRAM Error Report */ -/****************************************/ - -#define MV64460_SDRAM_ERROR_DATA_LOW 0x1444 -#define MV64460_SDRAM_ERROR_DATA_HIGH 0x1440 -#define MV64460_SDRAM_ERROR_ADDR 0x1450 -#define MV64460_SDRAM_RECEIVED_ECC 0x1448 -#define MV64460_SDRAM_CALCULATED_ECC 0x144c -#define MV64460_SDRAM_ECC_CONTROL 0x1454 -#define MV64460_SDRAM_ECC_ERROR_COUNTER 0x1458 - -/******************************************/ -/* Controlled Delay Line (CDL) Registers */ -/******************************************/ - -#define MV64460_DFCDL_CONFIG0 0x1480 -#define MV64460_DFCDL_CONFIG1 0x1484 -#define MV64460_DLL_WRITE 0x1488 -#define MV64460_DLL_READ 0x148c -#define MV64460_SRAM_ADDR 0x1490 -#define MV64460_SRAM_DATA0 0x1494 -#define MV64460_SRAM_DATA1 0x1498 -#define MV64460_SRAM_DATA2 0x149c -#define MV64460_DFCL_PROBE 0x14a0 - -/******************************************/ -/* Debug Registers */ -/******************************************/ - -#define MV64460_DUNIT_DEBUG_LOW 0x1460 -#define MV64460_DUNIT_DEBUG_HIGH 0x1464 -#define MV64460_DUNIT_MMASK 0X1b40 - -/****************************************/ -/* Device Parameters */ -/****************************************/ - -#define MV64460_DEVICE_BANK0_PARAMETERS 0x45c -#define MV64460_DEVICE_BANK1_PARAMETERS 0x460 -#define MV64460_DEVICE_BANK2_PARAMETERS 0x464 -#define MV64460_DEVICE_BANK3_PARAMETERS 0x468 -#define MV64460_DEVICE_BOOT_BANK_PARAMETERS 0x46c -#define MV64460_DEVICE_INTERFACE_CONTROL 0x4c0 -#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8 -#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc -#define MV64460_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4 - -/****************************************/ -/* Device interrupt registers */ -/****************************************/ - -#define MV64460_DEVICE_INTERRUPT_CAUSE 0x4d0 -#define MV64460_DEVICE_INTERRUPT_MASK 0x4d4 -#define MV64460_DEVICE_ERROR_ADDR 0x4d8 -#define MV64460_DEVICE_ERROR_DATA 0x4dc -#define MV64460_DEVICE_ERROR_PARITY 0x4e0 - -/****************************************/ -/* Device debug registers */ -/****************************************/ - -#define MV64460_DEVICE_DEBUG_LOW 0x4e4 -#define MV64460_DEVICE_DEBUG_HIGH 0x4e8 -#define MV64460_RUNIT_MMASK 0x4f0 - -/****************************************/ -/* PCI Slave Address Decoding registers */ -/****************************************/ - -#define MV64460_PCI_0_CS_0_BANK_SIZE 0xc08 -#define MV64460_PCI_1_CS_0_BANK_SIZE 0xc88 -#define MV64460_PCI_0_CS_1_BANK_SIZE 0xd08 -#define MV64460_PCI_1_CS_1_BANK_SIZE 0xd88 -#define MV64460_PCI_0_CS_2_BANK_SIZE 0xc0c -#define MV64460_PCI_1_CS_2_BANK_SIZE 0xc8c -#define MV64460_PCI_0_CS_3_BANK_SIZE 0xd0c -#define MV64460_PCI_1_CS_3_BANK_SIZE 0xd8c -#define MV64460_PCI_0_DEVCS_0_BANK_SIZE 0xc10 -#define MV64460_PCI_1_DEVCS_0_BANK_SIZE 0xc90 -#define MV64460_PCI_0_DEVCS_1_BANK_SIZE 0xd10 -#define MV64460_PCI_1_DEVCS_1_BANK_SIZE 0xd90 -#define MV64460_PCI_0_DEVCS_2_BANK_SIZE 0xd18 -#define MV64460_PCI_1_DEVCS_2_BANK_SIZE 0xd98 -#define MV64460_PCI_0_DEVCS_3_BANK_SIZE 0xc14 -#define MV64460_PCI_1_DEVCS_3_BANK_SIZE 0xc94 -#define MV64460_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14 -#define MV64460_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94 -#define MV64460_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c -#define MV64460_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c -#define MV64460_PCI_0_P2P_MEM1_BAR_SIZE 0xd20 -#define MV64460_PCI_1_P2P_MEM1_BAR_SIZE 0xda0 -#define MV64460_PCI_0_P2P_I_O_BAR_SIZE 0xd24 -#define MV64460_PCI_1_P2P_I_O_BAR_SIZE 0xda4 -#define MV64460_PCI_0_CPU_BAR_SIZE 0xd28 -#define MV64460_PCI_1_CPU_BAR_SIZE 0xda8 -#define MV64460_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00 -#define MV64460_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80 -#define MV64460_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c -#define MV64460_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c -#define MV64460_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c -#define MV64460_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc -#define MV64460_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48 -#define MV64460_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8 -#define MV64460_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48 -#define MV64460_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8 -#define MV64460_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c -#define MV64460_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc -#define MV64460_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c -#define MV64460_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc -#define MV64460_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04 -#define MV64460_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84 -#define MV64460_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08 -#define MV64460_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88 -#define MV64460_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C -#define MV64460_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C -#define MV64460_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10 -#define MV64460_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90 -#define MV64460_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50 -#define MV64460_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0 -#define MV64460_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50 -#define MV64460_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0 -#define MV64460_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58 -#define MV64460_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8 -#define MV64460_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54 -#define MV64460_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4 -#define MV64460_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54 -#define MV64460_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4 -#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c -#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc -#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60 -#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0 -#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64 -#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4 -#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68 -#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8 -#define MV64460_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c -#define MV64460_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec -#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70 -#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0 -#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74 -#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4 -#define MV64460_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00 -#define MV64460_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80 -#define MV64460_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38 -#define MV64460_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8 -#define MV64460_PCI_0_ADDR_DECODE_CONTROL 0xd3c -#define MV64460_PCI_1_ADDR_DECODE_CONTROL 0xdbc -#define MV64460_PCI_0_HEADERS_RETARGET_CONTROL 0xF40 -#define MV64460_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0 -#define MV64460_PCI_0_HEADERS_RETARGET_BASE 0xF44 -#define MV64460_PCI_1_HEADERS_RETARGET_BASE 0xFc4 -#define MV64460_PCI_0_HEADERS_RETARGET_HIGH 0xF48 -#define MV64460_PCI_1_HEADERS_RETARGET_HIGH 0xFc8 - -/***********************************/ -/* PCI Control Register Map */ -/***********************************/ - -#define MV64460_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20 -#define MV64460_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0 -#define MV64460_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C -#define MV64460_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C -#define MV64460_PCI_0_COMMAND 0xc00 -#define MV64460_PCI_1_COMMAND 0xc80 -#define MV64460_PCI_0_MODE 0xd00 -#define MV64460_PCI_1_MODE 0xd80 -#define MV64460_PCI_0_RETRY 0xc04 -#define MV64460_PCI_1_RETRY 0xc84 -#define MV64460_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04 -#define MV64460_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84 -#define MV64460_PCI_0_MSI_TRIGGER_TIMER 0xc38 -#define MV64460_PCI_1_MSI_TRIGGER_TIMER 0xcb8 -#define MV64460_PCI_0_ARBITER_CONTROL 0x1d00 -#define MV64460_PCI_1_ARBITER_CONTROL 0x1d80 -#define MV64460_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08 -#define MV64460_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88 -#define MV64460_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c -#define MV64460_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c -#define MV64460_PCI_0_CROSS_BAR_TIMEOUT 0x1d04 -#define MV64460_PCI_1_CROSS_BAR_TIMEOUT 0x1d84 -#define MV64460_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18 -#define MV64460_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98 -#define MV64460_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10 -#define MV64460_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90 -#define MV64460_PCI_0_P2P_CONFIG 0x1d14 -#define MV64460_PCI_1_P2P_CONFIG 0x1d94 - -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04 -#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14 -#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24 -#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34 -#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44 -#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54 -#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58 - -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84 -#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94 -#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 -#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 -#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 -#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 -#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8 - -/****************************************/ -/* PCI Configuration Access Registers */ -/****************************************/ - -#define MV64460_PCI_0_CONFIG_ADDR 0xcf8 -#define MV64460_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc -#define MV64460_PCI_1_CONFIG_ADDR 0xc78 -#define MV64460_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c -#define MV64460_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34 -#define MV64460_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4 - -/****************************************/ -/* PCI Error Report Registers */ -/****************************************/ - -#define MV64460_PCI_0_SERR_MASK 0xc28 -#define MV64460_PCI_1_SERR_MASK 0xca8 -#define MV64460_PCI_0_ERROR_ADDR_LOW 0x1d40 -#define MV64460_PCI_1_ERROR_ADDR_LOW 0x1dc0 -#define MV64460_PCI_0_ERROR_ADDR_HIGH 0x1d44 -#define MV64460_PCI_1_ERROR_ADDR_HIGH 0x1dc4 -#define MV64460_PCI_0_ERROR_ATTRIBUTE 0x1d48 -#define MV64460_PCI_1_ERROR_ATTRIBUTE 0x1dc8 -#define MV64460_PCI_0_ERROR_COMMAND 0x1d50 -#define MV64460_PCI_1_ERROR_COMMAND 0x1dd0 -#define MV64460_PCI_0_ERROR_CAUSE 0x1d58 -#define MV64460_PCI_1_ERROR_CAUSE 0x1dd8 -#define MV64460_PCI_0_ERROR_MASK 0x1d5c -#define MV64460_PCI_1_ERROR_MASK 0x1ddc - -/****************************************/ -/* PCI Debug Registers */ -/****************************************/ - -#define MV64460_PCI_0_MMASK 0X1D24 -#define MV64460_PCI_1_MMASK 0X1DA4 - -/*********************************************/ -/* PCI Configuration, Function 0, Registers */ -/*********************************************/ - -#define MV64460_PCI_DEVICE_AND_VENDOR_ID 0x000 -#define MV64460_PCI_STATUS_AND_COMMAND 0x004 -#define MV64460_PCI_CLASS_CODE_AND_REVISION_ID 0x008 -#define MV64460_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C - -#define MV64460_PCI_SCS_0_BASE_ADDR_LOW 0x010 -#define MV64460_PCI_SCS_0_BASE_ADDR_HIGH 0x014 -#define MV64460_PCI_SCS_1_BASE_ADDR_LOW 0x018 -#define MV64460_PCI_SCS_1_BASE_ADDR_HIGH 0x01C -#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020 -#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024 -#define MV64460_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c -#define MV64460_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 -#define MV64460_PCI_CAPABILTY_LIST_POINTER 0x034 -#define MV64460_PCI_INTERRUPT_PIN_AND_LINE 0x03C - /* capability list */ -#define MV64460_PCI_POWER_MANAGEMENT_CAPABILITY 0x040 -#define MV64460_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 -#define MV64460_PCI_VPD_ADDR 0x048 -#define MV64460_PCI_VPD_DATA 0x04c -#define MV64460_PCI_MSI_MESSAGE_CONTROL 0x050 -#define MV64460_PCI_MSI_MESSAGE_ADDR 0x054 -#define MV64460_PCI_MSI_MESSAGE_UPPER_ADDR 0x058 -#define MV64460_PCI_MSI_MESSAGE_DATA 0x05c -#define MV64460_PCI_X_COMMAND 0x060 -#define MV64460_PCI_X_STATUS 0x064 -#define MV64460_PCI_COMPACT_PCI_HOT_SWAP 0x068 - -/***********************************************/ -/* PCI Configuration, Function 1, Registers */ -/***********************************************/ - -#define MV64460_PCI_SCS_2_BASE_ADDR_LOW 0x110 -#define MV64460_PCI_SCS_2_BASE_ADDR_HIGH 0x114 -#define MV64460_PCI_SCS_3_BASE_ADDR_LOW 0x118 -#define MV64460_PCI_SCS_3_BASE_ADDR_HIGH 0x11c -#define MV64460_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120 -#define MV64460_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124 - -/***********************************************/ -/* PCI Configuration, Function 2, Registers */ -/***********************************************/ - -#define MV64460_PCI_DEVCS_0_BASE_ADDR_LOW 0x210 -#define MV64460_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214 -#define MV64460_PCI_DEVCS_1_BASE_ADDR_LOW 0x218 -#define MV64460_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c -#define MV64460_PCI_DEVCS_2_BASE_ADDR_LOW 0x220 -#define MV64460_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224 - -/***********************************************/ -/* PCI Configuration, Function 3, Registers */ -/***********************************************/ - -#define MV64460_PCI_DEVCS_3_BASE_ADDR_LOW 0x310 -#define MV64460_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314 -#define MV64460_PCI_BOOT_CS_BASE_ADDR_LOW 0x318 -#define MV64460_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c -#define MV64460_PCI_CPU_BASE_ADDR_LOW 0x220 -#define MV64460_PCI_CPU_BASE_ADDR_HIGH 0x224 - -/***********************************************/ -/* PCI Configuration, Function 4, Registers */ -/***********************************************/ - -#define MV64460_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410 -#define MV64460_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414 -#define MV64460_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418 -#define MV64460_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c -#define MV64460_PCI_P2P_I_O_BASE_ADDR 0x420 -#define MV64460_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424 - -/****************************************/ -/* Messaging Unit Registers (I20) */ -/****************************************/ - -#define MV64460_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010 -#define MV64460_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C -#define MV64460_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020 -#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024 -#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028 -#define MV64460_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C -#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030 -#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034 -#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040 -#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044 -#define MV64460_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050 -#define MV64460_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054 -#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060 -#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064 -#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068 -#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C -#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070 -#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074 -#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8 -#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC - -#define MV64460_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090 -#define MV64460_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C -#define MV64460_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0 -#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4 -#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8 -#define MV64460_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC -#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0 -#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4 -#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0 -#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4 -#define MV64460_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0 -#define MV64460_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4 -#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0 -#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4 -#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8 -#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC -#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0 -#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4 -#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078 -#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C - -#define MV64460_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10 -#define MV64460_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C -#define MV64460_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20 -#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24 -#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28 -#define MV64460_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C -#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30 -#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34 -#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40 -#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44 -#define MV64460_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50 -#define MV64460_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54 -#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60 -#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64 -#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68 -#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C -#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70 -#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74 -#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8 -#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC -#define MV64460_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90 -#define MV64460_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C -#define MV64460_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0 -#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4 -#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8 -#define MV64460_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC -#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0 -#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4 -#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0 -#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4 -#define MV64460_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0 -#define MV64460_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4 -#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0 -#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4 -#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8 -#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC -#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0 -#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4 -#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78 -#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C - -/****************************************/ -/* Ethernet Unit Registers */ -/****************************************/ - -#define MV64460_ETH_PHY_ADDR_REG 0x2000 -#define MV64460_ETH_SMI_REG 0x2004 -#define MV64460_ETH_UNIT_DEFAULT_ADDR_REG 0x2008 -#define MV64460_ETH_UNIT_DEFAULTID_REG 0x200c -#define MV64460_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080 -#define MV64460_ETH_UNIT_INTERRUPT_MASK_REG 0x2084 -#define MV64460_ETH_UNIT_INTERNAL_USE_REG 0x24fc -#define MV64460_ETH_UNIT_ERROR_ADDR_REG 0x2094 -#define MV64460_ETH_BAR_0 0x2200 -#define MV64460_ETH_BAR_1 0x2208 -#define MV64460_ETH_BAR_2 0x2210 -#define MV64460_ETH_BAR_3 0x2218 -#define MV64460_ETH_BAR_4 0x2220 -#define MV64460_ETH_BAR_5 0x2228 -#define MV64460_ETH_SIZE_REG_0 0x2204 -#define MV64460_ETH_SIZE_REG_1 0x220c -#define MV64460_ETH_SIZE_REG_2 0x2214 -#define MV64460_ETH_SIZE_REG_3 0x221c -#define MV64460_ETH_SIZE_REG_4 0x2224 -#define MV64460_ETH_SIZE_REG_5 0x222c -#define MV64460_ETH_HEADERS_RETARGET_BASE_REG 0x2230 -#define MV64460_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234 -#define MV64460_ETH_HIGH_ADDR_REMAP_REG_0 0x2280 -#define MV64460_ETH_HIGH_ADDR_REMAP_REG_1 0x2284 -#define MV64460_ETH_HIGH_ADDR_REMAP_REG_2 0x2288 -#define MV64460_ETH_HIGH_ADDR_REMAP_REG_3 0x228c -#define MV64460_ETH_BASE_ADDR_ENABLE_REG 0x2290 -#define MV64460_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2)) -#define MV64460_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7)) -#define MV64460_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10)) -#define MV64460_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10)) -#define MV64460_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10)) -#define MV64460_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10)) -#define MV64460_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10)) -#define MV64460_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10)) -#define MV64460_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10)) -#define MV64460_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10)) -#define MV64460_ETH_DSCP_0(port) (0x2420 + (port<<10)) -#define MV64460_ETH_DSCP_1(port) (0x2424 + (port<<10)) -#define MV64460_ETH_DSCP_2(port) (0x2428 + (port<<10)) -#define MV64460_ETH_DSCP_3(port) (0x242c + (port<<10)) -#define MV64460_ETH_DSCP_4(port) (0x2430 + (port<<10)) -#define MV64460_ETH_DSCP_5(port) (0x2434 + (port<<10)) -#define MV64460_ETH_DSCP_6(port) (0x2438 + (port<<10)) -#define MV64460_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10)) -#define MV64460_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10)) -#define MV64460_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10)) -#define MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10)) -#define MV64460_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10)) -#define MV64460_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10)) -#define MV64460_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10)) -#define MV64460_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10)) -#define MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10)) -#define MV64460_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10)) -#define MV64460_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10)) -#define MV64460_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10)) -#define MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10)) -#define MV64460_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10)) -#define MV64460_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10) -#define MV64460_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10)) -#define MV64460_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10)) -#define MV64460_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10)) -#define MV64460_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10)) -#define MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10)) -#define MV64460_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10)) -#define MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10)) -#define MV64460_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10)) -#define MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10)) -#define MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10)) -#define MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10)) - -/*******************************************/ -/* CUNIT Registers */ -/*******************************************/ - - /* Address Decoding Register Map */ - -#define MV64460_CUNIT_BASE_ADDR_REG0 0xf200 -#define MV64460_CUNIT_BASE_ADDR_REG1 0xf208 -#define MV64460_CUNIT_BASE_ADDR_REG2 0xf210 -#define MV64460_CUNIT_BASE_ADDR_REG3 0xf218 -#define MV64460_CUNIT_SIZE0 0xf204 -#define MV64460_CUNIT_SIZE1 0xf20c -#define MV64460_CUNIT_SIZE2 0xf214 -#define MV64460_CUNIT_SIZE3 0xf21c -#define MV64460_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240 -#define MV64460_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244 -#define MV64460_CUNIT_BASE_ADDR_ENABLE_REG 0xf250 -#define MV64460_MPSC0_ACCESS_PROTECTION_REG 0xf254 -#define MV64460_MPSC1_ACCESS_PROTECTION_REG 0xf258 -#define MV64460_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C - - /* Error Report Registers */ - -#define MV64460_CUNIT_INTERRUPT_CAUSE_REG 0xf310 -#define MV64460_CUNIT_INTERRUPT_MASK_REG 0xf314 -#define MV64460_CUNIT_ERROR_ADDR 0xf318 - - /* Cunit Control Registers */ - -#define MV64460_CUNIT_ARBITER_CONTROL_REG 0xf300 -#define MV64460_CUNIT_CONFIG_REG 0xb40c -#define MV64460_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304 - - /* Cunit Debug Registers */ - -#define MV64460_CUNIT_DEBUG_LOW 0xf340 -#define MV64460_CUNIT_DEBUG_HIGH 0xf344 -#define MV64460_CUNIT_MMASK 0xf380 - - /* Cunit Base Address Enable Window Bits*/ -#define MV64460_CUNIT_BASE_ADDR_WIN_0_BIT 0x0 -#define MV64460_CUNIT_BASE_ADDR_WIN_1_BIT 0x1 -#define MV64460_CUNIT_BASE_ADDR_WIN_2_BIT 0x2 -#define MV64460_CUNIT_BASE_ADDR_WIN_3_BIT 0x3 - - /* MPSCs Clocks Routing Registers */ - -#define MV64460_MPSC_ROUTING_REG 0xb400 -#define MV64460_MPSC_RX_CLOCK_ROUTING_REG 0xb404 -#define MV64460_MPSC_TX_CLOCK_ROUTING_REG 0xb408 - - /* MPSCs Interrupts Registers */ - -#define MV64460_MPSC_CAUSE_REG(port) (0xb804 + (port<<3)) -#define MV64460_MPSC_MASK_REG(port) (0xb884 + (port<<3)) - -#define MV64460_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12)) -#define MV64460_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12)) -#define MV64460_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG1(port) (0x800c + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG5(port) (0x801c + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG9(port) (0x802c + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12)) - - /* MPSC0 Registers */ - - -/***************************************/ -/* SDMA Registers */ -/***************************************/ - -#define MV64460_SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13)) -#define MV64460_SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13)) -#define MV64460_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13)) -#define MV64460_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13)) -#define MV64460_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13)) - -#define MV64460_SDMA_CAUSE_REG 0xb800 -#define MV64460_SDMA_MASK_REG 0xb880 - - -/****************************************/ -/* SDMA Address Space Targets */ -/****************************************/ - -#define MV64460_SDMA_DRAM_CS_0_TARGET 0x0e00 -#define MV64460_SDMA_DRAM_CS_1_TARGET 0x0d00 -#define MV64460_SDMA_DRAM_CS_2_TARGET 0x0b00 -#define MV64460_SDMA_DRAM_CS_3_TARGET 0x0700 - -#define MV64460_SDMA_DEV_CS_0_TARGET 0x1e01 -#define MV64460_SDMA_DEV_CS_1_TARGET 0x1d01 -#define MV64460_SDMA_DEV_CS_2_TARGET 0x1b01 -#define MV64460_SDMA_DEV_CS_3_TARGET 0x1701 - -#define MV64460_SDMA_BOOT_CS_TARGET 0x0f00 - -#define MV64460_SDMA_SRAM_TARGET 0x0003 -#define MV64460_SDMA_60X_BUS_TARGET 0x4003 - -#define MV64460_PCI_0_TARGET 0x0003 -#define MV64460_PCI_1_TARGET 0x0004 - - -/* Devices BAR and size registers */ - -#define MV64460_DEV_CS0_BASE_ADDR 0x028 -#define MV64460_DEV_CS0_SIZE 0x030 -#define MV64460_DEV_CS1_BASE_ADDR 0x228 -#define MV64460_DEV_CS1_SIZE 0x230 -#define MV64460_DEV_CS2_BASE_ADDR 0x248 -#define MV64460_DEV_CS2_SIZE 0x250 -#define MV64460_DEV_CS3_BASE_ADDR 0x038 -#define MV64460_DEV_CS3_SIZE 0x040 -#define MV64460_BOOTCS_BASE_ADDR 0x238 -#define MV64460_BOOTCS_SIZE 0x240 - -/* SDMA Window access protection */ -#define MV64460_SDMA_WIN_ACCESS_NOT_ALLOWED 0 -#define MV64460_SDMA_WIN_ACCESS_READ_ONLY 1 -#define MV64460_SDMA_WIN_ACCESS_FULL 2 - -/* BRG Interrupts */ - -#define MV64460_BRG_CONFIG_REG(brg) (0xb200 + (brg<<3)) -#define MV64460_BRG_BAUDE_TUNING_REG(brg) (0xb204 + (brg<<3)) -#define MV64460_BRG_CAUSE_REG 0xb834 -#define MV64460_BRG_MASK_REG 0xb8b4 - -/****************************************/ -/* DMA Channel Control */ -/****************************************/ - -#define MV64460_DMA_CHANNEL0_CONTROL 0x840 -#define MV64460_DMA_CHANNEL0_CONTROL_HIGH 0x880 -#define MV64460_DMA_CHANNEL1_CONTROL 0x844 -#define MV64460_DMA_CHANNEL1_CONTROL_HIGH 0x884 -#define MV64460_DMA_CHANNEL2_CONTROL 0x848 -#define MV64460_DMA_CHANNEL2_CONTROL_HIGH 0x888 -#define MV64460_DMA_CHANNEL3_CONTROL 0x84C -#define MV64460_DMA_CHANNEL3_CONTROL_HIGH 0x88C - - -/****************************************/ -/* IDMA Registers */ -/****************************************/ - -#define MV64460_DMA_CHANNEL0_BYTE_COUNT 0x800 -#define MV64460_DMA_CHANNEL1_BYTE_COUNT 0x804 -#define MV64460_DMA_CHANNEL2_BYTE_COUNT 0x808 -#define MV64460_DMA_CHANNEL3_BYTE_COUNT 0x80C -#define MV64460_DMA_CHANNEL0_SOURCE_ADDR 0x810 -#define MV64460_DMA_CHANNEL1_SOURCE_ADDR 0x814 -#define MV64460_DMA_CHANNEL2_SOURCE_ADDR 0x818 -#define MV64460_DMA_CHANNEL3_SOURCE_ADDR 0x81c -#define MV64460_DMA_CHANNEL0_DESTINATION_ADDR 0x820 -#define MV64460_DMA_CHANNEL1_DESTINATION_ADDR 0x824 -#define MV64460_DMA_CHANNEL2_DESTINATION_ADDR 0x828 -#define MV64460_DMA_CHANNEL3_DESTINATION_ADDR 0x82C -#define MV64460_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830 -#define MV64460_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834 -#define MV64460_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838 -#define MV64460_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C -#define MV64460_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870 -#define MV64460_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874 -#define MV64460_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878 -#define MV64460_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C - - /* IDMA Address Decoding Base Address Registers */ - -#define MV64460_DMA_BASE_ADDR_REG0 0xa00 -#define MV64460_DMA_BASE_ADDR_REG1 0xa08 -#define MV64460_DMA_BASE_ADDR_REG2 0xa10 -#define MV64460_DMA_BASE_ADDR_REG3 0xa18 -#define MV64460_DMA_BASE_ADDR_REG4 0xa20 -#define MV64460_DMA_BASE_ADDR_REG5 0xa28 -#define MV64460_DMA_BASE_ADDR_REG6 0xa30 -#define MV64460_DMA_BASE_ADDR_REG7 0xa38 - - /* IDMA Address Decoding Size Address Register */ - -#define MV64460_DMA_SIZE_REG0 0xa04 -#define MV64460_DMA_SIZE_REG1 0xa0c -#define MV64460_DMA_SIZE_REG2 0xa14 -#define MV64460_DMA_SIZE_REG3 0xa1c -#define MV64460_DMA_SIZE_REG4 0xa24 -#define MV64460_DMA_SIZE_REG5 0xa2c -#define MV64460_DMA_SIZE_REG6 0xa34 -#define MV64460_DMA_SIZE_REG7 0xa3C - - /* IDMA Address Decoding High Address Remap and Access - Protection Registers */ - -#define MV64460_DMA_HIGH_ADDR_REMAP_REG0 0xa60 -#define MV64460_DMA_HIGH_ADDR_REMAP_REG1 0xa64 -#define MV64460_DMA_HIGH_ADDR_REMAP_REG2 0xa68 -#define MV64460_DMA_HIGH_ADDR_REMAP_REG3 0xa6C -#define MV64460_DMA_BASE_ADDR_ENABLE_REG 0xa80 -#define MV64460_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70 -#define MV64460_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74 -#define MV64460_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78 -#define MV64460_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c -#define MV64460_DMA_ARBITER_CONTROL 0x860 -#define MV64460_DMA_CROSS_BAR_TIMEOUT 0x8d0 - - /* IDMA Headers Retarget Registers */ - -#define MV64460_DMA_HEADERS_RETARGET_CONTROL 0xa84 -#define MV64460_DMA_HEADERS_RETARGET_BASE 0xa88 - - /* IDMA Interrupt Register */ - -#define MV64460_DMA_INTERRUPT_CAUSE_REG 0x8c0 -#define MV64460_DMA_INTERRUPT_CAUSE_MASK 0x8c4 -#define MV64460_DMA_ERROR_ADDR 0x8c8 -#define MV64460_DMA_ERROR_SELECT 0x8cc - - /* IDMA Debug Register ( for internal use ) */ - -#define MV64460_DMA_DEBUG_LOW 0x8e0 -#define MV64460_DMA_DEBUG_HIGH 0x8e4 -#define MV64460_DMA_SPARE 0xA8C - -/****************************************/ -/* Timer_Counter */ -/****************************************/ - -#define MV64460_TIMER_COUNTER0 0x850 -#define MV64460_TIMER_COUNTER1 0x854 -#define MV64460_TIMER_COUNTER2 0x858 -#define MV64460_TIMER_COUNTER3 0x85C -#define MV64460_TIMER_COUNTER_0_3_CONTROL 0x864 -#define MV64460_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 -#define MV64460_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c - -/****************************************/ -/* Watchdog registers */ -/****************************************/ - -#define MV64460_WATCHDOG_CONFIG_REG 0xb410 -#define MV64460_WATCHDOG_VALUE_REG 0xb414 - -/****************************************/ -/* I2C Registers */ -/****************************************/ - -#define MV64460_I2C_SLAVE_ADDR 0xc000 -#define MV64460_I2C_EXTENDED_SLAVE_ADDR 0xc010 -#define MV64460_I2C_DATA 0xc004 -#define MV64460_I2C_CONTROL 0xc008 -#define MV64460_I2C_STATUS_BAUDE_RATE 0xc00C -#define MV64460_I2C_SOFT_RESET 0xc01c - -/****************************************/ -/* GPP Interface Registers */ -/****************************************/ - -#define MV64460_GPP_IO_CONTROL 0xf100 -#define MV64460_GPP_LEVEL_CONTROL 0xf110 -#define MV64460_GPP_VALUE 0xf104 -#define MV64460_GPP_INTERRUPT_CAUSE 0xf108 -#define MV64460_GPP_INTERRUPT_MASK0 0xf10c -#define MV64460_GPP_INTERRUPT_MASK1 0xf114 -#define MV64460_GPP_VALUE_SET 0xf118 -#define MV64460_GPP_VALUE_CLEAR 0xf11c - -/****************************************/ -/* Interrupt Controller Registers */ -/****************************************/ - -/****************************************/ -/* Interrupts */ -/****************************************/ - -#define MV64460_MAIN_INTERRUPT_CAUSE_LOW 0x004 -#define MV64460_MAIN_INTERRUPT_CAUSE_HIGH 0x00c -#define MV64460_CPU_INTERRUPT0_MASK_LOW 0x014 -#define MV64460_CPU_INTERRUPT0_MASK_HIGH 0x01c -#define MV64460_CPU_INTERRUPT0_SELECT_CAUSE 0x024 -#define MV64460_CPU_INTERRUPT1_MASK_LOW 0x034 -#define MV64460_CPU_INTERRUPT1_MASK_HIGH 0x03c -#define MV64460_CPU_INTERRUPT1_SELECT_CAUSE 0x044 -#define MV64460_INTERRUPT0_MASK_0_LOW 0x054 -#define MV64460_INTERRUPT0_MASK_0_HIGH 0x05c -#define MV64460_INTERRUPT0_SELECT_CAUSE 0x064 -#define MV64460_INTERRUPT1_MASK_0_LOW 0x074 -#define MV64460_INTERRUPT1_MASK_0_HIGH 0x07c -#define MV64460_INTERRUPT1_SELECT_CAUSE 0x084 - -/****************************************/ -/* MPP Interface Registers */ -/****************************************/ - -#define MV64460_MPP_CONTROL0 0xf000 -#define MV64460_MPP_CONTROL1 0xf004 -#define MV64460_MPP_CONTROL2 0xf008 -#define MV64460_MPP_CONTROL3 0xf00c - -/****************************************/ -/* Serial Initialization registers */ -/****************************************/ - -#define MV64460_SERIAL_INIT_LAST_DATA 0xf324 -#define MV64460_SERIAL_INIT_CONTROL 0xf328 -#define MV64460_SERIAL_INIT_STATUS 0xf32c - - -#endif /* __INCgt64460rh */ diff --git a/board/Marvell/db64460/pci.c b/board/Marvell/db64460/pci.c deleted file mode 100644 index 8c25198..0000000 --- a/board/Marvell/db64460/pci.c +++ /dev/null @@ -1,923 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* PCI.c - PCI functions */ - - -#include <common.h> -#include <pci.h> - -#include "../include/pci.h" - -#undef DEBUG -#undef IDE_SET_NATIVE_MODE -static unsigned int local_buses[] = { 0, 0 }; - -static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = { - {0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 }, - {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 }, -}; - - -#ifdef DEBUG -static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE }; -static void gt_pci_bus_mode_display (PCI_HOST host) -{ - unsigned int mode; - - - mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4; - switch (mode) { - case 0: - printf ("PCI %d bus mode: Conventional PCI\n", host); - break; - case 1: - printf ("PCI %d bus mode: 66 MHz PCIX\n", host); - break; - case 2: - printf ("PCI %d bus mode: 100 MHz PCIX\n", host); - break; - case 3: - printf ("PCI %d bus mode: 133 MHz PCIX\n", host); - break; - default: - printf ("Unknown BUS %d\n", mode); - } -} -#endif - -static const unsigned int pci_p2p_configuration_reg[] = { - PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION -}; - -static const unsigned int pci_configuration_address[] = { - PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS -}; - -static const unsigned int pci_configuration_data[] = { - PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, - PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER -}; - -static const unsigned int pci_error_cause_reg[] = { - PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE -}; - -static const unsigned int pci_arbiter_control[] = { - PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL -}; - -static const unsigned int pci_address_space_en[] = { - PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE -}; - -static const unsigned int pci_snoop_control_base_0_low[] = { - PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW -}; -static const unsigned int pci_snoop_control_top_0[] = { - PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0 -}; - -static const unsigned int pci_access_control_base_0_low[] = { - PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW -}; -static const unsigned int pci_access_control_top_0[] = { - PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0 -}; - -static const unsigned int pci_scs_bank_size[2][4] = { - {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE, - PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE}, - {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE, - PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE} -}; - -static const unsigned int pci_p2p_configuration[] = { - PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION -}; - - -/******************************************************************** -* pciWriteConfigReg - Write to a PCI configuration register -* - Make sure the GT is configured as a master before writing -* to another device on the PCI. -* - The function takes care of Big/Little endian conversion. -* -* -* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec -* (or any other PCI device spec) -* pciDevNum: The device number needs to be addressed. -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum, unsigned int data) -{ - volatile unsigned int DataForAddrReg; - unsigned int functionNum; - unsigned int busNum = 0; - unsigned int addr; - - if (pciDevNum > 32) /* illegal device Number */ - return; - if (pciDevNum == SELF) { /* configure our configuration space. */ - pciDevNum = - (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & - 0x1f; - busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & - 0xff0000; - } - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xfc; - DataForAddrReg = - (regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); - GT_REG_READ (pci_configuration_address[host], &addr); - if (addr != DataForAddrReg) - return; - GT_REG_WRITE (pci_configuration_data[host], data); -} - -/******************************************************************** -* pciReadConfigReg - Read from a PCI0 configuration register -* - Make sure the GT is configured as a master before reading -* from another device on the PCI. -* - The function takes care of Big/Little endian conversion. -* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec) -* pciDevNum: The device number needs to be addressed. -* RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum) -{ - volatile unsigned int DataForAddrReg; - unsigned int data; - unsigned int functionNum; - unsigned int busNum = 0; - - if (pciDevNum > 32) /* illegal device Number */ - return 0xffffffff; - if (pciDevNum == SELF) { /* configure our configuration space. */ - pciDevNum = - (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & - 0x1f; - busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & - 0xff0000; - } - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xfc; - DataForAddrReg = - (regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); - GT_REG_READ (pci_configuration_address[host], &data); - if (data != DataForAddrReg) - return 0xffffffff; - GT_REG_READ (pci_configuration_data[host], &data); - return data; -} - -/******************************************************************** -* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where -* the agent is placed on another Bus. For more -* information read P2P in the PCI spec. -* -* Inputs: unsigned int regOffset - The register offset as it apears in the -* GT spec (or any other PCI device spec). -* unsigned int pciDevNum - The device number needs to be addressed. -* unsigned int busNum - On which bus does the Target agent connect -* to. -* unsigned int data - data to be written. -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -* The configuration Address is configure as type-I (bits[1:0] = '01') due to -* PCI spec referring to P2P. -* -*********************************************************************/ -void pciOverBridgeWriteConfigReg (PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum, unsigned int data) -{ - unsigned int DataForReg; - unsigned int functionNum; - - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - busNum = busNum << 16; - if (pciDevNum == SELF) { /* This board */ - DataForReg = (regOffset | pciDevNum | functionNum) | BIT0; - } else { - DataForReg = (regOffset | pciDevNum | functionNum | busNum) | - BIT31 | BIT0; - } - GT_REG_WRITE (pci_configuration_address[host], DataForReg); - GT_REG_WRITE (pci_configuration_data[host], data); -} - - -/******************************************************************** -* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where -* the agent target locate on another PCI bus. -* - Make sure the GT is configured as a master -* before reading from another device on the PCI. -* - The function takes care of Big/Little endian -* conversion. -* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec). (configuration register offset.) -* pciDevNum: The device number needs to be addressed. -* busNum: the Bus number where the agent is place. -* RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -unsigned int pciOverBridgeReadConfigReg (PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum) -{ - unsigned int DataForReg; - unsigned int data; - unsigned int functionNum; - - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - busNum = busNum << 16; - if (pciDevNum == SELF) { /* This board */ - DataForReg = (regOffset | pciDevNum | functionNum) | BIT31; - } else { /* agent on another bus */ - - DataForReg = (regOffset | pciDevNum | functionNum | busNum) | - BIT0 | BIT31; - } - GT_REG_WRITE (pci_configuration_address[host], DataForReg); - GT_REG_READ (pci_configuration_data[host], &data); - return data; -} - - -/******************************************************************** -* pciGetRegOffset - Gets the register offset for this region config. -* -* INPUT: Bus, Region - The bus and region we ask for its base address. -* OUTPUT: N/A -* RETURNS: PCI register base address -*********************************************************************/ -static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region) -{ - switch (host) { - case PCI_HOST0: - switch (region) { - case PCI_IO: - return PCI_0I_O_LOW_DECODE_ADDRESS; - case PCI_REGION0: - return PCI_0MEMORY0_LOW_DECODE_ADDRESS; - case PCI_REGION1: - return PCI_0MEMORY1_LOW_DECODE_ADDRESS; - case PCI_REGION2: - return PCI_0MEMORY2_LOW_DECODE_ADDRESS; - case PCI_REGION3: - return PCI_0MEMORY3_LOW_DECODE_ADDRESS; - } - case PCI_HOST1: - switch (region) { - case PCI_IO: - return PCI_1I_O_LOW_DECODE_ADDRESS; - case PCI_REGION0: - return PCI_1MEMORY0_LOW_DECODE_ADDRESS; - case PCI_REGION1: - return PCI_1MEMORY1_LOW_DECODE_ADDRESS; - case PCI_REGION2: - return PCI_1MEMORY2_LOW_DECODE_ADDRESS; - case PCI_REGION3: - return PCI_1MEMORY3_LOW_DECODE_ADDRESS; - } - } - return PCI_0MEMORY0_LOW_DECODE_ADDRESS; -} - -static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region) -{ - switch (host) { - case PCI_HOST0: - switch (region) { - case PCI_IO: - return PCI_0I_O_ADDRESS_REMAP; - case PCI_REGION0: - return PCI_0MEMORY0_ADDRESS_REMAP; - case PCI_REGION1: - return PCI_0MEMORY1_ADDRESS_REMAP; - case PCI_REGION2: - return PCI_0MEMORY2_ADDRESS_REMAP; - case PCI_REGION3: - return PCI_0MEMORY3_ADDRESS_REMAP; - } - case PCI_HOST1: - switch (region) { - case PCI_IO: - return PCI_1I_O_ADDRESS_REMAP; - case PCI_REGION0: - return PCI_1MEMORY0_ADDRESS_REMAP; - case PCI_REGION1: - return PCI_1MEMORY1_ADDRESS_REMAP; - case PCI_REGION2: - return PCI_1MEMORY2_ADDRESS_REMAP; - case PCI_REGION3: - return PCI_1MEMORY3_ADDRESS_REMAP; - } - } - return PCI_0MEMORY0_ADDRESS_REMAP; -} - -/******************************************************************** -* pciGetBaseAddress - Gets the base address of a PCI. -* - If the PCI size is 0 then this base address has no meaning!!! -* -* -* INPUT: Bus, Region - The bus and region we ask for its base address. -* OUTPUT: N/A -* RETURNS: PCI base address. -*********************************************************************/ -unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region) -{ - unsigned int regBase; - unsigned int regEnd; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, ®Base); - GT_REG_READ (regOffset + 8, ®End); - - if (regEnd <= regBase) - return 0xffffffff; /* ERROR !!! */ - - regBase = regBase << 16; - return regBase; -} - -bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase, - unsigned int bankBase, unsigned int bankLength) -{ - unsigned int low = 0xfff; - unsigned int high = 0x0; - unsigned int regOffset = pciGetRegOffset (host, region); - unsigned int remapOffset = pciGetRemapOffset (host, region); - - if (bankLength != 0) { - low = (bankBase >> 16) & 0xffff; - high = ((bankBase + bankLength) >> 16) - 1; - } - - GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */ - GT_REG_WRITE (regOffset + 8, high); - - if (bankLength != 0) { /* must do AFTER writing maps */ - GT_REG_WRITE (remapOffset, remapBase >> 16); /* sorry, 32 bits only. - dont support upper 32 - in this driver */ - } - return true; -} - -unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region) -{ - unsigned int low; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, &low); - return (low & 0xffff) << 16; -} - -unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region) -{ - unsigned int low, high; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, &low); - GT_REG_READ (regOffset + 8, &high); - return ((high & 0xffff) + 1) << 16; -} - - -/* ronen - 7/Dec/03*/ -/******************************************************************** -* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS. -* Inputs: one of the PCI BAR -*********************************************************************/ -void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR) -{ - RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR); -} - -void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR) -{ - SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR); -} - -/******************************************************************** -* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave. -* -* Inputs: base and size of PCI SCS -*********************************************************************/ -void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank, - unsigned int pciDramBase, unsigned int pciDramSize) -{ - /*ronen different function for 3rd bank. */ - unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8; - - pciDramBase = pciDramBase & 0xfffff000; - pciDramBase = pciDramBase | (pciReadConfigReg (host, - PCI_SCS_0_BASE_ADDRESS - + offset, - SELF) & 0x00000fff); - pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF, - pciDramBase); - if (pciDramSize == 0) - pciDramSize++; - GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1); - gtPciEnableInternalBAR (host, bank); -} - -/******************************************************************** -* pciSetRegionFeatures - This function modifys one of the 8 regions with -* feature bits given as an input. -* - Be advised to check the spec before modifying them. -* Inputs: PCI_PROTECT_REGION region - one of the eight regions. -* unsigned int features - See file: pci.h there are defintion for those -* region features. -* unsigned int baseAddress - The region base Address. -* unsigned int topAddress - The region top Address. -* Returns: false if one of the parameters is erroneous true otherwise. -*********************************************************************/ -bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region, - unsigned int features, unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int accessLow; - unsigned int accessHigh; - unsigned int accessTop = baseAddress + regionLength; - - if (regionLength == 0) { /* close the region. */ - pciDisableAccessRegion (host, region); - return true; - } - /* base Address is store is bits [11:0] */ - accessLow = (baseAddress & 0xfff00000) >> 20; - /* All the features are update according to the defines in pci.h (to be on - the safe side we disable bits: [11:0] */ - accessLow = accessLow | (features & 0xfffff000); - /* write to the Low Access Region register */ - GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, - accessLow); - - accessHigh = (accessTop & 0xfff00000) >> 20; - - /* write to the High Access Region register */ - GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, - accessHigh - 1); - return true; -} - -/******************************************************************** -* pciDisableAccessRegion - Disable The given Region by writing MAX size -* to its low Address and MIN size to its high Address. -* -* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled. -* Returns: N/A. -*********************************************************************/ -void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region) -{ - /* writing back the registers default values. */ - GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, - 0x01001fff); - GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0); -} - -/******************************************************************** -* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism. -* -* Inputs: N/A -* Returns: true. -*********************************************************************/ -bool pciArbiterEnable (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31); - return true; -} - -/******************************************************************** -* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism. -* -* Inputs: N/A -* Returns: true -*********************************************************************/ -bool pciArbiterDisable (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff); - return true; -} - -/******************************************************************** -* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low) -* -* Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent. -* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent. -* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent. -* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent. -* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent. -* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent. -* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent. -* Returns: true -*********************************************************************/ -bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent, - PCI_AGENT_PRIO externalAgent0, - PCI_AGENT_PRIO externalAgent1, - PCI_AGENT_PRIO externalAgent2, - PCI_AGENT_PRIO externalAgent3, - PCI_AGENT_PRIO externalAgent4, - PCI_AGENT_PRIO externalAgent5) -{ - unsigned int regData; - unsigned int writeData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - writeData = (internalAgent << 7) + (externalAgent0 << 8) + - (externalAgent1 << 9) + (externalAgent2 << 10) + - (externalAgent3 << 11) + (externalAgent4 << 12) + - (externalAgent5 << 13); - regData = (regData & 0xffffc07f) | writeData; - GT_REG_WRITE (pci_arbiter_control[host], regData & regData); - return true; -} - -/******************************************************************** -* pciParkingDisable - Park on last option disable, with this function you can -* disable the park on last mechanism for each agent. -* disabling this option for all agents results parking -* on the internal master. -* -* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent. -* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. -* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. -* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. -* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. -* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. -* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. -* Returns: true -*********************************************************************/ -bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent, - PCI_AGENT_PARK externalAgent0, - PCI_AGENT_PARK externalAgent1, - PCI_AGENT_PARK externalAgent2, - PCI_AGENT_PARK externalAgent3, - PCI_AGENT_PARK externalAgent4, - PCI_AGENT_PARK externalAgent5) -{ - unsigned int regData; - unsigned int writeData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - writeData = (internalAgent << 14) + (externalAgent0 << 15) + - (externalAgent1 << 16) + (externalAgent2 << 17) + - (externalAgent3 << 18) + (externalAgent4 << 19) + - (externalAgent5 << 20); - regData = (regData & ~(0x7f << 14)) | writeData; - GT_REG_WRITE (pci_arbiter_control[host], regData); - return true; -} - -/******************************************************************** -* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to -* respond to grant assertion within a window specified in -* the input value: 'brokenValue'. -* -* Inputs: unsigned char brokenValue - A value which limits the Master to hold the -* grant without asserting frame. -* Returns: Error for illegal broken value otherwise true. -*********************************************************************/ -bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue) -{ - unsigned int data; - unsigned int regData; - - if (brokenValue > 0xf) - return false; /* brokenValue must be 4 bit */ - data = brokenValue << 3; - GT_REG_READ (pci_arbiter_control[host], ®Data); - regData = (regData & 0xffffff87) | data; - GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1); - return true; -} - -/******************************************************************** -* pciDisableBrokenAgentDetection - This function disable the Broken agent -* Detection mechanism. -* NOTE: This operation may cause a dead lock on the -* pci0 arbitration. -* -* Inputs: N/A -* Returns: true. -*********************************************************************/ -bool pciDisableBrokenAgentDetection (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - regData = regData & 0xfffffffd; - GT_REG_WRITE (pci_arbiter_control[host], regData); - return true; -} - -/******************************************************************** -* pciP2PConfig - This function set the PCI_n P2P configurate. -* For more information on the P2P read PCI spec. -* -* Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower -* Boundry. -* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper -* Boundry. -* unsigned int busNum - The CPI bus number to which the PCI interface -* is connected. -* unsigned int devNum - The PCI interface's device number. -* -* Returns: true. -*********************************************************************/ -bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow, - unsigned int SecondBusHigh, - unsigned int busNum, unsigned int devNum) -{ - unsigned int regData; - - regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) | - ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24); - GT_REG_WRITE (pci_p2p_configuration[host], regData); - return true; -} - -/******************************************************************** -* pciSetRegionSnoopMode - This function modifys one of the 4 regions which -* supports Cache Coherency in the PCI_n interface. -* Inputs: region - One of the four regions. -* snoopType - There is four optional Types: -* 1. No Snoop. -* 2. Snoop to WT region. -* 3. Snoop to WB region. -* 4. Snoop & Invalidate to WB region. -* baseAddress - Base Address of this region. -* regionLength - Region length. -* Returns: false if one of the parameters is wrong otherwise return true. -*********************************************************************/ -bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region, - PCI_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int snoopXbaseAddress; - unsigned int snoopXtopAddress; - unsigned int data; - unsigned int snoopHigh = baseAddress + regionLength; - - if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB)) - return false; - snoopXbaseAddress = - pci_snoop_control_base_0_low[host] + 0x10 * region; - snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region; - if (regionLength == 0) { /* closing the region */ - GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff); - GT_REG_WRITE (snoopXtopAddress, 0); - return true; - } - baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ - data = (baseAddress >> 20) | snoopType << 12; - GT_REG_WRITE (snoopXbaseAddress, data); - snoopHigh = (snoopHigh & 0xfff00000) >> 20; - GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1); - return true; -} - -static int gt_read_config_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, u32 * value) -{ - int bus = PCI_BUS (dev); - - if ((bus == local_buses[0]) || (bus == local_buses[1])) { - *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset, - PCI_DEV (dev)); - } else { - *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose-> - cfg_addr, offset, - PCI_DEV (dev), bus); - } - - return 0; -} - -static int gt_write_config_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, u32 value) -{ - int bus = PCI_BUS (dev); - - if ((bus == local_buses[0]) || (bus == local_buses[1])) { - pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset, - PCI_DEV (dev), value); - } else { - pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr, - offset, PCI_DEV (dev), bus, - value); - } - return 0; -} - - -static void gt_setup_ide (struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *entry) -{ - static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 }; - u32 bar_response, bar_value; - int bar; - - for (bar = 0; bar < 6; bar++) { - /*ronen different function for 3rd bank. */ - unsigned int offset = - (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8; - - pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset, - 0x0); - pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset, - &bar_response); - - pciauto_region_allocate (bar_response & - PCI_BASE_ADDRESS_SPACE_IO ? hose-> - pci_io : hose->pci_mem, ide_bar[bar], - &bar_value); - - pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4, - bar_value); - } -} - - -/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */ -/* and is curently not called *. */ -#if 0 -static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char pin, irq; - - pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin); - - if (pin == 1) { /* only allow INT A */ - irq = pci_irq_swizzle[(PCI_HOST) hose-> - cfg_addr][PCI_DEV (dev)]; - if (irq) - pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq); - } -} -#endif - -struct pci_config_table gt_config_table[] = { - {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide}, - - {} -}; - -struct pci_controller pci0_hose = { -/* fixup_irq: gt_fixup_irq, */ - config_table:gt_config_table, -}; - -struct pci_controller pci1_hose = { -/* fixup_irq: gt_fixup_irq, */ - config_table:gt_config_table, -}; - -void pci_init_board (void) -{ - unsigned int command; - -#ifdef DEBUG - gt_pci_bus_mode_display (PCI_HOST0); -#endif - - pci0_hose.first_busno = 0; - pci0_hose.last_busno = 0xff; - local_buses[0] = pci0_hose.first_busno; - - /* PCI memory space */ - pci_set_region (pci0_hose.regions + 0, - CONFIG_SYS_PCI0_0_MEM_SPACE, - CONFIG_SYS_PCI0_0_MEM_SPACE, - CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (pci0_hose.regions + 1, - CONFIG_SYS_PCI0_IO_SPACE_PCI, - CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO); - - pci_set_ops (&pci0_hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - gt_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - gt_write_config_dword); - pci0_hose.region_count = 2; - - pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0; - - pci_register_hose (&pci0_hose); - pciArbiterEnable (PCI_HOST0); - pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1); - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - - pci0_hose.last_busno = pci_hose_scan (&pci0_hose); - -#ifdef DEBUG - gt_pci_bus_mode_display (PCI_HOST1); -#endif - pci1_hose.first_busno = pci0_hose.last_busno + 1; - pci1_hose.last_busno = 0xff; - pci1_hose.current_busno = pci1_hose.first_busno; - local_buses[1] = pci1_hose.first_busno; - - /* PCI memory space */ - pci_set_region (pci1_hose.regions + 0, - CONFIG_SYS_PCI1_0_MEM_SPACE, - CONFIG_SYS_PCI1_0_MEM_SPACE, - CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (pci1_hose.regions + 1, - CONFIG_SYS_PCI1_IO_SPACE_PCI, - CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); - - pci_set_ops (&pci1_hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - gt_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - gt_write_config_dword); - - pci1_hose.region_count = 2; - - pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1; - - pci_register_hose (&pci1_hose); - - pciArbiterEnable (PCI_HOST1); - pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1); - - command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); - - pci1_hose.last_busno = pci_hose_scan (&pci1_hose); - - command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); - -} diff --git a/board/Marvell/db64460/sdram_init.c b/board/Marvell/db64460/sdram_init.c deleted file mode 100644 index 71c2d9e..0000000 --- a/board/Marvell/db64460/sdram_init.c +++ /dev/null @@ -1,1950 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * adaption for the Marvell DB64460 Board - * Ingo Assmus (ingo.assmus@keymile.com) - ************************************************************************/ - - -/* sdram_init.c - automatic memory sizing */ - -#include <common.h> -#include <74xx_7xx.h> -#include "../include/memory.h" -#include "../include/pci.h" -#include "../include/mv_gen_reg.h" -#include <net.h> - -#include "eth.h" -#include "mpsc.h" -#include "../common/i2c.h" -#include "64460.h" -#include "mv_regs.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define MAP_PCI - -int set_dfcdlInit (void); /* setup delay line of Mv64460 */ -int mvDmaIsChannelActive (int); -int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong); -int mvDmaTransfer (int, ulong, ulong, ulong, ulong); - -/* ------------------------------------------------------------------------- */ - -int -memory_map_bank (unsigned int bankNo, - unsigned int bankBase, unsigned int bankLength) -{ -#ifdef MAP_PCI - PCI_HOST host; -#endif - - - if (bankLength > 0) { - debug("mapping bank %d at %08x - %08x\n", - bankNo, bankBase, bankBase + bankLength - 1); - } else { - debug("unmapping bank %d\n", bankNo); - } - - memoryMapBank (bankNo, bankBase, bankLength); - -#ifdef MAP_PCI - for (host = PCI_HOST0; host <= PCI_HOST1; host++) { - const int features = - PREFETCH_ENABLE | - DELAYED_READ_ENABLE | - AGGRESSIVE_PREFETCH | - READ_LINE_AGGRESSIVE_PREFETCH | - READ_MULTI_AGGRESSIVE_PREFETCH | - MAX_BURST_4 | PCI_NO_SWAP; - - pciMapMemoryBank (host, bankNo, bankBase, bankLength); - - pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase, - bankLength); - - pciSetRegionFeatures (host, bankNo, features, bankBase, - bankLength); - } -#endif - return 0; -} - -#define GB (1 << 30) - -/* much of this code is based on (or is) the code in the pip405 port */ -/* thanks go to the authors of said port - Josh */ - -/* structure to store the relevant information about an sdram bank */ -typedef struct sdram_info { - uchar drb_size; - uchar registered, ecc; - uchar tpar; - uchar tras_clocks; - uchar burst_len; - uchar banks, slot; -} sdram_info_t; - -/* Typedefs for 'gtAuxilGetDIMMinfo' function */ - -typedef enum _memoryType { SDRAM, DDR } MEMORY_TYPE; - -typedef enum _voltageInterface { TTL_5V_TOLERANT, LVTTL, HSTL_1_5V, - SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN, -} VOLTAGE_INTERFACE; - -typedef enum _max_CL_supported_DDR { DDR_CL_1 = 1, DDR_CL_1_5 = 2, DDR_CL_2 = - 4, DDR_CL_2_5 = 8, DDR_CL_3 = 16, DDR_CL_3_5 = - 32, DDR_CL_FAULT } MAX_CL_SUPPORTED_DDR; -typedef enum _max_CL_supported_SD { SD_CL_1 = - 1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7, - SD_FAULT } MAX_CL_SUPPORTED_SD; - - -/* SDRAM/DDR information struct */ -typedef struct _gtMemoryDimmInfo { - MEMORY_TYPE memoryType; - unsigned int numOfRowAddresses; - unsigned int numOfColAddresses; - unsigned int numOfModuleBanks; - unsigned int dataWidth; - VOLTAGE_INTERFACE voltageInterface; - unsigned int errorCheckType; /* ECC , PARITY.. */ - unsigned int sdramWidth; /* 4,8,16 or 32 */ ; - unsigned int errorCheckDataWidth; /* 0 - no, 1 - Yes */ - unsigned int minClkDelay; - unsigned int burstLengthSupported; - unsigned int numOfBanksOnEachDevice; - unsigned int suportedCasLatencies; - unsigned int RefreshInterval; - unsigned int maxCASlatencySupported_LoP; /* LoP left of point (measured in ns) */ - unsigned int maxCASlatencySupported_RoP; /* RoP right of point (measured in ns) */ - MAX_CL_SUPPORTED_DDR maxClSupported_DDR; - MAX_CL_SUPPORTED_SD maxClSupported_SD; - unsigned int moduleBankDensity; - /* module attributes (true for yes) */ - bool bufferedAddrAndControlInputs; - bool registeredAddrAndControlInputs; - bool onCardPLL; - bool bufferedDQMBinputs; - bool registeredDQMBinputs; - bool differentialClockInput; - bool redundantRowAddressing; - - /* module general attributes */ - bool suportedAutoPreCharge; - bool suportedPreChargeAll; - bool suportedEarlyRasPreCharge; - bool suportedWrite1ReadBurst; - bool suported5PercentLowVCC; - bool suported5PercentUpperVCC; - /* module timing parameters */ - unsigned int minRasToCasDelay; - unsigned int minRowActiveRowActiveDelay; - unsigned int minRasPulseWidth; - unsigned int minRowPrechargeTime; /* measured in ns */ - - int addrAndCommandHoldTime; /* LoP left of point (measured in ns) */ - int addrAndCommandSetupTime; /* (measured in ns/100) */ - int dataInputSetupTime; /* LoP left of point (measured in ns) */ - int dataInputHoldTime; /* LoP left of point (measured in ns) */ -/* tAC times for highest 2nd and 3rd highest CAS Latency values */ - unsigned int clockToDataOut_LoP; /* LoP left of point (measured in ns) */ - unsigned int clockToDataOut_RoP; /* RoP right of point (measured in ns) */ - unsigned int clockToDataOutMinus1_LoP; /* LoP left of point (measured in ns) */ - unsigned int clockToDataOutMinus1_RoP; /* RoP right of point (measured in ns) */ - unsigned int clockToDataOutMinus2_LoP; /* LoP left of point (measured in ns) */ - unsigned int clockToDataOutMinus2_RoP; /* RoP right of point (measured in ns) */ - - unsigned int minimumCycleTimeAtMaxCasLatancy_LoP; /* LoP left of point (measured in ns) */ - unsigned int minimumCycleTimeAtMaxCasLatancy_RoP; /* RoP right of point (measured in ns) */ - - unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */ - unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns) */ - - unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */ - unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns) */ - - /* Parameters calculated from - the extracted DIMM information */ - unsigned int size; - unsigned int deviceDensity; /* 16,64,128,256 or 512 Mbit */ - unsigned int numberOfDevices; - uchar drb_size; /* DRAM size in n*64Mbit */ - uchar slot; /* Slot Number this module is inserted in */ - uchar spd_raw_data[128]; /* Content of SPD-EEPROM copied 1:1 */ -#ifdef DEBUG - uchar manufactura[8]; /* Content of SPD-EEPROM Byte 64-71 */ - uchar modul_id[18]; /* Content of SPD-EEPROM Byte 73-90 */ - uchar vendor_data[27]; /* Content of SPD-EEPROM Byte 99-125 */ - unsigned long modul_serial_no; /* Content of SPD-EEPROM Byte 95-98 */ - unsigned int manufac_date; /* Content of SPD-EEPROM Byte 93-94 */ - unsigned int modul_revision; /* Content of SPD-EEPROM Byte 91-92 */ - uchar manufac_place; /* Content of SPD-EEPROM Byte 72 */ - -#endif -} AUX_MEM_DIMM_INFO; - - -/* - * translate ns.ns/10 coding of SPD timing values - * into 10 ps unit values - */ -static inline unsigned short NS10to10PS (unsigned char spd_byte) -{ - unsigned short ns, ns10; - - /* isolate upper nibble */ - ns = (spd_byte >> 4) & 0x0F; - /* isolate lower nibble */ - ns10 = (spd_byte & 0x0F); - - return (ns * 100 + ns10 * 10); -} - -/* - * translate ns coding of SPD timing values - * into 10 ps unit values - */ -static inline unsigned short NSto10PS (unsigned char spd_byte) -{ - return (spd_byte * 100); -} - -/* This code reads the SPD chip on the sdram and populates - * the array which is passed in with the relevant information */ -/* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */ -static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) -{ - unsigned long spd_checksum; - -#ifdef ZUMA_NTL - /* zero all the values */ - memset (info, 0, sizeof (*info)); - -/* - if (!slot) { - info->slot = 0; - info->banks = 1; - info->registered = 0; - info->drb_size = 16;*/ /* 16 - 256MBit, 32 - 512MBit */ -/* info->tpar = 3; - info->tras_clocks = 5; - info->burst_len = 4; -*/ -#ifdef CONFIG_MV64460_ECC - /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */ - dimmInfo->errorCheckType = 2; -/* info->ecc = 2;*/ -#endif -} - -return 0; - -#else - uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; - int ret; - unsigned int i, j, density = 1; - -#ifdef DEBUG - unsigned int k; -#endif - unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp; - int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint; - uchar supp_cal, cal_val; - ulong memclk, tmemclk; - ulong tmp; - uchar trp_clocks = 0, tras_clocks; - uchar data[128]; - - memclk = gd->bus_clk; - tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ - - debug("before i2c read\n"); - - ret = i2c_read (addr, 0, 1, data, 128); - - debug("after i2c read\n"); - - /* zero all the values */ - memset (dimmInfo, 0, sizeof (*dimmInfo)); - - /* copy the SPD content 1:1 into the dimmInfo structure */ - for (i = 0; i <= 127; i++) { - dimmInfo->spd_raw_data[i] = data[i]; - } - - if (ret) { - debug("No DIMM in slot %d [err = %x]\n", slot, ret); - return 0; - } else - dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */ - -#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT - - for (i = 0; i <= 127; i++) { - printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i], - data[i]); - } - -#endif -#ifdef DEBUG -/* find Manufactura of Dimm Module */ - for (i = 0; i < sizeof (dimmInfo->manufactura); i++) { - dimmInfo->manufactura[i] = data[64 + i]; - } - printf ("\nThis RAM-Module is produced by: %s\n", - dimmInfo->manufactura); - -/* find Manul-ID of Dimm Module */ - for (i = 0; i < sizeof (dimmInfo->modul_id); i++) { - dimmInfo->modul_id[i] = data[73 + i]; - } - printf ("The Module-ID of this RAM-Module is: %s\n", - dimmInfo->modul_id); - -/* find Vendor-Data of Dimm Module */ - for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) { - dimmInfo->vendor_data[i] = data[99 + i]; - } - printf ("Vendor Data of this RAM-Module is: %s\n", - dimmInfo->vendor_data); - -/* find modul_serial_no of Dimm Module */ - dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95]))); - printf ("Serial No. of this RAM-Module is: %ld (%lx)\n", - dimmInfo->modul_serial_no, dimmInfo->modul_serial_no); - -/* find Manufac-Data of Dimm Module */ - dimmInfo->manufac_date = (*((unsigned int *) (&data[93]))); - printf ("Manufactoring Date of this RAM-Module is: %d.%d\n", data[93], data[94]); /*dimmInfo->manufac_date */ - -/* find modul_revision of Dimm Module */ - dimmInfo->modul_revision = (*((unsigned int *) (&data[91]))); - printf ("Module Revision of this RAM-Module is: %d.%d\n", data[91], data[92]); /* dimmInfo->modul_revision */ - -/* find manufac_place of Dimm Module */ - dimmInfo->manufac_place = (*((unsigned char *) (&data[72]))); - printf ("manufac_place of this RAM-Module is: %d\n", - dimmInfo->manufac_place); - -#endif - -/*------------------------------------------------------------------------------------------------------------------------------*/ -/* calculate SPD checksum */ -/*------------------------------------------------------------------------------------------------------------------------------*/ - spd_checksum = 0; - - for (i = 0; i <= 62; i++) { - spd_checksum += data[i]; - } - - if ((spd_checksum & 0xff) != data[63]) { - printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]); - hang (); - } - - else - printf ("SPD Checksum ok!\n"); - - -/*------------------------------------------------------------------------------------------------------------------------------*/ - for (i = 2; i <= 35; i++) { - switch (i) { - case 2: /* Memory type (DDR / SDRAM) */ - dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM; -#ifdef DEBUG - if (dimmInfo->memoryType == 0) - debug - ("Dram_type in slot %d is: SDRAM\n", - dimmInfo->slot); - if (dimmInfo->memoryType == 1) - debug - ("Dram_type in slot %d is: DDRAM\n", - dimmInfo->slot); -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 3: /* Number Of Row Addresses */ - dimmInfo->numOfRowAddresses = data[i]; - debug - ("Module Number of row addresses: %d\n", - dimmInfo->numOfRowAddresses); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 4: /* Number Of Column Addresses */ - dimmInfo->numOfColAddresses = data[i]; - debug - ("Module Number of col addresses: %d\n", - dimmInfo->numOfColAddresses); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 5: /* Number Of Module Banks */ - dimmInfo->numOfModuleBanks = data[i]; - debug - ("Number of Banks on Mod. : %d\n", - dimmInfo->numOfModuleBanks); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 6: /* Data Width */ - dimmInfo->dataWidth = data[i]; - debug - ("Module Data Width: %d\n", - dimmInfo->dataWidth); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 8: /* Voltage Interface */ - switch (data[i]) { - case 0x0: - dimmInfo->voltageInterface = TTL_5V_TOLERANT; - debug - ("Module is TTL_5V_TOLERANT\n"); - break; - case 0x1: - dimmInfo->voltageInterface = LVTTL; - debug - ("Module is LVTTL\n"); - break; - case 0x2: - dimmInfo->voltageInterface = HSTL_1_5V; - debug - ("Module is TTL_5V_TOLERANT\n"); - break; - case 0x3: - dimmInfo->voltageInterface = SSTL_3_3V; - debug - ("Module is HSTL_1_5V\n"); - break; - case 0x4: - dimmInfo->voltageInterface = SSTL_2_5V; - debug - ("Module is SSTL_2_5V\n"); - break; - default: - dimmInfo->voltageInterface = VOLTAGE_UNKNOWN; - debug - ("Module is VOLTAGE_UNKNOWN\n"); - break; - } - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 9: /* Minimum Cycle Time At Max CasLatancy */ - shift = (dimmInfo->memoryType == DDR) ? 4 : 2; - mult = (dimmInfo->memoryType == DDR) ? 10 : 25; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf : 0x03; - leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; - rightOfPoint = (data[i] & maskRightOfPoint) * mult; - dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP = - leftOfPoint; - dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP = - rightOfPoint; - debug - ("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n", - leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 10: /* Clock To Data Out */ - div = (dimmInfo->memoryType == DDR) ? 100 : 10; - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - dimmInfo->clockToDataOut_LoP = leftOfPoint; - dimmInfo->clockToDataOut_RoP = rightOfPoint; - debug("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->clockToDataOut */ - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - -/*#ifdef CONFIG_ECC */ - case 11: /* Error Check Type */ - dimmInfo->errorCheckType = data[i]; - debug - ("Error Check Type (0=NONE): %d\n", - dimmInfo->errorCheckType); - break; -/* #endif */ -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 12: /* Refresh Interval */ - dimmInfo->RefreshInterval = data[i]; - debug - ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n", - dimmInfo->RefreshInterval); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 13: /* Sdram Width */ - dimmInfo->sdramWidth = data[i]; - debug - ("Sdram Width: %d\n", - dimmInfo->sdramWidth); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 14: /* Error Check Data Width */ - dimmInfo->errorCheckDataWidth = data[i]; - debug - ("Error Check Data Width: %d\n", - dimmInfo->errorCheckDataWidth); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 15: /* Minimum Clock Delay */ - dimmInfo->minClkDelay = data[i]; - debug - ("Minimum Clock Delay: %d\n", - dimmInfo->minClkDelay); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 16: /* Burst Length Supported */ - /******-******-******-******* - * bit3 | bit2 | bit1 | bit0 * - *******-******-******-******* - burst length = * 8 | 4 | 2 | 1 * - ***************************** - - If for example bit0 and bit2 are set, the burst - length supported are 1 and 4. */ - - dimmInfo->burstLengthSupported = data[i]; -#ifdef DEBUG - debug - ("Burst Length Supported: "); - if (dimmInfo->burstLengthSupported & 0x01) - debug("1, "); - if (dimmInfo->burstLengthSupported & 0x02) - debug("2, "); - if (dimmInfo->burstLengthSupported & 0x04) - debug("4, "); - if (dimmInfo->burstLengthSupported & 0x08) - debug("8, "); - debug(" Bit \n"); -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 17: /* Number Of Banks On Each Device */ - dimmInfo->numOfBanksOnEachDevice = data[i]; - debug - ("Number Of Banks On Each Chip: %d\n", - dimmInfo->numOfBanksOnEachDevice); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 18: /* Suported Cas Latencies */ - - /* DDR: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | TBD | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * - ********************************************************* - SDRAM: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * - ********************************************************/ - dimmInfo->suportedCasLatencies = data[i]; -#ifdef DEBUG - debug - ("Suported Cas Latencies: (CL) "); - if (dimmInfo->memoryType == 0) { /* SDRAM */ - for (k = 0; k <= 7; k++) { - if (dimmInfo-> - suportedCasLatencies & (1 << k)) - debug - ("%d, ", - k + 1); - } - - } else { /* DDR-RAM */ - - if (dimmInfo->suportedCasLatencies & 1) - debug("1, "); - if (dimmInfo->suportedCasLatencies & 2) - debug("1.5, "); - if (dimmInfo->suportedCasLatencies & 4) - debug("2, "); - if (dimmInfo->suportedCasLatencies & 8) - debug("2.5, "); - if (dimmInfo->suportedCasLatencies & 16) - debug("3, "); - if (dimmInfo->suportedCasLatencies & 32) - debug("3.5, "); - - } - debug("\n"); -#endif - /* Calculating MAX CAS latency */ - for (j = 7; j > 0; j--) { - if (((dimmInfo-> - suportedCasLatencies >> j) & 0x1) == - 1) { - switch (dimmInfo->memoryType) { - case DDR: - /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */ - switch (j) { - case 7: - debug - ("Max. Cas Latencies (DDR): ERROR !!!\n"); - dimmInfo-> - maxClSupported_DDR - = - DDR_CL_FAULT; - hang (); - break; - case 6: - debug - ("Max. Cas Latencies (DDR): ERROR !!!\n"); - dimmInfo-> - maxClSupported_DDR - = - DDR_CL_FAULT; - hang (); - break; - case 5: - debug - ("Max. Cas Latencies (DDR): 3.5 clk's\n"); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_3_5; - break; - case 4: - debug - ("Max. Cas Latencies (DDR): 3 clk's \n"); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_3; - break; - case 3: - debug - ("Max. Cas Latencies (DDR): 2.5 clk's \n"); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_2_5; - break; - case 2: - debug - ("Max. Cas Latencies (DDR): 2 clk's \n"); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_2; - break; - case 1: - debug - ("Max. Cas Latencies (DDR): 1.5 clk's \n"); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_1_5; - break; - } - - /* ronen - in case we have a DIMM with minimumCycleTimeAtMaxCasLatancy - lower then our SDRAM cycle count, we won't be able to support this CAL - and we will have to use lower CAL. (minus - means from 3.0 to 2.5) */ - if ((dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_LoP - < - CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) - || - ((dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_LoP - == - CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) - && (dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_RoP - < - CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP))) - { - dimmInfo-> - maxClSupported_DDR - = - dimmInfo-> - maxClSupported_DDR - >> 1; - debug - ("*** Change actual Cas Latencies cause of minimumCycleTime n"); - } - /* ronen - checkif the Dimm frequency compared to the Sysclock. */ - if ((dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_LoP - > - CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) - || - ((dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_LoP - == - CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) - && (dimmInfo-> - minimumCycleTimeAtMaxCasLatancy_RoP - > - CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP))) - { - printf ("*********************************************************\n"); - printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n"); - printf ("*********************************************************\n"); - hang (); - } - - dimmInfo-> - maxCASlatencySupported_LoP - = - 1 + - (int) (5 * j / 10); - if (((5 * j) % 10) != 0) - dimmInfo-> - maxCASlatencySupported_RoP - = 5; - else - dimmInfo-> - maxCASlatencySupported_RoP - = 0; - debug - ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", - dimmInfo-> - maxCASlatencySupported_LoP, - dimmInfo-> - maxCASlatencySupported_RoP); - break; - case SDRAM: - /* CAS latency 1, 2, 3, 4, 5, 6, 7 */ - dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */ - debug - ("Max. Cas Latencies (SD): %d\n", - dimmInfo-> - maxClSupported_SD); - dimmInfo-> - maxCASlatencySupported_LoP - = j; - dimmInfo-> - maxCASlatencySupported_RoP - = 0; - debug - ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", - dimmInfo-> - maxCASlatencySupported_LoP, - dimmInfo-> - maxCASlatencySupported_RoP); - break; - } - break; - } - } - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 21: /* Buffered Address And Control Inputs */ - debug("\nModul Attributes (SPD Byte 21): \n"); - dimmInfo->bufferedAddrAndControlInputs = - data[i] & BIT0; - dimmInfo->registeredAddrAndControlInputs = - (data[i] & BIT1) >> 1; - dimmInfo->onCardPLL = (data[i] & BIT2) >> 2; - dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3; - dimmInfo->registeredDQMBinputs = - (data[i] & BIT4) >> 4; - dimmInfo->differentialClockInput = - (data[i] & BIT5) >> 5; - dimmInfo->redundantRowAddressing = - (data[i] & BIT6) >> 6; -#ifdef DEBUG - if (dimmInfo->bufferedAddrAndControlInputs == 1) - debug - (" - Buffered Address/Control Input: Yes \n"); - else - debug - (" - Buffered Address/Control Input: No \n"); - - if (dimmInfo->registeredAddrAndControlInputs == 1) - debug - (" - Registered Address/Control Input: Yes \n"); - else - debug - (" - Registered Address/Control Input: No \n"); - - if (dimmInfo->onCardPLL == 1) - debug - (" - On-Card PLL (clock): Yes \n"); - else - debug - (" - On-Card PLL (clock): No \n"); - - if (dimmInfo->bufferedDQMBinputs == 1) - debug - (" - Bufferd DQMB Inputs: Yes \n"); - else - debug - (" - Bufferd DQMB Inputs: No \n"); - - if (dimmInfo->registeredDQMBinputs == 1) - debug - (" - Registered DQMB Inputs: Yes \n"); - else - debug - (" - Registered DQMB Inputs: No \n"); - - if (dimmInfo->differentialClockInput == 1) - debug - (" - Differential Clock Input: Yes \n"); - else - debug - (" - Differential Clock Input: No \n"); - - if (dimmInfo->redundantRowAddressing == 1) - debug - (" - redundant Row Addressing: Yes \n"); - else - debug - (" - redundant Row Addressing: No \n"); - -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 22: /* Suported AutoPreCharge */ - debug("\nModul Attributes (SPD Byte 22): \n"); - dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0; - dimmInfo->suportedAutoPreCharge = - (data[i] & BIT1) >> 1; - dimmInfo->suportedPreChargeAll = - (data[i] & BIT2) >> 2; - dimmInfo->suportedWrite1ReadBurst = - (data[i] & BIT3) >> 3; - dimmInfo->suported5PercentLowVCC = - (data[i] & BIT4) >> 4; - dimmInfo->suported5PercentUpperVCC = - (data[i] & BIT5) >> 5; -#ifdef DEBUG - if (dimmInfo->suportedEarlyRasPreCharge == 1) - debug - (" - Early Ras Precharge: Yes \n"); - else - debug - (" - Early Ras Precharge: No \n"); - - if (dimmInfo->suportedAutoPreCharge == 1) - debug - (" - AutoPreCharge: Yes \n"); - else - debug - (" - AutoPreCharge: No \n"); - - if (dimmInfo->suportedPreChargeAll == 1) - debug - (" - Precharge All: Yes \n"); - else - debug - (" - Precharge All: No \n"); - - if (dimmInfo->suportedWrite1ReadBurst == 1) - debug - (" - Write 1/ReadBurst: Yes \n"); - else - debug - (" - Write 1/ReadBurst: No \n"); - - if (dimmInfo->suported5PercentLowVCC == 1) - debug - (" - lower VCC tolerance: 5 Percent \n"); - else - debug - (" - lower VCC tolerance: 10 Percent \n"); - - if (dimmInfo->suported5PercentUpperVCC == 1) - debug - (" - upper VCC tolerance: 5 Percent \n"); - else - debug - (" - upper VCC tolerance: 10 Percent \n"); - -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 23: /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ - shift = (dimmInfo->memoryType == DDR) ? 4 : 2; - mult = (dimmInfo->memoryType == DDR) ? 10 : 25; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf : 0x03; - leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; - rightOfPoint = (data[i] & maskRightOfPoint) * mult; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP = - leftOfPoint; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP = - rightOfPoint; - debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 24: /* Clock To Data Out 2nd highest Cas Latency Value */ - div = (dimmInfo->memoryType == DDR) ? 100 : 10; - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint; - dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint; - debug - ("Clock To Data Out (2nd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 25: /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ - shift = (dimmInfo->memoryType == DDR) ? 4 : 2; - mult = (dimmInfo->memoryType == DDR) ? 10 : 25; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf : 0x03; - leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; - rightOfPoint = (data[i] & maskRightOfPoint) * mult; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP = - leftOfPoint; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP = - rightOfPoint; - debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 26: /* Clock To Data Out 3rd highest Cas Latency Value */ - div = (dimmInfo->memoryType == DDR) ? 100 : 10; - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint; - dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint; - debug - ("Clock To Data Out (3rd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 27: /* Minimum Row Precharge Time */ - shift = (dimmInfo->memoryType == DDR) ? 2 : 0; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; - leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (data[i] & maskRightOfPoint) * 25; - - dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint); /* measured in n times 10ps Intervals */ - trp_clocks = - (dimmInfo->minRowPrechargeTime + - (tmemclk - 1)) / tmemclk; - debug - ("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n", - tmemclk, tmemclk / 100, tmemclk % 100); - debug - ("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 28: /* Minimum Row Active to Row Active Time */ - shift = (dimmInfo->memoryType == DDR) ? 2 : 0; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; - leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (data[i] & maskRightOfPoint) * 25; - - dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - debug - ("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 29: /* Minimum Ras-To-Cas Delay */ - shift = (dimmInfo->memoryType == DDR) ? 2 : 0; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; - leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (data[i] & maskRightOfPoint) * 25; - - dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - debug - ("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 30: /* Minimum Ras Pulse Width */ - dimmInfo->minRasPulseWidth = data[i]; - tras_clocks = - (NSto10PS (data[i]) + - (tmemclk - 1)) / tmemclk; - debug - ("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n", - dimmInfo->minRasPulseWidth, tras_clocks); - - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 31: /* Module Bank Density */ - dimmInfo->moduleBankDensity = data[i]; - debug - ("Module Bank Density: %d\n", - dimmInfo->moduleBankDensity); -#ifdef DEBUG - debug - ("*** Offered Densities (more than 1 = Multisize-Module): "); - { - if (dimmInfo->moduleBankDensity & 1) - debug("4MB, "); - if (dimmInfo->moduleBankDensity & 2) - debug("8MB, "); - if (dimmInfo->moduleBankDensity & 4) - debug("16MB, "); - if (dimmInfo->moduleBankDensity & 8) - debug("32MB, "); - if (dimmInfo->moduleBankDensity & 16) - debug("64MB, "); - if (dimmInfo->moduleBankDensity & 32) - debug("128MB, "); - if ((dimmInfo->moduleBankDensity & 64) - || (dimmInfo->moduleBankDensity & 128)) { - debug("ERROR, "); - hang (); - } - } - debug("\n"); -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 32: /* Address And Command Setup Time (measured in ns/1000) */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->addrAndCommandSetupTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - debug - ("Address And Command Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 33: /* Address And Command Hold Time */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->addrAndCommandHoldTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - debug - ("Address And Command Hold Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 34: /* Data Input Setup Time */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->dataInputSetupTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - debug - ("Data Input Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 35: /* Data Input Hold Time */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->dataInputHoldTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - debug - ("Data Input Hold Time [ns]: %d.%d\n\n", - sign * leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - } - } - /* calculating the sdram density */ - for (i = 0; - i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses; - i++) { - density = density * 2; - } - dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice * - dimmInfo->sdramWidth; - dimmInfo->numberOfDevices = - (dimmInfo->dataWidth / dimmInfo->sdramWidth) * - dimmInfo->numOfModuleBanks; - if ((dimmInfo->errorCheckType == 0x1) - || (dimmInfo->errorCheckType == 0x2) - || (dimmInfo->errorCheckType == 0x3)) { - dimmInfo->size = - (dimmInfo->deviceDensity / 8) * - (dimmInfo->numberOfDevices - - /* ronen on the 1G dimm we get wrong value. (was devicesForErrCheck) */ - dimmInfo->numberOfDevices / 8); - } else { - dimmInfo->size = - (dimmInfo->deviceDensity / 8) * - dimmInfo->numberOfDevices; - } - - /* compute the module DRB size */ - tmp = (1 << - (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses)); - tmp *= dimmInfo->numOfModuleBanks; - tmp *= dimmInfo->sdramWidth; - tmp = tmp >> 24; /* div by 0x4000000 (64M) */ - dimmInfo->drb_size = (uchar) tmp; - debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size); - - /* try a CAS latency of 3 first... */ - - /* bit 1 is CL2, bit 2 is CL3 */ - supp_cal = (dimmInfo->suportedCasLatencies & 0x6) >> 1; - - cal_val = 0; - if (supp_cal & 3) { - if (NS10to10PS (data[9]) <= tmemclk) - cal_val = 3; - } - - /* then 2... */ - if (supp_cal & 2) { - if (NS10to10PS (data[23]) <= tmemclk) - cal_val = 2; - } - - debug("cal_val = %d\n", cal_val); - - /* bummer, did't work... */ - if (cal_val == 0) { - debug("Couldn't find a good CAS latency\n"); - hang (); - return 0; - } - - return true; -#endif -} - -/* sets up the GT properly with information passed in */ -int setup_sdram (AUX_MEM_DIMM_INFO * info) -{ - ulong tmp, check; - ulong tmp_sdram_mode = 0; /* 0x141c */ - ulong tmp_dunit_control_low = 0; /* 0x1404 */ - int i; - - /* added 8/21/2003 P. Marchese */ - unsigned int sdram_config_reg; - - /* added 10/10/2003 P. Marchese */ - ulong sdram_chip_size; - - /* sanity checking */ - if (!info->numOfModuleBanks) { - printf ("setup_sdram called with 0 banks\n"); - return 1; - } - - /* delay line */ - set_dfcdlInit (); /* may be its not needed */ - debug("Delay line set done\n"); - - /* set SDRAM mode NOP */ /* To_do check it */ - GT_REG_WRITE (SDRAM_OPERATION, 0x5); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - debug - ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"); - } - - /* SDRAM configuration */ -/* added 8/21/2003 P. Marchese */ -/* code allows usage of registered DIMMS */ - - /* figure out the memory refresh internal */ - switch (info->RefreshInterval) { - case 0x0: - case 0x80: /* refresh period is 15.625 usec */ - sdram_config_reg = - (unsigned int) (((float) 15.625 * (float) CONFIG_SYS_BUS_CLK) - / (float) 1000000.0); - break; - case 0x1: - case 0x81: /* refresh period is 3.9 usec */ - sdram_config_reg = - (unsigned int) (((float) 3.9 * (float) CONFIG_SYS_BUS_CLK) / - (float) 1000000.0); - break; - case 0x2: - case 0x82: /* refresh period is 7.8 usec */ - sdram_config_reg = - (unsigned int) (((float) 7.8 * (float) CONFIG_SYS_BUS_CLK) / - (float) 1000000.0); - break; - case 0x3: - case 0x83: /* refresh period is 31.3 usec */ - sdram_config_reg = - (unsigned int) (((float) 31.3 * (float) CONFIG_SYS_BUS_CLK) / - (float) 1000000.0); - break; - case 0x4: - case 0x84: /* refresh period is 62.5 usec */ - sdram_config_reg = - (unsigned int) (((float) 62.5 * (float) CONFIG_SYS_BUS_CLK) / - (float) 1000000.0); - break; - case 0x5: - case 0x85: /* refresh period is 125 usec */ - sdram_config_reg = - (unsigned int) (((float) 125 * (float) CONFIG_SYS_BUS_CLK) / - (float) 1000000.0); - break; - default: /* refresh period undefined */ - printf ("DRAM refresh period is unknown!\n"); - printf ("Aborting DRAM setup with an error\n"); - hang (); - break; - } - debug("calculated refresh interval %0x\n", sdram_config_reg); - - /* make sure the refresh value is only 14 bits */ - if (sdram_config_reg > 0x1fff) - sdram_config_reg = 0x1fff; - debug("adjusted refresh interval %0x\n", sdram_config_reg); - - /* we want physical bank interleaving and */ - /* virtual bank interleaving enabled so do nothing */ - /* since these bits need to be zero to enable the interleaving */ - - /* registered DRAM ? */ - if (info->registeredAddrAndControlInputs == 1) { - /* it's registered DRAM, so set the reg. DRAM bit */ - sdram_config_reg = sdram_config_reg | BIT17; - debug("Enabling registered DRAM bit\n"); - } - /* turn on DRAM ECC? */ -#ifdef CONFIG_MV64460_ECC - if (info->errorCheckType == 0x2) { - /* DRAM has ECC, so turn it on */ - sdram_config_reg = sdram_config_reg | BIT18; - debug("Enabling ECC\n"); - } -#endif - /* set the data DQS pin configuration */ - switch (info->sdramWidth) { - case 0x4: /* memory is x4 */ - sdram_config_reg = sdram_config_reg | BIT20 | BIT21; - debug("Data DQS pins set for 16 pins\n"); - break; - case 0x8: /* memory is x8 or x16 */ - case 0x10: - sdram_config_reg = sdram_config_reg | BIT21; - debug("Data DQS pins set for 8 pins\n"); - break; - case 0x20: /* memory is x32 */ - /* both bits are cleared for x32 so nothing to do */ - debug("Data DQS pins set for 2 pins\n"); - break; - default: /* memory width unsupported */ - printf ("DRAM chip width is unknown!\n"); - printf ("Aborting DRAM setup with an error\n"); - hang (); - break; - } - - /*ronen db64460 */ - /* perform read buffer assignments */ - /* we are going to use the Power-up defaults */ - /* bit 27 = PCI bus #0 = buffer 0 */ - /* bit 28 = PCI bus #1 = buffer 0 */ - /* bit 29 = MPSC = buffer 0 */ - /* bit 30 = IDMA = buffer 0 */ - /* bit 31 = Gigabit = buffer 0 */ - sdram_config_reg = sdram_config_reg | 0x58000000; - sdram_config_reg = sdram_config_reg & 0xffffff00; - /* bit 14 FBSplit = FCRAM controller bsplit enable. */ - /* bit 15 vw = FCRAM Variable write length enable. */ - /* bit 16 DType = Dram Type (0 = FCRAM,1 = Standard) */ - sdram_config_reg = sdram_config_reg | BIT14 | BIT15; - - /* write the value into the SDRAM configuration register */ - GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg); - debug("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG)); - - /* SDRAM open pages control keep open as much as I can */ - GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0); - debug - ("sdram_open_pages_controll 0x1414: %08x\n", - GTREGREAD (SDRAM_OPEN_PAGES_CONTROL)); - - /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ - tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */ - if (tmp == 0) - debug("Core Signals are sync (by HW-Setting)!!!\n"); - else - debug - ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"); - - /* SDRAM set CAS Latency according to SPD information */ - switch (info->memoryType) { - case SDRAM: - printf ("### SD-RAM not supported !!!\n"); - printf ("Aborting!!!\n"); - hang (); - /* ToDo fill SD-RAM if needed !!!!! */ - break; - /* Calculate the settings for SDRAM mode and Dunit control low registers */ - /* Values set according to technical bulletin TB-92 rev. c */ - case DDR: - debug("### SET-CL for DDR-RAM\n"); - /* ronen db64460 - change the tmp_dunit_control_low setting!!! */ - switch (info->maxClSupported_DDR) { - case DDR_CL_3: - tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */ - if (tmp == 1) { /* clocks sync */ - if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0x05110051; - else - tmp_dunit_control_low = 0x24110051; - debug - ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n"); - } else { /* clk sync. bypassed */ - - if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0xC5000540; - else - tmp_dunit_control_low = 0xC4000540; - debug - ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } - break; - case DDR_CL_2_5: - tmp_sdram_mode = 0x62; /* CL=2.5 Burstlength = 4 */ - if (tmp == 1) { /* clocks sync */ - if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0x25110051; - else - tmp_dunit_control_low = 0x24110051; - debug - ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n"); - } else { /* clk sync. bypassed */ - - if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0xC5000540; - /* printf("CL = 2.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */ - /* printf("Aborting!!!\n");1 */ - /* hang();1 */ - } else - tmp_dunit_control_low = 0xC4000540; - debug - ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } - break; - case DDR_CL_2: - tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */ - if (tmp == 1) { /* clocks sync */ - if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0x04110051; - else - tmp_dunit_control_low = 0x03110051; - debug - ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n"); - } else { /* clk sync. bypassed */ - - if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ - /*printf("CL = 2, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */ - /*printf("Aborting!!!\n");1 */ - /*hang();1 */ - tmp_dunit_control_low = 0xC4000540; - } else - tmp_dunit_control_low = 0xC3000540;; - debug - ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } - break; - case DDR_CL_1_5: - tmp_sdram_mode = 0x52; /* CL=1.5 Burstlength = 4 */ - if (tmp == 1) { /* clocks sync */ - if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ - tmp_dunit_control_low = 0x24110051; - else - tmp_dunit_control_low = 0x23110051; - debug - ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n"); - } else { /* clk sync. bypassed */ - - if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ - /*printf("CL = 1.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */ - /*printf("Aborting!!!\n");1 */ - /*hang();1 */ - tmp_dunit_control_low = 0xC4000540; - } else - tmp_dunit_control_low = 0xC3000540; - debug - ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } - break; - - default: - printf ("Max. CL is out of range %d\n", - info->maxClSupported_DDR); - hang (); - break; - } /* end DDR switch */ - break; - } /* end CL switch */ - - /* Write results of CL detection procedure */ - /* set SDRAM mode reg. 0x141c */ - GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode); - - /* set SDRAM mode SetCommand 0x1418 */ - GT_REG_WRITE (SDRAM_OPERATION, 0x3); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - debug - ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); - } - - /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ - GT_REG_WRITE (D_UNIT_CONTROL_LOW, tmp_dunit_control_low); - - /* set SDRAM mode SetCommand 0x1418 */ - GT_REG_WRITE (SDRAM_OPERATION, 0x3); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - debug - ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"); - } - -/*------------------------------------------------------------------------------ */ - - /* bank parameters */ - /* SDRAM address decode register 0x1410 */ - /* program this with the default value */ - tmp = 0x02; /* power-up default address select decoding value */ - - debug("drb_size (n*64Mbit): %d\n", info->drb_size); -/* figure out the DRAM chip size */ - sdram_chip_size = - (1 << (info->numOfRowAddresses + info->numOfColAddresses)); - sdram_chip_size *= info->sdramWidth; - sdram_chip_size *= 4; - debug("computed sdram chip size is %#lx\n", sdram_chip_size); - /* divide sdram chip size by 64 Mbits */ - sdram_chip_size = sdram_chip_size / 0x4000000; - switch (sdram_chip_size) { - case 1: /* 64 Mbit */ - case 2: /* 128 Mbit */ - debug("RAM-Device_size 64Mbit or 128Mbit)\n"); - tmp |= (0x00 << 4); - break; - case 4: /* 256 Mbit */ - case 8: /* 512 Mbit */ - debug("RAM-Device_size 256Mbit or 512Mbit)\n"); - tmp |= (0x01 << 4); - break; - case 16: /* 1 Gbit */ - case 32: /* 2 Gbit */ - debug("RAM-Device_size 1Gbit or 2Gbit)\n"); - tmp |= (0x02 << 4); - break; - default: - printf ("Error in dram size calculation\n"); - printf ("RAM-Device_size is unsupported\n"); - hang (); - } - - /* SDRAM address control */ - GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp); - debug - ("setting up sdram address control (0x1410) with: %08lx \n", - tmp); - -/* ------------------------------------------------------------------------------ */ -/* same settings for registerd & non-registerd DDR SDRAM */ - debug - ("setting up sdram_timing_control_low (0x1408) with: %08x \n", - 0x01501220); - /*ronen db64460 */ - GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x01501220); - - -/* ------------------------------------------------------------------------------ */ - - /* SDRAM configuration */ - tmp = GTREGREAD (SDRAM_CONFIG); - - if (info->registeredAddrAndControlInputs - || info->registeredDQMBinputs) { - tmp |= (1 << 17); - debug - ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n", - info->registeredAddrAndControlInputs, - info->registeredDQMBinputs); - } - - /* Use buffer 1 to return read data to the CPU - * Page 426 MV6indent: Standard input:1464: Warning:old style assignment ambiguity in "=*". Assuming "= *" - -indent: Standard input:1465: Warning:old style assignment ambiguity in "=*". Assuming "= *" - -4460 */ - tmp |= (1 << 26); - debug - ("Before Buffer assignment - sdram_conf (0x1400): %08x\n", - GTREGREAD (SDRAM_CONFIG)); - debug - ("After Buffer assignment - sdram_conf (0x1400): %08x\n", - GTREGREAD (SDRAM_CONFIG)); - - /* SDRAM timing To_do: */ -/* ------------------------------------------------------------------------------ */ - /* ronen db64460 */ - debug - ("setting up sdram_timing_control_high (0x140c) with: %08x \n", - 0xc); - GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0xc); - - debug - ("setting up sdram address pads control (0x14c0) with: %08x \n", - 0x7d5014a); - GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a); - - debug - ("setting up sdram data pads control (0x14c4) with: %08x \n", - 0x7d5014a); - GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a); - -/* ------------------------------------------------------------------------------ */ - - /* set the SDRAM configuration for each bank */ - -/* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */ - { - i = info->slot; - debug - ("\n*** Running a MRS cycle for bank %d ***\n", i); - - /* map the bank */ - memory_map_bank (i, 0, GB / 4); - - /* set SDRAM mode */ /* To_do check it */ - GT_REG_WRITE (SDRAM_OPERATION, 0x3); - check = GTREGREAD (SDRAM_OPERATION); - debug - ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", - check); - - - /* switch back to normal operation mode */ - GT_REG_WRITE (SDRAM_OPERATION, 0); - check = GTREGREAD (SDRAM_OPERATION); - debug - ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", - check); - - /* unmap the bank */ - memory_map_bank (i, 0, 0); - } - - return 0; - -} - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ -long int dram_size (long int *base, long int maxsize) -{ - volatile long int *addr, *b = base; - long int cnt, val, save1, save2; - -#define STARTVAL (1<<20) /* start test at 1M */ - for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long); - cnt <<= 1) { - addr = base + cnt; /* pointer arith! */ - - save1 = *addr; /* save contents of addr */ - save2 = *b; /* save contents of base */ - - *addr = cnt; /* write cnt to addr */ - *b = 0; /* put null at base */ - - /* check at base address */ - if ((*b) != 0) { - *addr = save1; /* restore *addr */ - *b = save2; /* restore *b */ - return (0); - } - val = *addr; /* read *addr */ - val = *addr; /* read *addr */ - - *addr = save1; - *b = save2; - - if (val != cnt) { - debug - ("Found %08x at Address %08x (failure)\n", - (unsigned int) val, (unsigned int) addr); - /* fix boundary condition.. STARTVAL means zero */ - if (cnt == STARTVAL / sizeof (long)) - cnt = 0; - return (cnt * sizeof (long)); - } - } - return maxsize; -} - -/* ------------------------------------------------------------------------- */ - -/* ppcboot interface function to SDRAM init - this is where all the - * controlling logic happens */ -phys_size_t initdram (int board_type) -{ - int checkbank[4] = {[0 ... 3] = 0 }; - ulong realsize, total; - AUX_MEM_DIMM_INFO dimmInfo1; - AUX_MEM_DIMM_INFO dimmInfo2; - int nhr, bank_no; - ulong dest, memSpaceAttr; - - /* first, use the SPD to get info about the SDRAM/ DDRRAM */ - - /* check the NHR bit and skip mem init if it's already done */ - nhr = get_hid0 () & (1 << 16); - - if (nhr) { - printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n"); - } else { - /* DIMM0 */ - check_dimm (0, &dimmInfo1); - - /* DIMM1 */ - check_dimm (1, &dimmInfo2); - - memory_map_bank (0, 0, 0); - memory_map_bank (1, 0, 0); - memory_map_bank (2, 0, 0); - memory_map_bank (3, 0, 0); - - /* ronen check correct set of DIMMS */ - if (dimmInfo1.numOfModuleBanks && dimmInfo2.numOfModuleBanks) { - if (dimmInfo1.errorCheckType != - dimmInfo2.errorCheckType) - printf ("***WARNNING***!!!! different ECC support of the DIMMS\n"); - if (dimmInfo1.maxClSupported_DDR != - dimmInfo2.maxClSupported_DDR) - printf ("***WARNNING***!!!! different CAL setting of the DIMMS\n"); - if (dimmInfo1.registeredAddrAndControlInputs != - dimmInfo2.registeredAddrAndControlInputs) - printf ("***WARNNING***!!!! different Registration setting of the DIMMS\n"); - } - - if (dimmInfo1.numOfModuleBanks && setup_sdram (&dimmInfo1)) { - printf ("Setup for DIMM1 failed.\n"); - } - - if (dimmInfo2.numOfModuleBanks && setup_sdram (&dimmInfo2)) { - printf ("Setup for DIMM2 failed.\n"); - } - - /* set the NHR bit */ - set_hid0 (get_hid0 () | (1 << 16)); - } - /* next, size the SDRAM banks */ - - realsize = total = 0; - if (dimmInfo1.numOfModuleBanks > 0) { - checkbank[0] = 1; - } - if (dimmInfo1.numOfModuleBanks > 1) { - checkbank[1] = 1; - } - if (dimmInfo1.numOfModuleBanks > 2) - printf ("Error, SPD claims DIMM1 has >2 banks\n"); - - printf ("-- DIMM1 has %d banks\n", dimmInfo1.numOfModuleBanks); - - if (dimmInfo2.numOfModuleBanks > 0) { - checkbank[2] = 1; - } - if (dimmInfo2.numOfModuleBanks > 1) { - checkbank[3] = 1; - } - if (dimmInfo2.numOfModuleBanks > 2) - printf ("Error, SPD claims DIMM2 has >2 banks\n"); - - printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks); - - for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) { - /* skip over banks that are not populated */ - if (!checkbank[bank_no]) - continue; - - /* ronen - realsize = dram_size((long int *)total, check); */ - if (bank_no == 0 || bank_no == 1) { - if (checkbank[1] == 1) - realsize = dimmInfo1.size / 2; - else - realsize = dimmInfo1.size; - } - if (bank_no == 2 || bank_no == 3) { - if (checkbank[3] == 1) - realsize = dimmInfo2.size / 2; - else - realsize = dimmInfo2.size; - } - memory_map_bank (bank_no, total, realsize); - - /* ronen - initialize the DRAM for ECC */ -#ifdef CONFIG_MV64460_ECC - if ((dimmInfo1.errorCheckType != 0) && - ((dimmInfo2.errorCheckType != 0) - || (dimmInfo2.numOfModuleBanks == 0))) { - printf ("ECC Initialization of Bank %d:", bank_no); - memSpaceAttr = ((~(BIT0 << bank_no)) & 0xf) << 8; - mvDmaSetMemorySpace (0, 0, memSpaceAttr, total, - realsize); - for (dest = total; dest < total + realsize; - dest += _8M) { - mvDmaTransfer (0, total, dest, _8M, - BIT8 /*DMA_DTL_128BYTES */ | - BIT3 /*DMA_HOLD_SOURCE_ADDR */ - | - BIT11 - /*DMA_BLOCK_TRANSFER_MODE */ ); - while (mvDmaIsChannelActive (0)); - } - printf (" PASS\n"); - } -#endif - - total += realsize; - } - - /* ronen */ - switch ((GTREGREAD (0x141c) >> 4) & 0x7) { - case 0x2: - printf ("CAS Latency = 2"); - break; - case 0x3: - printf ("CAS Latency = 3"); - break; - case 0x5: - printf ("CAS Latency = 1.5"); - break; - case 0x6: - printf ("CAS Latency = 2.5"); - break; - } - printf (" tRP = %d tRAS = %d tRCD=%d\n", - ((GTREGREAD (0x1408) >> 8) & 0xf) + 1, - ((GTREGREAD (0x1408) >> 20) & 0xf) + 1, - ((GTREGREAD (0x1408) >> 4) & 0xf) + 1); - -/* Setup Ethernet DMA Adress window to DRAM Area */ - if (total > _256M) - printf ("*** ONLY the first 256MB DRAM memory are used out of the "); - else - printf ("Total SDRAM memory is "); - /* (cause all the 4 BATS are taken) */ - return (total); -} - - -/* ronen- add Idma functions for usage of the ecc dram init. */ -/******************************************************************************* -* mvDmaIsChannelActive - Checks if a engine is busy. -********************************************************************************/ -int mvDmaIsChannelActive (int engine) -{ - ulong data; - - data = GTREGREAD (MV64460_DMA_CHANNEL0_CONTROL + 4 * engine); - if (data & BIT14 /*activity status */ ) { - return 1; - } - return 0; -} - -/******************************************************************************* -* mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding -* map. -*******************************************************************************/ -int mvDmaSetMemorySpace (ulong memSpace, - ulong memSpaceTarget, - ulong memSpaceAttr, ulong baseAddress, ulong size) -{ - ulong temp; - - /* The base address must be aligned to the size. */ - if (baseAddress % size != 0) { - return 0; - } - if (size >= 0x10000 /*64K */ ) { - size &= 0xffff0000; - baseAddress = (baseAddress & 0xffff0000); - /* Set the new attributes */ - GT_REG_WRITE (MV64460_DMA_BASE_ADDR_REG0 + memSpace * 8, - (baseAddress | memSpaceTarget | memSpaceAttr)); - GT_REG_WRITE ((MV64460_DMA_SIZE_REG0 + memSpace * 8), - (size - 1) & 0xffff0000); - temp = GTREGREAD (MV64460_DMA_BASE_ADDR_ENABLE_REG); - GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG, - (temp & ~(BIT0 << memSpace))); - return 1; - } - return 0; -} - - -/******************************************************************************* -* mvDmaTransfer - Transfer data from sourceAddr to destAddr on one of the 4 -* DMA channels. -********************************************************************************/ -int mvDmaTransfer (int engine, ulong sourceAddr, - ulong destAddr, ulong numOfBytes, ulong command) -{ - ulong engOffReg = 0; /* Engine Offset Register */ - - if (numOfBytes > 0xffff) { - command = command | BIT31 /*DMA_16M_DESCRIPTOR_MODE */ ; - } - command = command | ((command >> 6) & 0x7); - engOffReg = engine * 4; - GT_REG_WRITE (MV64460_DMA_CHANNEL0_BYTE_COUNT + engOffReg, - numOfBytes); - GT_REG_WRITE (MV64460_DMA_CHANNEL0_SOURCE_ADDR + engOffReg, - sourceAddr); - GT_REG_WRITE (MV64460_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg, - destAddr); - command = - command | BIT12 /*DMA_CHANNEL_ENABLE */ | BIT9 - /*DMA_NON_CHAIN_MODE */ ; - /* Activate DMA engine By writting to mvDmaControlRegister */ - GT_REG_WRITE (MV64460_DMA_CHANNEL0_CONTROL + engOffReg, command); - return 1; -} - -/**************************************************************************************** - * SDRAM INIT * - * This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb * - * This procedure fits only the Atlantis * - * * - ***************************************************************************************/ - - -/**************************************************************************************** - * DFCDL initialize MV643xx Design Considerations * - * * - ***************************************************************************************/ -int set_dfcdlInit (void) -{ - /*ronen the dfcdl init are done by the I2C */ - return (0); -} diff --git a/board/Marvell/include/core.h b/board/Marvell/include/core.h deleted file mode 100644 index 3119d0a..0000000 --- a/board/Marvell/include/core.h +++ /dev/null @@ -1,236 +0,0 @@ -/* Core.h - Basic core logic functions and definitions */ - -/* Copyright Galileo Technology. */ - -/* -DESCRIPTION -This header file contains simple read/write macros for addressing -the SDRAM, devices, GT`s internal registers and PCI (using the PCI`s address -space). The macros take care of Big/Little endian conversions. -*/ - -#ifndef __INCcoreh -#define __INCcoreh - -#include "mv_gen_reg.h" - -extern unsigned int INTERNAL_REG_BASE_ADDR; - -/****************************************/ -/* GENERAL Definitions */ -/****************************************/ - -#define NO_BIT 0x00000000 -#define BIT0 0x00000001 -#define BIT1 0x00000002 -#define BIT2 0x00000004 -#define BIT3 0x00000008 -#define BIT4 0x00000010 -#define BIT5 0x00000020 -#define BIT6 0x00000040 -#define BIT7 0x00000080 -#define BIT8 0x00000100 -#define BIT9 0x00000200 -#define BIT10 0x00000400 -#define BIT11 0x00000800 -#define BIT12 0x00001000 -#define BIT13 0x00002000 -#define BIT14 0x00004000 -#define BIT15 0x00008000 -#define BIT16 0x00010000 -#define BIT17 0x00020000 -#define BIT18 0x00040000 -#define BIT19 0x00080000 -#define BIT20 0x00100000 -#define BIT21 0x00200000 -#define BIT22 0x00400000 -#define BIT23 0x00800000 -#define BIT24 0x01000000 -#define BIT25 0x02000000 -#define BIT26 0x04000000 -#define BIT27 0x08000000 -#define BIT28 0x10000000 -#define BIT29 0x20000000 -#define BIT30 0x40000000 -#define BIT31 0x80000000 - -#define _1K 0x00000400 -#define _2K 0x00000800 -#define _4K 0x00001000 -#define _8K 0x00002000 -#define _16K 0x00004000 -#define _32K 0x00008000 -#define _64K 0x00010000 -#define _128K 0x00020000 -#define _256K 0x00040000 -#define _512K 0x00080000 - -#define _1M 0x00100000 -#define _2M 0x00200000 -#define _3M 0x00300000 -#define _4M 0x00400000 -#define _5M 0x00500000 -#define _6M 0x00600000 -#define _7M 0x00700000 -#define _8M 0x00800000 -#define _9M 0x00900000 -#define _10M 0x00a00000 -#define _11M 0x00b00000 -#define _12M 0x00c00000 -#define _13M 0x00d00000 -#define _14M 0x00e00000 -#define _15M 0x00f00000 -#define _16M 0x01000000 - -#define _32M 0x02000000 -#define _64M 0x04000000 -#define _128M 0x08000000 -#define _256M 0x10000000 -#define _512M 0x20000000 - -#define _1G 0x40000000 -#define _2G 0x80000000 - -/* Little to Big endian conversion macros */ - -#ifdef LE /* Little Endian */ -#define SHORT_SWAP(X) (X) -#define WORD_SWAP(X) (X) -#define LONG_SWAP(X) ((l64)(X)) - -#else /* Big Endian */ -#define SHORT_SWAP(X) ((X <<8 ) | (X >> 8)) - -#define WORD_SWAP(X) (((X)&0xff)<<24)+ \ - (((X)&0xff00)<<8)+ \ - (((X)&0xff0000)>>8)+ \ - (((X)&0xff000000)>>24) - -#define LONG_SWAP(X) ( (l64) (((X)&0xffULL)<<56)+ \ - (((X)&0xff00ULL)<<40)+ \ - (((X)&0xff0000ULL)<<24)+ \ - (((X)&0xff000000ULL)<<8)+ \ - (((X)&0xff00000000ULL)>>8)+ \ - (((X)&0xff0000000000ULL)>>24)+ \ - (((X)&0xff000000000000ULL)>>40)+ \ - (((X)&0xff00000000000000ULL)>>56)) - -#endif - -#ifndef NULL -#define NULL 0 -#endif - -/* Those two definitions were defined to be compatible with MIPS */ -#define NONE_CACHEABLE 0x00000000 -#define CACHEABLE 0x00000000 - -/* 750 cache line */ -#define CACHE_LINE_SIZE 32 -#define CACHELINE_MASK_BITS (CACHE_LINE_SIZE - 1) -#define CACHELINE_ROUNDUP(A) (((A)+CACHELINE_MASK_BITS) & ~CACHELINE_MASK_BITS) - -/* Read/Write to/from GT`s internal registers */ -#define GT_REG_READ(offset, pData) \ -*pData = ( *((volatile unsigned int *)(NONE_CACHEABLE | \ - INTERNAL_REG_BASE_ADDR | (offset))) ) ; \ -*pData = WORD_SWAP(*pData) - -#define GTREGREAD(offset) \ - (WORD_SWAP( *((volatile unsigned int *)(NONE_CACHEABLE | \ - INTERNAL_REG_BASE_ADDR | (offset))) )) - -#define GT_REG_WRITE(offset, data) \ -*((unsigned int *)( INTERNAL_REG_BASE_ADDR | (offset))) = \ - WORD_SWAP(data) - -/* Write 32/16/8 bit */ -#define WRITE_CHAR(address, data) \ - *((unsigned char *)(address)) = data -#define WRITE_SHORT(address, data) \ - *((unsigned short *)(address)) = data -#define WRITE_WORD(address, data) \ - *((unsigned int *)(address)) = data - -#define GT_WRITE_CHAR(address, data) WRITE_CHAR(address, data) - -/* Write 32/16/8 bit NonCacheable */ -/* -#define GT_WRITE_CHAR(address, data) \ - (*((unsigned char *)NONE_CACHEABLE(address))) = data -#define GT_WRITE_SHORT(address, data) \ - (*((unsigned short *)NONE_CACHEABLE(address))) = data -#define GT_WRITE_WORD(address, data) \ - (*((unsigned int *)NONE_CACHEABLE(address))) = data -*/ - /*#define GT_WRITE_CHAR(address, data) ((*((volatile unsigned char *)NONE_CACHEABLE((address)))) = ((unsigned char)(data)))1 */ - - /*#define GT_WRITE_SHORT(address, data) ((*((volatile unsigned short *)NONE_CACHEABLE((address)))) = ((unsigned short)(data)))1 */ - - /*#define GT_WRITE_WORD(address, data) ((*((volatile unsigned int *)NONE_CACHEABLE((address)))) = ((unsigned int)(data)))1 */ - - -/* Read 32/16/8 bits - returns data in variable. */ -#define READ_CHAR(address, pData) \ - *pData = *((volatile unsigned char *)(address)) - -#define READ_SHORT(address, pData) \ - *pData = *((volatile unsigned short *)(address)) - -#define READ_WORD(address, pData) \ - *pData = *((volatile unsigned int *)(address)) - -/* Read 32/16/8 bit - returns data direct. */ -#define READCHAR(address) \ - *((volatile unsigned char *)((address) | NONE_CACHEABLE)) - -#define READSHORT(address) \ - *((volatile unsigned short *)((address) | NONE_CACHEABLE)) - -#define READWORD(address) \ - *((volatile unsigned int *)((address) | NONE_CACHEABLE)) - -/* Those two Macros were defined to be compatible with MIPS */ -#define VIRTUAL_TO_PHY(x) (((unsigned int)x) & 0xffffffff) -#define PHY_TO_VIRTUAL(x) (((unsigned int)x) | NONE_CACHEABLE) - -/* SET_REG_BITS(regOffset,bits) - - gets register offset and bits: a 32bit value. It set to logic '1' in the - internal register the bits which given as an input example: - SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic - '1' in register 0x840 while the other bits stays as is. */ -#define SET_REG_BITS(regOffset,bits) \ - *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR | \ - regOffset) |= (unsigned int)WORD_SWAP(bits) - -/* RESET_REG_BITS(regOffset,bits) - - gets register offset and bits: a 32bit value. It set to logic '0' in the - internal register the bits which given as an input example: - RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic - '0' in register 0x840 while the other bits stays as is. */ -#define RESET_REG_BITS(regOffset,bits) \ - *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR \ - | regOffset) &= ~( (unsigned int)WORD_SWAP(bits) ) -/* gets register offset and bits: a 32bit value. It set to logic '1' in the - internal register the bits which given as an input example: - GT_SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic - '1' in register 0x840 while the other bits stays as is. */ - /*#define GT_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)(NONE_CACHEABLE(INTERNAL_REG_BASE_ADDR) | (regOffset)))) |= ((unsigned int)WORD_SWAP(bits)))1 */ - /*#define GT_SET_REG_BITS(regOffset,bits) RESET_REG_BITS(regOffset,bits)1 */ -#define GT_SET_REG_BITS(regOffset,bits) SET_REG_BITS(regOffset,bits) -/* gets register offset and bits: a 32bit value. It set to logic '0' in the - internal register the bits which given as an input example: - GT_RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to - logic '0' in register 0x840 while the other bits stays as is. */ - /*#define GT_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)(NONE_CACHEABLE(INTERNAL_REG_BASE_ADDR) | (regOffset)))) &= ~((unsigned int)WORD_SWAP(bits)))1 */ -#define GT_RESET_REG_BITS(regOffset,bits) RESET_REG_BITS(regOffset,bits) - - -#define DEBUG_LED0_ON() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x8000,0) -#define DEBUG_LED1_ON() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0xc000,0) -#define DEBUG_LED2_ON() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x10000,0) -#define DEBUG_LED0_OFF() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x14000,0) -#define DEBUG_LED1_OFF() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x18000,0) -#define DEBUG_LED2_OFF() WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x1c000,0) - -#endif /* __INCcoreh */ diff --git a/board/Marvell/include/mv_gen_reg.h b/board/Marvell/include/mv_gen_reg.h deleted file mode 100644 index 008185e..0000000 --- a/board/Marvell/include/mv_gen_reg.h +++ /dev/null @@ -1,2296 +0,0 @@ -/* mv_gen_reg.h - Internal registers definition file */ -/* Copyright - Galileo technology. */ - - -/******************************************************************************* -* Copyright 2002, GALILEO TECHNOLOGY, LTD. * -* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * -* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * -* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * -* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * -* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * -* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * -* * -* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * -* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * -* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * -* (MJKK), GALILEO TECHNOLOGY LTD. (GTL) AND GALILEO TECHNOLOGY, INC. (GTI). * -******************************************************************************** -* mv_gen_reg.h - Marvell 64360 and 64460 Internal registers definition file. -* -* DESCRIPTION: -* None. -* -* DEPENDENCIES: -* None. -* -*******************************************************************************/ - -#ifndef __INCmv_gen_regh -#define __INCmv_gen_regh - - -/* Supported by the Atlantis */ -#define INCLUDE_PCI_1 -#define INCLUDE_PCI_0_ARBITER -#define INCLUDE_PCI_1_ARBITER -#define INCLUDE_SNOOP_SUPPORT -#define INCLUDE_P2P -#define INCLUDE_ETH_PORT_2 -#define INCLUDE_CPU_MAPPING -#define INCLUDE_MPSC - -/* Not supported features */ -#undef INCLUDE_CNTMR_4_7 -#undef INCLUDE_DMA_4_7 - - -/****************************************/ -/* Processor Address Space */ -/****************************************/ -/* DDR SDRAM BAR and size registers */ - -/* Sdram's BAR'S */ -#define SCS_0_LOW_DECODE_ADDRESS 0x008 -#define SCS_0_HIGH_DECODE_ADDRESS 0x010 -#define SCS_1_LOW_DECODE_ADDRESS 0x208 -#define SCS_1_HIGH_DECODE_ADDRESS 0x210 -#define SCS_2_LOW_DECODE_ADDRESS 0x018 -#define SCS_2_HIGH_DECODE_ADDRESS 0x020 -#define SCS_3_LOW_DECODE_ADDRESS 0x218 -#define SCS_3_HIGH_DECODE_ADDRESS 0x220 - -/* Make it fit the MV64360 and MV64460 Lowlevel driver */ -#define CS_0_BASE_ADDR SCS_0_LOW_DECODE_ADDRESS -#define CS_0_SIZE SCS_0_HIGH_DECODE_ADDRESS -#define CS_1_BASE_ADDR SCS_1_LOW_DECODE_ADDRESS -#define CS_1_SIZE SCS_1_HIGH_DECODE_ADDRESS -#define CS_2_BASE_ADDR SCS_2_LOW_DECODE_ADDRESS -#define CS_2_SIZE SCS_2_HIGH_DECODE_ADDRESS -#define CS_3_BASE_ADDR SCS_3_LOW_DECODE_ADDRESS -#define CS_3_SIZE SCS_3_HIGH_DECODE_ADDRESS - -/* Devices BAR'S */ -#define CS_0_LOW_DECODE_ADDRESS 0x028 -#define CS_0_HIGH_DECODE_ADDRESS 0x030 -#define CS_1_LOW_DECODE_ADDRESS 0x228 -#define CS_1_HIGH_DECODE_ADDRESS 0x230 -#define CS_2_LOW_DECODE_ADDRESS 0x248 -#define CS_2_HIGH_DECODE_ADDRESS 0x250 -#define CS_3_LOW_DECODE_ADDRESS 0x038 -#define CS_3_HIGH_DECODE_ADDRESS 0x040 -#define BOOTCS_LOW_DECODE_ADDRESS 0x238 -#define BOOTCS_HIGH_DECODE_ADDRESS 0x240 - -/* Make it fit the MV64360 and MV64460 Lowlevel driver */ -/* Devices BAR and size registers */ - -#define DEV_CS0_BASE_ADDR CS_0_LOW_DECODE_ADDRESS -#define DEV_CS0_SIZE CS_0_HIGH_DECODE_ADDRESS -#define DEV_CS1_BASE_ADDR CS_1_LOW_DECODE_ADDRESS -#define DEV_CS1_SIZE CS_1_HIGH_DECODE_ADDRESS -#define DEV_CS2_BASE_ADDR CS_2_LOW_DECODE_ADDRESS -#define DEV_CS2_SIZE CS_2_HIGH_DECODE_ADDRESS -#define DEV_CS3_BASE_ADDR CS_3_LOW_DECODE_ADDRESS -#define DEV_CS3_SIZE CS_3_HIGH_DECODE_ADDRESS -#define BOOTCS_BASE_ADDR BOOTCS_LOW_DECODE_ADDRESS -#define BOOTCS_SIZE BOOTCS_HIGH_DECODE_ADDRESS - -/* PCI 0 BAR and size registers old names of evb64260*/ - -#define PCI_0I_O_LOW_DECODE_ADDRESS 0x048 -#define PCI_0I_O_HIGH_DECODE_ADDRESS 0x050 -#define PCI_0MEMORY0_LOW_DECODE_ADDRESS 0x058 -#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS 0x060 -#define PCI_0MEMORY1_LOW_DECODE_ADDRESS 0x080 -#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS 0x088 -#define PCI_0MEMORY2_LOW_DECODE_ADDRESS 0x258 -#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS 0x260 -#define PCI_0MEMORY3_LOW_DECODE_ADDRESS 0x280 -#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS 0x288 - -/* Make it fit the MV64360 and MV64460 Lowlevel driver */ -#define PCI_0_IO_BASE_ADDR 0x048 -#define PCI_0_IO_SIZE 0x050 -#define PCI_0_MEMORY0_BASE_ADDR 0x058 -#define PCI_0_MEMORY0_SIZE 0x060 -#define PCI_0_MEMORY1_BASE_ADDR 0x080 -#define PCI_0_MEMORY1_SIZE 0x088 -#define PCI_0_MEMORY2_BASE_ADDR 0x258 -#define PCI_0_MEMORY2_SIZE 0x260 -#define PCI_0_MEMORY3_BASE_ADDR 0x280 -#define PCI_0_MEMORY3_SIZE 0x288 - -/* PCI 1 BAR and size registers old names of evb64260*/ -#define PCI_1I_O_LOW_DECODE_ADDRESS 0x090 -#define PCI_1I_O_HIGH_DECODE_ADDRESS 0x098 -#define PCI_1MEMORY0_LOW_DECODE_ADDRESS 0x0a0 -#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS 0x0a8 -#define PCI_1MEMORY1_LOW_DECODE_ADDRESS 0x0b0 -#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS 0x0b8 -#define PCI_1MEMORY2_LOW_DECODE_ADDRESS 0x2a0 -#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS 0x2a8 -#define PCI_1MEMORY3_LOW_DECODE_ADDRESS 0x2b0 -#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS 0x2b8 - -/* Make it fit the MV64360 and MV64460 Lowlevel driver */ -#define PCI_1_IO_BASE_ADDR 0x090 -#define PCI_1_IO_SIZE 0x098 -#define PCI_1_MEMORY0_BASE_ADDR 0x0a0 -#define PCI_1_MEMORY0_SIZE 0x0a8 -#define PCI_1_MEMORY1_BASE_ADDR 0x0b0 -#define PCI_1_MEMORY1_SIZE 0x0b8 -#define PCI_1_MEMORY2_BASE_ADDR 0x2a0 -#define PCI_1_MEMORY2_SIZE 0x2a8 -#define PCI_1_MEMORY3_BASE_ADDR 0x2b0 -#define PCI_1_MEMORY3_SIZE 0x2b8 - -/* internal registers space base address */ -#define INTERNAL_SPACE_DECODE 0x068 -#define INTERNAL_SPACE_BASE_ADDR INTERNAL_SPACE_DECODE - -/* SRAM base address */ -#define INTEGRATED_SRAM_BASE_ADDR 0x268 - -/* Enables the CS , DEV_CS , PCI 0 and PCI 1 - windows above */ -#define BASE_ADDR_ENABLE 0x278 - - -#define CPU_0_LOW_DECODE_ADDRESS 0x290 -#define CPU_0_HIGH_DECODE_ADDRESS 0x298 -#define CPU_1_LOW_DECODE_ADDRESS 0x2c0 -#define CPU_1_HIGH_DECODE_ADDRESS 0x2c8 - -/****************************************/ -/* PCI remap registers */ -/****************************************/ -/*****************************************************************************************/ - /* PCI 0 */ -/* old fashion evb 64260 */ -#define PCI_0I_O_ADDRESS_REMAP 0x0f0 -#define PCI_0MEMORY0_ADDRESS_REMAP 0x0f8 -#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP 0x320 -#define PCI_0MEMORY1_ADDRESS_REMAP 0x100 -#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP 0x328 -#define PCI_0MEMORY2_ADDRESS_REMAP 0x2f8 -#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP 0x330 -#define PCI_0MEMORY3_ADDRESS_REMAP 0x300 -#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP 0x338 - -#define PCI_0_IO_ADDR_REMAP PCI_0I_O_ADDRESS_REMAP -#define PCI_0_MEMORY0_LOW_ADDR_REMAP PCI_0MEMORY0_ADDRESS_REMAP -#define PCI_0_MEMORY0_HIGH_ADDR_REMAP PCI_0MEMORY0_HIGH_ADDRESS_REMAP -#define PCI_0_MEMORY1_LOW_ADDR_REMAP PCI_0MEMORY1_ADDRESS_REMAP -#define PCI_0_MEMORY1_HIGH_ADDR_REMAP PCI_0MEMORY1_HIGH_ADDRESS_REMAP -#define PCI_0_MEMORY2_LOW_ADDR_REMAP PCI_0MEMORY2_ADDRESS_REMAP -#define PCI_0_MEMORY2_HIGH_ADDR_REMAP PCI_0MEMORY2_HIGH_ADDRESS_REMAP -#define PCI_0_MEMORY3_LOW_ADDR_REMAP PCI_0MEMORY3_ADDRESS_REMAP -#define PCI_0_MEMORY3_HIGH_ADDR_REMAP PCI_0MEMORY3_HIGH_ADDRESS_REMAP - - /* PCI 1 */ -/* old fashion evb 64260 */ -#define PCI_1I_O_ADDRESS_REMAP 0x108 -#define PCI_1MEMORY0_ADDRESS_REMAP 0x110 -#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP 0x340 -#define PCI_1MEMORY1_ADDRESS_REMAP 0x118 -#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP 0x348 -#define PCI_1MEMORY2_ADDRESS_REMAP 0x310 -#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP 0x350 -#define PCI_1MEMORY3_ADDRESS_REMAP 0x318 -#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP 0x358 - -#define PCI_1_IO_ADDR_REMAP PCI_1I_O_ADDRESS_REMAP -#define PCI_1_MEMORY0_LOW_ADDR_REMAP PCI_1MEMORY0_ADDRESS_REMAP -#define PCI_1_MEMORY0_HIGH_ADDR_REMAP PCI_1MEMORY0_HIGH_ADDRESS_REMAP -#define PCI_1_MEMORY1_LOW_ADDR_REMAP PCI_1MEMORY1_ADDRESS_REMAP -#define PCI_1_MEMORY1_HIGH_ADDR_REMAP PCI_1MEMORY1_HIGH_ADDRESS_REMAP -#define PCI_1_MEMORY2_LOW_ADDR_REMAP PCI_1MEMORY2_ADDRESS_REMAP -#define PCI_1_MEMORY2_HIGH_ADDR_REMAP PCI_1MEMORY2_HIGH_ADDRESS_REMAP -#define PCI_1_MEMORY3_LOW_ADDR_REMAP PCI_1MEMORY3_ADDRESS_REMAP -#define PCI_1_MEMORY3_HIGH_ADDR_REMAP PCI_1MEMORY3_HIGH_ADDRESS_REMAP - -/* old fashion evb 64260 */ -#define CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0 -#define CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8 -#define CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0 -#define CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8 -#define CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0 -#define CPU_GE_HEADERS_RETARGET_BASE 0x3d8 - -/* MV64360 and MV64460 no changes needed*/ -/*****************************************************************************************/ - -/****************************************/ -/* CPU Control Registers */ -/****************************************/ -/* CPU MASTER CONTROL REGISTER */ -#define CPU_CONFIGURATION 0x000 -#define CPU_MASTER_CONTROL 0x160 - -#define CPU_CONFIG 0x000 -#define CPU_MODE 0x120 -#define CPU_MASTER_CONTROL 0x160 -/* new in MV64360 and MV64460 */ -#define CPU_CROSS_BAR_CONTROL_LOW 0x150 -#define CPU_CROSS_BAR_CONTROL_HIGH 0x158 -#define CPU_CROSS_BAR_TIMEOUT 0x168 - -/****************************************/ -/* SMP RegisterS */ -/****************************************/ - -#define SMP_WHO_AM_I 0x200 -#define SMP_CPU0_DOORBELL 0x214 -#define SMP_CPU0_DOORBELL_CLEAR 0x21C -#define SMP_CPU1_DOORBELL 0x224 -#define SMP_CPU1_DOORBELL_CLEAR 0x22C -#define SMP_CPU0_DOORBELL_MASK 0x234 -#define SMP_CPU1_DOORBELL_MASK 0x23C -#define SMP_SEMAPHOR0 0x244 -#define SMP_SEMAPHOR1 0x24c -#define SMP_SEMAPHOR2 0x254 -#define SMP_SEMAPHOR3 0x25c -#define SMP_SEMAPHOR4 0x264 -#define SMP_SEMAPHOR5 0x26c -#define SMP_SEMAPHOR6 0x274 -#define SMP_SEMAPHOR7 0x27c - - -/****************************************/ -/* CPU Sync Barrier */ -/****************************************/ -#define CPU_0_SYNC_BARRIER_TRIGGER 0x0c0 -#define CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8 -#define CPU_1_SYNC_BARRIER_TRIGGER 0x0d0 -#define CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8 - - -/****************************************/ -/* CPU Access Protect */ -/****************************************/ - -#define CPU_LOW_PROTECT_ADDRESS_0 0x180 -#define CPU_HIGH_PROTECT_ADDRESS_0 0x188 -#define CPU_LOW_PROTECT_ADDRESS_1 0x190 -#define CPU_HIGH_PROTECT_ADDRESS_1 0x198 -#define CPU_LOW_PROTECT_ADDRESS_2 0x1a0 -#define CPU_HIGH_PROTECT_ADDRESS_2 0x1a8 -#define CPU_LOW_PROTECT_ADDRESS_3 0x1b0 -#define CPU_HIGH_PROTECT_ADDRESS_3 0x1b8 -/*#define CPU_LOW_PROTECT_ADDRESS_4 0x1c0 -#define CPU_HIGH_PROTECT_ADDRESS_4 0x1c8 -#define CPU_LOW_PROTECT_ADDRESS_5 0x1d0 -#define CPU_HIGH_PROTECT_ADDRESS_5 0x1d8 -#define CPU_LOW_PROTECT_ADDRESS_6 0x1e0 -#define CPU_HIGH_PROTECT_ADDRESS_6 0x1e8 -#define CPU_LOW_PROTECT_ADDRESS_7 0x1f0 -#define CPU_HIGH_PROTECT_ADDRESS_7 0x1f8 -*/ - -#define CPU_PROTECT_WINDOW_0_BASE_ADDR CPU_LOW_PROTECT_ADDRESS_0 /* 0x180 */ -#define CPU_PROTECT_WINDOW_0_SIZE CPU_HIGH_PROTECT_ADDRESS_0 /* 0x188 */ -#define CPU_PROTECT_WINDOW_1_BASE_ADDR CPU_LOW_PROTECT_ADDRESS_1 /* 0x190 */ -#define CPU_PROTECT_WINDOW_1_SIZE CPU_HIGH_PROTECT_ADDRESS_1 /* 0x198 */ -#define CPU_PROTECT_WINDOW_2_BASE_ADDR CPU_LOW_PROTECT_ADDRESS_2 /*0x1a0 */ -#define CPU_PROTECT_WINDOW_2_SIZE CPU_HIGH_PROTECT_ADDRESS_2 /* 0x1a8 */ -#define CPU_PROTECT_WINDOW_3_BASE_ADDR CPU_LOW_PROTECT_ADDRESS_3 /* 0x1b0 */ -#define CPU_PROTECT_WINDOW_3_SIZE CPU_HIGH_PROTECT_ADDRESS_3 /* 0x1b8 */ - - -/****************************************/ -/* Snoop Control */ -/****************************************/ - -/*#define SNOOP_BASE_ADDRESS_0 0x380 -#define SNOOP_TOP_ADDRESS_0 0x388 -#define SNOOP_BASE_ADDRESS_1 0x390 -#define SNOOP_TOP_ADDRESS_1 0x398 -#define SNOOP_BASE_ADDRESS_2 0x3a0 -#define SNOOP_TOP_ADDRESS_2 0x3a8 -#define SNOOP_BASE_ADDRESS_3 0x3b0 -#define SNOOP_TOP_ADDRESS_3 0x3b8 -*/ - -/****************************************/ -/* Integrated SRAM Registers */ -/****************************************/ - -#define SRAM_CONFIG 0x380 -#define SRAM_TEST_MODE 0x3F4 -#define SRAM_ERROR_CAUSE 0x388 -#define SRAM_ERROR_ADDR 0x390 -#define SRAM_ERROR_ADDR_HIGH 0x3F8 -#define SRAM_ERROR_DATA_LOW 0x398 -#define SRAM_ERROR_DATA_HIGH 0x3a0 -#define SRAM_ERROR_DATA_PARITY 0x3a8 - -/****************************************/ -/* CPU Error Report */ -/****************************************/ - -#define CPU_ERROR_ADDRESS_LOW 0x070 -#define CPU_ERROR_ADDRESS_HIGH 0x078 -#define CPU_ERROR_DATA_LOW 0x128 -#define CPU_ERROR_DATA_HIGH 0x130 -#define CPU_ERROR_PARITY 0x138 -#define CPU_ERROR_CAUSE 0x140 -#define CPU_ERROR_MASK 0x148 - -#define CPU_ERROR_ADDR_LOW CPU_ERROR_ADDRESS_LOW /* 0x0701 */ -#define CPU_ERROR_ADDR_HIGH CPU_ERROR_ADDRESS_HIGH /* 0x0781 */ - -/****************************************/ -/* Pslave Debug */ -/* CPU Interface Debug Registers */ -/****************************************/ - -#define X_0_ADDRESS 0x360 -#define X_0_COMMAND_ID 0x368 -#define X_1_ADDRESS 0x370 -#define X_1_COMMAND_ID 0x378 - /*#define WRITE_DATA_LOW 0x3c01 */ - /*#define WRITE_DATA_HIGH 0x3c81 */ - /*#define WRITE_BYTE_ENABLE 0x3e01 */ - /*#define READ_DATA_LOW 0x3d01 */ - /*#define READ_DATA_HIGH 0x3d81 */ - /*#define READ_ID 0x3e81 */ - -#define PUNIT_SLAVE_DEBUG_LOW X_0_ADDRESS /* 0x3601 */ -#define PUNIT_SLAVE_DEBUG_HIGH X_0_COMMAND_ID /* 0x3681 */ -#define PUNIT_MASTER_DEBUG_LOW X_1_ADDRESS /* 0x3701 */ -#define PUNIT_MASTER_DEBUG_HIGH X_1_COMMAND_ID /* 0x3781 */ -#define PUNIT_MMASK 0x3e4 - - -/****************************************/ -/* SDRAM and Device Address Space */ -/****************************************/ - -/****************************************/ -/* SDRAM Configuration */ -/****************************************/ -#define SDRAM_CONFIG 0x1400 /* MV64260 0x448 some changes*/ -#define D_UNIT_CONTROL_LOW 0x1404 /* NEW in MV64360 and MV64460 */ -#define D_UNIT_CONTROL_HIGH 0x1424 /* NEW in MV64360 and MV64460 */ -#define SDRAM_TIMING_CONTROL_LOW 0x1408 /* MV64260 0x4b4 new SDRAM TIMING REGISTER */ -#define SDRAM_TIMING_CONTROL_HIGH 0x140c /* MV64260 0x4b4 new SDRAM TIMING REGISTER */ -#define SDRAM_ADDR_CONTROL 0x1410 /* MV64260 0x47c some changes*/ -#define SDRAM_OPEN_PAGES_CONTROL 0x1414 /* NEW in MV64360 and MV64460 */ -#define SDRAM_OPERATION 0x1418 /* MV64260 0x474 some changes*/ -#define SDRAM_MODE 0x141c /* NEW in MV64360 and MV64460 */ -#define EXTENDED_DRAM_MODE 0x1420 /* NEW in MV64360 and MV64460 */ -#define SDRAM_CROSS_BAR_CONTROL_LOW 0x1430 /* MV64260 0x4a8 NO changes*/ -#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434 /* MV64260 0x4ac NO changes*/ -#define SDRAM_CROSS_BAR_TIMEOUT 0x1438 /* MV64260 0x4b0 NO changes*/ -#define SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0 /* what is this ??? */ -#define SDRAM_DATA_PADS_CALIBRATION 0x14c4 /* what is this ??? */ -/****************************************/ -/* SDRAM Configuration MV64260 */ -/****************************************/ - /*#define SDRAM_CONFIGURATION 0x4481 */ - /*#define SDRAM_OPERATION_MODE 0x4741 */ - /*#define SDRAM_ADDRESS_DECODE 0x47c1 */ - /*#define SDRAM_UMA_CONTROL 0x4a4 eliminated in MV64360 and MV64460 */ - /*#define SDRAM_CROSS_BAR_CONTROL_LOW 0x4a81 */ - /*#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac1 */ - /*#define SDRAM_CROSS_BAR_TIMEOUT 0x4b01 */ - /*#define SDRAM_TIMING 0x4b41 */ - - -/****************************************/ -/* SDRAM Error Report */ -/****************************************/ -#define SDRAM_ERROR_DATA_LOW 0x1444 /* MV64260 0x484 NO changes*/ -#define SDRAM_ERROR_DATA_HIGH 0x1440 /* MV64260 0x480 NO changes*/ -#define SDRAM_ERROR_ADDR 0x1450 /* MV64260 0x490 NO changes*/ -#define SDRAM_RECEIVED_ECC 0x1448 /* MV64260 0x488 NO changes*/ -#define SDRAM_CALCULATED_ECC 0x144c /* MV64260 0x48c NO changes*/ -#define SDRAM_ECC_CONTROL 0x1454 /* MV64260 0x494 NO changes*/ -#define SDRAM_ECC_ERROR_COUNTER 0x1458 /* MV64260 0x498 NO changes*/ -#define SDRAM_MMASK 0x1B40 /* NEW Register in MV64360 and MV64460 DO NOT USE !!!*/ -/****************************************/ -/* SDRAM Error Report MV64260 */ -/****************************************/ - /*#define SDRAM_ERROR_DATA_LOW 0x4841 */ - /*#define SDRAM_ERROR_DATA_HIGH 0x4801 */ - /*#define SDRAM_AND_DEVICE_ERROR_ADDRESS 0x4901 */ - /*#define SDRAM_RECEIVED_ECC 0x4881 */ - /*#define SDRAM_CALCULATED_ECC 0x48c1 */ - /*#define SDRAM_ECC_CONTROL 0x4941 */ - /*#define SDRAM_ECC_ERROR_COUNTER 0x4981 */ - -/******************************************/ -/* Controlled Delay Line (CDL) Registers */ -/******************************************/ -#define DFCDL_CONFIG0 0x1480 -#define DFCDL_CONFIG1 0x1484 -#define DLL_WRITE 0x1488 -#define DLL_READ 0x148c -#define SRAM_ADDR 0x1490 -#define SRAM_DATA0 0x1494 -#define SRAM_DATA1 0x1498 -#define SRAM_DATA2 0x149c -#define DFCL_PROBE 0x14a0 - - -/****************************************/ -/* SDRAM Parameters only in MV64260 */ -/****************************************/ - - /*#define SDRAM_BANK0PARAMETERS 0x44C eliminated in MV64360 and MV64460 */ - /*#define SDRAM_BANK1PARAMETERS 0x450 eliminated in MV64360 and MV64460 */ - /*#define SDRAM_BANK2PARAMETERS 0x454 eliminated in MV64360 and MV64460 */ - /*#define SDRAM_BANK3PARAMETERS 0x458 eliminated in MV64360 and MV64460 */ - -/******************************************/ -/* Debug Registers */ -/******************************************/ - -#define DUNIT_DEBUG_LOW 0x1460 -#define DUNIT_DEBUG_HIGH 0x1464 -#define DUNIT_MMASK 0x1b40 - -/****************************************/ -/* SDunit Debug (for internal use) */ -/****************************************/ - -#define X0_ADDRESS 0x500 -#define X0_COMMAND_AND_ID 0x504 -#define X0_WRITE_DATA_LOW 0x508 -#define X0_WRITE_DATA_HIGH 0x50c -#define X0_WRITE_BYTE_ENABLE 0x518 -#define X0_READ_DATA_LOW 0x510 -#define X0_READ_DATA_HIGH 0x514 -#define X0_READ_ID 0x51c -#define X1_ADDRESS 0x520 -#define X1_COMMAND_AND_ID 0x524 -#define X1_WRITE_DATA_LOW 0x528 -#define X1_WRITE_DATA_HIGH 0x52c -#define X1_WRITE_BYTE_ENABLE 0x538 -#define X1_READ_DATA_LOW 0x530 -#define X1_READ_DATA_HIGH 0x534 -#define X1_READ_ID 0x53c -#define X0_SNOOP_ADDRESS 0x540 -#define X0_SNOOP_COMMAND 0x544 -#define X1_SNOOP_ADDRESS 0x548 -#define X1_SNOOP_COMMAND 0x54c - -/****************************************/ -/* Device Parameters */ -/****************************************/ - -#define DEVICE_BANK0PARAMETERS 0x45c -#define DEVICE_BANK1PARAMETERS 0x460 -#define DEVICE_BANK2PARAMETERS 0x464 -#define DEVICE_BANK3PARAMETERS 0x468 -#define DEVICE_BOOT_BANK_PARAMETERS 0x46c -#define DEVICE_CONTROL 0x4c0 -#define DEVICE_CROSS_BAR_CONTROL_LOW 0x4c8 -#define DEVICE_CROSS_BAR_CONTROL_HIGH 0x4cc -#define DEVICE_CROSS_BAR_TIMEOUT 0x4c4 - -/****************************************/ -/* Device Parameters */ -/****************************************/ - -#define DEVICE_BANK0_PARAMETERS DEVICE_BANK0PARAMETERS /* 0x45c1 */ -#define DEVICE_BANK1_PARAMETERS DEVICE_BANK1PARAMETERS /* 0x4601 */ -#define DEVICE_BANK2_PARAMETERS DEVICE_BANK2PARAMETERS /* 0x4641 */ -#define DEVICE_BANK3_PARAMETERS DEVICE_BANK3PARAMETERS /* 0x4681 */ -/*#define DEVICE_BOOT_BANK_PARAMETERS 0x46c1 */ -#define DEVICE_INTERFACE_CONTROL DEVICE_CONTROL /* 0x4c01 */ -#define DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW DEVICE_CROSS_BAR_CONTROL_LOW /* 0x4c81 */ -#define DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH DEVICE_CROSS_BAR_CONTROL_HIGH /* 0x4cc1 */ -#define DEVICE_INTERFACE_CROSS_BAR_TIMEOUT DEVICE_CROSS_BAR_TIMEOUT /* 0x4c41 */ - - -/****************************************/ -/* Device Interrupt */ -/****************************************/ - -#define DEVICE_INTERRUPT_CAUSE 0x4d0 -#define DEVICE_INTERRUPT_MASK 0x4d4 -#define DEVICE_ERROR_ADDRESS 0x4d8 - /*#define DEVICE_INTERRUPT_CAUSE 0x4d01 */ - /*#define DEVICE_INTERRUPT_MASK 0x4d41 */ -#define DEVICE_ERROR_ADDR DEVICE_ERROR_ADDRESS /*0x4d81 */ -#define DEVICE_ERROR_DATA 0x4dc -#define DEVICE_ERROR_PARITY 0x4e0 - -/****************************************/ -/* Device debug registers */ -/****************************************/ - -#define DEVICE_DEBUG_LOW 0x4e4 -#define DEVICE_DEBUG_HIGH 0x4e8 -#define RUNIT_MMASK 0x4f0 - -/****************************************/ -/* DMA Record */ -/****************************************/ - - /*#define CHANNEL4_DMA_BYTE_COUNT 0x9001 */ - /*#define CHANNEL5_DMA_BYTE_COUNT 0x9041 */ - /*#define CHANNEL6_DMA_BYTE_COUNT 0x9081 */ - /*#define CHANNEL7_DMA_BYTE_COUNT 0x90C1 */ - /*#define CHANNEL4_DMA_SOURCE_ADDRESS 0x9101 */ - /*#define CHANNEL5_DMA_SOURCE_ADDRESS 0x9141 */ - /*#define CHANNEL6_DMA_SOURCE_ADDRESS 0x9181 */ - /*#define CHANNEL7_DMA_SOURCE_ADDRESS 0x91C1 */ - /*#define CHANNEL4_DMA_DESTINATION_ADDRESS 0x9201 */ - /*#define CHANNEL5_DMA_DESTINATION_ADDRESS 0x9241 */ - /*#define CHANNEL6_DMA_DESTINATION_ADDRESS 0x9281 */ - /*#define CHANNEL7_DMA_DESTINATION_ADDRESS 0x92C1 */ - /*#define CHANNEL4NEXT_RECORD_POINTER 0x9301 */ - /*#define CHANNEL5NEXT_RECORD_POINTER 0x9341 */ - /*#define CHANNEL6NEXT_RECORD_POINTER 0x9381 */ - /*#define CHANNEL7NEXT_RECORD_POINTER 0x93C1 */ - /*#define CHANNEL4CURRENT_DESCRIPTOR_POINTER 0x9701 */ - /*#define CHANNEL5CURRENT_DESCRIPTOR_POINTER 0x9741 */ - /*#define CHANNEL6CURRENT_DESCRIPTOR_POINTER 0x9781 */ - /*#define CHANNEL7CURRENT_DESCRIPTOR_POINTER 0x97C1 */ - /*#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS 0x8901 */ - /*#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS 0x8941 */ - /*#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS 0x8981 */ - /*#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS 0x89c1 */ - /*#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS 0x9901 */ - /*#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS 0x9941 */ - /*#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS 0x9981 */ - /*#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS 0x99c1 */ - /*#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a01 */ - /*#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a41 */ - /*#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a81 */ - /*#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8ac1 */ - /*#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a01 */ - /*#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a41 */ - /*#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a81 */ - /*#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9ac1 */ - /*#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b01 */ - /*#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b41 */ - /*#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b81 */ - /*#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8bc1 */ - /*#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b01 */ - /*#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b41 */ - /*#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b81 */ - /*#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9bc1 */ - -/****************************************/ -/* DMA Channel Control */ -/****************************************/ - -#define CHANNEL0CONTROL 0x840 -#define CHANNEL0CONTROL_HIGH 0x880 -#define CHANNEL1CONTROL 0x844 -#define CHANNEL1CONTROL_HIGH 0x884 -#define CHANNEL2CONTROL 0x848 -#define CHANNEL2CONTROL_HIGH 0x888 -#define CHANNEL3CONTROL 0x84C -#define CHANNEL3CONTROL_HIGH 0x88C - -#define DMA_CHANNEL0_CONTROL CHANNEL0CONTROL /*0x8401 */ -#define DMA_CHANNEL0_CONTROL_HIGH CHANNEL0CONTROL_HIGH /*0x8801 */ -#define DMA_CHANNEL1_CONTROL CHANNEL1CONTROL /* 0x8441 */ -#define DMA_CHANNEL1_CONTROL_HIGH CHANNEL1CONTROL_HIGH /*0x8841 */ -#define DMA_CHANNEL2_CONTROL CHANNEL2CONTROL /*0x8481 */ -#define DMA_CHANNEL2_CONTROL_HIGH CHANNEL2CONTROL_HIGH /*0x8881 */ -#define DMA_CHANNEL3_CONTROL CHANNEL3CONTROL /*0x84C1 */ -#define DMA_CHANNEL3_CONTROL_HIGH CHANNEL3CONTROL_HIGH /*0x88C1 */ - - /*#define CHANNEL4CONTROL 0x9401 */ - /*#define CHANNEL4CONTROL_HIGH 0x9801 */ - /*#define CHANNEL5CONTROL 0x9441 */ - /*#define CHANNEL5CONTROL_HIGH 0x9841 */ - /*#define CHANNEL6CONTROL 0x9481 */ - /*#define CHANNEL6CONTROL_HIGH 0x9881 */ - /*#define CHANNEL7CONTROL 0x94C1 */ - /*#define CHANNEL7CONTROL_HIGH 0x98C1 */ - - -/****************************************/ -/* DMA Arbiter */ -/****************************************/ - - /*#define ARBITER_CONTROL_0_3 0x8601 */ -#define ARBITER_CONTROL_4_7 0x960 -/****************************************/ -/* IDMA Registers */ -/****************************************/ - -#define DMA_CHANNEL0_BYTE_COUNT CHANNEL0_DMA_BYTE_COUNT /*0x8001 */ -#define DMA_CHANNEL1_BYTE_COUNT CHANNEL1_DMA_BYTE_COUNT /*0x8041 */ -#define DMA_CHANNEL2_BYTE_COUNT CHANNEL2_DMA_BYTE_COUNT /*0x8081 */ -#define DMA_CHANNEL3_BYTE_COUNT CHANNEL3_DMA_BYTE_COUNT /*0x80C1 */ -#define DMA_CHANNEL0_SOURCE_ADDR CHANNEL0_DMA_SOURCE_ADDRESS /*0x8101 */ -#define DMA_CHANNEL1_SOURCE_ADDR CHANNEL1_DMA_SOURCE_ADDRESS /*0x8141 */ -#define DMA_CHANNEL2_SOURCE_ADDR CHANNEL2_DMA_SOURCE_ADDRESS /*0x8181 */ -#define DMA_CHANNEL3_SOURCE_ADDR CHANNEL3_DMA_SOURCE_ADDRESS /*0x81c1 */ -#define DMA_CHANNEL0_DESTINATION_ADDR CHANNEL0_DMA_DESTINATION_ADDRESS /*0x8201 */ -#define DMA_CHANNEL1_DESTINATION_ADDR CHANNEL1_DMA_DESTINATION_ADDRESS /*0x8241 */ -#define DMA_CHANNEL2_DESTINATION_ADDR CHANNEL2_DMA_DESTINATION_ADDRESS /*0x8281 */ -#define DMA_CHANNEL3_DESTINATION_ADDR CHANNEL3_DMA_DESTINATION_ADDRESS /*0x82C1 */ -#define DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER CHANNEL0NEXT_RECORD_POINTER /*0x8301 */ -#define DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER CHANNEL1NEXT_RECORD_POINTER /*0x8341 */ -#define DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER CHANNEL2NEXT_RECORD_POINTER /*0x8381 */ -#define DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER CHANNEL3NEXT_RECORD_POINTER /*0x83C1 */ -#define DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER CHANNEL0CURRENT_DESCRIPTOR_POINTER /*0x8701 */ -#define DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER CHANNEL1CURRENT_DESCRIPTOR_POINTER /*0x8741 */ -#define DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER CHANNEL2CURRENT_DESCRIPTOR_POINTER /*0x8781 */ -#define DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER CHANNEL3CURRENT_DESCRIPTOR_POINTER /*0x87C1 */ - -#define CHANNEL3CURRENT_DESCRIPTOR_POINTER 0x87C -#define CHANNEL2CURRENT_DESCRIPTOR_POINTER 0x878 -#define CHANNEL1CURRENT_DESCRIPTOR_POINTER 0x874 -#define CHANNEL0CURRENT_DESCRIPTOR_POINTER 0x870 -#define CHANNEL0NEXT_RECORD_POINTER 0x830 -#define CHANNEL1NEXT_RECORD_POINTER 0x834 -#define CHANNEL2NEXT_RECORD_POINTER 0x838 -#define CHANNEL3NEXT_RECORD_POINTER 0x83C -#define CHANNEL0_DMA_DESTINATION_ADDRESS 0x820 -#define CHANNEL1_DMA_DESTINATION_ADDRESS 0x824 -#define CHANNEL2_DMA_DESTINATION_ADDRESS 0x828 -#define CHANNEL3_DMA_DESTINATION_ADDRESS 0x82C -#define CHANNEL0_DMA_SOURCE_ADDRESS 0x810 -#define CHANNEL1_DMA_SOURCE_ADDRESS 0x814 -#define CHANNEL2_DMA_SOURCE_ADDRESS 0x818 -#define CHANNEL3_DMA_SOURCE_ADDRESS 0x81C -#define CHANNEL0_DMA_BYTE_COUNT 0x800 -#define CHANNEL1_DMA_BYTE_COUNT 0x804 -#define CHANNEL2_DMA_BYTE_COUNT 0x808 -#define CHANNEL3_DMA_BYTE_COUNT 0x80C - - /* IDMA Address Decoding Base Address Registers */ - -#define DMA_BASE_ADDR_REG0 0xa00 -#define DMA_BASE_ADDR_REG1 0xa08 -#define DMA_BASE_ADDR_REG2 0xa10 -#define DMA_BASE_ADDR_REG3 0xa18 -#define DMA_BASE_ADDR_REG4 0xa20 -#define DMA_BASE_ADDR_REG5 0xa28 -#define DMA_BASE_ADDR_REG6 0xa30 -#define DMA_BASE_ADDR_REG7 0xa38 - - /* IDMA Address Decoding Size Address Register */ - -#define DMA_SIZE_REG0 0xa04 -#define DMA_SIZE_REG1 0xa0c -#define DMA_SIZE_REG2 0xa14 -#define DMA_SIZE_REG3 0xa1c -#define DMA_SIZE_REG4 0xa24 -#define DMA_SIZE_REG5 0xa2c -#define DMA_SIZE_REG6 0xa34 -#define DMA_SIZE_REG7 0xa3C - - /* IDMA Address Decoding High Address Remap and Access - Protection Registers */ - -#define DMA_HIGH_ADDR_REMAP_REG0 0xa60 -#define DMA_HIGH_ADDR_REMAP_REG1 0xa64 -#define DMA_HIGH_ADDR_REMAP_REG2 0xa68 -#define DMA_HIGH_ADDR_REMAP_REG3 0xa6C -#define DMA_BASE_ADDR_ENABLE_REG 0xa80 -#define DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70 -#define DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74 -#define DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78 -#define DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c -#define DMA_ARBITER_CONTROL 0x860 -#define DMA_CROSS_BAR_TIMEOUT 0x8d0 - - /* IDMA Headers Retarget Registers */ - - /*#define CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e01 */ - /*#define CPU_IDMA_HEADERS_RETARGET_BASE 0x3e81 */ - -#define DMA_HEADERS_RETARGET_CONTROL 0xa84 -#define DMA_HEADERS_RETARGET_BASE 0xa88 - -/****************************************/ -/* DMA Interrupt */ -/****************************************/ - -#define CHANELS0_3_INTERRUPT_CAUSE 0x8c0 -#define CHANELS0_3_INTERRUPT_MASK 0x8c4 -#define CHANELS0_3_ERROR_ADDRESS 0x8c8 -#define CHANELS0_3_ERROR_SELECT 0x8cc - /*#define CHANELS4_7_INTERRUPT_CAUSE 0x9c01 */ - /*#define CHANELS4_7_INTERRUPT_MASK 0x9c41 */ - /*#define CHANELS4_7_ERROR_ADDRESS 0x9c81 */ - /*#define CHANELS4_7_ERROR_SELECT 0x9cc1 */ - -#define DMA_INTERRUPT_CAUSE_REG CHANELS0_3_INTERRUPT_CAUSE /*0x8c01 */ -#define DMA_INTERRUPT_CAUSE_MASK CHANELS0_3_INTERRUPT_MASK /*0x8c41 */ -#define DMA_ERROR_ADDR CHANELS0_3_ERROR_ADDRESS /*0x8c81 */ -#define DMA_ERROR_SELECT CHANELS0_3_ERROR_SELECT /*0x8cc1 */ - - -/****************************************/ -/* DMA Debug (for internal use) */ -/****************************************/ - -#define DMA_X0_ADDRESS 0x8e0 -#define DMA_X0_COMMAND_AND_ID 0x8e4 - /*#define DMA_X0_WRITE_DATA_LOW 0x8e81 */ - /*#define DMA_X0_WRITE_DATA_HIGH 0x8ec1 */ - /*#define DMA_X0_WRITE_BYTE_ENABLE 0x8f81 */ - /*#define DMA_X0_READ_DATA_LOW 0x8f01 */ - /*#define DMA_X0_READ_DATA_HIGH 0x8f41 */ - /*#define DMA_X0_READ_ID 0x8fc1 */ - /*#define DMA_X1_ADDRESS 0x9e01 */ - /*#define DMA_X1_COMMAND_AND_ID 0x9e41 */ - /*#define DMA_X1_WRITE_DATA_LOW 0x9e81 */ - /*#define DMA_X1_WRITE_DATA_HIGH 0x9ec1 */ - /*#define DMA_X1_WRITE_BYTE_ENABLE 0x9f81 */ - /*#define DMA_X1_READ_DATA_LOW 0x9f01 */ - /*#define DMA_X1_READ_DATA_HIGH 0x9f41 */ - /*#define DMA_X1_READ_ID 0x9fc1 */ - - /* IDMA Debug Register ( for internal use ) */ - -#define DMA_DEBUG_LOW DMA_X0_ADDRESS /* 0x8e01 */ -#define DMA_DEBUG_HIGH DMA_X0_COMMAND_AND_ID /*0x8e41 */ -#define DMA_SPARE 0xA8C - - -/****************************************/ -/* Timer_Counter */ -/****************************************/ - -#define TIMER_COUNTER0 0x850 -#define TIMER_COUNTER1 0x854 -#define TIMER_COUNTER2 0x858 -#define TIMER_COUNTER3 0x85C -#define TIMER_COUNTER_0_3_CONTROL 0x864 -#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 -#define TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c - /*#define TIMER_COUNTER4 0x9501 */ - /*#define TIMER_COUNTER5 0x9541 */ - /*#define TIMER_COUNTER6 0x9581 */ - /*#define TIMER_COUNTER7 0x95C1 */ - /*#define TIMER_COUNTER_4_7_CONTROL 0x9641 */ - /*#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE 0x9681 */ - /*#define TIMER_COUNTER_4_7_INTERRUPT_MASK 0x96c1 */ - -/****************************************/ -/* PCI Slave Address Decoding */ -/****************************************/ -/****************************************/ -/* PCI Slave Address Decoding registers */ -/****************************************/ -#define PCI_0_CS_0_BANK_SIZE PCI_0SCS_0_BANK_SIZE /*0xc081 */ -#define PCI_1_CS_0_BANK_SIZE PCI_1SCS_0_BANK_SIZE /* 0xc881 */ -#define PCI_0_CS_1_BANK_SIZE PCI_0SCS_1_BANK_SIZE /*0xd081 */ -#define PCI_1_CS_1_BANK_SIZE PCI_1SCS_1_BANK_SIZE /* 0xd881 */ -#define PCI_0_CS_2_BANK_SIZE PCI_0SCS_2_BANK_SIZE /*0xc0c1 */ -#define PCI_1_CS_2_BANK_SIZE PCI_1SCS_2_BANK_SIZE /*0xc8c1 */ -#define PCI_0_CS_3_BANK_SIZE PCI_0SCS_3_BANK_SIZE /*0xd0c1 */ -#define PCI_1_CS_3_BANK_SIZE PCI_1SCS_3_BANK_SIZE /*0xd8c1 */ -#define PCI_0_DEVCS_0_BANK_SIZE PCI_0CS_0_BANK_SIZE /*0xc101 */ -#define PCI_1_DEVCS_0_BANK_SIZE PCI_1CS_0_BANK_SIZE /*0xc901 */ -#define PCI_0_DEVCS_1_BANK_SIZE PCI_0CS_1_BANK_SIZE /*0xd101 */ -#define PCI_1_DEVCS_1_BANK_SIZE PCI_1CS_1_BANK_SIZE /* 0xd901 */ -#define PCI_0_DEVCS_2_BANK_SIZE PCI_0CS_2_BANK_SIZE /* 0xd181 */ -#define PCI_1_DEVCS_2_BANK_SIZE PCI_1CS_2_BANK_SIZE /*0xd981 */ -#define PCI_0_DEVCS_3_BANK_SIZE PCI_0CS_3_BANK_SIZE /* 0xc141 */ -#define PCI_1_DEVCS_3_BANK_SIZE PCI_1CS_3_BANK_SIZE /*0xc941 */ -#define PCI_0_DEVCS_BOOT_BANK_SIZE PCI_0CS_BOOT_BANK_SIZE /*0xd141 */ -#define PCI_1_DEVCS_BOOT_BANK_SIZE PCI_1CS_BOOT_BANK_SIZE /* 0xd941 */ -#define PCI_0_P2P_MEM0_BAR_SIZE PCI_0P2P_MEM0_BAR_SIZE /*0xd1c1 */ -#define PCI_1_P2P_MEM0_BAR_SIZE PCI_1P2P_MEM0_BAR_SIZE /*0xd9c1 */ -#define PCI_0_P2P_MEM1_BAR_SIZE PCI_0P2P_MEM1_BAR_SIZE /*0xd201 */ -#define PCI_1_P2P_MEM1_BAR_SIZE PCI_1P2P_MEM1_BAR_SIZE /*0xda01 */ -#define PCI_0_P2P_I_O_BAR_SIZE PCI_0P2P_I_O_BAR_SIZE /*0xd241 */ -#define PCI_1_P2P_I_O_BAR_SIZE PCI_1P2P_I_O_BAR_SIZE /*0xda41 */ -#define PCI_0_CPU_BAR_SIZE PCI_0CPU_BAR_SIZE /*0xd281 */ -#define PCI_1_CPU_BAR_SIZE PCI_1CPU_BAR_SIZE /*0xda81 */ -#define PCI_0_INTERNAL_SRAM_BAR_SIZE PCI_0DAC_SCS_0_BANK_SIZE /*0xe001 */ -#define PCI_1_INTERNAL_SRAM_BAR_SIZE PCI_1DAC_SCS_0_BANK_SIZE /*0xe801 */ -#define PCI_0_EXPANSION_ROM_BAR_SIZE PCI_0EXPANSION_ROM_BAR_SIZE /*0xd2c1 */ -#define PCI_1_EXPANSION_ROM_BAR_SIZE PCI_1EXPANSION_ROM_BAR_SIZE /*0xd9c1 */ -#define PCI_0_BASE_ADDR_REG_ENABLE PCI_0BASE_ADDRESS_REGISTERS_ENABLE /*0xc3c1 */ -#define PCI_1_BASE_ADDR_REG_ENABLE PCI_1BASE_ADDRESS_REGISTERS_ENABLE /*0xcbc1 */ -#define PCI_0_CS_0_BASE_ADDR_REMAP PCI_0SCS_0_BASE_ADDRESS_REMAP /*0xc481 */ -#define PCI_1_CS_0_BASE_ADDR_REMAP PCI_1SCS_0_BASE_ADDRESS_REMAP /*0xcc81 */ -#define PCI_0_CS_1_BASE_ADDR_REMAP PCI_0SCS_1_BASE_ADDRESS_REMAP /*0xd481 */ -#define PCI_1_CS_1_BASE_ADDR_REMAP PCI_1SCS_1_BASE_ADDRESS_REMAP /*0xdc81 */ -#define PCI_0_CS_2_BASE_ADDR_REMAP PCI_0SCS_2_BASE_ADDRESS_REMAP /*0xc4c1 */ -#define PCI_1_CS_2_BASE_ADDR_REMAP PCI_1SCS_2_BASE_ADDRESS_REMAP /*0xccc1 */ -#define PCI_0_CS_3_BASE_ADDR_REMAP PCI_0SCS_3_BASE_ADDRESS_REMAP /*0xd4c1 */ -#define PCI_1_CS_3_BASE_ADDR_REMAP PCI_1SCS_3_BASE_ADDRESS_REMAP /* 0xdcc1 */ -#define PCI_0_CS_0_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP -#define PCI_1_CS_0_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP -#define PCI_0_CS_1_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP -#define PCI_1_CS_1_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP -#define PCI_0_CS_2_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP -#define PCI_1_CS_2_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP -#define PCI_0_CS_3_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP -#define PCI_1_CS_3_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP -#define PCI_0_DEVCS_0_BASE_ADDR_REMAP PCI_0CS_0_BASE_ADDRESS_REMAP /*0xc501 */ -#define PCI_1_DEVCS_0_BASE_ADDR_REMAP PCI_1CS_0_BASE_ADDRESS_REMAP /*0xcd01 */ -#define PCI_0_DEVCS_1_BASE_ADDR_REMAP PCI_0CS_1_BASE_ADDRESS_REMAP /*0xd501 */ -#define PCI_1_DEVCS_1_BASE_ADDR_REMAP PCI_1CS_1_BASE_ADDRESS_REMAP /*0xdd01 */ -#define PCI_0_DEVCS_2_BASE_ADDR_REMAP PCI_0CS_2_BASE_ADDRESS_REMAP /*0xd581 */ -#define PCI_1_DEVCS_2_BASE_ADDR_REMAP PCI_1CS_2_BASE_ADDRESS_REMAP /*0xdd81 */ -#define PCI_0_DEVCS_3_BASE_ADDR_REMAP PCI_0CS_3_BASE_ADDRESS_REMAP /*0xc541 */ -#define PCI_1_DEVCS_3_BASE_ADDR_REMAP PCI_1CS_3_BASE_ADDRESS_REMAP /*0xcd41 */ -#define PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP /*0xd541 */ -#define PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP /*0xdd41 */ -#define PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW /*0xd5c1 */ -#define PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW /*0xddc1 */ -#define PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH /*0xd601 */ -#define PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH /*0xde01 */ -#define PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW /*0xd641 */ -#define PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW /*0xde41 */ -#define PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH /*0xd681 */ -#define PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH /*0xde81 */ -#define PCI_0_P2P_I_O_BASE_ADDR_REMAP PCI_0P2P_I_O_BASE_ADDRESS_REMAP /*0xd6c1 */ -#define PCI_1_P2P_I_O_BASE_ADDR_REMAP PCI_1P2P_I_O_BASE_ADDRESS_REMAP /*0xdec 1 */ -#define PCI_0_CPU_BASE_ADDR_REMAP_LOW PCI_0CPU_BASE_ADDRESS_REMAP /*0xd701 */ -#define PCI_1_CPU_BASE_ADDR_REMAP_LOW PCI_1CPU_BASE_ADDRESS_REMAP /*0xdf01 */ -#define PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74 -#define PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4 -#define PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP /*0xf001 */ -#define PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80 -#define PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP /*0xf381 */ -#define PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP /*0xfb81 */ -#define PCI_0_ADDR_DECODE_CONTROL PCI_0ADDRESS_DECODE_CONTROL /*0xd3c1 */ -#define PCI_1_ADDR_DECODE_CONTROL PCI_1ADDRESS_DECODE_CONTROL /*0xdbc1 */ -#define PCI_0_HEADERS_RETARGET_CONTROL 0xF40 -#define PCI_1_HEADERS_RETARGET_CONTROL 0xFc0 -#define PCI_0_HEADERS_RETARGET_BASE 0xF44 -#define PCI_1_HEADERS_RETARGET_BASE 0xFc4 -#define PCI_0_HEADERS_RETARGET_HIGH 0xF48 -#define PCI_1_HEADERS_RETARGET_HIGH 0xFc8 - -#define PCI_0SCS_0_BANK_SIZE 0xc08 -#define PCI_1SCS_0_BANK_SIZE 0xc88 -#define PCI_0SCS_1_BANK_SIZE 0xd08 -#define PCI_1SCS_1_BANK_SIZE 0xd88 -#define PCI_0SCS_2_BANK_SIZE 0xc0c -#define PCI_1SCS_2_BANK_SIZE 0xc8c -#define PCI_0SCS_3_BANK_SIZE 0xd0c -#define PCI_1SCS_3_BANK_SIZE 0xd8c -#define PCI_0CS_0_BANK_SIZE 0xc10 -#define PCI_1CS_0_BANK_SIZE 0xc90 -#define PCI_0CS_1_BANK_SIZE 0xd10 -#define PCI_1CS_1_BANK_SIZE 0xd90 -#define PCI_0CS_2_BANK_SIZE 0xd18 -#define PCI_1CS_2_BANK_SIZE 0xd98 -#define PCI_0CS_3_BANK_SIZE 0xc14 -#define PCI_1CS_3_BANK_SIZE 0xc94 -#define PCI_0CS_BOOT_BANK_SIZE 0xd14 -#define PCI_1CS_BOOT_BANK_SIZE 0xd94 -#define PCI_0P2P_MEM0_BAR_SIZE 0xd1c -#define PCI_1P2P_MEM0_BAR_SIZE 0xd9c -#define PCI_0P2P_MEM1_BAR_SIZE 0xd20 -#define PCI_1P2P_MEM1_BAR_SIZE 0xda0 -#define PCI_0P2P_I_O_BAR_SIZE 0xd24 -#define PCI_1P2P_I_O_BAR_SIZE 0xda4 -#define PCI_0CPU_BAR_SIZE 0xd28 -#define PCI_1CPU_BAR_SIZE 0xda8 -#define PCI_0DAC_SCS_0_BANK_SIZE 0xe00 -#define PCI_1DAC_SCS_0_BANK_SIZE 0xe80 -#define PCI_0DAC_SCS_1_BANK_SIZE 0xe04 -#define PCI_1DAC_SCS_1_BANK_SIZE 0xe84 -#define PCI_0DAC_SCS_2_BANK_SIZE 0xe08 -#define PCI_1DAC_SCS_2_BANK_SIZE 0xe88 -#define PCI_0DAC_SCS_3_BANK_SIZE 0xe0c -#define PCI_1DAC_SCS_3_BANK_SIZE 0xe8c -#define PCI_0DAC_CS_0_BANK_SIZE 0xe10 -#define PCI_1DAC_CS_0_BANK_SIZE 0xe90 -#define PCI_0DAC_CS_1_BANK_SIZE 0xe14 -#define PCI_1DAC_CS_1_BANK_SIZE 0xe94 -#define PCI_0DAC_CS_2_BANK_SIZE 0xe18 -#define PCI_1DAC_CS_2_BANK_SIZE 0xe98 -#define PCI_0DAC_CS_3_BANK_SIZE 0xe1c -#define PCI_1DAC_CS_3_BANK_SIZE 0xe9c -#define PCI_0DAC_BOOTCS_BANK_SIZE 0xe20 -#define PCI_1DAC_BOOTCS_BANK_SIZE 0xea0 - -#define PCI_0DAC_P2P_MEM0_BAR_SIZE 0xe24 -#define PCI_1DAC_P2P_MEM0_BAR_SIZE 0xea4 -#define PCI_0DAC_P2P_MEM1_BAR_SIZE 0xe28 -#define PCI_1DAC_P2P_MEM1_BAR_SIZE 0xea8 -#define PCI_0DAC_CPU_BAR_SIZE 0xe2c -#define PCI_1DAC_CPU_BAR_SIZE 0xeac -#define PCI_0EXPANSION_ROM_BAR_SIZE 0xd2c -#define PCI_1EXPANSION_ROM_BAR_SIZE 0xdac -#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 0xc3c -#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 0xcbc -#define PCI_0SCS_0_BASE_ADDRESS_REMAP 0xc48 -#define PCI_1SCS_0_BASE_ADDRESS_REMAP 0xcc8 -#define PCI_0SCS_1_BASE_ADDRESS_REMAP 0xd48 -#define PCI_1SCS_1_BASE_ADDRESS_REMAP 0xdc8 -#define PCI_0SCS_2_BASE_ADDRESS_REMAP 0xc4c -#define PCI_1SCS_2_BASE_ADDRESS_REMAP 0xccc -#define PCI_0SCS_3_BASE_ADDRESS_REMAP 0xd4c -#define PCI_1SCS_3_BASE_ADDRESS_REMAP 0xdcc -#define PCI_0CS_0_BASE_ADDRESS_REMAP 0xc50 -#define PCI_1CS_0_BASE_ADDRESS_REMAP 0xcd0 -#define PCI_0CS_1_BASE_ADDRESS_REMAP 0xd50 -#define PCI_1CS_1_BASE_ADDRESS_REMAP 0xdd0 -#define PCI_0CS_2_BASE_ADDRESS_REMAP 0xd58 -#define PCI_1CS_2_BASE_ADDRESS_REMAP 0xdd8 -#define PCI_0CS_3_BASE_ADDRESS_REMAP 0xc54 -#define PCI_1CS_3_BASE_ADDRESS_REMAP 0xcd4 -#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP 0xd54 -#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP 0xdd4 -#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xd5c -#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xddc -#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xd60 -#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xde0 -#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xd64 -#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xde4 -#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xd68 -#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xde8 -#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP 0xd6c -#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP 0xdec -#define PCI_0CPU_BASE_ADDRESS_REMAP 0xd70 -#define PCI_1CPU_BASE_ADDRESS_REMAP 0xdf0 -#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP 0xf00 -#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP 0xff0 -#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP 0xf04 -#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP 0xf84 -#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP 0xf08 -#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP 0xf88 -#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP 0xf0c -#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP 0xf8c -#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP 0xf10 -#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP 0xf90 -#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP 0xf14 -#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP 0xf94 -#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP 0xf18 -#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP 0xf98 -#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP 0xf1c -#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP 0xf9c -#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP 0xf20 -#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP 0xfa0 -#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xf24 -#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xfa4 -#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xf28 -#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xfa8 -#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xf2c -#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xfac -#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xf30 -#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xfb0 -#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP 0xf34 -#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP 0xfb4 -#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP 0xf38 -#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP 0xfb8 -#define PCI_0ADDRESS_DECODE_CONTROL 0xd3c -#define PCI_1ADDRESS_DECODE_CONTROL 0xdbc - -/****************************************/ -/* PCI Control */ -/****************************************/ - -#define PCI_0COMMAND 0xc00 -#define PCI_1COMMAND 0xc80 -#define PCI_0MODE 0xd00 -#define PCI_1MODE 0xd80 -#define PCI_0TIMEOUT_RETRY 0xc04 -#define PCI_1TIMEOUT_RETRY 0xc84 -#define PCI_0READ_BUFFER_DISCARD_TIMER 0xd04 -#define PCI_1READ_BUFFER_DISCARD_TIMER 0xd84 -#define MSI_0TRIGGER_TIMER 0xc38 -#define MSI_1TRIGGER_TIMER 0xcb8 -#define PCI_0ARBITER_CONTROL 0x1d00 -#define PCI_1ARBITER_CONTROL 0x1d80 -/* changing untill here */ -#define PCI_0CROSS_BAR_CONTROL_LOW 0x1d08 -#define PCI_0CROSS_BAR_CONTROL_HIGH 0x1d0c -#define PCI_0CROSS_BAR_TIMEOUT 0x1d04 -#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d18 -#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d1c -#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER 0x1d10 -#define PCI_0P2P_CONFIGURATION 0x1d14 -#define PCI_0ACCESS_CONTROL_BASE_0_LOW 0x1e00 -#define PCI_0ACCESS_CONTROL_BASE_0_HIGH 0x1e04 -#define PCI_0ACCESS_CONTROL_TOP_0 0x1e08 -#define PCI_0ACCESS_CONTROL_BASE_1_LOW 0x1e10 -#define PCI_0ACCESS_CONTROL_BASE_1_HIGH 0x1e14 -#define PCI_0ACCESS_CONTROL_TOP_1 0x1e18 -#define PCI_0ACCESS_CONTROL_BASE_2_LOW 0x1e20 -#define PCI_0ACCESS_CONTROL_BASE_2_HIGH 0x1e24 -#define PCI_0ACCESS_CONTROL_TOP_2 0x1e28 -#define PCI_0ACCESS_CONTROL_BASE_3_LOW 0x1e30 -#define PCI_0ACCESS_CONTROL_BASE_3_HIGH 0x1e34 -#define PCI_0ACCESS_CONTROL_TOP_3 0x1e38 -#define PCI_0ACCESS_CONTROL_BASE_4_LOW 0x1e40 -#define PCI_0ACCESS_CONTROL_BASE_4_HIGH 0x1e44 -#define PCI_0ACCESS_CONTROL_TOP_4 0x1e48 -#define PCI_0ACCESS_CONTROL_BASE_5_LOW 0x1e50 -#define PCI_0ACCESS_CONTROL_BASE_5_HIGH 0x1e54 -#define PCI_0ACCESS_CONTROL_TOP_5 0x1e58 -#define PCI_0ACCESS_CONTROL_BASE_6_LOW 0x1e60 -#define PCI_0ACCESS_CONTROL_BASE_6_HIGH 0x1e64 -#define PCI_0ACCESS_CONTROL_TOP_6 0x1e68 -#define PCI_0ACCESS_CONTROL_BASE_7_LOW 0x1e70 -#define PCI_0ACCESS_CONTROL_BASE_7_HIGH 0x1e74 -#define PCI_0ACCESS_CONTROL_TOP_7 0x1e78 -#define PCI_1CROSS_BAR_CONTROL_LOW 0x1d88 -#define PCI_1CROSS_BAR_CONTROL_HIGH 0x1d8c -#define PCI_1CROSS_BAR_TIMEOUT 0x1d84 -#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d98 -#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d9c -#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER 0x1d90 -#define PCI_1P2P_CONFIGURATION 0x1d94 -#define PCI_1ACCESS_CONTROL_BASE_0_LOW 0x1e80 -#define PCI_1ACCESS_CONTROL_BASE_0_HIGH 0x1e84 -#define PCI_1ACCESS_CONTROL_TOP_0 0x1e88 -#define PCI_1ACCESS_CONTROL_BASE_1_LOW 0x1e90 -#define PCI_1ACCESS_CONTROL_BASE_1_HIGH 0x1e94 -#define PCI_1ACCESS_CONTROL_TOP_1 0x1e98 -#define PCI_1ACCESS_CONTROL_BASE_2_LOW 0x1ea0 -#define PCI_1ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 -#define PCI_1ACCESS_CONTROL_TOP_2 0x1ea8 -#define PCI_1ACCESS_CONTROL_BASE_3_LOW 0x1eb0 -#define PCI_1ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 -#define PCI_1ACCESS_CONTROL_TOP_3 0x1eb8 -#define PCI_1ACCESS_CONTROL_BASE_4_LOW 0x1ec0 -#define PCI_1ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 -#define PCI_1ACCESS_CONTROL_TOP_4 0x1ec8 -#define PCI_1ACCESS_CONTROL_BASE_5_LOW 0x1ed0 -#define PCI_1ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 -#define PCI_1ACCESS_CONTROL_TOP_5 0x1ed8 -#define PCI_1ACCESS_CONTROL_BASE_6_LOW 0x1ee0 -#define PCI_1ACCESS_CONTROL_BASE_6_HIGH 0x1ee4 -#define PCI_1ACCESS_CONTROL_TOP_6 0x1ee8 -#define PCI_1ACCESS_CONTROL_BASE_7_LOW 0x1ef0 -#define PCI_1ACCESS_CONTROL_BASE_7_HIGH 0x1ef4 -#define PCI_1ACCESS_CONTROL_TOP_7 0x1ef8 - -/****************************************/ -/* PCI Snoop Control */ -/****************************************/ - -#define PCI_0SNOOP_CONTROL_BASE_0_LOW 0x1f00 -#define PCI_0SNOOP_CONTROL_BASE_0_HIGH 0x1f04 -#define PCI_0SNOOP_CONTROL_TOP_0 0x1f08 -#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW 0x1f10 -#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH 0x1f14 -#define PCI_0SNOOP_CONTROL_TOP_1 0x1f18 -#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW 0x1f20 -#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH 0x1f24 -#define PCI_0SNOOP_CONTROL_TOP_2 0x1f28 -#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW 0x1f30 -#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH 0x1f34 -#define PCI_0SNOOP_CONTROL_TOP_3 0x1f38 -#define PCI_1SNOOP_CONTROL_BASE_0_LOW 0x1f80 -#define PCI_1SNOOP_CONTROL_BASE_0_HIGH 0x1f84 -#define PCI_1SNOOP_CONTROL_TOP_0 0x1f88 -#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW 0x1f90 -#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH 0x1f94 -#define PCI_1SNOOP_CONTROL_TOP_1 0x1f98 -#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW 0x1fa0 -#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH 0x1fa4 -#define PCI_1SNOOP_CONTROL_TOP_2 0x1fa8 -#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW 0x1fb0 -#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH 0x1fb4 -#define PCI_1SNOOP_CONTROL_TOP_3 0x1fb8 - -/****************************************/ -/* PCI Configuration Address */ -/****************************************/ - -#define PCI_0CONFIGURATION_ADDRESS 0xcf8 -#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER 0xcfc -#define PCI_1CONFIGURATION_ADDRESS 0xc78 -#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER 0xc7c -#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xc34 -#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xcb4 - -/****************************************/ -/* PCI Error Report */ -/****************************************/ - -#define PCI_0SERR_MASK 0xc28 -#define PCI_0ERROR_ADDRESS_LOW 0x1d40 -#define PCI_0ERROR_ADDRESS_HIGH 0x1d44 -#define PCI_0ERROR_DATA_LOW 0x1d48 -#define PCI_0ERROR_DATA_HIGH 0x1d4c -#define PCI_0ERROR_COMMAND 0x1d50 -#define PCI_0ERROR_CAUSE 0x1d58 -#define PCI_0ERROR_MASK 0x1d5c -#define PCI_1SERR_MASK 0xca8 -#define PCI_1ERROR_ADDRESS_LOW 0x1dc0 -#define PCI_1ERROR_ADDRESS_HIGH 0x1dc4 -#define PCI_1ERROR_DATA_LOW 0x1dc8 -#define PCI_1ERROR_DATA_HIGH 0x1dcc -#define PCI_1ERROR_COMMAND 0x1dd0 -#define PCI_1ERROR_CAUSE 0x1dd8 -#define PCI_1ERROR_MASK 0x1ddc - - -/****************************************/ -/* Lslave Debug (for internal use) */ -/****************************************/ - -#define L_SLAVE_X0_ADDRESS 0x1d20 -#define L_SLAVE_X0_COMMAND_AND_ID 0x1d24 -#define L_SLAVE_X1_ADDRESS 0x1d28 -#define L_SLAVE_X1_COMMAND_AND_ID 0x1d2c -#define L_SLAVE_WRITE_DATA_LOW 0x1d30 -#define L_SLAVE_WRITE_DATA_HIGH 0x1d34 -#define L_SLAVE_WRITE_BYTE_ENABLE 0x1d60 -#define L_SLAVE_READ_DATA_LOW 0x1d38 -#define L_SLAVE_READ_DATA_HIGH 0x1d3c -#define L_SLAVE_READ_ID 0x1d64 - -/****************************************/ -/* PCI Configuration Function 0 */ -/****************************************/ - -#define PCI_DEVICE_AND_VENDOR_ID 0x000 -#define PCI_STATUS_AND_COMMAND 0x004 -#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 -#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C -#define PCI_SCS_0_BASE_ADDRESS 0x010 -#define PCI_SCS_1_BASE_ADDRESS 0x014 -#define PCI_SCS_2_BASE_ADDRESS 0x018 -#define PCI_SCS_3_BASE_ADDRESS 0x01C -#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x020 -#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x024 -#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02C -#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER 0x030 -#define PCI_CAPABILTY_LIST_POINTER 0x034 -#define PCI_INTERRUPT_PIN_AND_LINE 0x03C -#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040 -#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 -#define PCI_VPD_ADDRESS 0x048 -#define PCI_VPD_DATA 0x04c -#define PCI_MSI_MESSAGE_CONTROL 0x050 -#define PCI_MSI_MESSAGE_ADDRESS 0x054 -#define PCI_MSI_MESSAGE_UPPER_ADDRESS 0x058 -#define PCI_MSI_MESSAGE_DATA 0x05c -#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY 0x058 - -/****************************************/ -/* PCI Configuration Function 1 */ -/****************************************/ - -#define PCI_CS_0_BASE_ADDRESS 0x110 -#define PCI_CS_1_BASE_ADDRESS 0x114 -#define PCI_CS_2_BASE_ADDRESS 0x118 -#define PCI_CS_3_BASE_ADDRESS 0x11c -#define PCI_BOOTCS_BASE_ADDRESS 0x120 - -/****************************************/ -/* PCI Configuration Function 2 */ -/****************************************/ - -#define PCI_P2P_MEM0_BASE_ADDRESS 0x210 - /*#define PCI_P2P_MEM1_BASE_ADDRESS 0x2141 */ -#define PCI_P2P_I_O_BASE_ADDRESS 0x218 - /*#define PCI_CPU_BASE_ADDRESS 0x21c1 */ - -/****************************************/ -/* PCI Configuration Function 4 */ -/****************************************/ - -#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 0x410 -#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH 0x414 -#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW 0x418 -#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH 0x41c -#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW 0x420 -#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH 0x424 - - -/****************************************/ -/* PCI Configuration Function 5 */ -/****************************************/ - -#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 0x510 -#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH 0x514 -#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW 0x518 -#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH 0x51c -#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW 0x520 -#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH 0x524 - - -/****************************************/ -/* PCI Configuration Function 6 */ -/****************************************/ - -#define PCI_DAC_CS_0_BASE_ADDRESS_LOW 0x610 -#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH 0x614 -#define PCI_DAC_CS_1_BASE_ADDRESS_LOW 0x618 -#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH 0x61c -#define PCI_DAC_CS_2_BASE_ADDRESS_LOW 0x620 -#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH 0x624 - -/****************************************/ -/* PCI Configuration Function 7 */ -/****************************************/ - -#define PCI_DAC_CS_3_BASE_ADDRESS_LOW 0x710 -#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH 0x714 -#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW 0x718 -#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH 0x71c -#define PCI_DAC_CPU_BASE_ADDRESS_LOW 0x720 -#define PCI_DAC_CPU_BASE_ADDRESS_HIGH 0x724 - -/****************************** MV64360 and MV64460 PCI ***************************/ -/***********************************/ -/* PCI Control Register Map */ -/***********************************/ - -#define PCI_0_DLL_STATUS_AND_COMMAND 0x1d20 -#define PCI_1_DLL_STATUS_AND_COMMAND 0x1da0 -#define PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C -#define PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C -#define PCI_0_COMMAND 0xc00 -#define PCI_1_COMMAND 0xc80 -#define PCI_0_MODE 0xd00 -#define PCI_1_MODE 0xd80 -#define PCI_0_RETRY 0xc04 -#define PCI_1_RETRY 0xc84 -#define PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04 -#define PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84 -#define PCI_0_MSI_TRIGGER_TIMER 0xc38 -#define PCI_1_MSI_TRIGGER_TIMER 0xcb8 -#define PCI_0_ARBITER_CONTROL 0x1d00 -#define PCI_1_ARBITER_CONTROL 0x1d80 -#define PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08 -#define PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88 -#define PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c -#define PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c -#define PCI_0_CROSS_BAR_TIMEOUT 0x1d04 -#define PCI_1_CROSS_BAR_TIMEOUT 0x1d84 -#define PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18 -#define PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98 -#define PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10 -#define PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90 -#define PCI_0_P2P_CONFIG 0x1d14 -#define PCI_1_P2P_CONFIG 0x1d94 - -#define PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00 -#define PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04 -#define PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08 -#define PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10 -#define PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14 -#define PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18 -#define PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20 -#define PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24 -#define PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28 -#define PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30 -#define PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34 -#define PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38 -#define PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40 -#define PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44 -#define PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48 -#define PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50 -#define PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54 -#define PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58 - -#define PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80 -#define PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84 -#define PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88 -#define PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90 -#define PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94 -#define PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98 -#define PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0 -#define PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 -#define PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8 -#define PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0 -#define PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 -#define PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8 -#define PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0 -#define PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 -#define PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8 -#define PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0 -#define PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 -#define PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8 - -/****************************************/ -/* PCI Configuration Access Registers */ -/****************************************/ - -#define PCI_0_CONFIG_ADDR 0xcf8 -#define PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc -#define PCI_1_CONFIG_ADDR 0xc78 -#define PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c -#define PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34 -#define PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4 - -/****************************************/ -/* PCI Error Report Registers */ -/****************************************/ - -#define PCI_0_SERR_MASK 0xc28 -#define PCI_1_SERR_MASK 0xca8 -#define PCI_0_ERROR_ADDR_LOW 0x1d40 -#define PCI_1_ERROR_ADDR_LOW 0x1dc0 -#define PCI_0_ERROR_ADDR_HIGH 0x1d44 -#define PCI_1_ERROR_ADDR_HIGH 0x1dc4 -#define PCI_0_ERROR_ATTRIBUTE 0x1d48 -#define PCI_1_ERROR_ATTRIBUTE 0x1dc8 -#define PCI_0_ERROR_COMMAND 0x1d50 -#define PCI_1_ERROR_COMMAND 0x1dd0 -#define PCI_0_ERROR_CAUSE 0x1d58 -#define PCI_1_ERROR_CAUSE 0x1dd8 -#define PCI_0_ERROR_MASK 0x1d5c -#define PCI_1_ERROR_MASK 0x1ddc - -/****************************************/ -/* PCI Debug Registers */ -/****************************************/ - -#define PCI_0_MMASK 0X1D24 -#define PCI_1_MMASK 0X1DA4 - -/*********************************************/ -/* PCI Configuration, Function 0, Registers */ -/*********************************************/ - -#define PCI_DEVICE_AND_VENDOR_ID 0x000 -#define PCI_STATUS_AND_COMMAND 0x004 -#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 -#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C - -#define PCI_SCS_0_BASE_ADDR_LOW 0x010 -#define PCI_SCS_0_BASE_ADDR_HIGH 0x014 -#define PCI_SCS_1_BASE_ADDR_LOW 0x018 -#define PCI_SCS_1_BASE_ADDR_HIGH 0x01C -#define PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020 -#define PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024 - /*#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c1 */ -#define PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 -#define PCI_CAPABILTY_LIST_POINTER 0x034 -#define PCI_INTERRUPT_PIN_AND_LINE 0x03C - /* capability list */ -#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040 -#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 -#define PCI_VPD_ADDR 0x048 -#define PCI_VPD_DATA 0x04c -#define PCI_MSI_MESSAGE_CONTROL 0x050 -#define PCI_MSI_MESSAGE_ADDR 0x054 -#define PCI_MSI_MESSAGE_UPPER_ADDR 0x058 -#define PCI_MSI_MESSAGE_DATA 0x05c -#define PCI_X_COMMAND 0x060 -#define PCI_X_STATUS 0x064 -#define PCI_COMPACT_PCI_HOT_SWAP 0x068 - -/***********************************************/ -/* PCI Configuration, Function 1, Registers */ -/***********************************************/ - -#define PCI_SCS_2_BASE_ADDR_LOW 0x110 -#define PCI_SCS_2_BASE_ADDR_HIGH 0x114 -#define PCI_SCS_3_BASE_ADDR_LOW 0x118 -#define PCI_SCS_3_BASE_ADDR_HIGH 0x11c -#define PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120 -#define PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124 - -/***********************************************/ -/* PCI Configuration, Function 2, Registers */ -/***********************************************/ - -#define PCI_DEVCS_0_BASE_ADDR_LOW 0x210 -#define PCI_DEVCS_0_BASE_ADDR_HIGH 0x214 -#define PCI_DEVCS_1_BASE_ADDR_LOW 0x218 -#define PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c -#define PCI_DEVCS_2_BASE_ADDR_LOW 0x220 -#define PCI_DEVCS_2_BASE_ADDR_HIGH 0x224 - -/***********************************************/ -/* PCI Configuration, Function 3, Registers */ -/***********************************************/ - -#define PCI_DEVCS_3_BASE_ADDR_LOW 0x310 -#define PCI_DEVCS_3_BASE_ADDR_HIGH 0x314 -#define PCI_BOOT_CS_BASE_ADDR_LOW 0x318 -#define PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c -#define PCI_CPU_BASE_ADDR_LOW 0x220 -#define PCI_CPU_BASE_ADDR_HIGH 0x224 - -/***********************************************/ -/* PCI Configuration, Function 4, Registers */ -/***********************************************/ - -#define PCI_P2P_MEM0_BASE_ADDR_LOW 0x410 -#define PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414 -#define PCI_P2P_MEM1_BASE_ADDR_LOW 0x418 -#define PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c -#define PCI_P2P_I_O_BASE_ADDR 0x420 -#define PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424 - -/****************************** MV64360 and MV64460 PCI End ***************************/ -/****************************************/ -/* I20 Support registers */ -/****************************************/ - -#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010 -#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014 -#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018 -#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01C -#define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020 -#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024 -#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028 -#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02C -#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030 -#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034 -#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040 -#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044 -#define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050 -#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054 -#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060 -#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064 -#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068 -#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06C -#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070 -#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074 -#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078 -#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07C - -#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C10 -#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C14 -#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C18 -#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C1C -#define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C20 -#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C24 -#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C28 -#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C2C -#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C30 -#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C34 -#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C40 -#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C44 -#define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1C50 -#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1C54 -#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C60 -#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C64 -#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C68 -#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C6C -#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C70 -#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C74 -#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C78 -#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C7C - - -/****************************************/ -/* Messaging Unit Registers (I20) */ -/****************************************/ - -#define I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010 -#define I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014 -#define I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018 -#define I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C -#define I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020 -#define I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024 -#define I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028 -#define I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C -#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030 -#define I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034 -#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040 -#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044 -#define I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050 -#define I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054 -#define I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060 -#define I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064 -#define I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068 -#define I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C -#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070 -#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074 -#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8 -#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC - -#define I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090 -#define I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094 -#define I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098 -#define I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C -#define I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0 -#define I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4 -#define I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8 -#define I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC -#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0 -#define I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4 -#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0 -#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4 -#define I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0 -#define I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4 -#define I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0 -#define I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4 -#define I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8 -#define I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC -#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0 -#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4 -#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078 -#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C - -#define I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10 -#define I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14 -#define I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18 -#define I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C -#define I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20 -#define I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24 -#define I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28 -#define I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C -#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30 -#define I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34 -#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40 -#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44 -#define I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50 -#define I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54 -#define I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60 -#define I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64 -#define I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68 -#define I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C -#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70 -#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74 -#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8 -#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC -#define I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90 -#define I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94 -#define I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98 -#define I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C -#define I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0 -#define I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4 -#define I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8 -#define I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC -#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0 -#define I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4 -#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0 -#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4 -#define I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0 -#define I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4 -#define I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0 -#define I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4 -#define I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8 -#define I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC -#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0 -#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4 -#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78 -#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C - - -/****************************************/ -/* Communication Unit Registers */ -/****************************************/ -/* -#define ETHERNET_0_ADDRESS_CONTROL_LOW 0xf200 -#define ETHERNET_0_ADDRESS_CONTROL_HIGH 0xf204 -#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf208 -#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf20c -#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf210 -#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf214 -#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS 0xf218 -#define ETHERNET_1_ADDRESS_CONTROL_LOW 0xf220 -#define ETHERNET_1_ADDRESS_CONTROL_HIGH 0xf224 -#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf228 -#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf22c -#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf230 -#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf234 -#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS 0xf238 -#define ETHERNET_2_ADDRESS_CONTROL_LOW 0xf240 -#define ETHERNET_2_ADDRESS_CONTROL_HIGH 0xf244 -#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf248 -#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf24c -#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf250 -#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf254 -#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS 0xf258 - */ -#define MPSC_0_ADDRESS_CONTROL_LOW 0xf280 -#define MPSC_0_ADDRESS_CONTROL_HIGH 0xf284 -#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf288 -#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf28c -#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf290 -#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf294 -#define MPSC_1_ADDRESS_CONTROL_LOW 0xf2c0 -#define MPSC_1_ADDRESS_CONTROL_HIGH 0xf2c4 -#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2c8 -#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2cc -#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d0 -#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d4 - /*#define SERIAL_INIT_PCI_HIGH_ADDRESS 0xf3201 */ -#define COMM_UNIT_ARBITER_CONTROL 0xf300 -#define COMM_UNIT_CROSS_BAR_TIMEOUT 0xf304 -#define COMM_UNIT_INTERRUPT_CAUSE 0xf310 -#define COMM_UNIT_INTERRUPT_MASK 0xf314 -#define COMM_UNIT_ERROR_ADDRESS 0xf314 -/****************************************/ -/* Serial Initialization registers */ -/****************************************/ - - /*#define SERIAL_INIT_LAST_DATA 0xf3241 */ - /*#define SERIAL_INIT_STATUS_AND_CONTROL 0xf3281 */ -#define SERIAL_INIT_LAST_DATA 0xf324 -#define SERIAL_INIT_CONTROL 0xf328 -#define SERIAL_INIT_STATUS 0xf32c - - -/****************************************/ -/* Ethernet Unit Registers */ -/****************************************/ - -#define ETH_PHY_ADDR_REG 0x2000 -#define ETH_SMI_REG 0x2004 -#define ETH_UNIT_DEFAULT_ADDR_REG 0x2008 -#define ETH_UNIT_DEFAULTID_REG 0x200c -#define ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080 -#define ETH_UNIT_INTERRUPT_MASK_REG 0x2084 -#define ETH_UNIT_INTERNAL_USE_REG 0x24fc -#define ETH_UNIT_ERROR_ADDR_REG 0x2094 -#define ETH_BAR_0 0x2200 -#define ETH_BAR_1 0x2208 -#define ETH_BAR_2 0x2210 -#define ETH_BAR_3 0x2218 -#define ETH_BAR_4 0x2220 -#define ETH_BAR_5 0x2228 -#define ETH_SIZE_REG_0 0x2204 -#define ETH_SIZE_REG_1 0x220c -#define ETH_SIZE_REG_2 0x2214 -#define ETH_SIZE_REG_3 0x221c -#define ETH_SIZE_REG_4 0x2224 -#define ETH_SIZE_REG_5 0x222c -#define ETH_HEADERS_RETARGET_BASE_REG 0x2230 -#define ETH_HEADERS_RETARGET_CONTROL_REG 0x2234 -#define ETH_HIGH_ADDR_REMAP_REG_0 0x2280 -#define ETH_HIGH_ADDR_REMAP_REG_1 0x2284 -#define ETH_HIGH_ADDR_REMAP_REG_2 0x2288 -#define ETH_HIGH_ADDR_REMAP_REG_3 0x228c -#define ETH_BASE_ADDR_ENABLE_REG 0x2290 -#define ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2)) -#define ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7)) -#define ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10)) -#define ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10)) -#define ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10)) -#define ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10)) -#define ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10)) -#define ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10)) -#define ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10)) -#define ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10)) -#define ETH_DSCP_0(port) (0x2420 + (port<<10)) -#define ETH_DSCP_1(port) (0x2424 + (port<<10)) -#define ETH_DSCP_2(port) (0x2428 + (port<<10)) -#define ETH_DSCP_3(port) (0x242c + (port<<10)) -#define ETH_DSCP_4(port) (0x2430 + (port<<10)) -#define ETH_DSCP_5(port) (0x2434 + (port<<10)) -#define ETH_DSCP_6(port) (0x2438 + (port<<10)) -#define ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10)) -#define ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10)) -#define ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10)) -#define ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10)) -#define ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10)) -#define ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10)) -#define ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10)) -#define ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10)) -#define ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10)) -#define ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10)) -#define ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10)) -#define ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10)) -#define ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10)) -#define ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10)) -#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10)) -#define ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10) -#define ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10)) -#define ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10)) -#define ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10)) -#define ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10)) -#define ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10)) -#define ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10)) -#define ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10)) -#define ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10)) -#define ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10)) -#define ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10)) -#define ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10)) -#define ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10)) -#define ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10)) -#define ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10)) -#define ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10)) -#define ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10)) -#define ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10)) -#define ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10)) -#define ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10)) -#define ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10)) -#define ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10)) -#define ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10)) -#define ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10)) -#define ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10)) -#define ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10)) -#define ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10)) -#define ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10)) -#define ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10)) -#define ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10)) -#define ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10)) -#define ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10)) -#define ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10)) -#define ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10)) -#define ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10)) - -/****************************************/ -/* Cunit Debug (for internal use) */ -/****************************************/ - -#define CUNIT_ADDRESS 0xf340 -#define CUNIT_COMMAND_AND_ID 0xf344 -#define CUNIT_WRITE_DATA_LOW 0xf348 -#define CUNIT_WRITE_DATA_HIGH 0xf34c -#define CUNIT_WRITE_BYTE_ENABLE 0xf358 -#define CUNIT_READ_DATA_LOW 0xf350 -#define CUNIT_READ_DATA_HIGH 0xf354 -#define CUNIT_READ_ID 0xf35c - -/****************************************/ -/* Fast Ethernet Unit Registers */ -/****************************************/ - -/****************************************/ -/* Ethernet Unit Registers */ -/****************************************/ - -#define ETH_PHY_ADDR_REG 0x2000 -#define ETH_SMI_REG 0x2004 -#define ETH_UNIT_DEFAULT_ADDR_REG 0x2008 -#define ETH_UNIT_DEFAULTID_REG 0x200c -#define ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080 -#define ETH_UNIT_INTERRUPT_MASK_REG 0x2084 -#define ETH_UNIT_INTERNAL_USE_REG 0x24fc -#define ETH_UNIT_ERROR_ADDR_REG 0x2094 -#define ETH_BAR_0 0x2200 -#define ETH_BAR_1 0x2208 -#define ETH_BAR_2 0x2210 -#define ETH_BAR_3 0x2218 -#define ETH_BAR_4 0x2220 -#define ETH_BAR_5 0x2228 -#define ETH_SIZE_REG_0 0x2204 -#define ETH_SIZE_REG_1 0x220c -#define ETH_SIZE_REG_2 0x2214 -#define ETH_SIZE_REG_3 0x221c -#define ETH_SIZE_REG_4 0x2224 -#define ETH_SIZE_REG_5 0x222c -#define ETH_HEADERS_RETARGET_BASE_REG 0x2230 -#define ETH_HEADERS_RETARGET_CONTROL_REG 0x2234 -#define ETH_HIGH_ADDR_REMAP_REG_0 0x2280 -#define ETH_HIGH_ADDR_REMAP_REG_1 0x2284 -#define ETH_HIGH_ADDR_REMAP_REG_2 0x2288 -#define ETH_HIGH_ADDR_REMAP_REG_3 0x228c -#define ETH_BASE_ADDR_ENABLE_REG 0x2290 -#define ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2)) -#define ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7)) -#define ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10)) -#define ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10)) -#define ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10)) -#define ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10)) -#define ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10)) -#define ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10)) -#define ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10)) -#define ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10)) -#define ETH_DSCP_0(port) (0x2420 + (port<<10)) -#define ETH_DSCP_1(port) (0x2424 + (port<<10)) -#define ETH_DSCP_2(port) (0x2428 + (port<<10)) -#define ETH_DSCP_3(port) (0x242c + (port<<10)) -#define ETH_DSCP_4(port) (0x2430 + (port<<10)) -#define ETH_DSCP_5(port) (0x2434 + (port<<10)) -#define ETH_DSCP_6(port) (0x2438 + (port<<10)) -#define ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10)) -#define ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10)) -#define ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10)) -#define ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10)) -#define ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10)) -#define ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10)) -#define ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10)) -#define ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10)) -#define ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10)) -#define ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10)) -#define ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10)) -#define ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10)) -#define ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10)) -#define ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10)) -#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10)) -#define ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10) -#define ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10)) -#define ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10)) -#define ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10)) -#define ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10)) -#define ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10)) -#define ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10)) -#define ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10)) -#define ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10)) -#define ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10)) -#define ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10)) -#define ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10)) -#define ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10)) -#define ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10)) -#define ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10)) -#define ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10)) -#define ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10)) -#define ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10)) -#define ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10)) -#define ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10)) -#define ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10)) -#define ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10)) -#define ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10)) -#define ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10)) -#define ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10)) -#define ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10)) -#define ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10)) -#define ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10)) -#define ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10)) -#define ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10)) -#define ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10)) -#define ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10)) -#define ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10)) -#define ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10)) -#define ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10)) -#define ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10)) -#define ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10)) - -/* Compat with interrupts.c */ -#define ETHERNET0_INTERRUPT_CAUSE_REGISTER ETH_INTERRUPT_CAUSE_REG(0) -#define ETHERNET1_INTERRUPT_CAUSE_REGISTER ETH_INTERRUPT_CAUSE_REG(1) -#define ETHERNET2_INTERRUPT_CAUSE_REGISTER ETH_INTERRUPT_CAUSE_REG(2) - -#define ETHERNET0_INTERRUPT_MASK_REGISTER ETH_INTERRUPT_MASK_REG(0) -#define ETHERNET1_INTERRUPT_MASK_REGISTER ETH_INTERRUPT_MASK_REG(1) -#define ETHERNET2_INTERRUPT_MASK_REGISTER ETH_INTERRUPT_MASK_REG(2) - -/* Ethernet GT64260 */ -/* -#define ETHERNET_PHY_ADDRESS_REGISTER 0x2000 -#define ETHERNET_SMI_REGISTER 0x2010 -*/ -/* Ethernet 0 */ -/* -#define ETHERNET0_PORT_CONFIGURATION_REGISTER 0x2400 -#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER 0x2408 -#define ETHERNET0_PORT_COMMAND_REGISTER 0x2410 -#define ETHERNET0_PORT_STATUS_REGISTER 0x2418 -#define ETHERNET0_SERIAL_PARAMETRS_REGISTER 0x2420 -#define ETHERNET0_HASH_TABLE_POINTER_REGISTER 0x2428 -#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2430 -#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2438 -#define ETHERNET0_SDMA_CONFIGURATION_REGISTER 0x2440 -#define ETHERNET0_SDMA_COMMAND_REGISTER 0x2448 -#define ETHERNET0_INTERRUPT_CAUSE_REGISTER 0x2450 -#define ETHERNET0_INTERRUPT_MASK_REGISTER 0x2458 -#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 0x2480 -#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1 0x2484 -#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2 0x2488 -#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3 0x248c -#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 0x24a0 -#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1 0x24a4 -#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2 0x24a8 -#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3 0x24ac -#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 0x24e0 -#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1 0x24e4 -#define ETHERNET0_MIB_COUNTER_BASE 0x2500 -*/ -/* Ethernet 1 */ -/* -#define ETHERNET1_PORT_CONFIGURATION_REGISTER 0x2800 -#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER 0x2808 -#define ETHERNET1_PORT_COMMAND_REGISTER 0x2810 -#define ETHERNET1_PORT_STATUS_REGISTER 0x2818 -#define ETHERNET1_SERIAL_PARAMETRS_REGISTER 0x2820 -#define ETHERNET1_HASH_TABLE_POINTER_REGISTER 0x2828 -#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2830 -#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2838 -#define ETHERNET1_SDMA_CONFIGURATION_REGISTER 0x2840 -#define ETHERNET1_SDMA_COMMAND_REGISTER 0x2848 -#define ETHERNET1_INTERRUPT_CAUSE_REGISTER 0x2850 -#define ETHERNET1_INTERRUPT_MASK_REGISTER 0x2858 -#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0 0x2880 -#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1 0x2884 -#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2 0x2888 -#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3 0x288c -#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0 0x28a0 -#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1 0x28a4 -#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2 0x28a8 -#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3 0x28ac -#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0 0x28e0 -#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1 0x28e4 -#define ETHERNET1_MIB_COUNTER_BASE 0x2900 -*/ -/* Ethernet 2 */ -/* -#define ETHERNET2_PORT_CONFIGURATION_REGISTER 0x2c00 -#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER 0x2c08 -#define ETHERNET2_PORT_COMMAND_REGISTER 0x2c10 -#define ETHERNET2_PORT_STATUS_REGISTER 0x2c18 -#define ETHERNET2_SERIAL_PARAMETRS_REGISTER 0x2c20 -#define ETHERNET2_HASH_TABLE_POINTER_REGISTER 0x2c28 -#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2c30 -#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2c38 -#define ETHERNET2_SDMA_CONFIGURATION_REGISTER 0x2c40 -#define ETHERNET2_SDMA_COMMAND_REGISTER 0x2c48 -#define ETHERNET2_INTERRUPT_CAUSE_REGISTER 0x2c50 -#define ETHERNET2_INTERRUPT_MASK_REGISTER 0x2c58 -#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0 0x2c80 -#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1 0x2c84 -#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2 0x2c88 -#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3 0x2c8c -#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0 0x2ca0 -#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1 0x2ca4 -#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2 0x2ca8 -#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3 0x2cac -#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0 0x2ce0 -#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1 0x2ce4 -#define ETHERNET2_MIB_COUNTER_BASE 0x2d00 -*/ - -/****************************************/ -/* SDMA Registers */ -/****************************************/ - -#define SDMA_GROUP_CONFIGURATION_REGISTER 0xb1f0 -#define CHANNEL0_CONFIGURATION_REGISTER 0x4000 -#define CHANNEL0_COMMAND_REGISTER 0x4008 -#define CHANNEL0_RX_CMD_STATUS 0x4800 -#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES 0x4804 -#define CHANNEL0_RX_BUFFER_POINTER 0x4808 -#define CHANNEL0_RX_NEXT_POINTER 0x480c -#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER 0x4810 -#define CHANNEL0_TX_CMD_STATUS 0x4C00 -#define CHANNEL0_TX_PACKET_SIZE 0x4C04 -#define CHANNEL0_TX_BUFFER_POINTER 0x4C08 -#define CHANNEL0_TX_NEXT_POINTER 0x4C0c -#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER 0x4c10 -#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER 0x4c14 -/* -#define CHANNEL1_CONFIGURATION_REGISTER 0x5000 -#define CHANNEL1_COMMAND_REGISTER 0x5008 -#define CHANNEL1_RX_CMD_STATUS 0x5800 -#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES 0x5804 -#define CHANNEL1_RX_BUFFER_POINTER 0x5808 -#define CHANNEL1_RX_NEXT_POINTER 0x580c -#define CHANNEL1_TX_CMD_STATUS 0x5C00 -#define CHANNEL1_TX_PACKET_SIZE 0x5C04 -#define CHANNEL1_TX_BUFFER_POINTER 0x5C08 -#define CHANNEL1_TX_NEXT_POINTER 0x5C0c -#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x5810 -#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER 0x5c10 -#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER 0x5c14 -#define CHANNEL2_CONFIGURATION_REGISTER 0x6000 -#define CHANNEL2_COMMAND_REGISTER 0x6008 -#define CHANNEL2_RX_CMD_STATUS 0x6800 -#define CHANNEL2_RX_PACKET_AND_BUFFER_SIZES 0x6804 -#define CHANNEL2_RX_BUFFER_POINTER 0x6808 -#define CHANNEL2_RX_NEXT_POINTER 0x680c -#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810 -#define CHANNEL2_TX_CMD_STATUS 0x6C00 -#define CHANNEL2_TX_PACKET_SIZE 0x6C04 -#define CHANNEL2_TX_BUFFER_POINTER 0x6C08 -#define CHANNEL2_TX_NEXT_POINTER 0x6C0c -#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810 -#define CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER 0x6c10 -#define CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER 0x6c14 -*/ -/* SDMA Interrupt */ -/* -#define SDMA_CAUSE 0xb820 -#define SDMA_MASK 0xb8a0 -*/ -/***************************************/ -/* SDMA Registers */ -/***************************************/ - -#define SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13)) -#define SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13)) -#define SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13)) -#define SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13)) -#define SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13)) - -#define SDMA_CAUSE_REG 0xb800 -#define SDMA_MASK_REG 0xb880 - -/****************************************/ -/* Baude Rate Generators Registers */ -/****************************************/ - -/* BRG 0 */ -#define BRG0_CONFIGURATION_REGISTER 0xb200 -#define BRG0_BAUDE_TUNING_REGISTER 0xb204 - -/* BRG 1 */ -#define BRG1_CONFIGURATION_REGISTER 0xb208 -#define BRG1_BAUDE_TUNING_REGISTER 0xb20c - -/* BRG 2 */ -#define BRG2_CONFIGURATION_REGISTER 0xb210 -#define BRG2_BAUDE_TUNING_REGISTER 0xb214 - -/* BRG Interrupts */ -#define BRG_CAUSE_REGISTER 0xb834 -#define BRG_MASK_REGISTER 0xb8b4 -#define BRG_CONFIG_REG(brg) (0xb200 + (brg<<3)) -#define BRG_BAUDE_TUNING_REG(brg) (0xb208 + (brg<<3)) -#define BRG_CAUSE_REG BRG_CAUSE_REGISTER /*0xb8341 */ -#define BRG_MASK_REG BRG_MASK_REGISTER /*0xb8b41 */ - -/* MISC */ - -#define MAIN_ROUTING_REGISTER 0xb400 -#define RECEIVE_CLOCK_ROUTING_REGISTER 0xb404 -#define TRANSMIT_CLOCK_ROUTING_REGISTER 0xb408 -#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER 0xb40c - -/****************************************/ -/* Watchdog registers */ -/****************************************/ -#define WATCHDOG_CONFIGURATION_REGISTER 0xb410 -#define WATCHDOG_VALUE_REGISTER 0xb414 -#define WATCHDOG_CONFIG_REG WATCHDOG_CONFIGURATION_REGISTER /*0xb4101 */ -#define WATCHDOG_VALUE_REG WATCHDOG_VALUE_REGISTER /*0xb4141 */ - - -/****************************************/ -/* Flex TDM Registers */ -/****************************************/ - -/* FTDM Port */ - -#define FLEXTDM_TRANSMIT_READ_POINTER 0xa800 -#define FLEXTDM_RECEIVE_READ_POINTER 0xa804 -#define FLEXTDM_CONFIGURATION_REGISTER 0xa808 -#define FLEXTDM_AUX_CHANNELA_TX_REGISTER 0xa80c -#define FLEXTDM_AUX_CHANNELA_RX_REGISTER 0xa810 -#define FLEXTDM_AUX_CHANNELB_TX_REGISTER 0xa814 -#define FLEXTDM_AUX_CHANNELB_RX_REGISTER 0xa818 - -/* FTDM Interrupts */ - -#define FTDM_CAUSE_REGISTER 0xb830 -#define FTDM_MASK_REGISTER 0xb8b0 - - -/****************************************/ -/* GPP Interface Registers */ -/****************************************/ - -#define GPP_IO_CONTROL 0xf100 -#define GPP_LEVEL_CONTROL 0xf110 -#define GPP_VALUE 0xf104 -#define GPP_INTERRUPT_CAUSE 0xf108 -#define GPP_INTERRUPT_MASK 0xf10c -#define GPP_INTERRUPT_MASK0 GPP_INTERRUPT_MASK /* 0xf10c1 */ -#define GPP_INTERRUPT_MASK1 0xf114 -#define GPP_VALUE_SET 0xf118 -#define GPP_VALUE_CLEAR 0xf11c - -/****************************************/ -/* MPP Interface Registers */ -/****************************************/ -#define MPP_CONTROL0 0xf000 -#define MPP_CONTROL1 0xf004 -#define MPP_CONTROL2 0xf008 -#define MPP_CONTROL3 0xf00c -#define DEBUG_PORT_MULTIPLEX 0xf014 - /*#define SERIAL_PORT_MULTIPLEX 0xf0101 */ - -/****************************************/ -/* Interrupt Controller Registers */ -/****************************************/ - -/****************************************/ -/* Interrupts */ -/****************************************/ -/****************************************/ -/* Interrupts (checked I.A. 14.10.02) */ -/****************************************/ - -#define LOW_INTERRUPT_CAUSE_REGISTER 0x004 /* gt64260: 0xc181 */ -#define HIGH_INTERRUPT_CAUSE_REGISTER 0x00c /* gt64260: 0xc681 */ -#define CPU_INTERRUPT_MASK_REGISTER_LOW 0x014 /* gt64260: 0xc1c1 */ -#define CPU_INTERRUPT_MASK_REGISTER_HIGH 0x01c /* gt64260: 0xc6c1 */ -#define CPU_SELECT_CAUSE_REGISTER 0x024 /* gt64260: 0xc701 */ -#define CPU_INTERRUPT_1_MASK_REGISTER_LOW 0x034 /* new in the MV64360 and MV64460 */ -#define CPU_INTERRUPT_1_MASK_REGISTER_HIGH 0x03c /* new in the MV64360 and MV64460 */ -#define CPU_SELECT_1_CAUSE_REGISTER 0x044 /* new in the MV64360 and MV64460 */ -#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW 0x054 /* gt64260: 0xc241 */ -#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0x05c /* gt64260: 0xc641 */ -#define PCI_0SELECT_CAUSE 0x064 /* gt64260: 0xc741 */ -#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW 0x074 /* gt64260: 0xca41 */ -#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0x07c /* gt64260: 0xce41 */ -#define PCI_1SELECT_CAUSE 0x084 /* gt64260: 0xcf41 */ -/*#define CPU_INT_0_MASK 0xe60 signal is not multiplexed on MPP in the MV64360 and MV64460 */ -/*#define CPU_INT_1_MASK 0xe64 signal is not multiplexed on MPP in the MV64360 and MV64460 */ -/*#define CPU_INT_2_MASK 0xe68 signal is not multiplexed on MPP in the MV64360 and MV64460 */ -/*#define CPU_INT_3_MASK 0xe6c signal is not multiplexed on MPP in the MV64360 and MV64460 */ - -#define MAIN_INTERRUPT_CAUSE_LOW LOW_INTERRUPT_CAUSE_REGISTER /* 0x0041 */ -#define MAIN_INTERRUPT_CAUSE_HIGH HIGH_INTERRUPT_CAUSE_REGISTER /* 0x00c1 */ -#define CPU_INTERRUPT0_MASK_LOW CPU_INTERRUPT_MASK_REGISTER_LOW /* 0x0141 */ -#define CPU_INTERRUPT0_MASK_HIGH CPU_INTERRUPT_MASK_REGISTER_HIGH /*0x01c1 */ -#define CPU_INTERRUPT0_SELECT_CAUSE CPU_SELECT_CAUSE_REGISTER /* 0x0241 */ -#define CPU_INTERRUPT1_MASK_LOW CPU_INTERRUPT_1_MASK_REGISTER_LOW /* 0x0341 */ -#define CPU_INTERRUPT1_MASK_HIGH CPU_INTERRUPT_1_MASK_REGISTER_HIGH /* 0x03c1 */ -#define CPU_INTERRUPT1_SELECT_CAUSE CPU_SELECT_1_CAUSE_REGISTER /* 0x0441 */ -#define INTERRUPT0_MASK_0_LOW PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW /* 0x0541 */ -#define INTERRUPT0_MASK_0_HIGH PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH /* 0x05c1 */ -#define INTERRUPT0_SELECT_CAUSE PCI_0SELECT_CAUSE /* 0x0641 */ -#define INTERRUPT1_MASK_0_LOW PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW /* 0x0741 */ -#define INTERRUPT1_MASK_0_HIGH PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH /* 0x07c1 */ -#define INTERRUPT1_SELECT_CAUSE PCI_1SELECT_CAUSE /* 0x0841 */ - -/****************************************/ -/* I2C Registers */ -/****************************************/ - -#define I2C_SLAVE_ADDRESS 0xc000 -#define I2C_EXTENDED_SLAVE_ADDRESS 0xc040 -#define I2C_DATA 0xc004 -#define I2C_CONTROL 0xc008 -#define I2C_STATUS_BAUDE_RATE 0xc00C -#define I2C_SOFT_RESET 0xc01c -#define I2C_SLAVE_ADDR I2C_SLAVE_ADDRESS /* 0xc0001 */ -#define I2C_EXTENDED_SLAVE_ADDR I2C_EXTENDED_SLAVE_ADDRESS /*0xc0101 */ - -/****************************************/ -/* MPSC Registers */ -/****************************************/ - - /* MPSCs Clocks Routing Registers */ - -#define MPSC_ROUTING_REG 0xb400 -#define MPSC_RX_CLOCK_ROUTING_REG 0xb404 -#define MPSC_TX_CLOCK_ROUTING_REG 0xb408 - - /* MPSCs Interrupts Registers */ - -#define MPSC_CAUSE_REG(port) (0xb804 + (port<<3)) -#define MPSC_MASK_REG(port) (0xb884 + (port<<3)) - -#define MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12)) -#define MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12)) -#define MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12)) -#define MPSC_CHANNEL_REG1(port) (0x800c + (port<<12)) -#define MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12)) -#define MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12)) -#define MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12)) -#define MPSC_CHANNEL_REG5(port) (0x801c + (port<<12)) -#define MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12)) -#define MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12)) -#define MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12)) -#define MPSC_CHANNEL_REG9(port) (0x802c + (port<<12)) -#define MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12)) - - -/* MPSC0 */ - -#define MPSC0_MAIN_CONFIGURATION_LOW 0x8000 -#define MPSC0_MAIN_CONFIGURATION_HIGH 0x8004 -#define MPSC0_PROTOCOL_CONFIGURATION 0x8008 -#define CHANNEL0_REGISTER1 0x800c -#define CHANNEL0_REGISTER2 0x8010 -#define CHANNEL0_REGISTER3 0x8014 -#define CHANNEL0_REGISTER4 0x8018 -#define CHANNEL0_REGISTER5 0x801c -#define CHANNEL0_REGISTER6 0x8020 -#define CHANNEL0_REGISTER7 0x8024 -#define CHANNEL0_REGISTER8 0x8028 -#define CHANNEL0_REGISTER9 0x802c -#define CHANNEL0_REGISTER10 0x8030 -#define CHANNEL0_REGISTER11 0x8034 - -/* MPSC1 */ - -#define MPSC1_MAIN_CONFIGURATION_LOW 0x8840 -#define MPSC1_MAIN_CONFIGURATION_HIGH 0x8844 -#define MPSC1_PROTOCOL_CONFIGURATION 0x8848 -#define CHANNEL1_REGISTER1 0x884c -#define CHANNEL1_REGISTER2 0x8850 -#define CHANNEL1_REGISTER3 0x8854 -#define CHANNEL1_REGISTER4 0x8858 -#define CHANNEL1_REGISTER5 0x885c -#define CHANNEL1_REGISTER6 0x8860 -#define CHANNEL1_REGISTER7 0x8864 -#define CHANNEL1_REGISTER8 0x8868 -#define CHANNEL1_REGISTER9 0x886c -#define CHANNEL1_REGISTER10 0x8870 -#define CHANNEL1_REGISTER11 0x8874 - -/* MPSC2 */ - -#define MPSC2_MAIN_CONFIGURATION_LOW 0x9040 -#define MPSC2_MAIN_CONFIGURATION_HIGH 0x9044 -#define MPSC2_PROTOCOL_CONFIGURATION 0x9048 -#define CHANNEL2_REGISTER1 0x904c -#define CHANNEL2_REGISTER2 0x9050 -#define CHANNEL2_REGISTER3 0x9054 -#define CHANNEL2_REGISTER4 0x9058 -#define CHANNEL2_REGISTER5 0x905c -#define CHANNEL2_REGISTER6 0x9060 -#define CHANNEL2_REGISTER7 0x9064 -#define CHANNEL2_REGISTER8 0x9068 -#define CHANNEL2_REGISTER9 0x906c -#define CHANNEL2_REGISTER10 0x9070 -#define CHANNEL2_REGISTER11 0x9074 - -/* MPSCs Interrupts */ - -#define MPSC0_CAUSE 0xb824 -#define MPSC0_MASK 0xb8a4 -#define MPSC1_CAUSE 0xb828 -#define MPSC1_MASK 0xb8a8 -#define MPSC2_CAUSE 0xb82c -#define MPSC2_MASK 0xb8ac - -/*******************************************/ -/* CUNIT Registers */ -/*******************************************/ - - /* Address Decoding Register Map */ - -#define CUNIT_BASE_ADDR_REG0 0xf200 -#define CUNIT_BASE_ADDR_REG1 0xf208 -#define CUNIT_BASE_ADDR_REG2 0xf210 -#define CUNIT_BASE_ADDR_REG3 0xf218 -#define CUNIT_SIZE0 0xf204 -#define CUNIT_SIZE1 0xf20c -#define CUNIT_SIZE2 0xf214 -#define CUNIT_SIZE3 0xf21c -#define CUNIT_HIGH_ADDR_REMAP_REG0 0xf240 -#define CUNIT_HIGH_ADDR_REMAP_REG1 0xf244 -#define CUNIT_BASE_ADDR_ENABLE_REG 0xf250 -#define MPSC0_ACCESS_PROTECTION_REG 0xf254 -#define MPSC1_ACCESS_PROTECTION_REG 0xf258 -#define CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C - - /* Error Report Registers */ - -#define CUNIT_INTERRUPT_CAUSE_REG 0xf310 -#define CUNIT_INTERRUPT_MASK_REG 0xf314 -#define CUNIT_ERROR_ADDR 0xf318 - - /* Cunit Control Registers */ - -#define CUNIT_ARBITER_CONTROL_REG 0xf300 -#define CUNIT_CONFIG_REG 0xb40c -#define CUNIT_CRROSBAR_TIMEOUT_REG 0xf304 - - /* Cunit Debug Registers */ - -#define CUNIT_DEBUG_LOW 0xf340 -#define CUNIT_DEBUG_HIGH 0xf344 -#define CUNIT_MMASK 0xf380 - -#endif /* __INCmv_gen_regh */ diff --git a/board/eltec/mhpc/Kconfig b/board/eltec/mhpc/Kconfig deleted file mode 100644 index 5a4c884..0000000 --- a/board/eltec/mhpc/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MHPC - -config SYS_BOARD - default "mhpc" - -config SYS_VENDOR - default "eltec" - -config SYS_CONFIG_NAME - default "MHPC" - -endif diff --git a/board/eltec/mhpc/MAINTAINERS b/board/eltec/mhpc/MAINTAINERS deleted file mode 100644 index 4d84a35..0000000 --- a/board/eltec/mhpc/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MHPC BOARD -M: Frank Gottschling <fgottschling@eltec.de> -S: Maintained -F: board/eltec/mhpc/ -F: include/configs/MHPC.h -F: configs/MHPC_defconfig diff --git a/board/eltec/mhpc/Makefile b/board/eltec/mhpc/Makefile deleted file mode 100644 index f3fcc2f..0000000 --- a/board/eltec/mhpc/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = mhpc.o flash.o diff --git a/board/eltec/mhpc/flash.c b/board/eltec/mhpc/flash.c deleted file mode 100644 index ad89df9..0000000 --- a/board/eltec/mhpc/flash.c +++ /dev/null @@ -1,414 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> -#include <linux/byteorder/swab.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Protection Flags: - */ -#define FLAG_PROTECT_SET 0x01 -#define FLAG_PROTECT_CLEAR 0x02 - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - size_b0 = flash_get_size((FPW *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE+monitor_flash_len-1, - &flash_info[0]); - - flash_info[0].size = size_b0; - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000); - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F640J5 : - printf ("28F640J5 \n"); break; - default: printf ("Unknown Chip Type=0x%lXh\n", - info->flash_id & FLASH_TYPEMASK); break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (FPW *addr, flash_info_t *info) -{ - FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW)0xAA00AA00; - addr[0x2AAA] = (FPW)0x55005500; - addr[0x5555] = (FPW)0x90009000; - - value = SWAP(addr[0]); - - switch (value) { - case (FPW)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW)0xFF00FF00; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - value = SWAP(addr[1]); /* device ID no swap !*/ - - switch (value) { - case (FPW)INTEL_ID_28F640J5 : - info->flash_id += FLASH_28F640J5 ; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 8 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW)0xFF00FF00; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, now, last; - int rc = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *)(info->start[sect]); - FPW status; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = (FPW)0x50005000; /* clear status register */ - *addr = (FPW)0x20002000; /* erase setup */ - *addr = (FPW)0xD000D000; /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((status = SWAP(*addr)) & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW)0xB000B000; /* suspend erase */ - *addr = (FPW)0xFF00FF00; /* reset to read mode */ - rc = 1; - break; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - *addr = (FPW)0xFF00FF00; /* reset to read mode */ - printf (" done\n"); - } - } - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) - data = (data << 8) | (*(uchar *)cp); - - for (; i<port_width && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_data(info, wp, data)) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - while (cnt >= port_width) { - data = 0; - for (i=0; i<port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data(info, wp, data)) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if ((wp & 0xfff) == 0) - { - printf("%08lX",wp); - printf("\x1b[8D"); - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<port_width && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_data(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *)dest; - ulong status; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf("not erased at %08lx (%x)\n",(ulong)addr,*addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = (FPW)0x40004000; /* write setup */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - while (((status = SWAP(*addr)) & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = (FPW)0xFF00FF00; /* restore read mode */ - return (1); - } - } - - *addr = (FPW)0xFF00FF00; /* restore read mode */ - - return (0); -} diff --git a/board/eltec/mhpc/mhpc.c b/board/eltec/mhpc/mhpc.c deleted file mode 100644 index 5781b2a..0000000 --- a/board/eltec/mhpc/mhpc.c +++ /dev/null @@ -1,465 +0,0 @@ -/* - * (C) Copyright 2001 - * ELTEC Elektronik AG - * Frank Gottschling <fgottschling@eltec.de> - * - * Board specific routines for the miniHiPerCam - * - * - initialisation (eeprom) - * - memory controller - * - serial io initialisation - * - ethernet io initialisation - * - * ----------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <cli.h> -#include <linux/ctype.h> -#include <commproc.h> -#include "mpc8xx.h" -#include <video_fb.h> - -extern void eeprom_init (void); -extern int eeprom_read (unsigned dev_addr, unsigned offset, - unsigned char *buffer, unsigned cnt); -extern int eeprom_write (unsigned dev_addr, unsigned offset, - unsigned char *buffer, unsigned cnt); - -/* globals */ -void *video_hw_init (void); -void video_set_lut (unsigned int index, /* color number */ - unsigned char r, /* red */ - unsigned char g, /* green */ - unsigned char b /* blue */ - ); - -GraphicDevice gdev; - -/* locals */ -static void video_circle (char *center, int radius, int color, int pitch); -static void video_test_image (void); -static void video_default_lut (unsigned int clut_type); - -/* revision info foer MHPC EEPROM offset 480 */ -typedef struct { - char board[12]; /* 000 - Board Revision information */ - char sensor; /* 012 - Sensor Type information */ - char serial[8]; /* 013 - Board serial number */ - char etheraddr[6]; /* 021 - Ethernet node addresse */ - char revision[2]; /* 027 - Revision code */ - char option[3]; /* 029 - resevered for options */ -} revinfo; - -/* ------------------------------------------------------------------------- */ - -static const unsigned int sdram_table[] = { - /* read single beat cycle */ - 0xef0efc04, 0x0e2dac04, 0x01ba5c04, 0x1ff5fc00, - 0xfffffc05, 0xeffafc34, 0x0ff0bc34, 0x1ff57c35, - - /* read burst cycle */ - 0xef0efc04, 0x0e3dac04, 0x10ff5c04, 0xf0fffc00, - 0xf0fffc00, 0xf1fffc00, 0xfffffc00, 0xfffffc05, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - - /* write single beat cycle */ - 0xef0efc04, 0x0e29ac00, 0x01b25c04, 0x1ff5fc05, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - - /* write burst cycle */ - 0xef0ef804, 0x0e39a000, 0x10f75000, 0xf0fff440, - 0xf0fffc40, 0xf1fffc04, 0xfffffc05, 0xfffffc04, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - - /* periodic timer expired */ - 0xeffebc84, 0x1ffd7c04, 0xfffffc04, 0xfffffc84, - 0xeffebc04, 0x1ffd7c04, 0xfffffc04, 0xfffffc05, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - - /* exception */ - 0xfffffc04, 0xfffffc05, 0xfffffc04, 0xfffffc04 -}; - -/* ------------------------------------------------------------------------- */ - -int board_early_init_f (void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = &(im->im_cpm); - volatile iop8xx_t *ip = (iop8xx_t *) & (im->im_ioport); - - /* reset the port A s.a. cpm-routines */ - ip->iop_padat = 0x0000; - ip->iop_papar = 0x0000; - ip->iop_padir = 0x0800; - ip->iop_paodr = 0x0000; - - /* reset the port B for digital and LCD output */ - cp->cp_pbdat = 0x0300; - cp->cp_pbpar = 0x5001; - cp->cp_pbdir = 0x5301; - cp->cp_pbodr = 0x0000; - - /* reset the port C configured for SMC1 serial port and aqc. control */ - ip->iop_pcdat = 0x0800; - ip->iop_pcpar = 0x0000; - ip->iop_pcdir = 0x0e30; - ip->iop_pcso = 0x0000; - - /* Config port D for LCD output */ - ip->iop_pdpar = 0x1fff; - ip->iop_pddir = 0x1fff; - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity - */ -int checkboard (void) -{ - puts ("Board: ELTEC miniHiperCam\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -int misc_init_r (void) -{ - revinfo mhpcRevInfo; - char nid[32]; - char *mhpcSensorTypes[] = { "OMNIVISON OV7610/7620 color", - "OMNIVISON OV7110 b&w", NULL - }; - char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0, - 0, 0, 0, 0, 10, 11, 12, 13, 14, 15 - }; - int i; - - /* check revision data */ - eeprom_read (CONFIG_SYS_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo, 32); - - if (strncmp ((char *) &mhpcRevInfo.board[2], "MHPC", 4) != 0) { - printf ("Enter revision number (0-9): %c ", - mhpcRevInfo.revision[0]); - if (0 != cli_readline(NULL)) { - mhpcRevInfo.revision[0] = - (char) toupper (console_buffer[0]); - } - - printf ("Enter revision character (A-Z): %c ", - mhpcRevInfo.revision[1]); - if (1 == cli_readline(NULL)) { - mhpcRevInfo.revision[1] = - (char) toupper (console_buffer[0]); - } - - printf ("Enter board name (V-XXXX-XXXX): %s ", - (char *) &mhpcRevInfo.board); - if (11 == cli_readline(NULL)) { - for (i = 0; i < 11; i++) { - mhpcRevInfo.board[i] = - (char) toupper (console_buffer[i]); - mhpcRevInfo.board[11] = '\0'; - } - } - - printf ("Supported sensor types:\n"); - i = 0; - do { - printf ("\n \'%d\' : %s\n", i, mhpcSensorTypes[i]); - } while (mhpcSensorTypes[++i] != NULL); - - do { - printf ("\nEnter sensor number (0-255): %d ", - (int) mhpcRevInfo.sensor); - if (0 != cli_readline(NULL)) { - mhpcRevInfo.sensor = - (unsigned char) - simple_strtoul (console_buffer, NULL, - 10); - } - } while (mhpcRevInfo.sensor >= i); - - printf ("Enter serial number: %s ", - (char *) &mhpcRevInfo.serial); - if (6 == cli_readline(NULL)) { - for (i = 0; i < 6; i++) { - mhpcRevInfo.serial[i] = console_buffer[i]; - } - mhpcRevInfo.serial[6] = '\0'; - } - - printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ", mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1], mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3], mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]); - if (12 == cli_readline(NULL)) { - for (i = 0; i < 12; i += 2) { - mhpcRevInfo.etheraddr[i >> 1] = - (char) (16 * - hex[toupper - (console_buffer[i]) - - '0'] + - hex[toupper - (console_buffer[i + 1]) - - '0']); - } - } - - /* setup new revision data */ - eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo, - 32); - } - - /* set environment */ - sprintf (nid, "%02x:%02x:%02x:%02x:%02x:%02x", - mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1], - mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3], - mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]); - setenv ("ethaddr", nid); - - /* print actual board identification */ - printf ("Ident: %s %s Ser %s Rev %c%c\n", - mhpcRevInfo.board, - (mhpcRevInfo.sensor == 0 ? "color" : "b&w"), - (char *) &mhpcRevInfo.serial, mhpcRevInfo.revision[0], - mhpcRevInfo.revision[1]); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ - memctl->memc_mbmr = MBMR_GPL_B4DIS; /* should this be mamr? - NTL */ - memctl->memc_mptpr = MPTPR_PTP_DIV64; - memctl->memc_mar = 0x00008800; - - /* - * Map controller SDRAM bank 0 - */ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - udelay (200); - - /* - * Map controller SDRAM bank 1 - */ - memctl->memc_or2 = CONFIG_SYS_OR2; - memctl->memc_br2 = CONFIG_SYS_BR2; - - /* - * Perform SDRAM initializsation sequence - */ - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay (1); - memctl->memc_mcr = 0x80002730; /* SDRAM bank 0 - execute twice */ - udelay (1); - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (10000); - - /* leave place for framebuffers */ - return (SDRAM_MAX_SIZE - SDRAM_RES_SIZE); -} - -/* ------------------------------------------------------------------------- */ - -static void video_circle (char *center, int radius, int color, int pitch) -{ - int x, y, d, dE, dSE; - - x = 0; - y = radius; - d = 1 - radius; - dE = 3; - dSE = -2 * radius + 5; - - *(center + x + y * pitch) = color; - *(center + y + x * pitch) = color; - *(center + y - x * pitch) = color; - *(center + x - y * pitch) = color; - *(center - x - y * pitch) = color; - *(center - y - x * pitch) = color; - *(center - y + x * pitch) = color; - *(center - x + y * pitch) = color; - while (y > x) { - if (d < 0) { - d += dE; - dE += 2; - dSE += 2; - x++; - } else { - d += dSE; - dE += 2; - dSE += 4; - x++; - y--; - } - *(center + x + y * pitch) = color; - *(center + y + x * pitch) = color; - *(center + y - x * pitch) = color; - *(center + x - y * pitch) = color; - *(center - x - y * pitch) = color; - *(center - y - x * pitch) = color; - *(center - y + x * pitch) = color; - *(center - x + y * pitch) = color; - } -} - -/* ------------------------------------------------------------------------- */ - -static void video_test_image (void) -{ - char *di; - int i, n; - - /* draw raster */ - for (i = 0; i < LCD_VIDEO_ROWS; i += 32) { - memset ((char *) (LCD_VIDEO_ADDR + i * LCD_VIDEO_COLS), - LCD_VIDEO_FG, LCD_VIDEO_COLS); - for (n = i + 1; n < i + 32; n++) - memset ((char *) (LCD_VIDEO_ADDR + - n * LCD_VIDEO_COLS), LCD_VIDEO_BG, - LCD_VIDEO_COLS); - } - - for (i = 0; i < LCD_VIDEO_COLS; i += 32) { - for (n = 0; n < LCD_VIDEO_ROWS; n++) - *(char *) (LCD_VIDEO_ADDR + n * LCD_VIDEO_COLS + i) = - LCD_VIDEO_FG; - } - - /* draw gray bar */ - di = (char *) (LCD_VIDEO_ADDR + (LCD_VIDEO_COLS - 256) / 64 * 32 + - 97 * LCD_VIDEO_COLS); - for (n = 0; n < 63; n++) { - for (i = 0; i < 256; i++) { - *di++ = (char) i; - *(di + LCD_VIDEO_COLS * 64) = (i & 1) * 255; - } - di += LCD_VIDEO_COLS - 256; - } - - video_circle ((char *) LCD_VIDEO_ADDR + LCD_VIDEO_COLS / 2 + - LCD_VIDEO_ROWS / 2 * LCD_VIDEO_COLS, LCD_VIDEO_ROWS / 2, - LCD_VIDEO_FG, LCD_VIDEO_COLS); -} - -/* ------------------------------------------------------------------------- */ - -static void video_default_lut (unsigned int clut_type) -{ - unsigned int i; - unsigned char RGB[] = { - 0x00, 0x00, 0x00, /* black */ - 0x80, 0x80, 0x80, /* gray */ - 0xff, 0x00, 0x00, /* red */ - 0x00, 0xff, 0x00, /* green */ - 0x00, 0x00, 0xff, /* blue */ - 0x00, 0xff, 0xff, /* cyan */ - 0xff, 0x00, 0xff, /* magenta */ - 0xff, 0xff, 0x00, /* yellow */ - 0x80, 0x00, 0x00, /* dark red */ - 0x00, 0x80, 0x00, /* dark green */ - 0x00, 0x00, 0x80, /* dark blue */ - 0x00, 0x80, 0x80, /* dark cyan */ - 0x80, 0x00, 0x80, /* dark magenta */ - 0x80, 0x80, 0x00, /* dark yellow */ - 0xc0, 0xc0, 0xc0, /* light gray */ - 0xff, 0xff, 0xff, /* white */ - }; - - switch (clut_type) { - case 1: - for (i = 0; i < 240; i++) - video_set_lut (i, i, i, i); - for (i = 0; i < 16; i++) - video_set_lut (i + 240, RGB[i * 3], RGB[i * 3 + 1], - RGB[i * 3 + 2]); - break; - default: - for (i = 0; i < 256; i++) - video_set_lut (i, i, i, i); - } -} - -/* ------------------------------------------------------------------------- */ - -void *video_hw_init (void) -{ - unsigned int clut = 0; - unsigned char *penv; - immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - /* enable video only on CLUT value */ - if ((penv = (uchar *)getenv ("clut")) != NULL) - clut = (u_int) simple_strtoul ((char *)penv, NULL, 10); - else - return NULL; - - /* disable graphic before write LCD regs. */ - immr->im_lcd.lcd_lccr = 0x96000866; - - /* config LCD regs. */ - immr->im_lcd.lcd_lcfaa = LCD_VIDEO_ADDR; - immr->im_lcd.lcd_lchcr = 0x010a0093; - immr->im_lcd.lcd_lcvcr = 0x900f0024; - - printf ("Video: 640x480 8Bit Index Lut %s\n", - (clut == 1 ? "240/16 (gray/vga)" : "256(gray)")); - - video_default_lut (clut); - - /* clear framebuffer */ - memset ((char *) (LCD_VIDEO_ADDR), LCD_VIDEO_BG, - LCD_VIDEO_ROWS * LCD_VIDEO_COLS); - - /* enable graphic */ - immr->im_lcd.lcd_lccr = 0x96000867; - - /* fill in Graphic Device */ - gdev.frameAdrs = LCD_VIDEO_ADDR; - gdev.winSizeX = LCD_VIDEO_COLS; - gdev.winSizeY = LCD_VIDEO_ROWS; - gdev.gdfBytesPP = 1; - gdev.gdfIndex = GDF__8BIT_INDEX; - - if (clut > 1) - /* return Graphic Device for console */ - return (void *) &gdev; - else - /* just graphic enabled - draw something beautiful */ - video_test_image (); - - return NULL; /* this disabels cfb - console */ -} - -/* ------------------------------------------------------------------------- */ - -void video_set_lut (unsigned int index, - unsigned char r, unsigned char g, unsigned char b) -{ - unsigned int lum; - unsigned short *pLut = (unsigned short *) (CONFIG_SYS_IMMR + 0x0e00); - - /* 16 bit lut values, 12 bit used, xxxx BBGG RRii iiii */ - /* y = 0.299*R + 0.587*G + 0.114*B */ - lum = (2990 * r + 5870 * g + 1140 * b) / 10000; - pLut[index] = - ((b & 0xc0) << 4) | ((g & 0xc0) << 2) | (r & 0xc0) | (lum & - 0x3f); -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/eltec/mhpc/u-boot.lds.debug b/board/eltec/mhpc/u-boot.lds.debug deleted file mode 100644 index b0091db..0000000 --- a/board/eltec/mhpc/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/cpci750/64360.h b/board/esd/cpci750/64360.h deleted file mode 100644 index 92133f0..0000000 --- a/board/esd/cpci750/64360.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus <ingo.assmus@keymile.com> - * for cpci750 Reinhard Arlt - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * main board support/init for the cpci750. - */ - -#ifndef __64360_H__ -#define __64360_H__ - -/* CPU Configuration bits */ -#define CPU_CONF_ADDR_MISS_EN (1 << 8) -#define CPU_CONF_SINGLE_CPU (1 << 11) -#define CPU_CONF_ENDIANESS (1 << 12) -#define CPU_CONF_PIPELINE (1 << 13) -#define CPU_CONF_STOP_RETRY (1 << 17) -#define CPU_CONF_MULTI_DECODE (1 << 18) -#define CPU_CONF_DP_VALID (1 << 19) -#define CPU_CONF_PERR_PROP (1 << 22) -#define CPU_CONF_AACK_DELAY_2 (1 << 25) -#define CPU_CONF_AP_VALID (1 << 26) -#define CPU_CONF_REMAP_WR_DIS (1 << 27) - -/* CPU Master Control bits */ -#define CPU_MAST_CTL_ARB_EN (1 << 8) -#define CPU_MAST_CTL_MASK_BR_1 (1 << 9) -#define CPU_MAST_CTL_M_WR_TRIG (1 << 10) -#define CPU_MAST_CTL_M_RD_TRIG (1 << 11) -#define CPU_MAST_CTL_CLEAN_BLK (1 << 12) -#define CPU_MAST_CTL_FLUSH_BLK (1 << 13) - -#endif /* __64360_H__ */ diff --git a/board/esd/cpci750/Kconfig b/board/esd/cpci750/Kconfig deleted file mode 100644 index 32d4ee6..0000000 --- a/board/esd/cpci750/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_CPCI750 - -config SYS_BOARD - default "cpci750" - -config SYS_VENDOR - default "esd" - -config SYS_CONFIG_NAME - default "CPCI750" - -endif diff --git a/board/esd/cpci750/MAINTAINERS b/board/esd/cpci750/MAINTAINERS deleted file mode 100644 index 4a46457..0000000 --- a/board/esd/cpci750/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -CPCI750 BOARD -M: Reinhard Arlt <reinhard.arlt@esd-electronics.com> -S: Maintained -F: board/esd/cpci750/ -F: include/configs/CPCI750.h -F: configs/CPCI750_defconfig diff --git a/board/esd/cpci750/Makefile b/board/esd/cpci750/Makefile deleted file mode 100644 index a3300c9..0000000 --- a/board/esd/cpci750/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2001 -# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = misc.o -obj-y += cpci750.o serial.o ../../Marvell/common/memory.o pci.o \ - mv_eth.o mpsc.o i2c.o \ - sdram_init.o ide.o diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c deleted file mode 100644 index fcaf3e6..0000000 --- a/board/esd/cpci750/cpci750.c +++ /dev/null @@ -1,1088 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com - * modifications for the cpci750 by reinhard.arlt@esd-electronics.com - */ - -/* - * cpci750.c - main board support/init for the esd cpci750. - */ - -#include <common.h> -#include <command.h> -#include <74xx_7xx.h> -#include "../../Marvell/include/memory.h" -#include "../../Marvell/include/pci.h" -#include "../../Marvell/include/mv_gen_reg.h" -#include <net.h> - -#include "eth.h" -#include "mpsc.h" -#include "i2c.h" -#include "64360.h" -#include "mv_regs.h" - -#undef DEBUG -/*#define DEBUG */ - -#ifdef CONFIG_PCI -#define MAP_PCI -#endif /* of CONFIG_PCI */ - -#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -static char show_config_tab[][15] = {{"PCI0DLL_2 "}, /* 31 */ - {"PCI0DLL_1 "}, /* 30 */ - {"PCI0DLL_0 "}, /* 29 */ - {"PCI1DLL_2 "}, /* 28 */ - {"PCI1DLL_1 "}, /* 27 */ - {"PCI1DLL_0 "}, /* 26 */ - {"BbEP2En "}, /* 25 */ - {"SDRAMRdDataDel"}, /* 24 */ - {"SDRAMRdDel "}, /* 23 */ - {"SDRAMSync "}, /* 22 */ - {"SDRAMPipeSel_1"}, /* 21 */ - {"SDRAMPipeSel_0"}, /* 20 */ - {"SDRAMAddDel "}, /* 19 */ - {"SDRAMClkSel "}, /* 18 */ - {"Reserved(1!) "}, /* 17 */ - {"PCIRty "}, /* 16 */ - {"BootCSWidth_1 "}, /* 15 */ - {"BootCSWidth_0 "}, /* 14 */ - {"PCI1PadsCal "}, /* 13 */ - {"PCI0PadsCal "}, /* 12 */ - {"MultiMVId_1 "}, /* 11 */ - {"MultiMVId_0 "}, /* 10 */ - {"MultiGTEn "}, /* 09 */ - {"Int60xArb "}, /* 08 */ - {"CPUBusConfig_1"}, /* 07 */ - {"CPUBusConfig_0"}, /* 06 */ - {"DefIntSpc "}, /* 05 */ - {0 }, /* 04 */ - {"SROMAdd_1 "}, /* 03 */ - {"SROMAdd_0 "}, /* 02 */ - {"DRAMPadCal "}, /* 01 */ - {"SInitEn "}, /* 00 */ - {0 }, /* 31 */ - {0 }, /* 30 */ - {0 }, /* 29 */ - {0 }, /* 28 */ - {0 }, /* 27 */ - {0 }, /* 26 */ - {0 }, /* 25 */ - {0 }, /* 24 */ - {0 }, /* 23 */ - {0 }, /* 22 */ - {"JTAGCalBy "}, /* 21 */ - {"GB2Sel "}, /* 20 */ - {"GB1Sel "}, /* 19 */ - {"DRAMPLL_MDiv_5"}, /* 18 */ - {"DRAMPLL_MDiv_4"}, /* 17 */ - {"DRAMPLL_MDiv_3"}, /* 16 */ - {"DRAMPLL_MDiv_2"}, /* 15 */ - {"DRAMPLL_MDiv_1"}, /* 14 */ - {"DRAMPLL_MDiv_0"}, /* 13 */ - {"GB0Sel "}, /* 12 */ - {"DRAMPLLPU "}, /* 11 */ - {"DRAMPLL_HIKVCO"}, /* 10 */ - {"DRAMPLLNP "}, /* 09 */ - {"DRAMPLL_NDiv_7"}, /* 08 */ - {"DRAMPLL_NDiv_6"}, /* 07 */ - {"CPUPadCal "}, /* 06 */ - {"DRAMPLL_NDiv_5"}, /* 05 */ - {"DRAMPLL_NDiv_4"}, /* 04 */ - {"DRAMPLL_NDiv_3"}, /* 03 */ - {"DRAMPLL_NDiv_2"}, /* 02 */ - {"DRAMPLL_NDiv_1"}, /* 01 */ - {"DRAMPLL_NDiv_0"}}; /* 00 */ - -extern flash_info_t flash_info[]; - -extern int do_bootvx (cmd_tbl_t *, int, int, char *[]); - -/* ------------------------------------------------------------------------- */ - -/* this is the current GT register space location */ -/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */ - -/* Unfortunately, we cant change it while we are in flash, so we initialize it - * to the "final" value. This means that any debug_led calls before - * board_early_init_f wont work right (like in cpu_init_f). - * See also my_remap_gt_regs below. (NTL) - */ - -void board_prebootm_init (void); -unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS; -int display_mem_map (void); - -/* - * Skip video initialization on slave variant. - * This function will overwrite the weak default in cfb_console.c - */ -int board_video_skip(void) -{ - return CPCI750_SLAVE_TEST; -} - -/* ------------------------------------------------------------------------- */ - -/* - * This is a version of the GT register space remapping function that - * doesn't touch globals (meaning, it's ok to run from flash.) - * - * Unfortunately, this has the side effect that a writable - * INTERNAL_REG_BASE_ADDR is impossible. Oh well. - */ - -void my_remap_gt_regs (u32 cur_loc, u32 new_loc) -{ - u32 temp; - - /* check and see if it's already moved */ - -/* original ppcboot 1.1.6 source - - temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 20) - return; - - temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 20); - - out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp); - - while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp); -original ppcboot 1.1.6 source end */ - - temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 16) - return; - - temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 16); - - out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp); - - while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp); -} - -#ifdef CONFIG_PCI - -static void gt_pci_config (void) -{ - unsigned int stat; - unsigned int data; - unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */ - - /* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's - * config registers by writing ones to the bus and device. - * We then update the Virtual register with the correct value for the bus and device. - */ - if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ - GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); - - GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat); - - GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); - GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); - - } - if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ - GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); - GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat); - - GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); - GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); - } - - /* Enable master */ - PCI_MASTER_ENABLE (0, SELF); - PCI_MASTER_ENABLE (1, SELF); - - /* Enable PCI0/1 Mem0 and IO 0 disable all others */ - GT_REG_READ (BASE_ADDR_ENABLE, &stat); - stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1 - << - 18); - stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15)); - GT_REG_WRITE (BASE_ADDR_ENABLE, stat); - - /* ronen- add write to pci remap registers for 64460. - in 64360 when writing to pci base go and overide remap automaticaly, - in 64460 it doesn't */ - GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_SPACE >> 16); - GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_SPACE_PCI >> 16); - GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_SPACE >> 16); - GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_SPACE_PCI >> 16); - GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16); - - /* PCI interface settings */ - /* Timeout set to retry forever */ - GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0); - GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0); - - /* ronen - enable only CS0 and Internal reg!! */ - GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); - GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); - -/*ronen update the pci internal registers base address.*/ -#ifdef MAP_PCI - for (stat = 0; stat <= PCI_HOST1; stat++) { - data = pciReadConfigReg(stat, - PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, - SELF); - data = (data & 0x0f) | CONFIG_SYS_GT_REGS; - pciWriteConfigReg (stat, - PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, - SELF, data); - } -#endif - -} -#endif - -/* Setup CPU interface paramaters */ -static void gt_cpu_config (void) -{ - cpu_t cpu = get_cpu_type (); - ulong tmp; - - /* cpu configuration register */ - tmp = GTREGREAD (CPU_CONFIGURATION); - - /* set the SINGLE_CPU bit see MV64360 P.399 */ -#ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ - tmp |= CPU_CONF_SINGLE_CPU; -#endif - - tmp &= ~CPU_CONF_AACK_DELAY_2; - - tmp |= CPU_CONF_DP_VALID; - tmp |= CPU_CONF_AP_VALID; - - tmp |= CPU_CONF_PIPELINE; - - GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */ - - /* CPU master control register */ - tmp = GTREGREAD (CPU_MASTER_CONTROL); - - tmp |= CPU_MAST_CTL_ARB_EN; - - if ((cpu == CPU_7400) || - (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) { - - tmp |= CPU_MAST_CTL_CLEAN_BLK; - tmp |= CPU_MAST_CTL_FLUSH_BLK; - - } else { - /* cleanblock must be cleared for CPUs - * that do not support this command (603e, 750) - * see Res#1 */ - tmp &= ~CPU_MAST_CTL_CLEAN_BLK; - tmp &= ~CPU_MAST_CTL_FLUSH_BLK; - } - GT_REG_WRITE (CPU_MASTER_CONTROL, tmp); -} - -/* - * board_early_init_f. - * - * set up gal. device mappings, etc. - */ -int board_early_init_f (void) -{ - - /* - * set up the GT the way the kernel wants it - * the call to move the GT register space will obviously - * fail if it has already been done, but we're going to assume - * that if it's not at the power-on location, it's where we put - * it last time. (huber) - */ - - my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS); - - /* No PCI in first release of Port To_do: enable it. */ -#ifdef CONFIG_PCI - gt_pci_config (); -#endif - /* mask all external interrupt sources */ - GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0); - /* new in MV6436x */ - GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0); - /* --------------------- */ - GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); - GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); - /* does not exist in MV6436x - GT_REG_WRITE(CPU_INT_0_MASK, 0); - GT_REG_WRITE(CPU_INT_1_MASK, 0); - GT_REG_WRITE(CPU_INT_2_MASK, 0); - GT_REG_WRITE(CPU_INT_3_MASK, 0); - --------------------- */ - - - /* ----- DEVICE BUS SETTINGS ------ */ - - /* - * EVB - * 0 - SRAM ???? - * 1 - RTC ???? - * 2 - UART ???? - * 3 - Flash checked 32Bit Intel Strata - * boot - BootCS checked 8Bit 29LV040B - * - */ - - /* - * the dual 7450 module requires burst access to the boot - * device, so the serial rom copies the boot device to the - * on-board sram on the eval board, and updates the correct - * registers to boot from the sram. (device0) - */ - - memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE); - memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE); - memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE); - memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE); - - - /* configure device timing */ - GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR); - GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR); - GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR); - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_DEV3_PAR); - -#ifdef CONFIG_SYS_32BIT_BOOT_PAR /* set port parameters for Flash device module access */ - /* detect if we are booting from the 32 bit flash */ - if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) { - /* 32 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); - GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, - CONFIG_SYS_32BIT_BOOT_PAR); - } else { - /* 8 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR); - GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); - } -#else - /* 8 bit boot flash only */ -/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/ -#endif - - - gt_cpu_config (); - - /* MPP setup */ - GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0); - GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1); - GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2); - GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3); - - GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL); - DEBUG_LED0_ON (); - DEBUG_LED1_ON (); - DEBUG_LED2_ON (); - - return 0; -} - -/* various things to do after relocation */ - -int misc_init_r () -{ - icache_enable (); -#ifdef CONFIG_SYS_L2 - l2cache_enable (); -#endif -#ifdef CONFIG_MPSC - - mpsc_sdma_init (); - mpsc_init2 (); -#endif - -#if 0 - /* disable the dcache and MMU */ - dcache_lock (); -#endif - if (flash_info[3].size < CONFIG_SYS_FLASH_INCREMENT) { - unsigned int flash_offset; - unsigned int l; - - flash_offset = CONFIG_SYS_FLASH_INCREMENT - flash_info[3].size; - for (l = 0; l < CONFIG_SYS_MAX_FLASH_SECT; l++) { - if (flash_info[3].start[l] != 0) { - flash_info[3].start[l] += flash_offset; - } - } - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[3]); - } - return 0; -} - -void after_reloc (ulong dest_addr, gd_t * gd) -{ - memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE, - CONFIG_SYS_BOOT_SIZE); - - display_mem_map (); - GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); - GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); - - /* now, jump to the main ppcboot board init code */ - board_init_r (gd, dest_addr); - /* NOTREACHED */ -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - * - * right now, assume borad type. (there is just one...after all) - */ - -int checkboard (void) -{ - int l_type = 0; - - printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME); - return (l_type); -} - -/* utility functions */ -void debug_led (int led, int mode) -{ -} - -int display_mem_map (void) -{ - int i, j; - unsigned int base, size, width; - - /* SDRAM */ - printf ("SD (DDR) RAM\n"); - for (i = 0; i <= BANK3; i++) { - base = memoryGetBankBaseAddress (i); - size = memoryGetBankSize (i); - if (size != 0) { - printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n", - i, base, size >> 20); - } - } -#ifdef CONFIG_PCI - /* CPU's PCI windows */ - for (i = 0; i <= PCI_HOST1; i++) { - printf ("\nCPU's PCI %d windows\n", i); - base = pciGetSpaceBase (i, PCI_IO); - size = pciGetSpaceSize (i, PCI_IO); - printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base, - size >> 20); - for (j = 0; - j <= - PCI_REGION0 - /*ronen currently only first PCI MEM is used 3 */ ; - j++) { - base = pciGetSpaceBase (i, j); - size = pciGetSpaceSize (i, j); - printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20); - } - } -#endif /* of CONFIG_PCI */ - /* Devices */ - printf ("\nDEVICES\n"); - for (i = 0; i <= DEVICE3; i++) { - base = memoryGetDeviceBaseAddress (i); - size = memoryGetDeviceSize (i); - width = memoryGetDeviceWidth (i) * 8; - printf ("DEV %d: base - 0x%08x size - %dM bytes\twidth - %d bits", i, base, size >> 20, width); - if (i == 0) - printf ("\t- FLASH\n"); - else if (i == 1) - printf ("\t- FLASH\n"); - else if (i == 2) - printf ("\t- FLASH\n"); - else - printf ("\t- RTC/REGS/CAN\n"); - } - - /* Bootrom */ - base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */ - size = memoryGetDeviceSize (BOOT_DEVICE); - width = memoryGetDeviceWidth (BOOT_DEVICE) * 8; - printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\t- FLASH\n", - base, size >> 20, width); - return (0); -} - -/* - * Command loadpci: wait for signal from host and boot image. - */ -int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - volatile unsigned int *ptr; - int count = 0; - int count2 = 0; - int status = 0; - char addr[16]; - char str[] = "\\|/-"; - char *local_args[2]; - - /* - * Mark sync address - */ - ptr = 0; - ptr[0] = 0xffffffff; - ptr[1] = 0xffffffff; - puts("\nWaiting for image from pci host -"); - - /* - * Wait for host to write the start address - */ - while (*ptr == 0xffffffff) { - count++; - if (!(count % 100)) { - count2++; - putc(0x08); /* backspace */ - putc(str[count2 % 4]); - } - - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - return 0; - } - - udelay(1000); - } - - sprintf(addr, "%08x", *ptr); - printf("\nBooting Image at addr 0x%s ...\n", addr); - setenv("loadaddr", addr); - - switch (ptr[1] == 0) { - case 0: - /* - * Boot image via bootm - */ - local_args[0] = argv[0]; - local_args[1] = NULL; - status = do_bootm (cmdtp, 0, 1, local_args); - break; - case 1: - /* - * Boot image via bootvx - */ - local_args[0] = argv[0]; - local_args[1] = NULL; - status = do_bootvx (cmdtp, 0, 1, local_args); - break; - } - - return status; -} - -U_BOOT_CMD( - loadpci, 1, 1, do_loadpci, - "loadpci - Wait for pci-image and boot it\n", - NULL - ); - -/* DRAM check routines copied from gw8260 */ - -#if defined (CONFIG_SYS_DRAM_TEST) - -/*********************************************************************/ -/* NAME: move64() - moves a double word (64-bit) */ -/* */ -/* DESCRIPTION: */ -/* this function performs a double word move from the data at */ -/* the source pointer to the location at the destination pointer. */ -/* */ -/* INPUTS: */ -/* unsigned long long *src - pointer to data to move */ -/* */ -/* OUTPUTS: */ -/* unsigned long long *dest - pointer to locate to move data */ -/* */ -/* RETURNS: */ -/* None */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* May cloober fr0. */ -/* */ -/*********************************************************************/ -static void move64 (unsigned long long *src, unsigned long long *dest) -{ - asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ - "stfd 0, 0(4)" /* *dest = fpr0 */ - : : : "fr0"); /* Clobbers fr0 */ - return; -} - - -#if defined (CONFIG_SYS_DRAM_TEST_DATA) - -unsigned long long pattern[] = { - 0xaaaaaaaaaaaaaaaaLL, - 0xccccccccccccccccLL, - 0xf0f0f0f0f0f0f0f0LL, - 0xff00ff00ff00ff00LL, - 0xffff0000ffff0000LL, - 0xffffffff00000000LL, - 0x00000000ffffffffLL, - 0x0000ffff0000ffffLL, - 0x00ff00ff00ff00ffLL, - 0x0f0f0f0f0f0f0f0fLL, - 0x3333333333333333LL, - 0x5555555555555555LL, -}; - -/*********************************************************************/ -/* NAME: mem_test_data() - test data lines for shorts and opens */ -/* */ -/* DESCRIPTION: */ -/* Tests data lines for shorts and opens by forcing adjacent data */ -/* to opposite states. Because the data lines could be routed in */ -/* an arbitrary manner the must ensure test patterns ensure that */ -/* every case is tested. By using the following series of binary */ -/* patterns every combination of adjacent bits is test regardless */ -/* of routing. */ -/* */ -/* ...101010101010101010101010 */ -/* ...110011001100110011001100 */ -/* ...111100001111000011110000 */ -/* ...111111110000000011111111 */ -/* */ -/* Carrying this out, gives us six hex patterns as follows: */ -/* */ -/* 0xaaaaaaaaaaaaaaaa */ -/* 0xcccccccccccccccc */ -/* 0xf0f0f0f0f0f0f0f0 */ -/* 0xff00ff00ff00ff00 */ -/* 0xffff0000ffff0000 */ -/* 0xffffffff00000000 */ -/* */ -/* The number test patterns will always be given by: */ -/* */ -/* log(base 2)(number data bits) = log2 (64) = 6 */ -/* */ -/* To test for short and opens to other signals on our boards. we */ -/* simply */ -/* test with the 1's complemnt of the paterns as well. */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* Assumes only one one SDRAM bank */ -/* */ -/*********************************************************************/ -int mem_test_data (void) -{ - unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START; - unsigned long long temp64 = 0; - int num_patterns = sizeof (pattern) / sizeof (pattern[0]); - int i; - unsigned int hi, lo; - - for (i = 0; i < num_patterns; i++) { - move64 (&(pattern[i]), pmem); - move64 (pmem, &temp64); - - /* hi = (temp64>>32) & 0xffffffff; */ - /* lo = temp64 & 0xffffffff; */ - /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */ - - hi = (pattern[i] >> 32) & 0xffffffff; - lo = pattern[i] & 0xffffffff; - /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */ - - if (temp64 != pattern[i]) { - printf ("\n Data Test Failed, pattern 0x%08x%08x", - hi, lo); - return 1; - } - } - - return 0; -} -#endif /* CONFIG_SYS_DRAM_TEST_DATA */ - -#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS) -/*********************************************************************/ -/* NAME: mem_test_address() - test address lines */ -/* */ -/* DESCRIPTION: */ -/* This function performs a test to verify that each word im */ -/* memory is uniquly addressable. The test sequence is as follows: */ -/* */ -/* 1) write the address of each word to each word. */ -/* 2) verify that each location equals its address */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern and address */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_test_address (void) -{ - volatile unsigned int *pmem = - (volatile unsigned int *) CONFIG_SYS_MEMTEST_START; - const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4; - unsigned int i; - - /* write address to each location */ - for (i = 0; i < size; i++) { - pmem[i] = i; - } - - /* verify each loaction */ - for (i = 0; i < size; i++) { - if (pmem[i] != i) { - printf ("\n Address Test Failed at 0x%x", i); - return 1; - } - } - return 0; -} -#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */ - -#if defined (CONFIG_SYS_DRAM_TEST_WALK) -/*********************************************************************/ -/* NAME: mem_march() - memory march */ -/* */ -/* DESCRIPTION: */ -/* Marches up through memory. At each location verifies rmask if */ -/* read = 1. At each location write wmask if write = 1. Displays */ -/* failing address and pattern. */ -/* */ -/* INPUTS: */ -/* volatile unsigned long long * base - start address of test */ -/* unsigned int size - number of dwords(64-bit) to test */ -/* unsigned long long rmask - read verify mask */ -/* unsigned long long wmask - wrtie verify mask */ -/* short read - verifies rmask if read = 1 */ -/* short write - writes wmask if write = 1 */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern and address */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_march (volatile unsigned long long *base, - unsigned int size, - unsigned long long rmask, - unsigned long long wmask, short read, short write) -{ - unsigned int i; - unsigned long long temp = 0; - unsigned int hitemp, lotemp, himask, lomask; - - for (i = 0; i < size; i++) { - if (read != 0) { - /* temp = base[i]; */ - move64 ((unsigned long long *) &(base[i]), &temp); - if (rmask != temp) { - hitemp = (temp >> 32) & 0xffffffff; - lotemp = temp & 0xffffffff; - himask = (rmask >> 32) & 0xffffffff; - lomask = rmask & 0xffffffff; - - printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp); - return 1; - } - } - if (write != 0) { - /* base[i] = wmask; */ - move64 (&wmask, (unsigned long long *) &(base[i])); - } - } - return 0; -} -#endif /* CONFIG_SYS_DRAM_TEST_WALK */ - -/*********************************************************************/ -/* NAME: mem_test_walk() - a simple walking ones test */ -/* */ -/* DESCRIPTION: */ -/* Performs a walking ones through entire physical memory. The */ -/* test uses as series of memory marches, mem_march(), to verify */ -/* and write the test patterns to memory. The test sequence is as */ -/* follows: */ -/* 1) march writing 0000...0001 */ -/* 2) march verifying 0000...0001 , writing 0000...0010 */ -/* 3) repeat step 2 shifting masks left 1 bit each time unitl */ -/* the write mask equals 1000...0000 */ -/* 4) march verifying 1000...0000 */ -/* The test fails if any of the memory marches return a failure. */ -/* */ -/* OUTPUTS: */ -/* Displays which pass on the memory test is executing */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_test_walk (void) -{ - unsigned long long mask; - volatile unsigned long long *pmem = - (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START; - const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8; - - unsigned int i; - - mask = 0x01; - - printf ("Initial Pass"); - mem_march (pmem, size, 0x0, 0x1, 0, 1); - - printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); - printf (" "); - printf (" "); - printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); - - for (i = 0; i < 63; i++) { - printf ("Pass %2d", i + 2); - if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) { - /*printf("mask: 0x%x, pass: %d, ", mask, i); */ - return 1; - } - mask = mask << 1; - printf ("\b\b\b\b\b\b\b"); - } - - printf ("Last Pass"); - if (mem_march (pmem, size, 0, mask, 0, 1) != 0) { - /* printf("mask: 0x%x", mask); */ - return 1; - } - printf ("\b\b\b\b\b\b\b\b\b"); - printf (" "); - printf ("\b\b\b\b\b\b\b\b\b"); - - return 0; -} - -/*********************************************************************/ -/* NAME: testdram() - calls any enabled memory tests */ -/* */ -/* DESCRIPTION: */ -/* Runs memory tests if the environment test variables are set to */ -/* 'y'. */ -/* */ -/* INPUTS: */ -/* testdramdata - If set to 'y', data test is run. */ -/* testdramaddress - If set to 'y', address test is run. */ -/* testdramwalk - If set to 'y', walking ones test is run */ -/* */ -/* OUTPUTS: */ -/* None */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int testdram (void) -{ - int rundata = 0; - int runaddress = 0; - int runwalk = 0; - -#ifdef CONFIG_SYS_DRAM_TEST_DATA - rundata = getenv_yesno("testdramdata") == 1; -#endif -#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS - runaddress = getenv_yesno("testdramaddress") == 1; -#endif -#ifdef CONFIG_SYS_DRAM_TEST_WALK - runwalk = getenv_yesno("testdramwalk") == 1; -#endif - - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END); - } -#ifdef CONFIG_SYS_DRAM_TEST_DATA - if (rundata == 1) { - printf ("Test DATA ... "); - if (mem_test_data () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif -#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS - if (runaddress == 1) { - printf ("Test ADDRESS ... "); - if (mem_test_address () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif -#ifdef CONFIG_SYS_DRAM_TEST_WALK - if (runwalk == 1) { - printf ("Test WALKING ONEs ... "); - if (mem_test_walk () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("passed\n"); - } - return 0; - -} -#endif /* CONFIG_SYS_DRAM_TEST */ - -/* ronen - the below functions are used by the bootm function */ -/* - we map the base register to fbe00000 (same mapping as in the LSP) */ -/* - we turn off the RX gig dmas - to prevent the dma from overunning */ -/* the kernel data areas. */ -/* - we diable and invalidate the icache and dcache. */ -void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc) -{ - u32 temp; - - temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 16) - return; - - temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 16); - - out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp); - - while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE | - new_loc | - (INTERNAL_SPACE_DECODE))))) - != temp); - -} - -void board_prebootm_init () -{ - -/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */ - GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16); - -/* Stop GigE Rx DMA engines */ - GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00); -/* GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00); */ -/* GV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00); */ - -/* Relocate MV64360 internal regs */ - my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, CONFIG_SYS_DFL_GT_REGS); - - icache_disable (); - dcache_disable (); -} - -int do_show_config(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned int reset_sample_low; - unsigned int reset_sample_high; - unsigned int l, l1, l2; - - GT_REG_READ(0x3c4, &reset_sample_low); - GT_REG_READ(0x3d4, &reset_sample_high); - printf("Reset configuration 0x%08x 0x%08x\n", reset_sample_low, reset_sample_high); - - l2 = 0; - for (l=0; l<63; l++) { - if (show_config_tab[l][0] != 0) { - printf("%14s:%1x ", show_config_tab[l], - ((reset_sample_low >> (31 - (l & 0x1f)))) & 0x01); - l2++; - if ((l2 % 4) == 0) - printf("\n"); - } else { - l1++; - } - if (l == 32) - reset_sample_low = reset_sample_high; - } - printf("\n"); - - return(0); -} - -U_BOOT_CMD( - show_config, 1, 1, do_show_config, - "Show Marvell strapping register", - "Show Marvell strapping register (ResetSampleLow ResetSampleHigh)" -); - -int do_pldver(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - printf("PLD version:0x%02x\n", in_8((void *)CONFIG_SYS_PLD_VER)); - - return 0; -} - -U_BOOT_CMD( - pldver, 1, 1, do_pldver, - "Show PLD version", - "Show PLD version)"); - -int board_eth_init(bd_t *bis) -{ - return mv6436x_eth_initialize(bis); -} diff --git a/board/esd/cpci750/eth.h b/board/esd/cpci750/eth.h deleted file mode 100644 index 4e42768..0000000 --- a/board/esd/cpci750/eth.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * eth.h - header file for the polled mode GT ethernet driver - */ - -#ifndef __EVB64360_ETH_H__ -#define __EVB64360_ETH_H__ - -#include <asm/types.h> -#include <asm/io.h> -#include <asm/byteorder.h> -#include <common.h> - - -int db64360_eth0_poll(void); -int db64360_eth0_transmit(unsigned int s, volatile char *p); -void db64360_eth0_disable(void); -bool network_start(bd_t *bis); - -int mv6436x_eth_initialize(bd_t *); - -#endif /* __EVB64360_ETH_H__ */ diff --git a/board/esd/cpci750/i2c.c b/board/esd/cpci750/i2c.c deleted file mode 100644 index bad0dac..0000000 --- a/board/esd/cpci750/i2c.c +++ /dev/null @@ -1,475 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Hacked for the DB64360 board by Ingo.Assmus@keymile.com - * extra improvments by Brain Waite - * for cpci750 by reinhard.arlt@esd-electronics.com - */ -#include <common.h> -#include <mpc8xx.h> -#include <malloc.h> -#include <i2c.h> -#include "../../Marvell/include/mv_gen_reg.h" -#include "../../Marvell/include/core.h" - -#define I2C_DELAY 100 -#undef DEBUG_I2C - -#ifdef DEBUG_I2C -#define DP(x) x -#else -#define DP(x) -#endif - -/* Assuming that there is only one master on the bus (us) */ - -void i2c_init (int speed, int slaveaddr) -{ - unsigned int n, m, freq, margin, power; - unsigned int actualN = 0, actualM = 0; - unsigned int minMargin = 0xffffffff; - unsigned int tclk = CONFIG_SYS_TCLK; - unsigned int i2cFreq = speed; /* 100000 max. Fast mode not supported */ - - DP (puts ("i2c_init\n")); -/* gtI2cMasterInit */ - for (n = 0; n < 8; n++) { - for (m = 0; m < 16; m++) { - power = 2 << n; /* power = 2^(n+1) */ - freq = tclk / (10 * (m + 1) * power); - if (i2cFreq > freq) - margin = i2cFreq - freq; - else - margin = freq - i2cFreq; - if (margin < minMargin) { - minMargin = margin; - actualN = n; - actualM = m; - } - } - } - - DP (puts ("setup i2c bus\n")); - - /* Setup bus */ - /* gtI2cReset */ - GT_REG_WRITE (I2C_SOFT_RESET, 0); - asm(" sync"); - GT_REG_WRITE (I2C_CONTROL, 0); - asm(" sync"); - - DP (puts ("set baudrate\n")); - - GT_REG_WRITE (I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN); - asm(" sync"); - - DP (puts ("udelay...\n")); - - udelay (I2C_DELAY); - - GT_REG_WRITE (I2C_CONTROL, (0x1 << 2) | (0x1 << 6)); - asm(" sync"); -} - - -static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit) -{ - unsigned int status, data, bits = 7; - unsigned int control; - int count = 0; - - DP (puts ("i2c_select_device\n")); - - /* Output slave address */ - - if (ten_bit) { - bits = 10; - } - - GT_REG_READ (I2C_CONTROL, &control); - control |= (0x1 << 2); - GT_REG_WRITE (I2C_CONTROL, control); - asm(" sync"); - - GT_REG_READ (I2C_CONTROL, &control); - control |= (0x1 << 5); /* generate the I2C_START_BIT */ - GT_REG_WRITE (I2C_CONTROL, control); - asm(" sync"); - RESET_REG_BITS (I2C_CONTROL, (0x01 << 3)); - asm(" sync"); - - GT_REG_READ (I2C_CONTROL, &status); - while ((status & 0x08) != 0x08) { - GT_REG_READ (I2C_CONTROL, &status); - } - - - count = 0; - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - while (((status & 0xff) != 0x08) && ((status & 0xff) != 0x10)){ - if (count > 200) { -#ifdef DEBUG_I2C - printf ("Failed to set startbit: 0x%02x\n", status); -#endif - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - asm(" sync"); - return (status); - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - - DP (puts ("i2c_select_device:write addr byte\n")); - - /* assert the address */ - - data = (dev_addr << 1); - /* set the read bit */ - data |= read; - GT_REG_WRITE (I2C_DATA, data); - asm(" sync"); - RESET_REG_BITS (I2C_CONTROL, BIT3); - asm(" sync"); - - GT_REG_READ (I2C_CONTROL, &status); - while ((status & 0x08) != 0x08) { - GT_REG_READ (I2C_CONTROL, &status); - } - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count = 0; - while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) { - if (count > 200) { -#ifdef DEBUG_I2C - printf ("Failed to write address: 0x%02x\n", status); -#endif - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - return (status); - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - asm(" sync"); - count++; - } - - if (bits == 10) { - printf ("10 bit I2C addressing not yet implemented\n"); - return (0xff); - } - - return (0); -} - -static uchar i2c_get_data (uchar * return_data, int len) -{ - - unsigned int data, status; - int count = 0; - - DP (puts ("i2c_get_data\n")); - - while (len) { - - RESET_REG_BITS (I2C_CONTROL, BIT3); - asm(" sync"); - - /* Get and return the data */ - - GT_REG_READ (I2C_CONTROL, &status); - while ((status & 0x08) != 0x08) { - GT_REG_READ (I2C_CONTROL, &status); - } - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - while ((status & 0xff) != 0x50) { - if (count > 20) { -#ifdef DEBUG_I2C - printf ("Failed to get data len status: 0x%02x\n", status); -#endif - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - asm(" sync"); - return 0; - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - GT_REG_READ (I2C_DATA, &data); - len--; - *return_data = (uchar) data; - return_data++; - - } - RESET_REG_BITS (I2C_CONTROL, BIT2 | BIT3); - asm(" sync"); - count = 0; - - GT_REG_READ (I2C_CONTROL, &status); - while ((status & 0x08) != 0x08) { - GT_REG_READ (I2C_CONTROL, &status); - } - - while ((status & 0xff) != 0x58) { - if (count > 2000) { - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - return (status); - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /* stop */ - asm(" sync"); - RESET_REG_BITS (I2C_CONTROL, (0x1 << 3)); - asm(" sync"); - - return (0); -} - - -static uchar i2c_write_data (unsigned int *data, int len) -{ - unsigned int status; - int count; - unsigned int temp; - unsigned int *temp_ptr = data; - - DP (puts ("i2c_write_data\n")); - - while (len) { - count = 0; - temp = (unsigned int) (*temp_ptr); - GT_REG_WRITE (I2C_DATA, temp); - asm(" sync"); - RESET_REG_BITS (I2C_CONTROL, (0x1 << 3)); - asm(" sync"); - - GT_REG_READ (I2C_CONTROL, &status); - while ((status & 0x08) != 0x08) { - GT_REG_READ (I2C_CONTROL, &status); - } - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - while ((status & 0xff) != 0x28) { - if (count > 200) { - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - asm(" sync"); - return (status); - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - len--; - temp_ptr++; - } - return (0); -} - - -static uchar i2c_write_byte (unsigned char *data, int len) -{ - unsigned int status; - int count; - unsigned int temp; - unsigned char *temp_ptr = data; - - DP (puts ("i2c_write_byte\n")); - - while (len) { - count = 0; - /* Set and assert the data */ - temp = *temp_ptr; - GT_REG_WRITE (I2C_DATA, temp); - asm(" sync"); - RESET_REG_BITS (I2C_CONTROL, (0x1 << 3)); - asm(" sync"); - - - GT_REG_READ (I2C_CONTROL, &status); - while ((status & 0x08) != 0x08) { - GT_REG_READ (I2C_CONTROL, &status); - } - - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - while ((status & 0xff) != 0x28) { - if (count > 200) { - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); /*stop */ - asm(" sync"); - return (status); - } - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status); - count++; - } - len--; - temp_ptr++; - } - return (0); -} - -static uchar -i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit, - int alen) -{ - uchar status; - unsigned int table[2]; - - table[1] = (offset ) & 0x0ff; /* low byte */ - table[0] = (offset >> 8) & 0x0ff; /* high byte */ - - DP (puts ("i2c_set_dev_offset\n")); - - status = i2c_select_device (dev_addr, 0, ten_bit); - if (status) { -#ifdef DEBUG_I2C -22 printf ("Failed to select device setting offset: 0x%02x\n", - status); -#endif - return status; - } -/* check the address offset length */ - if (alen == 0) - /* no address offset */ - return (0); - else if (alen == 1) { - /* 1 byte address offset */ - status = i2c_write_data (&offset, 1); - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to write data: 0x%02x\n", status); -#endif - return status; - } - } else if (alen == 2) { - /* 2 bytes address offset */ - status = i2c_write_data (table, 2); - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to write data: 0x%02x\n", status); -#endif - return status; - } - } else { - /* address offset unknown or not supported */ - printf ("Address length offset %d is not supported\n", alen); - return 1; - } - return 0; /* sucessful completion */ -} - -int -i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data, - int len) -{ - uchar status = 0; - unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED; - - DP (puts ("i2c_read\n")); - - /* set the i2c frequency */ - i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE); - - status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */ - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to set slave address & offset: 0x%02x\n", - status); -#endif - return status; - } - - status = i2c_select_device (dev_addr, 1, 0); - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to select device for data read: 0x%02x\n", - status); -#endif - return status; - } - - status = i2c_get_data (data, len); - if (status) { -#ifdef DEBUG_I2C - printf ("Data not read: 0x%02x\n", status); -#endif - return status; - } - - return 0; -} - - -void i2c_stop (void) -{ - GT_REG_WRITE (I2C_CONTROL, (0x1 << 4)); - asm(" sync"); -} - - -int -i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data, - int len) -{ - uchar status = 0; - unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED; - - DP (puts ("i2c_write\n")); - - /* set the i2c frequency */ - i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE); - - status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */ - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to set slave address & offset: 0x%02x\n", - status); -#endif - return status; - } - - - status = i2c_write_byte (data, len); /* write the data */ - if (status) { -#ifdef DEBUG_I2C - printf ("Data not written: 0x%02x\n", status); -#endif - return status; - } - /* issue a stop bit */ - i2c_stop (); - return 0; -} - - -int i2c_probe (uchar chip) -{ - -#ifdef DEBUG_I2C - unsigned int i2c_status; -#endif - uchar status = 0; - unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED; - - DP (puts ("i2c_probe\n")); - - /* set the i2c frequency */ - i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE); - - status = i2c_set_dev_offset (chip, 0, 0, 0); /* send the slave address + no offset */ - if (status) { -#ifdef DEBUG_I2C - printf ("Failed to set slave address: 0x%02x\n", status); -#endif - return (int) status; - } -#ifdef DEBUG_I2C - GT_REG_READ (I2C_STATUS_BAUDE_RATE, &i2c_status); - printf ("address %#x returned %#x\n", chip, i2c_status); -#endif - /* issue a stop bit */ - i2c_stop (); - return 0; /* successful completion */ -} diff --git a/board/esd/cpci750/i2c.h b/board/esd/cpci750/i2c.h deleted file mode 100644 index a879ea9..0000000 --- a/board/esd/cpci750/i2c.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Hacked for the DB64360 board by Ingo.Assmus@keymile.com - */ - -#ifndef __I2C_H__ -#define __I2C_H__ - -/* function declarations */ -uchar i2c_read(uchar, unsigned int, int, uchar*, int); - -#endif diff --git a/board/esd/cpci750/ide.c b/board/esd/cpci750/ide.c deleted file mode 100644 index f555c08..0000000 --- a/board/esd/cpci750/ide.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* ide.c - ide support functions */ - - -#include <common.h> -#if defined(CONFIG_CMD_IDE) -#include <ata.h> -#include <ide.h> -#include <pci.h> - -int cpci_hd_type; - -int ata_device(int dev) -{ - int retval; - - retval = (dev & 1) << 4; - if (cpci_hd_type == 2) - retval ^= 1 << 4; - return retval; -} - - -int ide_preinit (void) -{ - int status; - pci_dev_t devbusfn; - int l; - - status = 1; - cpci_hd_type = 0; - if (CPCI750_SLAVE_TEST != 0) - return status; - for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) { - ide_bus_offset[l] = -ATA_STATUS; - } - devbusfn = pci_find_device (0x1103, 0x0004, 0); - if (devbusfn != -1) { - cpci_hd_type = 1; - } else { - devbusfn = pci_find_device (0x1095, 0x3114, 0); - if (devbusfn != -1) { - cpci_hd_type = 2; - } - } - if (devbusfn != -1) { - ulong *ide_bus_offset_ptr; - - status = 0; - - ide_bus_offset_ptr = &ide_bus_offset[0]; - pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, - (u32 *)ide_bus_offset_ptr); - ide_bus_offset[0] &= 0xfffffffe; - ide_bus_offset[0] += CONFIG_SYS_PCI0_IO_SPACE; - ide_bus_offset_ptr = &ide_bus_offset[1]; - pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2, - (u32 *)ide_bus_offset_ptr); - ide_bus_offset[1] &= 0xfffffffe; - ide_bus_offset[1] += CONFIG_SYS_PCI0_IO_SPACE; - } - return status; -} - -void ide_set_reset (int flag) { - return; -} - -#endif /* of CONFIG_CMDS_IDE */ diff --git a/board/esd/cpci750/local.h b/board/esd/cpci750/local.h deleted file mode 100644 index 084f99f..0000000 --- a/board/esd/cpci750/local.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus <ingo.assmus@keymile.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * include/local.h - local configuration options, board specific - */ - -#ifndef __LOCAL_H -#define __LOCAL_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -/* This tells PPCBoot that the config options are compiled in */ -/* #undef ENV_IS_EMBEDDED */ -/* Don't touch this! PPCBOOT figures this out based on other - * magic. */ - -/* Uncomment and define any of the below options */ - -/* #define CONFIG_750CX */ /* The 750CX doesn't support as many things in L2CR */ -#define CONFIG_750FX /* The 750FX doesn't support as many things in L2CR like 750CX*/ - -/* These want string arguments */ -/* #define CONFIG_BOOTARGS */ -/* #define CONFIG_BOOTCOMMAND */ -/* #define CONFIG_RAMBOOTCOMMAND */ -/* #define CONFIG_NFSBOOTCOMMAND */ -/* #define CONFIG_SYS_AUTOLOAD */ -/* #define CONFIG_PREBOOT */ - -/* These don't */ - -/* #define CONFIG_BOOTDELAY */ -/* #define CONFIG_BAUDRATE */ -/* #define CONFIG_LOADS_ECHO */ -/* #define CONFIG_ETHADDR */ -/* #define CONFIG_ETH2ADDR */ -/* #define CONFIG_ETH3ADDR */ -/* #define CONFIG_IPADDR */ -/* #define CONFIG_SERVERIP */ -/* #define CONFIG_ROOTPATH */ -/* #define CONFIG_GATEWAYIP */ -/* #define CONFIG_NETMASK */ -/* #define CONFIG_HOSTNAME */ -/* #define CONFIG_BOOTFILE */ -/* #define CONFIG_LOADADDR */ - -/* these hardware addresses are pretty bogus, please change them to - suit your needs */ - -/* first ethernet */ -/* #define CONFIG_ETHADDR 86:06:2d:7e:c6:53 */ -#define CONFIG_ETHADDR 64:36:00:00:00:01 - -/* next two ethernet hwaddrs */ -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 86:06:2d:7e:c6:54 -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 86:06:2d:7e:c6:55 - -#define CONFIG_ENV_OVERWRITE -#endif /* __CONFIG_H */ diff --git a/board/esd/cpci750/misc.S b/board/esd/cpci750/misc.S deleted file mode 100644 index 233fd83..0000000 --- a/board/esd/cpci750/misc.S +++ /dev/null @@ -1,245 +0,0 @@ -#include <config.h> -#include <74xx_7xx.h> -#include "version.h" - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#include <asm/cache.h> -#include <asm/mmu.h> - -#include "../../Marvell/include/mv_gen_reg.h" - -#ifdef CONFIG_ECC - /* Galileo specific asm code for initializing ECC */ - .globl board_relocate_rom -board_relocate_rom: - mflr r7 - /* update the location of the GT registers */ - lis r11, CONFIG_SYS_GT_REGS@h - /* if we're using ECC, we must use the DMA engine to copy ourselves */ - bl start_idma_transfer_0 - bl wait_for_idma_0 - bl stop_idma_engine_0 - - mtlr r7 - blr - - .globl board_init_ecc -board_init_ecc: - mflr r7 - /* NOTE: r10 still contains the location we've been relocated to - * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */ - - /* now that we're running from ram, init the rest of main memory - * for ECC use */ - lis r8, CONFIG_SYS_MONITOR_LEN@h - ori r8, r8, CONFIG_SYS_MONITOR_LEN@l - - divw r3, r10, r8 - - /* set up the counter, and init the starting address */ - mtctr r3 - li r12, 0 - - /* bytes per transfer */ - mr r5, r8 -about_to_init_ecc: -1: mr r3, r12 - mr r4, r12 - bl start_idma_transfer_0 - bl wait_for_idma_0 - bl stop_idma_engine_0 - add r12, r12, r8 - bdnz 1b - - mtlr r7 - blr - - /* r3: dest addr - * r4: source addr - * r5: byte count - * r11: gt regbase - * trashes: r6, r5 - */ -start_idma_transfer_0: - /* set the byte count, including the OWN bit */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_BYTE_COUNT - stwbrx r5, 0, (r6) - - /* set the source address */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS - stwbrx r4, 0, (r6) - - /* set the dest address */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS - stwbrx r3, 0, (r6) - - /* set the next record pointer */ - li r5, 0 - mr r6, r11 - ori r6, r6, CHANNEL0NEXT_RECORD_POINTER - stwbrx r5, 0, (r6) - - /* set the low control register */ - /* bit 9 is NON chained mode, bit 31 is new style descriptors. - bit 12 is channel enable */ - ori r5, r5, (1 << 12) | (1 << 12) | (1 << 11) - /* 15 shifted by 16 (oris) == bit 31 */ - oris r5, r5, (1 << 15) - mr r6, r11 - ori r6, r6, CHANNEL0CONTROL - stwbrx r5, 0, (r6) - - blr - - /* this waits for the bytecount to return to zero, indicating - * that the trasfer is complete */ -wait_for_idma_0: - mr r5, r11 - lis r6, 0xff - ori r6, r6, 0xffff - ori r5, r5, CHANNEL0_DMA_BYTE_COUNT -1: lwbrx r4, 0, (r5) - and. r4, r4, r6 - bne 1b - - blr - - /* this turns off channel 0 of the idma engine */ -stop_idma_engine_0: - /* shut off the DMA engine */ - li r5, 0 - mr r6, r11 - ori r6, r6, CHANNEL0CONTROL - stwbrx r5, 0, (r6) - - blr -#endif - -#ifdef CONFIG_SYS_BOARD_ASM_INIT - /* NOTE: trashes r3-r7 */ - .globl board_asm_init -board_asm_init: - /* just move the GT registers to where they belong */ - lis r3, CONFIG_SYS_DFL_GT_REGS@h - ori r3, r3, CONFIG_SYS_DFL_GT_REGS@l - lis r4, CONFIG_SYS_GT_REGS@h - ori r4, r4, CONFIG_SYS_GT_REGS@l - li r5, INTERNAL_SPACE_DECODE - - /* test to see if we've already moved */ - lwbrx r6, r5, r4 - andi. r6, r6, 0xffff - /* check loading of R7 is: 0x0F80 should: 0xf800: DONE */ -/* rlwinm r7, r4, 8, 16, 31 - rlwinm r7, r4, 12, 16, 31 */ /* original */ - rlwinm r7, r4, 16, 16, 31 - /* -----------------------------------------------------*/ - cmp cr0, r7, r6 - beqlr - - /* nope, have to move the registers */ - lwbrx r6, r5, r3 - andis. r6, r6, 0xffff - or r6, r6, r7 - stwbrx r6, r5, r3 - - /* now, poll for the change */ -1: lwbrx r7, r5, r4 - cmp cr0, r7, r6 - bne 1b - - lis r3, CONFIG_SYS_INT_SRAM_BASE@h - ori r3, r3, CONFIG_SYS_INT_SRAM_BASE@l - rlwinm r3, r3, 16, 16, 31 - lis r4, CONFIG_SYS_GT_REGS@h - ori r4, r4, CONFIG_SYS_GT_REGS@l - li r5, INTEGRATED_SRAM_BASE_ADDR - stwbrx r3, r5, r4 - -2: lwbrx r6, r5, r4 - cmp cr0, r3, r6 - bne 2b - - /* done! */ - blr -#endif - -/* For use of the debug LEDs */ - .global led_on0_relocated -led_on0_relocated: - xor r21, r21, r21 - xor r18, r18, r18 - lis r18, 0xFC80 - ori r18, r18, 0x8000 -/* stw r21, 0x0(r18) */ - sync - blr - - .global led_off0_relocated -led_off0_relocated: - xor r21, r21, r21 - xor r18, r18, r18 - lis r18, 0xFC81 - ori r18, r18, 0x4000 -/* stw r21, 0x0(r18) */ - sync - blr - - .global led_on0 -led_on0: - xor r18, r18, r18 - lis r18, 0x1c80 - ori r18, r18, 0x8000 -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_off0 -led_off0: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0x4000 -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_on1 -led_on1: - xor r18, r18, r18 - lis r18, 0x1c80 - ori r18, r18, 0xc000 -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_off1 -led_off1: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0x8000 -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_on2 -led_on2: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0x0000 -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_off2 -led_off2: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0xc000 -/* stw r18, 0x0(r18) */ - sync - blr diff --git a/board/esd/cpci750/mpsc.c b/board/esd/cpci750/mpsc.c deleted file mode 100644 index a158774..0000000 --- a/board/esd/cpci750/mpsc.c +++ /dev/null @@ -1,1002 +0,0 @@ -/* - * (C) Copyright 2001 - * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com> - * - ************************************************************************/ - -/* - * mpsc.c - driver for console over the MPSC. - */ - - -#include <common.h> -#include <config.h> -#include <asm/cache.h> - -#include <malloc.h> -#include "mpsc.h" - -#include "mv_regs.h" - -#include "../../Marvell/include/memory.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* Define this if you wish to use the MPSC as a register based UART. - * This will force the serial port to not use the SDMA engine at all. - */ - -#undef CONFIG_MPSC_DEBUG_PORT - - -int (*mpsc_putchar) (char ch) = mpsc_putchar_early; -char (*mpsc_getchar) (void) = mpsc_getchar_debug; -int (*mpsc_test_char) (void) = mpsc_test_char_debug; - - -static volatile unsigned int *rx_desc_base = NULL; -static unsigned int rx_desc_index = 0; -static volatile unsigned int *tx_desc_base = NULL; -static unsigned int tx_desc_index = 0; - -/* local function declarations */ -static int galmpsc_connect (int channel, int connect); -static int galmpsc_route_rx_clock (int channel, int brg); -static int galmpsc_route_tx_clock (int channel, int brg); -static int galmpsc_write_config_regs (int mpsc, int mode); -static int galmpsc_config_channel_regs (int mpsc); -static int galmpsc_set_char_length (int mpsc, int value); -static int galmpsc_set_stop_bit_length (int mpsc, int value); -static int galmpsc_set_parity (int mpsc, int value); -static int galmpsc_enter_hunt (int mpsc); -static int galmpsc_set_brkcnt (int mpsc, int value); -static int galmpsc_set_tcschar (int mpsc, int value); -static int galmpsc_set_snoop (int mpsc, int value); -static int galmpsc_shutdown (int mpsc); - -static int galsdma_set_RFT (int channel); -static int galsdma_set_SFM (int channel); -static int galsdma_set_rxle (int channel); -static int galsdma_set_txle (int channel); -static int galsdma_set_burstsize (int channel, unsigned int value); -static int galsdma_set_RC (int channel, unsigned int value); - -static int galbrg_set_CDV (int channel, int value); -static int galbrg_enable (int channel); -static int galbrg_disable (int channel); -static int galbrg_set_clksrc (int channel, int value); -static int galbrg_set_CUV (int channel, int value); - -static void galsdma_enable_rx (void); -static int galsdma_set_mem_space (unsigned int memSpace, - unsigned int memSpaceTarget, - unsigned int memSpaceAttr, - unsigned int baseAddress, - unsigned int size); - - -#define SOFTWARE_CACHE_MANAGEMENT - -#ifdef SOFTWARE_CACHE_MANAGEMENT -#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));} -#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));} -#else -#define FLUSH_DCACHE(a,b) -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) -#define INVALIDATE_DCACHE(a,b) -#endif - -#ifdef CONFIG_MPSC_DEBUG_PORT -static void mpsc_debug_init (void) -{ - - volatile unsigned int temp; - - /* Clear the CFR (CHR4) */ - /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */ - temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP)); - temp &= 0xffffff00; - temp |= BIT29; - GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP), - temp); - - /* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */ - temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP)); - temp |= (BIT12 | BIT15); - GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP), - temp); - - /* Set int mask */ - temp = GTREGREAD (GALMPSC_0_INT_MASK); - temp |= BIT6; - GT_REG_WRITE (GALMPSC_0_INT_MASK, temp); -} -#endif - -char mpsc_getchar_debug (void) -{ - volatile int temp; - volatile unsigned int cause; - - cause = GTREGREAD (GALMPSC_0_INT_CAUSE); - while ((cause & BIT6) == 0) { - cause = GTREGREAD (GALMPSC_0_INT_CAUSE); - } - - temp = GTREGREAD (GALMPSC_CHANNELREG_10 + - (CHANNEL * GALMPSC_REG_GAP)); - /* By writing 1's to the set bits, the register is cleared */ - GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP), - temp); - GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6); - return (temp >> 16) & 0xff; -} - -/* special function for running out of flash. doesn't modify any - * global variables [josh] */ -int mpsc_putchar_early (char ch) -{ - int mpsc = CHANNEL; - int temp = - GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - galmpsc_set_tcschar (mpsc, ch); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), - temp | 0x200); - -#define MAGIC_FACTOR (10*1000000) - - udelay (MAGIC_FACTOR / gd->baudrate); - return 0; -} - -/* This is used after relocation, see serial.c and mpsc_init2 */ -static int mpsc_putchar_sdma (char ch) -{ - volatile unsigned int *p; - unsigned int temp; - - - /* align the descriptor */ - p = tx_desc_base; - memset ((void *) p, 0, 8 * sizeof (unsigned int)); - - /* fill one 64 bit buffer */ - /* word swap, pad with 0 */ - p[4] = 0; /* x */ - p[5] = (unsigned int) ch; /* x */ - - /* CHANGED completely according to GT64260A dox - NTL */ - p[0] = 0x00010001; /* 0 */ - p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* 4 */ - p[2] = 0; /* 8 */ - p[3] = (unsigned int) &p[4]; /* c */ - -#if 0 - p[9] = DESC_FIRST | DESC_LAST; - p[10] = (unsigned int) &p[0]; - p[11] = (unsigned int) &p[12]; -#endif - - FLUSH_DCACHE (&p[0], &p[8]); - - GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &p[0]); - GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &p[0]); - - temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF)); - temp |= (TX_DEMAND | TX_STOP); - GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp); - - INVALIDATE_DCACHE (&p[1], &p[2]); - - while (p[1] & DESC_OWNER_BIT) { - udelay (100); - INVALIDATE_DCACHE (&p[1], &p[2]); - } - return 0; -} - -char mpsc_getchar_sdma (void) -{ - static unsigned int done = 0; - volatile char ch; - unsigned int len = 0, idx = 0, temp; - - volatile unsigned int *p; - - - do { - p = &rx_desc_base[rx_desc_index * 8]; - - INVALIDATE_DCACHE (&p[0], &p[1]); - /* Wait for character */ - while (p[1] & DESC_OWNER_BIT) { - udelay (100); - INVALIDATE_DCACHE (&p[0], &p[1]); - } - - /* Handle error case */ - if (p[1] & (1 << 15)) { - printf ("oops, error: %08x\n", p[1]); - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + - (CHANNEL * GALMPSC_REG_GAP)); - temp |= (1 << 23); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + - (CHANNEL * GALMPSC_REG_GAP), temp); - - /* Can't poll on abort bit, so we just wait. */ - udelay (100); - - galsdma_enable_rx (); - } - - /* Number of bytes left in this descriptor */ - len = p[0] & 0xffff; - - if (len) { - /* Where to look */ - idx = 5; - if (done > 3) - idx = 4; - if (done > 7) - idx = 7; - if (done > 11) - idx = 6; - - INVALIDATE_DCACHE (&p[idx], &p[idx + 1]); - ch = p[idx] & 0xff; - done++; - } - - if (done < len) { - /* this descriptor has more bytes still - * shift down the char we just read, and leave the - * buffer in place for the next time around - */ - p[idx] = p[idx] >> 8; - FLUSH_DCACHE (&p[idx], &p[idx + 1]); - } - - if (done == len) { - /* nothing left in this descriptor. - * go to next one - */ - p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; - p[0] = 0x00100000; - FLUSH_DCACHE (&p[0], &p[1]); - /* Next descriptor */ - rx_desc_index = (rx_desc_index + 1) % RX_DESC; - done = 0; - } - } while (len == 0); /* galileo bug.. len might be zero */ - - return ch; -} - - -int mpsc_test_char_debug (void) -{ - if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0) - return 0; - else { - return 1; - } -} - - -int mpsc_test_char_sdma (void) -{ - volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8]; - - INVALIDATE_DCACHE (&p[1], &p[2]); - - if (p[1] & DESC_OWNER_BIT) - return 0; - else - return 1; -} - -int mpsc_init (int baud) -{ - /* BRG CONFIG */ - galbrg_set_baudrate (CHANNEL, baud); - galbrg_set_clksrc (CHANNEL, 8); /* set source=Tclk */ - galbrg_set_CUV (CHANNEL, 0); /* set up CountUpValue */ - galbrg_enable (CHANNEL); /* Enable BRG */ - - /* Set up clock routing */ - galmpsc_connect (CHANNEL, GALMPSC_CONNECT); /* connect it */ - - galmpsc_route_rx_clock (CHANNEL, CHANNEL); /* chosse BRG0 for Rx */ - galmpsc_route_tx_clock (CHANNEL, CHANNEL); /* chose BRG0 for Tx */ - - /* reset MPSC state */ - galmpsc_shutdown (CHANNEL); - - /* SDMA CONFIG */ - galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8); /* in 64 bit words (8 bytes) */ - galsdma_set_txle (CHANNEL); - galsdma_set_rxle (CHANNEL); - galsdma_set_RC (CHANNEL, 0xf); - galsdma_set_SFM (CHANNEL); - galsdma_set_RFT (CHANNEL); - - /* MPSC CONFIG */ - galmpsc_write_config_regs (CHANNEL, GALMPSC_UART); - galmpsc_config_channel_regs (CHANNEL); - galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8); /* 8 */ - galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE); /* N */ - galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */ - -#ifdef CONFIG_MPSC_DEBUG_PORT - mpsc_debug_init (); -#endif - - /* COMM_MPSC CONFIG */ -#ifdef SOFTWARE_CACHE_MANAGEMENT - galmpsc_set_snoop (CHANNEL, 0); /* disable snoop */ -#else - galmpsc_set_snoop (CHANNEL, 1); /* enable snoop */ -#endif - - return 0; -} - - -void mpsc_sdma_init (void) -{ -/* Setup SDMA channel0 SDMA_CONFIG_REG*/ - GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff); - -/* Enable MPSC-Window0 for DRAM Bank0 */ - if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT, - MV64360_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_0_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK0)) != true) - printf ("%s: SDMA_Window0 memory setup failed !!! \n", - __FUNCTION__); - - -/* Disable MPSC-Window1 */ - if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_1_BIT, - MV64360_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_1_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK3)) != true) - printf ("%s: SDMA_Window1 memory setup failed !!! \n", - __FUNCTION__); - - -/* Disable MPSC-Window2 */ - if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_2_BIT, - MV64360_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_2_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK3)) != true) - printf ("%s: SDMA_Window2 memory setup failed !!! \n", - __FUNCTION__); - - -/* Disable MPSC-Window3 */ - if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_3_BIT, - MV64360_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress - (CS_3_LOW_DECODE_ADDRESS), - memoryGetBankSize (BANK3)) != true) - printf ("%s: SDMA_Window3 memory setup failed !!! \n", - __FUNCTION__); - -/* Setup MPSC0 access mode Window0 full access */ - GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG, - (MV64360_SDMA_WIN_ACCESS_FULL << - (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); - -/* Setup MPSC1 access mode Window1 full access */ - GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG, - (MV64360_SDMA_WIN_ACCESS_FULL << - (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); - -/* Setup MPSC internal address space base address */ - GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS); - -/* no high address remap*/ - GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00); - GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00); - -/* clear interrupt cause register for MPSC (fault register)*/ - GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00); -} - - -void mpsc_init2 (void) -{ - int i; - -#ifndef CONFIG_MPSC_DEBUG_PORT - mpsc_putchar = mpsc_putchar_sdma; - mpsc_getchar = mpsc_getchar_sdma; - mpsc_test_char = mpsc_test_char_sdma; -#endif - /* RX descriptors */ - rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) * - sizeof (unsigned int)); - - /* align descriptors */ - rx_desc_base = (unsigned int *) - (((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0); - - rx_desc_index = 0; - - memset ((void *) rx_desc_base, 0, - (RX_DESC * 8) * sizeof (unsigned int)); - - for (i = 0; i < RX_DESC; i++) { - rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4]; /* Buffer */ - rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8]; /* Next descriptor */ - rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* Command & control */ - rx_desc_base[i * 8] = 0x00100000; - } - rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0]; - - FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]); - GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &rx_desc_base[0]); - - /* TX descriptors */ - tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) * - sizeof (unsigned int)); - - /* align descriptors */ - tx_desc_base = (unsigned int *) - (((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0); - - tx_desc_index = -1; - - memset ((void *) tx_desc_base, 0, - (TX_DESC * 8) * sizeof (unsigned int)); - - for (i = 0; i < TX_DESC; i++) { - tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323; - tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323; - tx_desc_base[i * 8 + 3] = - (unsigned int) &tx_desc_base[i * 8 + 4]; - tx_desc_base[i * 8 + 2] = - (unsigned int) &tx_desc_base[(i + 1) * 8]; - tx_desc_base[i * 8 + 1] = - DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; - - /* set sbytecnt and shadow byte cnt to 1 */ - tx_desc_base[i * 8] = 0x00010001; - } - tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0]; - - FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]); - - udelay (100); - - galsdma_enable_rx (); - - return; -} - -int galbrg_set_baudrate (int channel, int rate) -{ - int clock; - - galbrg_disable (channel); /*ok */ - -#ifdef ZUMA_NTL - /* from tclk */ - clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; -#else - clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; -#endif - - galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */ - - galbrg_enable (channel); - - gd->baudrate = rate; - - return 0; -} - -/* ------------------------------------------------------------------ */ - -/* Below are all the private functions that no one else needs */ - -static int galbrg_set_CDV (int channel, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFFF0000; - temp |= (value & 0x0000FFFF); - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_enable (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp |= 0x00010000; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_disable (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFFEFFFF; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_set_clksrc (int channel, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFC3FFFF; /* Bit 18 - 21 (MV 64260 18-22) */ - temp |= (value << 18); - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - return 0; -} - -static int galbrg_set_CUV (int channel, int value) -{ - /* set CountUpValue */ - GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value); - - return 0; -} - -#if 0 -static int galbrg_reset (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp |= 0x20000; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} -#endif - -static int galsdma_set_RFT (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000001; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_SFM (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000002; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_rxle (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000040; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_txle (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000080; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_RC (int channel, unsigned int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp &= ~0x0000003c; - temp |= (value << 2); - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_burstsize (int channel, unsigned int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp &= 0xFFFFCFFF; - switch (value) { - case 8: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x3 << 12))); - break; - - case 4: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x2 << 12))); - break; - - case 2: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x1 << 12))); - break; - - case 1: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x0 << 12))); - break; - - default: - return -1; - break; - } - - return 0; -} - -static int galmpsc_connect (int channel, int connect) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_ROUTING_REGISTER); - - if ((channel == 0) && connect) - temp &= ~0x00000007; - else if ((channel == 1) && connect) - temp &= ~(0x00000007 << 6); - else if ((channel == 0) && !connect) - temp |= 0x00000007; - else - temp |= (0x00000007 << 6); - - /* Just in case... */ - temp &= 0x3fffffff; - - GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp); - - return 0; -} - -static int galmpsc_route_rx_clock (int channel, int brg) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_RxC_ROUTE); - - if (channel == 0) { - temp &= ~0x0000000F; - temp |= brg; - } else { - temp &= ~0x00000F00; - temp |= (brg << 8); - } - - GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp); - - return 0; -} - -static int galmpsc_route_tx_clock (int channel, int brg) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_TxC_ROUTE); - - if (channel == 0) { - temp &= ~0x0000000F; - temp |= brg; - } else { - temp &= ~0x00000F00; - temp |= (brg << 8); - } - - GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp); - - return 0; -} - -static int galmpsc_write_config_regs (int mpsc, int mode) -{ - if (mode == GALMPSC_UART) { - /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */ - GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP), - 0x000004c4); - - /* Main config reg High (32x Rx/Tx clock mode, width=8bits */ - GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP), - 0x024003f8); - /* 22 2222 1111 */ - /* 54 3210 9876 */ - /* 0000 0010 0000 0000 */ - /* 1 */ - /* 098 7654 3210 */ - /* 0000 0011 1111 1000 */ - } else - return -1; - - return 0; -} - -static int galmpsc_config_channel_regs (int mpsc) -{ - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1); - GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0); - - galmpsc_set_brkcnt (mpsc, 0x3); - galmpsc_set_tcschar (mpsc, 0xab); - - return 0; -} - -static int galmpsc_set_brkcnt (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP)); - temp &= 0x0000FFFF; - temp |= (value << 16); - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_tcschar (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFF0000; - temp |= value; - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_char_length (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFFCFFF; - temp |= (value << 12); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_stop_bit_length (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFFBFFF; - temp |= (value << 14); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_parity (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - if (value != -1) { - temp &= 0xFFF3FFF3; - temp |= ((value << 18) | (value << 2)); - temp |= ((value << 17) | (value << 1)); - } else { - temp &= 0xFFF1FFF1; - } - - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_enter_hunt (int mpsc) -{ - int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - temp |= 0x80000000; - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) & - MPSC_ENTER_HUNT) { - udelay (1); - } - return 0; -} - - -static int galmpsc_shutdown (int mpsc) -{ - unsigned int temp; - - /* cause RX abort (clears RX) */ - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - temp |= MPSC_RX_ABORT | MPSC_TX_ABORT; - temp &= ~MPSC_ENTER_HUNT; - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - GT_REG_WRITE (GALSDMA_0_COM_REG, 0); - GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT); - - /* shut down the MPSC */ - GT_REG_WRITE (GALMPSC_MCONF_LOW, 0); - GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0); - - udelay (100); - - /* shut down the sdma engines. */ - /* reset config to default */ - GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc); - - udelay (100); - - /* clear the SDMA current and first TX and RX pointers */ - GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0); - GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0); - GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0); - - udelay (100); - - return 0; -} - -static void galsdma_enable_rx (void) -{ - int temp; - - /* Enable RX processing */ - temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF)); - temp |= RX_ENABLE; - GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp); - - galmpsc_enter_hunt (CHANNEL); -} - -static int galmpsc_set_snoop (int mpsc, int value) -{ - int reg = - mpsc ? MPSC_1_ADDRESS_CONTROL_LOW : - MPSC_0_ADDRESS_CONTROL_LOW; - int temp = GTREGREAD (reg); - - if (value) - temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30); - else - temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30)); - GT_REG_WRITE (reg, temp); - return 0; -} - -/******************************************************************************* -* galsdma_set_mem_space - Set MV64360 IDMA memory decoding map. -* -* DESCRIPTION: -* the MV64360 SDMA has its own address decoding map that is de-coupled -* from the CPU interface address decoding windows. The SDMA channels -* share four address windows. Each region can be individually configured -* by this function by associating it to a target interface and setting -* base and size values. -* -* NOTE!!! -* The size must be in 64Kbyte granularity. -* The base address must be aligned to the size. -* The size must be a series of 1s followed by a series of zeros -* -* OUTPUT: -* None. -* -* RETURN: -* true for success, false otherwise. -* -*******************************************************************************/ - -static int galsdma_set_mem_space (unsigned int memSpace, - unsigned int memSpaceTarget, - unsigned int memSpaceAttr, - unsigned int baseAddress, unsigned int size) -{ - unsigned int temp; - - if (size == 0) { - GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG, - 1 << memSpace); - return true; - } - - /* The base address must be aligned to the size. */ - if (baseAddress % size != 0) { - return false; - } - if (size < 0x10000) { - return false; - } - - /* Align size and base to 64K */ - baseAddress &= 0xffff0000; - size &= 0xffff0000; - temp = size >> 16; - - /* Checking that the size is a sequence of '1' followed by a - sequence of '0' starting from LSB to MSB. */ - while ((temp > 0) && (temp & 0x1)) { - temp = temp >> 1; - } - - if (temp != 0) { - GT_REG_WRITE (MV64360_CUNIT_BASE_ADDR_REG0 + memSpace * 8, - (baseAddress | memSpaceTarget | memSpaceAttr)); - GT_REG_WRITE ((MV64360_CUNIT_SIZE0 + memSpace * 8), - (size - 1) & 0xffff0000); - GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG, - 1 << memSpace); - } else { - /* An invalid size was specified */ - return false; - } - return true; -} diff --git a/board/esd/cpci750/mpsc.h b/board/esd/cpci750/mpsc.h deleted file mode 100644 index 241f28a..0000000 --- a/board/esd/cpci750/mpsc.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * (C) Copyright 2001 - * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com> - * - ************************************************************************/ - - -/* - * mpsc.h - header file for MPSC in uart mode (console driver) - */ - -#ifndef __MPSC_H__ -#define __MPSC_H__ - -/* include actual Galileo defines */ -#include "../../Marvell/include/mv_gen_reg.h" - -/* driver related defines */ - -int mpsc_init(int baud); -void mpsc_sdma_init(void); -void mpsc_init2(void); -int galbrg_set_baudrate(int channel, int rate); - -int mpsc_putchar_early(char ch); -char mpsc_getchar_debug(void); -int mpsc_test_char_debug(void); - -int mpsc_test_char_sdma(void); - -extern int (*mpsc_putchar)(char ch); -extern char (*mpsc_getchar)(void); -extern int (*mpsc_test_char)(void); - -#define CHANNEL CONFIG_MPSC_PORT - -#define TX_DESC 5 -#define RX_DESC 20 - -#define DESC_FIRST 0x00010000 -#define DESC_LAST 0x00020000 -#define DESC_OWNER_BIT 0x80000000 - -#define TX_DEMAND 0x00800000 -#define TX_STOP 0x00010000 -#define RX_ENABLE 0x00000080 - -#define SDMA_RX_ABORT (1 << 15) -#define SDMA_TX_ABORT (1 << 31) -#define MPSC_TX_ABORT (1 << 7) -#define MPSC_RX_ABORT (1 << 23) -#define MPSC_ENTER_HUNT (1 << 31) - -/* MPSC defines */ - -#define GALMPSC_CONNECT 0x1 -#define GALMPSC_DISCONNECT 0x0 - -#define GALMPSC_UART 0x1 - -#define GALMPSC_STOP_BITS_1 0x0 -#define GALMPSC_STOP_BITS_2 0x1 -#define GALMPSC_CHAR_LENGTH_8 0x3 -#define GALMPSC_CHAR_LENGTH_7 0x2 - -#define GALMPSC_PARITY_ODD 0x0 -#define GALMPSC_PARITY_EVEN 0x2 -#define GALMPSC_PARITY_MARK 0x3 -#define GALMPSC_PARITY_SPACE 0x1 -#define GALMPSC_PARITY_NONE -1 - -#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */ -#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */ -#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */ -#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */ -#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */ -#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */ -#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */ - -#define GALMPSC_REG_GAP 0x1000 - -#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */ -#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */ -#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */ -#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */ -#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */ -#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */ -#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */ -#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */ -#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */ -#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */ -#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */ -#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */ - -#define GALSDMA_COMMAND_FIRST (1 << 16) -#define GALSDMA_COMMAND_LAST (1 << 17) -#define GALSDMA_COMMAND_ENABLEINT (1 << 23) -#define GALSDMA_COMMAND_AUTO (1 << 30) -#define GALSDMA_COMMAND_OWNER (1 << 31) - -#define GALSDMA_RX 0 -#define GALSDMA_TX 1 - -/* CHANNEL2 should be CHANNEL1, according to documentation, - * but to work with the current GTREGS file... - */ -#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */ -#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */ -#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */ -#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */ -#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */ -#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */ -#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */ -#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */ -#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */ -#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */ -#define GALSDMA_REG_DIFF 0x2000 - -/* WRONG in gt64260R.h */ -#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */ -#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */ -#define GALMPSC_0_INT_CAUSE 0xb804 -#define GALMPSC_0_INT_MASK 0xb884 - -#define GALSDMA_MODE_UART 0 -#define GALSDMA_MODE_BISYNC 1 -#define GALSDMA_MODE_HDLC 2 -#define GALSDMA_MODE_TRANSPARENT 3 - -#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */ -#define GALBRG_REG_GAP 0x0008 -#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */ - -#endif /* __MPSC_H__ */ diff --git a/board/esd/cpci750/mv_eth.c b/board/esd/cpci750/mv_eth.c deleted file mode 100644 index cbdcfe3..0000000 --- a/board/esd/cpci750/mv_eth.c +++ /dev/null @@ -1,3131 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus <ingo.assmus@keymile.com> - * - * based on - Driver for MV64360X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * SPDX-License-Identifier: GPL-2.0 - */ - -/* - * mv_eth.c - header file for the polled mode GT ethernet driver - */ -#include <common.h> -#include <net.h> -#include <malloc.h> - -#include "mv_eth.h" - -/* enable Debug outputs */ - -#undef DEBUG_MV_ETH - -#ifdef DEBUG_MV_ETH -#define DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -#undef MV64360_CHECKSUM_OFFLOAD -/************************************************************************* -************************************************************************** -************************************************************************** -* The first part is the high level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ - -/* Definition for configuring driver */ -/* #define UPDATE_STATS_BY_SOFTWARE */ -#undef MV64360_RX_QUEUE_FILL_ON_TASK - - -/* Constants */ -#define MAGIC_ETH_RUNNING 8031971 -#define MV64360_INTERNAL_SRAM_SIZE _256K -#define EXTRA_BYTES 32 -#define WRAP ETH_HLEN + 2 + 4 + 16 -#define BUFFER_MTU dev->mtu + WRAP -#define INT_CAUSE_UNMASK_ALL 0x0007ffff -#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff -#ifdef MV64360_RX_FILL_ON_TASK -#define INT_CAUSE_MASK_ALL 0x00000000 -#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL -#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT -#endif - -/* Read/Write to/from MV64360 internal registers */ -#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset)) -#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data) -#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits))) -#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits))) - -/* Static function declarations */ -static int mv64360_eth_real_open (struct eth_device *eth); -static int mv64360_eth_real_stop (struct eth_device *eth); -static struct net_device_stats *mv64360_eth_get_stats (struct eth_device - *dev); -static void eth_port_init_mac_tables (ETH_PORT eth_port_num); -static void mv64360_eth_update_stat (struct eth_device *dev); -bool db64360_eth_start (struct eth_device *eth); -unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, - unsigned int mib_offset); -int mv64360_eth_receive (struct eth_device *dev); - -int mv64360_eth_xmit (struct eth_device *, volatile void *packet, int length); - -#ifndef UPDATE_STATS_BY_SOFTWARE -static void mv64360_eth_print_stat (struct eth_device *dev); -#endif - -extern unsigned int INTERNAL_REG_BASE_ADDR; - -/************************************************* - *Helper functions - used inside the driver only * - *************************************************/ -#ifdef DEBUG_MV_ETH -void print_globals (struct eth_device *dev) -{ - printf ("Ethernet PRINT_Globals-Debug function\n"); - printf ("Base Address for ETH_PORT_INFO: %08x\n", - (unsigned int) dev->priv); - printf ("Base Address for mv64360_eth_priv: %08x\n", - (unsigned int) &(((ETH_PORT_INFO *) dev->priv)-> - port_private)); - - printf ("GT Internal Base Address: %08x\n", - INTERNAL_REG_BASE_ADDR); - printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64360_TX_QUEUE_SIZE); - printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64360_RX_QUEUE_SIZE); - printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n", - (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> - p_rx_buffer_base[0], - (MV64360_RX_QUEUE_SIZE * MV64360_RX_BUFFER_SIZE) + 32); - printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n", - (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> - p_tx_buffer_base[0], - (MV64360_TX_QUEUE_SIZE * MV64360_TX_BUFFER_SIZE) + 32); -} -#endif - -#define my_cpu_to_le32(x) my_le32_to_cpu((x)) - -unsigned long my_le32_to_cpu (unsigned long x) -{ - return (((x & 0x000000ffU) << 24) | - ((x & 0x0000ff00U) << 8) | - ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24)); -} - - -/********************************************************************** - * mv64360_eth_print_phy_status - * - * Prints gigabit ethenret phy status - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64360_eth_print_phy_status (struct eth_device *dev) -{ - struct mv64360_eth_priv *port_private; - unsigned int port_num; - ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv; - unsigned int port_status, phy_reg_data; - - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Check Link status on phy */ - eth_port_read_smi_reg (port_num, 1, &phy_reg_data); - if (!(phy_reg_data & 0x20)) { - printf ("Ethernet port changed link status to DOWN\n"); - } else { - port_status = - MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num)); - printf ("Ethernet status port %d: Link up", port_num); - printf (", %s", - (port_status & BIT2) ? "Full Duplex" : "Half Duplex"); - if (port_status & BIT4) - printf (", Speed 1 Gbps"); - else - printf (", %s", - (port_status & BIT5) ? "Speed 100 Mbps" : - "Speed 10 Mbps"); - printf ("\n"); - } -} - -/********************************************************************** - * u-boot entry functions for mv64360_eth - * - **********************************************************************/ -int db64360_eth_probe (struct eth_device *dev) -{ - return ((int) db64360_eth_start (dev)); -} - -int db64360_eth_poll (struct eth_device *dev) -{ - return mv64360_eth_receive (dev); -} - -int db64360_eth_transmit(struct eth_device *dev, void *packet, int length) -{ - mv64360_eth_xmit (dev, packet, length); - return 0; -} - -void db64360_eth_disable (struct eth_device *dev) -{ - mv64360_eth_stop (dev); -} - - -void mv6436x_eth_initialize (bd_t * bis) -{ - struct eth_device *dev; - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - int devnum, x, temp; - char *s, *e, buf[64]; - - for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) { - dev = calloc (sizeof (*dev), 1); - if (!dev) { - printf ("%s: mv_enet%d allocation failure, %s\n", - __FUNCTION__, devnum, "eth_device structure"); - return; - } - - /* must be less than sizeof(dev->name) */ - sprintf (dev->name, "mv_enet%d", devnum); - -#ifdef DEBUG - printf ("Initializing %s\n", dev->name); -#endif - - /* Extract the MAC address from the environment */ - switch (devnum) { - case 0: - s = "ethaddr"; - break; - - case 1: - s = "eth1addr"; - break; - - case 2: - s = "eth2addr"; - break; - - default: /* this should never happen */ - printf ("%s: Invalid device number %d\n", - __FUNCTION__, devnum); - return; - } - - temp = getenv_f(s, buf, sizeof (buf)); - s = (temp > 0) ? buf : NULL; - -#ifdef DEBUG - printf ("Setting MAC %d to %s\n", devnum, s); -#endif - for (x = 0; x < 6; ++x) { - dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - /* ronen - set the MAC addr in the HW */ - eth_port_uc_addr_set (devnum, dev->enetaddr, 0); - - dev->init = (void *) db64360_eth_probe; - dev->halt = (void *) ethernet_phy_reset; - dev->send = (void *) db64360_eth_transmit; - dev->recv = (void *) db64360_eth_poll; - - ethernet_private = - calloc (sizeof (*ethernet_private), 1); - dev->priv = (void *) ethernet_private; - if (!ethernet_private) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Private Device Structure"); - free (dev); - return; - } - /* start with an zeroed ETH_PORT_INFO */ - memset (ethernet_private, 0, sizeof (ETH_PORT_INFO)); - memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); - - /* set pointer to memory for stats data structure etc... */ - port_private = - calloc (sizeof (*ethernet_private), 1); - ethernet_private->port_private = (void *)port_private; - if (!port_private) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Port Private Device Structure"); - - free (ethernet_private); - free (dev); - return; - } - - port_private->stats = - calloc (sizeof (struct net_device_stats), 1); - if (!port_private->stats) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Net stat Structure"); - - free (port_private); - free (ethernet_private); - free (dev); - return; - } - memset (ethernet_private->port_private, 0, - sizeof (struct mv64360_eth_priv)); - switch (devnum) { - case 0: - ethernet_private->port_num = ETH_0; - break; - case 1: - ethernet_private->port_num = ETH_1; - break; - case 2: - ethernet_private->port_num = ETH_2; - break; - default: - printf ("Invalid device number %d\n", devnum); - break; - }; - - port_private->port_num = devnum; - /* - * Read MIB counter on the GT in order to reset them, - * then zero all the stats fields in memory - */ - mv64360_eth_update_stat (dev); - memset (port_private->stats, 0, - sizeof (struct net_device_stats)); - /* Extract the MAC address from the environment */ - switch (devnum) { - case 0: - s = "ethaddr"; - break; - - case 1: - s = "eth1addr"; - break; - - case 2: - s = "eth2addr"; - break; - - default: /* this should never happen */ - printf ("%s: Invalid device number %d\n", - __FUNCTION__, devnum); - return; - } - - temp = getenv_f(s, buf, sizeof (buf)); - s = (temp > 0) ? buf : NULL; - -#ifdef DEBUG - printf ("Setting MAC %d to %s\n", devnum, s); -#endif - for (x = 0; x < 6; ++x) { - dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - - DP (printf ("Allocating descriptor and buffer rings\n")); - - ethernet_private->p_rx_desc_area_base[0] = - (ETH_RX_DESC *) memalign (16, - RX_DESC_ALIGNED_SIZE * - MV64360_RX_QUEUE_SIZE + 1); - ethernet_private->p_tx_desc_area_base[0] = - (ETH_TX_DESC *) memalign (16, - TX_DESC_ALIGNED_SIZE * - MV64360_TX_QUEUE_SIZE + 1); - - ethernet_private->p_rx_buffer_base[0] = - (char *) memalign (16, - MV64360_RX_QUEUE_SIZE * - MV64360_TX_BUFFER_SIZE + 1); - ethernet_private->p_tx_buffer_base[0] = - (char *) memalign (16, - MV64360_RX_QUEUE_SIZE * - MV64360_TX_BUFFER_SIZE + 1); - -#ifdef DEBUG_MV_ETH - /* DEBUG OUTPUT prints adresses of globals */ - print_globals (dev); -#endif - eth_register (dev); - - } - DP (printf ("%s: exit\n", __FUNCTION__)); - -} - -/********************************************************************** - * mv64360_eth_open - * - * This function is called when openning the network device. The function - * should initialize all the hardware, initialize cyclic Rx/Tx - * descriptors chain and buffers and allocate an IRQ to the network - * device. - * - * Input : a pointer to the network device structure - * / / ronen - changed the output to match net/eth.c needs - * Output : nonzero of success , zero if fails. - * under construction - **********************************************************************/ - -int mv64360_eth_open (struct eth_device *dev) -{ - return (mv64360_eth_real_open (dev)); -} - -/* Helper function for mv64360_eth_open */ -static int mv64360_eth_real_open (struct eth_device *dev) -{ - - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - u32 phy_reg_data; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - /* ronen - when we update the MAC env params we only update dev->enetaddr - see ./net/eth.c eth_set_enetaddr() */ - memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); - - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Stop RX Queues */ - MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Clear the ethernet port interrupts */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0); - MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); - - /* Unmask RX buffer and TX end interrupt */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), - INT_CAUSE_UNMASK_ALL); - - /* Unmask phy and link status changes interrupts */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), - INT_CAUSE_UNMASK_ALL_EXT); - - /* Set phy address of the port */ - ethernet_private->port_phy_addr = 0x8 + port_num; - - /* Activate the DMA channels etc */ - eth_port_init (ethernet_private); - - - /* "Allocate" setup TX rings */ - - for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) { - unsigned int size; - - port_private->tx_ring_size[queue] = MV64360_TX_QUEUE_SIZE; - size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */ - ethernet_private->tx_desc_area_size[queue] = size; - - /* first clear desc area completely */ - memset ((void *) ethernet_private->p_tx_desc_area_base[queue], - 0, ethernet_private->tx_desc_area_size[queue]); - - /* initialize tx desc ring with low level driver */ - if (ether_init_tx_desc_ring - (ethernet_private, ETH_Q0, - port_private->tx_ring_size[queue], - MV64360_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , - (unsigned int) ethernet_private-> - p_tx_desc_area_base[queue], - (unsigned int) ethernet_private-> - p_tx_buffer_base[queue]) == false) - printf ("### Error initializing TX Ring\n"); - } - - /* "Allocate" setup RX rings */ - for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) { - unsigned int size; - - /* Meantime RX Ring are fixed - but must be configurable by user */ - port_private->rx_ring_size[queue] = MV64360_RX_QUEUE_SIZE; - size = (port_private->rx_ring_size[queue] * - RX_DESC_ALIGNED_SIZE); - ethernet_private->rx_desc_area_size[queue] = size; - - /* first clear desc area completely */ - memset ((void *) ethernet_private->p_rx_desc_area_base[queue], - 0, ethernet_private->rx_desc_area_size[queue]); - if ((ether_init_rx_desc_ring - (ethernet_private, ETH_Q0, - port_private->rx_ring_size[queue], - MV64360_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , - (unsigned int) ethernet_private-> - p_rx_desc_area_base[queue], - (unsigned int) ethernet_private-> - p_rx_buffer_base[queue])) == false) - printf ("### Error initializing RX Ring\n"); - } - - eth_port_start (ethernet_private); - - /* Set maximum receive buffer to 9700 bytes */ - MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num), - (0x5 << 17) | - (MV_REG_READ - (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num)) - & 0xfff1ffff)); - - /* - * Set ethernet MTU for leaky bucket mechanism to 0 - this will - * disable the leaky bucket mechanism . - */ - - MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0); - MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num)); - - /* Check Link status on phy */ - eth_port_read_smi_reg (port_num, 1, &phy_reg_data); - if (!(phy_reg_data & 0x20)) { - /* Reset PHY */ - if ((ethernet_phy_reset (port_num)) != true) { - printf ("$$ Warnning: No link on port %d \n", - port_num); - return 0; - } else { - eth_port_read_smi_reg (port_num, 1, &phy_reg_data); - if (!(phy_reg_data & 0x20)) { - printf ("### Error: Phy is not active\n"); - return 0; - } - } - } else { - mv64360_eth_print_phy_status (dev); - } - port_private->eth_running = MAGIC_ETH_RUNNING; - return 1; -} - - -static int mv64360_eth_free_tx_rings (struct eth_device *dev) -{ - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - volatile ETH_TX_DESC *p_tx_curr_desc; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Stop Tx Queues */ - MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Free TX rings */ - DP (printf ("Clearing previously allocated TX queues... ")); - for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) { - /* Free on TX rings */ - for (p_tx_curr_desc = - ethernet_private->p_tx_desc_area_base[queue]; - ((unsigned int) p_tx_curr_desc <= (unsigned int) - ethernet_private->p_tx_desc_area_base[queue] + - ethernet_private->tx_desc_area_size[queue]); - p_tx_curr_desc = - (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc + - TX_DESC_ALIGNED_SIZE)) { - /* this is inside for loop */ - if (p_tx_curr_desc->return_info != 0) { - p_tx_curr_desc->return_info = 0; - DP (printf ("freed\n")); - } - } - DP (printf ("Done\n")); - } - return 0; -} - -static int mv64360_eth_free_rx_rings (struct eth_device *dev) -{ - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - volatile ETH_RX_DESC *p_rx_curr_desc; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - - /* Stop RX Queues */ - MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Free RX rings */ - DP (printf ("Clearing previously allocated RX queues... ")); - for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) { - /* Free preallocated skb's on RX rings */ - for (p_rx_curr_desc = - ethernet_private->p_rx_desc_area_base[queue]; - (((unsigned int) p_rx_curr_desc < - ((unsigned int) ethernet_private-> - p_rx_desc_area_base[queue] + - ethernet_private->rx_desc_area_size[queue]))); - p_rx_curr_desc = - (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc + - RX_DESC_ALIGNED_SIZE)) { - if (p_rx_curr_desc->return_info != 0) { - p_rx_curr_desc->return_info = 0; - DP (printf ("freed\n")); - } - } - DP (printf ("Done\n")); - } - return 0; -} - -/********************************************************************** - * mv64360_eth_stop - * - * This function is used when closing the network device. - * It updates the hardware, - * release all memory that holds buffers and descriptors and release the IRQ. - * Input : a pointer to the device structure - * Output : zero if success , nonzero if fails - *********************************************************************/ - -int mv64360_eth_stop (struct eth_device *dev) -{ - /* Disable all gigE address decoder */ - MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f); - DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__)); - mv64360_eth_real_stop (dev); - - return 0; -}; - -/* Helper function for mv64360_eth_stop */ - -static int mv64360_eth_real_stop (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - - mv64360_eth_free_tx_rings (dev); - mv64360_eth_free_rx_rings (dev); - - eth_port_reset (ethernet_private->port_num); - /* Disable ethernet port interrupts */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0); - MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); - /* Mask RX buffer and TX end interrupt */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), 0); - /* Mask phy and link status changes interrupts */ - MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0); - MV_RESET_REG_BITS (MV64360_CPU_INTERRUPT0_MASK_HIGH, - BIT0 << port_num); - /* Print Network statistics */ -#ifndef UPDATE_STATS_BY_SOFTWARE - /* - * Print statistics (only if ethernet is running), - * then zero all the stats fields in memory - */ - if (port_private->eth_running == MAGIC_ETH_RUNNING) { - port_private->eth_running = 0; - mv64360_eth_print_stat (dev); - } - memset (port_private->stats, 0, sizeof (struct net_device_stats)); -#endif - DP (printf ("\nEthernet stopped ... \n")); - return 0; -} - - -/********************************************************************** - * mv64360_eth_start_xmit - * - * This function is queues a packet in the Tx descriptor for - * required port. - * - * Input : skb - a pointer to socket buffer - * dev - a pointer to the required port - * - * Output : zero upon success - **********************************************************************/ - -int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr, - int dataSize) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - PKT_INFO pkt_info; - ETH_FUNC_RET_STATUS status; - struct net_device_stats *stats; - ETH_FUNC_RET_STATUS release_result; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - - stats = port_private->stats; - - /* Update packet info data structure */ - pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */ - pkt_info.byte_cnt = dataSize; - pkt_info.buf_ptr = (unsigned int) dataPtr; - pkt_info.return_info = 0; - - status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info); - if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) { - printf ("Error on transmitting packet .."); - if (status == ETH_QUEUE_FULL) - printf ("ETH Queue is full. \n"); - if (status == ETH_QUEUE_LAST_RESOURCE) - printf ("ETH Queue: using last available resource. \n"); - goto error; - } - - /* Update statistics and start of transmittion time */ - stats->tx_bytes += dataSize; - stats->tx_packets++; - - /* Check if packet(s) is(are) transmitted correctly (release everything) */ - do { - release_result = - eth_tx_return_desc (ethernet_private, ETH_Q0, - &pkt_info); - switch (release_result) { - case ETH_OK: - DP (printf ("descriptor released\n")); - if (pkt_info.cmd_sts & BIT0) { - printf ("Error in TX\n"); - stats->tx_errors++; - - } - break; - case ETH_RETRY: - DP (printf ("transmission still in process\n")); - break; - - case ETH_ERROR: - printf ("routine can not access Tx desc ring\n"); - break; - - case ETH_END_OF_JOB: - DP (printf ("the routine has nothing to release\n")); - break; - default: /* should not happen */ - break; - } - } while (release_result == ETH_OK); - - - return 0; /* success */ - error: - return 1; /* Failed - higher layers will free the skb */ -} - -/********************************************************************** - * mv64360_eth_receive - * - * This function is forward packets that are received from the port's - * queues toward kernel core or FastRoute them to another interface. - * - * Input : dev - a pointer to the required interface - * max - maximum number to receive (0 means unlimted) - * - * Output : number of served packets - **********************************************************************/ - -int mv64360_eth_receive (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - PKT_INFO pkt_info; - struct net_device_stats *stats; - - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - stats = port_private->stats; - - while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) == - ETH_OK)) { - -#ifdef DEBUG_MV_ETH - if (pkt_info.byte_cnt != 0) { - printf ("%s: Received %d byte Packet @ 0x%x\n", - __FUNCTION__, pkt_info.byte_cnt, - pkt_info.buf_ptr); - } -#endif - /* Update statistics. Note byte count includes 4 byte CRC count */ - stats->rx_packets++; - stats->rx_bytes += pkt_info.byte_cnt; - - /* - * In case received a packet without first / last bits on OR the error - * summary bit is on, the packets needs to be dropeed. - */ - if (((pkt_info. - cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != - (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) - || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) { - stats->rx_dropped++; - - printf ("Received packet spread on multiple descriptors\n"); - - /* Is this caused by an error ? */ - if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) { - stats->rx_errors++; - } - - /* free these descriptors again without forwarding them to the higher layers */ - pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ - pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ - - if (eth_rx_return_buff - (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { - printf ("Error while returning the RX Desc to Ring\n"); - } else { - DP (printf ("RX Desc returned to Ring\n")); - } - /* /free these descriptors again */ - } else { - -/* !!! call higher layer processing */ -#ifdef DEBUG_MV_ETH - printf ("\nNow send it to upper layer protocols (NetReceive) ...\n"); -#endif - /* let the upper layer handle the packet */ - NetReceive ((uchar *) pkt_info.buf_ptr, - (int) pkt_info.byte_cnt); - -/* **************************************************************** */ -/* free descriptor */ - pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ - pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ - DP (printf - ("RX: pkt_info.buf_ptr = %x\n", - pkt_info.buf_ptr)); - if (eth_rx_return_buff - (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { - printf ("Error while returning the RX Desc to Ring\n"); - } else { - DP (printf ("RX Desc returned to Ring\n")); - } - -/* **************************************************************** */ - - } - } - mv64360_eth_get_stats (dev); /* update statistics */ - return 1; -} - -/********************************************************************** - * mv64360_eth_get_stats - * - * Returns a pointer to the interface statistics. - * - * Input : dev - a pointer to the required interface - * - * Output : a pointer to the interface's statistics - **********************************************************************/ - -static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - - mv64360_eth_update_stat (dev); - - return port_private->stats; -} - - -/********************************************************************** - * mv64360_eth_update_stat - * - * Update the statistics structure in the private data structure - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64360_eth_update_stat (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - struct net_device_stats *stats; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - stats = port_private->stats; - - /* These are false updates */ - stats->rx_packets += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_FRAMES_RECEIVED); - stats->tx_packets += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_FRAMES_SENT); - stats->rx_bytes += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_RECEIVED_LOW); - /* - * Ideally this should be as follows - - * - * stats->rx_bytes += stats->rx_bytes + - * ((unsigned long) ethReadMibCounter (ethernet_private->port_num , - * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32); - * - * But the unsigned long in PowerPC and MIPS are 32bit. So the next read - * is just a dummy read for proper work of the GigE port - */ - (void)eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH); - stats->tx_bytes += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_SENT_LOW); - (void)eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_SENT_HIGH); - stats->rx_errors += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_MAC_RECEIVE_ERROR); - - /* Rx dropped is for received packet with CRC error */ - stats->rx_dropped += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_BAD_CRC_EVENT); - stats->multicast += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_MULTICAST_FRAMES_RECEIVED); - stats->collisions += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_COLLISION) + - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_LATE_COLLISION); - /* detailed rx errors */ - stats->rx_length_errors += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_UNDERSIZE_RECEIVED) - + - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_OVERSIZE_RECEIVED); - /* detailed tx errors */ -} - -#ifndef UPDATE_STATS_BY_SOFTWARE -/********************************************************************** - * mv64360_eth_print_stat - * - * Update the statistics structure in the private data structure - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64360_eth_print_stat (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - struct net_device_stats *stats; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - stats = port_private->stats; - - /* These are false updates */ - printf ("\n### Network statistics: ###\n"); - printf ("--------------------------\n"); - printf (" Packets received: %ld\n", stats->rx_packets); - printf (" Packets send: %ld\n", stats->tx_packets); - printf (" Received bytes: %ld\n", stats->rx_bytes); - printf (" Send bytes: %ld\n", stats->tx_bytes); - if (stats->rx_errors != 0) - printf (" Rx Errors: %ld\n", - stats->rx_errors); - if (stats->rx_dropped != 0) - printf (" Rx dropped (CRC Errors): %ld\n", - stats->rx_dropped); - if (stats->multicast != 0) - printf (" Rx mulicast frames: %ld\n", - stats->multicast); - if (stats->collisions != 0) - printf (" No. of collisions: %ld\n", - stats->collisions); - if (stats->rx_length_errors != 0) - printf (" Rx length errors: %ld\n", - stats->rx_length_errors); -} -#endif - -/************************************************************************** - *network_start - Network Kick Off Routine UBoot - *Inputs : - *Outputs : - **************************************************************************/ - -bool db64360_eth_start (struct eth_device *dev) -{ - return (mv64360_eth_open (dev)); /* calls real open */ -} - -/************************************************************************* -************************************************************************** -************************************************************************** -* The second part is the low level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ -/* - * based on Linux code - * arch/powerpc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - */ - -/******************************************************************************** - * Marvell's Gigabit Ethernet controller low level driver - * - * DESCRIPTION: - * This file introduce low level API to Marvell's Gigabit Ethernet - * controller. This Gigabit Ethernet Controller driver API controls - * 1) Operations (i.e. port init, start, reset etc'). - * 2) Data flow (i.e. port send, receive etc'). - * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO - * struct. - * This struct includes user configuration information as well as - * driver internal data needed for its operations. - * - * Supported Features: - * - This low level driver is OS independent. Allocating memory for - * the descriptor rings and buffers are not within the scope of - * this driver. - * - The user is free from Rx/Tx queue managing. - * - This low level driver introduce functionality API that enable - * the to operate Marvell's Gigabit Ethernet Controller in a - * convenient way. - * - Simple Gigabit Ethernet port operation API. - * - Simple Gigabit Ethernet port data flow API. - * - Data flow and operation API support per queue functionality. - * - Support cached descriptors for better performance. - * - Enable access to all four DRAM banks and internal SRAM memory - * spaces. - * - PHY access and control API. - * - Port control register configuration API. - * - Full control over Unicast and Multicast MAC configurations. - * - * Operation flow: - * - * Initialization phase - * This phase complete the initialization of the ETH_PORT_INFO - * struct. - * User information regarding port configuration has to be set - * prior to calling the port initialization routine. For example, - * the user has to assign the port_phy_addr field which is board - * depended parameter. - * In this phase any port Tx/Rx activity is halted, MIB counters - * are cleared, PHY address is set according to user parameter and - * access to DRAM and internal SRAM memory spaces. - * - * Driver ring initialization - * Allocating memory for the descriptor rings and buffers is not - * within the scope of this driver. Thus, the user is required to - * allocate memory for the descriptors ring and buffers. Those - * memory parameters are used by the Rx and Tx ring initialization - * routines in order to curve the descriptor linked list in a form - * of a ring. - * Note: Pay special attention to alignment issues when using - * cached descriptors/buffers. In this phase the driver store - * information in the ETH_PORT_INFO struct regarding each queue - * ring. - * - * Driver start - * This phase prepares the Ethernet port for Rx and Tx activity. - * It uses the information stored in the ETH_PORT_INFO struct to - * initialize the various port registers. - * - * Data flow: - * All packet references to/from the driver are done using PKT_INFO - * struct. - * This struct is a unified struct used with Rx and Tx operations. - * This way the user is not required to be familiar with neither - * Tx nor Rx descriptors structures. - * The driver's descriptors rings are management by indexes. - * Those indexes controls the ring resources and used to indicate - * a SW resource error: - * 'current' - * This index points to the current available resource for use. For - * example in Rx process this index will point to the descriptor - * that will be passed to the user upon calling the receive routine. - * In Tx process, this index will point to the descriptor - * that will be assigned with the user packet info and transmitted. - * 'used' - * This index points to the descriptor that need to restore its - * resources. For example in Rx process, using the Rx buffer return - * API will attach the buffer returned in packet info to the - * descriptor pointed by 'used'. In Tx process, using the Tx - * descriptor return will merely return the user packet info with - * the command status of the transmitted buffer pointed by the - * 'used' index. Nevertheless, it is essential to use this routine - * to update the 'used' index. - * 'first' - * This index supports Tx Scatter-Gather. It points to the first - * descriptor of a packet assembled of multiple buffers. For example - * when in middle of Such packet we have a Tx resource error the - * 'curr' index get the value of 'first' to indicate that the ring - * returned to its state before trying to transmit this packet. - * - * Receive operation: - * The eth_port_receive API set the packet information struct, - * passed by the caller, with received information from the - * 'current' SDMA descriptor. - * It is the user responsibility to return this resource back - * to the Rx descriptor ring to enable the reuse of this source. - * Return Rx resource is done using the eth_rx_return_buff API. - * - * Transmit operation: - * The eth_port_send API supports Scatter-Gather which enables to - * send a packet spanned over multiple buffers. This means that - * for each packet info structure given by the user and put into - * the Tx descriptors ring, will be transmitted only if the 'LAST' - * bit will be set in the packet info command status field. This - * API also consider restriction regarding buffer alignments and - * sizes. - * The user must return a Tx resource after ensuring the buffer - * has been transmitted to enable the Tx ring indexes to update. - * - * BOARD LAYOUT - * This device is on-board. No jumper diagram is necessary. - * - * EXTERNAL INTERFACE - * - * Prior to calling the initialization routine eth_port_init() the user - * must set the following fields under ETH_PORT_INFO struct: - * port_num User Ethernet port number. - * port_phy_addr User PHY address of Ethernet port. - * port_mac_addr[6] User defined port MAC address. - * port_config User port configuration value. - * port_config_extend User port config extend value. - * port_sdma_config User port SDMA config value. - * port_serial_control User port serial control value. - * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr. - * *port_private User scratch pad for user specific data structures. - * - * This driver introduce a set of default values: - * PORT_CONFIG_VALUE Default port configuration value - * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value - * PORT_SDMA_CONFIG_VALUE Default sdma control value - * PORT_SERIAL_CONTROL_VALUE Default port serial control value - * - * This driver data flow is done using the PKT_INFO struct which is - * a unified struct for Rx and Tx operations: - * byte_cnt Tx/Rx descriptor buffer byte count. - * l4i_chk CPU provided TCP Checksum. For Tx operation only. - * cmd_sts Tx/Rx descriptor command status. - * buf_ptr Tx/Rx descriptor buffer pointer. - * return_info Tx/Rx user resource return information. - * - * - * EXTERNAL SUPPORT REQUIREMENTS - * - * This driver requires the following external support: - * - * D_CACHE_FLUSH_LINE (address, address offset) - * - * This macro applies assembly code to flush and invalidate cache - * line. - * address - address base. - * address offset - address offset - * - * - * CPU_PIPE_FLUSH - * - * This macro applies assembly code to flush the CPU pipeline. - * - *******************************************************************************/ -/* includes */ - -/* defines */ -/* SDMA command macros */ -#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \ - MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue)) - -#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \ - MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\ - (1 << (8 + tx_queue))) - -#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \ -MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue)) - -#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \ -MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue))) - -#define CURR_RFD_GET(p_curr_desc, queue) \ - ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue]) - -#define CURR_RFD_SET(p_curr_desc, queue) \ - (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc)) - -#define USED_RFD_GET(p_used_desc, queue) \ - ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue]) - -#define USED_RFD_SET(p_used_desc, queue)\ -(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc)) - - -#define CURR_TFD_GET(p_curr_desc, queue) \ - ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue]) - -#define CURR_TFD_SET(p_curr_desc, queue) \ - (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc)) - -#define USED_TFD_GET(p_used_desc, queue) \ - ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue]) - -#define USED_TFD_SET(p_used_desc, queue) \ - (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc)) - -#define FIRST_TFD_GET(p_first_desc, queue) \ - ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue]) - -#define FIRST_TFD_SET(p_first_desc, queue) \ - (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc)) - - -/* Macros that save access to desc in order to find next desc pointer */ -#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) - -#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) - -#define LINK_UP_TIMEOUT 100000 -#define PHY_BUSY_TIMEOUT 10000000 - -/* locals */ - -/* PHY routines */ -static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr); -static int ethernet_phy_get (ETH_PORT eth_port_num); - -/* Ethernet Port routines */ -static void eth_set_access_control (ETH_PORT eth_port_num, - ETH_WIN_PARAM * param); -static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble, - ETH_QUEUE queue, int option); -#if 0 /* FIXME */ -static bool eth_port_smc_addr (ETH_PORT eth_port_num, - unsigned char mc_byte, - ETH_QUEUE queue, int option); -static bool eth_port_omc_addr (ETH_PORT eth_port_num, - unsigned char crc8, - ETH_QUEUE queue, int option); -#endif - -static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, - int byte_count); - -void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl); - - -typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK; -u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank) -{ - u32 result = 0; - u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE); - - if (enable & (1 << bank)) - return 0; - if (bank == BANK0) - result = MV_REG_READ (MV64360_CS_0_BASE_ADDR); - if (bank == BANK1) - result = MV_REG_READ (MV64360_CS_1_BASE_ADDR); - if (bank == BANK2) - result = MV_REG_READ (MV64360_CS_2_BASE_ADDR); - if (bank == BANK3) - result = MV_REG_READ (MV64360_CS_3_BASE_ADDR); - result &= 0x0000ffff; - result = result << 16; - return result; -} - -u32 mv_get_dram_bank_size (MEMORY_BANK bank) -{ - u32 result = 0; - u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE); - - if (enable & (1 << bank)) - return 0; - if (bank == BANK0) - result = MV_REG_READ (MV64360_CS_0_SIZE); - if (bank == BANK1) - result = MV_REG_READ (MV64360_CS_1_SIZE); - if (bank == BANK2) - result = MV_REG_READ (MV64360_CS_2_SIZE); - if (bank == BANK3) - result = MV_REG_READ (MV64360_CS_3_SIZE); - result += 1; - result &= 0x0000ffff; - result = result << 16; - return result; -} - -u32 mv_get_internal_sram_base (void) -{ - u32 result; - - result = MV_REG_READ (MV64360_INTEGRATED_SRAM_BASE_ADDR); - result &= 0x0000ffff; - result = result << 16; - return result; -} - -/******************************************************************************* -* eth_port_init - Initialize the Ethernet port driver -* -* DESCRIPTION: -* This function prepares the ethernet port to start its activity: -* 1) Completes the ethernet port driver struct initialization toward port -* start routine. -* 2) Resets the device to a quiescent state in case of warm reboot. -* 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. -* 4) Clean MAC tables. The reset status of those tables is unknown. -* 5) Set PHY address. -* Note: Call this routine prior to eth_port_start routine and after setting -* user values in the user fields of Ethernet port control struct (i.e. -* port_phy_addr). -* -* INPUT: -* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct -* -* OUTPUT: -* See description. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl) -{ - int queue; - ETH_WIN_PARAM win_param; - - p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE; - p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE; - p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE; - p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE; - - p_eth_port_ctrl->port_rx_queue_command = 0; - p_eth_port_ctrl->port_tx_queue_command = 0; - - /* Zero out SW structs */ - for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { - CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); - USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); - p_eth_port_ctrl->rx_resource_err[queue] = false; - } - - for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { - CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - p_eth_port_ctrl->tx_resource_err[queue] = false; - } - - eth_port_reset (p_eth_port_ctrl->port_num); - - /* Set access parameters for DRAM bank 0 */ - win_param.win = ETH_WIN0; /* Use Ethernet window 0 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK0); - win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 1 */ - win_param.win = ETH_WIN1; /* Use Ethernet window 1 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK1); - win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 2 */ - win_param.win = ETH_WIN2; /* Use Ethernet window 2 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK2); - win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 3 */ - win_param.win = ETH_WIN3; /* Use Ethernet window 3 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK3); - win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for Internal SRAM */ - win_param.win = ETH_WIN4; /* Use Ethernet window 0 */ - win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */ - win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0; - win_param.high_addr = 0; - win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */ - win_param.size = MV64360_INTERNAL_SRAM_SIZE; /* Get bank size */ - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - eth_port_init_mac_tables (p_eth_port_ctrl->port_num); - - ethernet_phy_set (p_eth_port_ctrl->port_num, - p_eth_port_ctrl->port_phy_addr); - - return; - -} - -/******************************************************************************* -* eth_port_start - Start the Ethernet port activity. -* -* DESCRIPTION: -* This routine prepares the Ethernet port for Rx and Tx activity: -* 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that -* has been initialized a descriptor's ring (using ether_init_tx_desc_ring -* for Tx and ether_init_rx_desc_ring for Rx) -* 2. Initialize and enable the Ethernet configuration port by writing to -* the port's configuration and command registers. -* 3. Initialize and enable the SDMA by writing to the SDMA's -* configuration and command registers. -* After completing these steps, the ethernet port SDMA can starts to -* perform Rx and Tx activities. -* -* Note: Each Rx and Tx queue descriptor's list must be initialized prior -* to calling this function (use ether_init_tx_desc_ring for Tx queues and -* ether_init_rx_desc_ring for Rx queues). -* -* INPUT: -* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct -* -* OUTPUT: -* Ethernet port is ready to receive and transmit. -* -* RETURN: -* false if the port PHY is not up. -* true otherwise. -* -*******************************************************************************/ -static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl) -{ - int queue; - volatile ETH_TX_DESC *p_tx_curr_desc; - volatile ETH_RX_DESC *p_rx_curr_desc; - unsigned int phy_reg_data; - ETH_PORT eth_port_num = p_eth_port_ctrl->port_num; - - - /* Assignment of Tx CTRP of given queue */ - for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { - CURR_TFD_GET (p_tx_curr_desc, queue); - MV_REG_WRITE ((MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0 - (eth_port_num) - + (4 * queue)), - ((unsigned int) p_tx_curr_desc)); - - } - - /* Assignment of Rx CRDP of given queue */ - for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { - CURR_RFD_GET (p_rx_curr_desc, queue); - MV_REG_WRITE ((MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0 - (eth_port_num) - + (4 * queue)), - ((unsigned int) p_rx_curr_desc)); - - if (p_rx_curr_desc != NULL) - /* Add the assigned Ethernet address to the port's address table */ - eth_port_uc_addr_set (p_eth_port_ctrl->port_num, - p_eth_port_ctrl->port_mac_addr, - queue); - } - - /* Assign port configuration and command. */ - MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num), - p_eth_port_ctrl->port_config); - - MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), - p_eth_port_ctrl->port_config_extend); - - MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - p_eth_port_ctrl->port_serial_control); - - MV_SET_REG_BITS (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - ETH_SERIAL_PORT_ENABLE); - - /* Assign port SDMA configuration */ - MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num), - p_eth_port_ctrl->port_sdma_config); - - MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT - (eth_port_num), 0x3fffffff); - MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG - (eth_port_num), 0x03fffcff); - /* Turn off the port/queue bandwidth limitation */ - MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0); - - /* Enable port Rx. */ - MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num), - p_eth_port_ctrl->port_rx_queue_command); - - /* Check if link is up */ - eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); - - if (!(phy_reg_data & 0x20)) - return false; - - return true; -} - -/******************************************************************************* -* eth_port_uc_addr_set - This function Set the port Unicast address. -* -* DESCRIPTION: -* This function Set the port Ethernet MAC address. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* char * p_addr Address to be set -* ETH_QUEUE queue Rx queue number for this MAC address. -* -* OUTPUT: -* Set MAC address low and high registers. also calls eth_port_uc_addr() -* To set the unicast table with the proper information. -* -* RETURN: -* N/A. -* -*******************************************************************************/ -static void eth_port_uc_addr_set (ETH_PORT eth_port_num, - unsigned char *p_addr, ETH_QUEUE queue) -{ - unsigned int mac_h; - unsigned int mac_l; - - mac_l = (p_addr[4] << 8) | (p_addr[5]); - mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | - (p_addr[2] << 8) | (p_addr[3] << 0); - - MV_REG_WRITE (MV64360_ETH_MAC_ADDR_LOW (eth_port_num), mac_l); - MV_REG_WRITE (MV64360_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h); - - /* Accept frames of this address */ - eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR); - - return; -} - -/******************************************************************************* -* eth_port_uc_addr - This function Set the port unicast address table -* -* DESCRIPTION: -* This function locates the proper entry in the Unicast table for the -* specified MAC nibble and sets its properties according to function -* parameters. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char uc_nibble Unicast MAC Address last nibble. -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* This function add/removes MAC addresses from the port unicast address -* table. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_uc_addr (ETH_PORT eth_port_num, - unsigned char uc_nibble, - ETH_QUEUE queue, int option) -{ - unsigned int unicast_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the Unicast table entry */ - uc_nibble = (0xf & uc_nibble); - tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */ - reg_offset = uc_nibble % 4; /* Entry offset within the above register */ - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified unicast DA table entry */ - unicast_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset)); - - unicast_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset), unicast_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at unicast DA filter table entry */ - unicast_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset)); - - unicast_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset), unicast_reg); - - break; - - default: - return false; - } - return true; -} - -#if 0 /* FIXME */ -/******************************************************************************* -* eth_port_mc_addr - Multicast address settings. -* -* DESCRIPTION: -* This API controls the MV device MAC multicast support. -* The MV device supports multicast using two tables: -* 1) Special Multicast Table for MAC addresses of the form -* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). -* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -* Table entries in the DA-Filter table. -* In this case, the function calls eth_port_smc_addr() routine to set the -* Special Multicast Table. -* 2) Other Multicast Table for multicast of another type. A CRC-8bit -* is used as an index to the Other Multicast Table entries in the -* DA-Filter table. -* In this case, the function calculates the CRC-8bit value and calls -* eth_port_omc_addr() routine to set the Other Multicast Table. -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char *p_addr Unicast MAC Address. -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if add_address_table_entry( ) failed. -* -*******************************************************************************/ -static void eth_port_mc_addr (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue, int option) -{ - unsigned int mac_h; - unsigned int mac_l; - unsigned char crc_result = 0; - int mac_array[48]; - int crc[8]; - int i; - - - if ((p_addr[0] == 0x01) && - (p_addr[1] == 0x00) && - (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) - - eth_port_smc_addr (eth_port_num, p_addr[5], queue, option); - else { - /* Calculate CRC-8 out of the given address */ - mac_h = (p_addr[0] << 8) | (p_addr[1]); - mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) | - (p_addr[4] << 8) | (p_addr[5] << 0); - - for (i = 0; i < 32; i++) - mac_array[i] = (mac_l >> i) & 0x1; - for (i = 32; i < 48; i++) - mac_array[i] = (mac_h >> (i - 32)) & 0x1; - - - crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ - mac_array[39] ^ mac_array[35] ^ mac_array[34] ^ - mac_array[31] ^ mac_array[30] ^ mac_array[28] ^ - mac_array[23] ^ mac_array[21] ^ mac_array[19] ^ - mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ - mac_array[12] ^ mac_array[8] ^ mac_array[7] ^ - mac_array[6] ^ mac_array[0]; - - crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[41] ^ mac_array[39] ^ - mac_array[36] ^ mac_array[34] ^ mac_array[32] ^ - mac_array[30] ^ mac_array[29] ^ mac_array[28] ^ - mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ - mac_array[21] ^ mac_array[20] ^ mac_array[18] ^ - mac_array[17] ^ mac_array[16] ^ mac_array[15] ^ - mac_array[14] ^ mac_array[13] ^ mac_array[12] ^ - mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ - mac_array[0]; - - crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[42] ^ mac_array[39] ^ - mac_array[37] ^ mac_array[34] ^ mac_array[33] ^ - mac_array[29] ^ mac_array[28] ^ mac_array[25] ^ - mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ - mac_array[15] ^ mac_array[13] ^ mac_array[12] ^ - mac_array[10] ^ mac_array[8] ^ mac_array[6] ^ - mac_array[2] ^ mac_array[1] ^ mac_array[0]; - - crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[40] ^ mac_array[38] ^ - mac_array[35] ^ mac_array[34] ^ mac_array[30] ^ - mac_array[29] ^ mac_array[26] ^ mac_array[25] ^ - mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ - mac_array[14] ^ mac_array[13] ^ mac_array[11] ^ - mac_array[9] ^ mac_array[7] ^ mac_array[3] ^ - mac_array[2] ^ mac_array[1]; - - crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ - mac_array[35] ^ mac_array[31] ^ mac_array[30] ^ - mac_array[27] ^ mac_array[26] ^ mac_array[24] ^ - mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ - mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ - mac_array[8] ^ mac_array[4] ^ mac_array[3] ^ - mac_array[2]; - - crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ - mac_array[42] ^ mac_array[40] ^ mac_array[37] ^ - mac_array[36] ^ mac_array[32] ^ mac_array[31] ^ - mac_array[28] ^ mac_array[27] ^ mac_array[25] ^ - mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ - mac_array[15] ^ mac_array[13] ^ mac_array[11] ^ - mac_array[9] ^ mac_array[5] ^ mac_array[4] ^ - mac_array[3]; - - crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ - mac_array[41] ^ mac_array[38] ^ mac_array[37] ^ - mac_array[33] ^ mac_array[32] ^ mac_array[29] ^ - mac_array[28] ^ mac_array[26] ^ mac_array[21] ^ - mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ - mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ - mac_array[6] ^ mac_array[5] ^ mac_array[4]; - - crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ - mac_array[39] ^ mac_array[38] ^ mac_array[34] ^ - mac_array[33] ^ mac_array[30] ^ mac_array[29] ^ - mac_array[27] ^ mac_array[22] ^ mac_array[20] ^ - mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ - mac_array[13] ^ mac_array[11] ^ mac_array[7] ^ - mac_array[6] ^ mac_array[5]; - - for (i = 0; i < 8; i++) - crc_result = crc_result | (crc[i] << i); - - eth_port_omc_addr (eth_port_num, crc_result, queue, option); - } - return; -} - -/******************************************************************************* -* eth_port_smc_addr - Special Multicast address settings. -* -* DESCRIPTION: -* This routine controls the MV device special MAC multicast support. -* The Special Multicast Table for MAC addresses supports MAC of the form -* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). -* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -* Table entries in the DA-Filter table. -* This function set the Special Multicast Table appropriate entry -* according to the argument given. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits). -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_smc_addr (ETH_PORT eth_port_num, - unsigned char mc_byte, - ETH_QUEUE queue, int option) -{ - unsigned int smc_table_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the SMC table entry */ - tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */ - reg_offset = mc_byte % 4; /* Entry offset within the above register */ - queue &= 0x7; - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified Special DA table entry */ - smc_table_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - smc_table_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at specified Special DA table entry */ - smc_table_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - smc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); - break; - - default: - return false; - } - return true; -} - -/******************************************************************************* -* eth_port_omc_addr - Multicast address settings. -* -* DESCRIPTION: -* This routine controls the MV device Other MAC multicast support. -* The Other Multicast Table is used for multicast of another type. -* A CRC-8bit is used as an index to the Other Multicast Table entries -* in the DA-Filter table. -* The function gets the CRC-8bit value from the calling routine and -* set the Other Multicast Table appropriate entry according to the -* CRC-8 argument given. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_omc_addr (ETH_PORT eth_port_num, - unsigned char crc8, - ETH_QUEUE queue, int option) -{ - unsigned int omc_table_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the OMC table entry */ - tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ - reg_offset = crc8 % 4; /* Entry offset within the above register */ - queue &= 0x7; - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified Other DA table entry */ - omc_table_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - omc_table_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at specified Other DA table entry */ - omc_table_reg = - MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - omc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); - break; - - default: - return false; - } - return true; -} -#endif - -/******************************************************************************* -* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables -* -* DESCRIPTION: -* Go through all the DA filter tables (Unicast, Special Multicast & Other -* Multicast) and set each entry to 0. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* Multicast and Unicast packets are rejected. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void eth_port_init_mac_tables (ETH_PORT eth_port_num) -{ - int table_index; - - /* Clear DA filter unicast table (Ex_dFUT) */ - for (table_index = 0; table_index <= 0xC; table_index += 4) - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) + table_index), 0); - - for (table_index = 0; table_index <= 0xFC; table_index += 4) { - /* Clear DA filter special multicast table (Ex_dFSMT) */ - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); - /* Clear DA filter other multicast table (Ex_dFOMT) */ - MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); - } -} - -/******************************************************************************* -* eth_clear_mib_counters - Clear all MIB counters -* -* DESCRIPTION: -* This function clears all MIB counters of a specific ethernet port. -* A read from the MIB counter will reset the counter. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* After reading all MIB counters, the counters resets. -* -* RETURN: -* MIB counter value. -* -*******************************************************************************/ -static void eth_clear_mib_counters (ETH_PORT eth_port_num) -{ - int i; - - /* Perform dummy reads from MIB counters */ - for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; - i += 4) { - (void)MV_REG_READ ((MV64360_ETH_MIB_COUNTERS_BASE - (eth_port_num) + i)); - } - - return; -} - -/******************************************************************************* -* eth_read_mib_counter - Read a MIB counter -* -* DESCRIPTION: -* This function reads a MIB counter of a specific ethernet port. -* NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the -* following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH -* register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and -* ETH_MIB_GOOD_OCTETS_SENT_HIGH -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros). -* -* OUTPUT: -* After reading the MIB counter, the counter resets. -* -* RETURN: -* MIB counter value. -* -*******************************************************************************/ -unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, - unsigned int mib_offset) -{ - return (MV_REG_READ (MV64360_ETH_MIB_COUNTERS_BASE (eth_port_num) - + mib_offset)); -} - -/******************************************************************************* -* ethernet_phy_set - Set the ethernet port PHY address. -* -* DESCRIPTION: -* This routine set the ethernet port PHY address according to given -* parameter. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* Set PHY Address Register with given PHY address parameter. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr) -{ - unsigned int reg_data; - - reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG); - - reg_data &= ~(0x1F << (5 * eth_port_num)); - reg_data |= (phy_addr << (5 * eth_port_num)); - - MV_REG_WRITE (MV64360_ETH_PHY_ADDR_REG, reg_data); - - return; -} - -/******************************************************************************* - * ethernet_phy_get - Get the ethernet port PHY address. - * - * DESCRIPTION: - * This routine returns the given ethernet port PHY address. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * None. - * - * RETURN: - * PHY address. - * - *******************************************************************************/ -static int ethernet_phy_get (ETH_PORT eth_port_num) -{ - unsigned int reg_data; - - reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG); - - return ((reg_data >> (5 * eth_port_num)) & 0x1f); -} - -/******************************************************************************* - * ethernet_phy_reset - Reset Ethernet port PHY. - * - * DESCRIPTION: - * This routine utilize the SMI interface to reset the ethernet port PHY. - * The routine waits until the link is up again or link up is timeout. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * The ethernet port PHY renew its link. - * - * RETURN: - * None. - * -*******************************************************************************/ -static bool ethernet_phy_reset (ETH_PORT eth_port_num) -{ - unsigned int time_out = 50; - unsigned int phy_reg_data; - - /* Reset the PHY */ - eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data); - phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */ - eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data); - - /* Poll on the PHY LINK */ - do { - eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); - - if (time_out-- == 0) - return false; - } - while (!(phy_reg_data & 0x20)); - - return true; -} - -/******************************************************************************* - * eth_port_reset - Reset Ethernet port - * - * DESCRIPTION: - * This routine resets the chip by aborting any SDMA engine activity and - * clearing the MIB counters. The Receiver and the Transmit unit are in - * idle state after this command is performed and the port is disabled. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * Channel activity is halted. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_port_reset (ETH_PORT eth_port_num) -{ - unsigned int reg_data; - - /* Stop Tx port activity. Check port Tx activity. */ - reg_data = - MV_REG_READ (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num)); - - if (reg_data & 0xFF) { - /* Issue stop command for active channels only */ - MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num), (reg_data << 8)); - - /* Wait for all Tx activity to terminate. */ - do { - /* Check port cause register that all Tx queues are stopped */ - reg_data = - MV_REG_READ - (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num)); - } - while (reg_data & 0xFF); - } - - /* Stop Rx port activity. Check port Rx activity. */ - reg_data = - MV_REG_READ (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num)); - - if (reg_data & 0xFF) { - /* Issue stop command for active channels only */ - MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num), (reg_data << 8)); - - /* Wait for all Rx activity to terminate. */ - do { - /* Check port cause register that all Rx queues are stopped */ - reg_data = - MV_REG_READ - (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num)); - } - while (reg_data & 0xFF); - } - - - /* Clear all MIB counters */ - eth_clear_mib_counters (eth_port_num); - - /* Reset the Enable bit in the Configuration Register */ - reg_data = - MV_REG_READ (MV64360_ETH_PORT_SERIAL_CONTROL_REG - (eth_port_num)); - reg_data &= ~ETH_SERIAL_PORT_ENABLE; - MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - reg_data); - - return; -} - -#if 0 /* Not needed here */ -/******************************************************************************* - * ethernet_set_config_reg - Set specified bits in configuration register. - * - * DESCRIPTION: - * This function sets specified bits in the given ethernet - * configuration register. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int value 32 bit value. - * - * OUTPUT: - * The set bits in the value parameter are set in the configuration - * register. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void ethernet_set_config_reg (ETH_PORT eth_port_num, - unsigned int value) -{ - unsigned int eth_config_reg; - - eth_config_reg = - MV_REG_READ (MV64360_ETH_PORT_CONFIG_REG (eth_port_num)); - eth_config_reg |= value; - MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num), - eth_config_reg); - - return; -} -#endif - -#if 0 /* FIXME */ -/******************************************************************************* - * ethernet_reset_config_reg - Reset specified bits in configuration register. - * - * DESCRIPTION: - * This function resets specified bits in the given Ethernet - * configuration register. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int value 32 bit value. - * - * OUTPUT: - * The set bits in the value parameter are reset in the configuration - * register. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void ethernet_reset_config_reg (ETH_PORT eth_port_num, - unsigned int value) -{ - unsigned int eth_config_reg; - - eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG - (eth_port_num)); - eth_config_reg &= ~value; - MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), - eth_config_reg); - - return; -} -#endif - -#if 0 /* Not needed here */ -/******************************************************************************* - * ethernet_get_config_reg - Get the port configuration register - * - * DESCRIPTION: - * This function returns the configuration register value of the given - * ethernet port. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * None. - * - * RETURN: - * Port configuration register value. - * - *******************************************************************************/ -static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num) -{ - unsigned int eth_config_reg; - - eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG - (eth_port_num)); - return eth_config_reg; -} - -#endif - -/******************************************************************************* - * eth_port_read_smi_reg - Read PHY registers - * - * DESCRIPTION: - * This routine utilize the SMI interface to interact with the PHY in - * order to perform PHY register read. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int phy_reg PHY register address offset. - * unsigned int *value Register value buffer. - * - * OUTPUT: - * Write the value of a specified PHY register into given buffer. - * - * RETURN: - * false if the PHY is busy or read data is not in valid state. - * true otherwise. - * - *******************************************************************************/ -static bool eth_port_read_smi_reg (ETH_PORT eth_port_num, - unsigned int phy_reg, unsigned int *value) -{ - unsigned int reg_value; - unsigned int time_out = PHY_BUSY_TIMEOUT; - int phy_addr; - - phy_addr = ethernet_phy_get (eth_port_num); -/* printf(" Phy-Port %d has addess %d \n",eth_port_num, phy_addr );*/ - - /* first check that it is not busy */ - do { - reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while (reg_value & ETH_SMI_BUSY); - - /* not busy */ - - MV_REG_WRITE (MV64360_ETH_SMI_REG, - (phy_addr << 16) | (phy_reg << 21) | - ETH_SMI_OPCODE_READ); - - time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */ - - do { - reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */ - - /* Wait for the data to update in the SMI register */ -#define PHY_UPDATE_TIMEOUT 10000 - for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++); - - reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); - - *value = reg_value & 0xffff; - - return true; -} - -/******************************************************************************* - * eth_port_write_smi_reg - Write to PHY registers - * - * DESCRIPTION: - * This routine utilize the SMI interface to interact with the PHY in - * order to perform writes to PHY registers. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int phy_reg PHY register address offset. - * unsigned int value Register value. - * - * OUTPUT: - * Write the given value to the specified PHY register. - * - * RETURN: - * false if the PHY is busy. - * true otherwise. - * - *******************************************************************************/ -static bool eth_port_write_smi_reg (ETH_PORT eth_port_num, - unsigned int phy_reg, unsigned int value) -{ - unsigned int reg_value; - unsigned int time_out = PHY_BUSY_TIMEOUT; - int phy_addr; - - phy_addr = ethernet_phy_get (eth_port_num); - - /* first check that it is not busy */ - do { - reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while (reg_value & ETH_SMI_BUSY); - - /* not busy */ - MV_REG_WRITE (MV64360_ETH_SMI_REG, - (phy_addr << 16) | (phy_reg << 21) | - ETH_SMI_OPCODE_WRITE | (value & 0xffff)); - return true; -} - -/******************************************************************************* - * eth_set_access_control - Config address decode parameters for Ethernet unit - * - * DESCRIPTION: - * This function configures the address decode parameters for the Gigabit - * Ethernet Controller according the given parameters struct. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * ETH_WIN_PARAM *param Address decode parameter struct. - * - * OUTPUT: - * An access window is opened using the given access parameters. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_set_access_control (ETH_PORT eth_port_num, - ETH_WIN_PARAM * param) -{ - unsigned int access_prot_reg; - - /* Set access control register */ - access_prot_reg = MV_REG_READ (MV64360_ETH_ACCESS_PROTECTION_REG - (eth_port_num)); - access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */ - access_prot_reg |= (param->access_ctrl << (param->win * 2)); - MV_REG_WRITE (MV64360_ETH_ACCESS_PROTECTION_REG (eth_port_num), - access_prot_reg); - - /* Set window Size reg (SR) */ - MV_REG_WRITE ((MV64360_ETH_SIZE_REG_0 + - (ETH_SIZE_REG_GAP * param->win)), - (((param->size / 0x10000) - 1) << 16)); - - /* Set window Base address reg (BA) */ - MV_REG_WRITE ((MV64360_ETH_BAR_0 + (ETH_BAR_GAP * param->win)), - (param->target | param->attributes | param->base_addr)); - /* High address remap reg (HARR) */ - if (param->win < 4) - MV_REG_WRITE ((MV64360_ETH_HIGH_ADDR_REMAP_REG_0 + - (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)), - param->high_addr); - - /* Base address enable reg (BARER) */ - if (param->enable == 1) - MV_RESET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG, - (1 << param->win)); - else - MV_SET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG, - (1 << param->win)); -} - -/******************************************************************************* - * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. - * - * DESCRIPTION: - * This function prepares a Rx chained list of descriptors and packet - * buffers in a form of a ring. The routine must be called after port - * initialization routine and before port start routine. - * The Ethernet SDMA engine uses CPU bus addresses to access the various - * devices in the system (i.e. DRAM). This function uses the ethernet - * struct 'virtual to physical' routine (set by the user) to set the ring - * with physical addresses. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * int rx_desc_num Number of Rx descriptors - * int rx_buff_size Size of Rx buffer - * unsigned int rx_desc_base_addr Rx descriptors memory area base addr. - * unsigned int rx_buff_base_addr Rx buffer memory area base addr. - * - * OUTPUT: - * The routine updates the Ethernet port control struct with information - * regarding the Rx descriptors and buffers. - * - * RETURN: - * false if the given descriptors memory area is not aligned according to - * Ethernet SDMA specifications. - * true otherwise. - * - *******************************************************************************/ -static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE rx_queue, - int rx_desc_num, - int rx_buff_size, - unsigned int rx_desc_base_addr, - unsigned int rx_buff_base_addr) -{ - ETH_RX_DESC *p_rx_desc; - ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */ - unsigned int buffer_addr; - int ix; /* a counter */ - - - p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr; - p_rx_prev_desc = p_rx_desc; - buffer_addr = rx_buff_base_addr; - - /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ - if (rx_buff_base_addr & 0xF) - return false; - - /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */ - if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE)) - return false; - - /* Rx buffers must be 64-bit aligned. */ - if ((rx_buff_base_addr + rx_buff_size) & 0x7) - return false; - - /* initialize the Rx descriptors ring */ - for (ix = 0; ix < rx_desc_num; ix++) { - p_rx_desc->buf_size = rx_buff_size; - p_rx_desc->byte_cnt = 0x0000; - p_rx_desc->cmd_sts = - ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; - p_rx_desc->next_desc_ptr = - ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE; - p_rx_desc->buf_ptr = buffer_addr; - p_rx_desc->return_info = 0x00000000; - D_CACHE_FLUSH_LINE (p_rx_desc, 0); - buffer_addr += rx_buff_size; - p_rx_prev_desc = p_rx_desc; - p_rx_desc = (ETH_RX_DESC *) - ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE); - } - - /* Closing Rx descriptors ring */ - p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr); - D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0); - - /* Save Rx desc pointer to driver struct. */ - CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); - USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); - - p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] = - (ETH_RX_DESC *) rx_desc_base_addr; - p_eth_port_ctrl->rx_desc_area_size[rx_queue] = - rx_desc_num * RX_DESC_ALIGNED_SIZE; - - p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue); - - return true; -} - -/******************************************************************************* - * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. - * - * DESCRIPTION: - * This function prepares a Tx chained list of descriptors and packet - * buffers in a form of a ring. The routine must be called after port - * initialization routine and before port start routine. - * The Ethernet SDMA engine uses CPU bus addresses to access the various - * devices in the system (i.e. DRAM). This function uses the ethernet - * struct 'virtual to physical' routine (set by the user) to set the ring - * with physical addresses. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * int tx_desc_num Number of Tx descriptors - * int tx_buff_size Size of Tx buffer - * unsigned int tx_desc_base_addr Tx descriptors memory area base addr. - * unsigned int tx_buff_base_addr Tx buffer memory area base addr. - * - * OUTPUT: - * The routine updates the Ethernet port control struct with information - * regarding the Tx descriptors and buffers. - * - * RETURN: - * false if the given descriptors memory area is not aligned according to - * Ethernet SDMA specifications. - * true otherwise. - * - *******************************************************************************/ -static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE tx_queue, - int tx_desc_num, - int tx_buff_size, - unsigned int tx_desc_base_addr, - unsigned int tx_buff_base_addr) -{ - - ETH_TX_DESC *p_tx_desc; - ETH_TX_DESC *p_tx_prev_desc; - unsigned int buffer_addr; - int ix; /* a counter */ - - - /* save the first desc pointer to link with the last descriptor */ - p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr; - p_tx_prev_desc = p_tx_desc; - buffer_addr = tx_buff_base_addr; - - /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ - if (tx_buff_base_addr & 0xF) - return false; - - /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */ - if ((tx_buff_size > TX_BUFFER_MAX_SIZE) - || (tx_buff_size < TX_BUFFER_MIN_SIZE)) - return false; - - /* Initialize the Tx descriptors ring */ - for (ix = 0; ix < tx_desc_num; ix++) { - p_tx_desc->byte_cnt = 0x0000; - p_tx_desc->l4i_chk = 0x0000; - p_tx_desc->cmd_sts = 0x00000000; - p_tx_desc->next_desc_ptr = - ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE; - - p_tx_desc->buf_ptr = buffer_addr; - p_tx_desc->return_info = 0x00000000; - D_CACHE_FLUSH_LINE (p_tx_desc, 0); - buffer_addr += tx_buff_size; - p_tx_prev_desc = p_tx_desc; - p_tx_desc = (ETH_TX_DESC *) - ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE); - - } - /* Closing Tx descriptors ring */ - p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr; - D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0); - /* Set Tx desc pointer in driver struct. */ - CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); - USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); - - /* Init Tx ring base and size parameters */ - p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] = - (ETH_TX_DESC *) tx_desc_base_addr; - p_eth_port_ctrl->tx_desc_area_size[tx_queue] = - (tx_desc_num * TX_DESC_ALIGNED_SIZE); - - /* Add the queue to the list of Tx queues of this port */ - p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue); - - return true; -} - -/******************************************************************************* - * eth_port_send - Send an Ethernet packet - * - * DESCRIPTION: - * This routine send a given packet described by p_pktinfo parameter. It - * supports transmitting of a packet spaned over multiple buffers. The - * routine updates 'curr' and 'first' indexes according to the packet - * segment passed to the routine. In case the packet segment is first, - * the 'first' index is update. In any case, the 'curr' index is updated. - * If the routine get into Tx resource error it assigns 'curr' index as - * 'first'. This way the function can abort Tx process of multiple - * descriptors per packet. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Tx ring 'curr' and 'first' indexes are updated. - * - * RETURN: - * ETH_QUEUE_FULL in case of Tx resource error. - * ETH_ERROR in case the routine can not access Tx desc ring. - * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_TX_DESC *p_tx_desc_first; - volatile ETH_TX_DESC *p_tx_desc_curr; - volatile ETH_TX_DESC *p_tx_next_desc_curr; - volatile ETH_TX_DESC *p_tx_desc_used; - unsigned int command_status; - - /* Do not process Tx ring in case of Tx ring resource error */ - if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) - return ETH_QUEUE_FULL; - - /* Get the Tx Desc ring indexes */ - CURR_TFD_GET (p_tx_desc_curr, tx_queue); - USED_TFD_GET (p_tx_desc_used, tx_queue); - - if (p_tx_desc_curr == NULL) - return ETH_ERROR; - - /* The following parameters are used to save readings from memory */ - p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue); - command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC; - - if (command_status & (ETH_TX_FIRST_DESC)) { - /* Update first desc */ - FIRST_TFD_SET (p_tx_desc_curr, tx_queue); - p_tx_desc_first = p_tx_desc_curr; - } else { - FIRST_TFD_GET (p_tx_desc_first, tx_queue); - command_status |= ETH_BUFFER_OWNED_BY_DMA; - } - - /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */ - /* boundary. We use the memory allocated for Tx descriptor. This memory */ - /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */ - if (p_pkt_info->byte_cnt <= 8) { - printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */ - return ETH_ERROR; - - p_tx_desc_curr->buf_ptr = - (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC; - eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr, - p_pkt_info->byte_cnt); - } else - p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr; - - p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt; - p_tx_desc_curr->return_info = p_pkt_info->return_info; - - if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) { - /* Set last desc with DMA ownership and interrupt enable. */ - p_tx_desc_curr->cmd_sts = command_status | - ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT; - - if (p_tx_desc_curr != p_tx_desc_first) - p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA; - - /* Flush CPU pipe */ - - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0); - CPU_PIPE_FLUSH; - - /* Apply send command */ - ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num); - - /* Finish Tx packet. Update first desc in case of Tx resource error */ - p_tx_desc_first = p_tx_next_desc_curr; - FIRST_TFD_SET (p_tx_desc_first, tx_queue); - - } else { - p_tx_desc_curr->cmd_sts = command_status; - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); - } - - /* Check for ring index overlap in the Tx desc ring */ - if (p_tx_next_desc_curr == p_tx_desc_used) { - /* Update the current descriptor */ - CURR_TFD_SET (p_tx_desc_first, tx_queue); - - p_eth_port_ctrl->tx_resource_err[tx_queue] = true; - return ETH_QUEUE_LAST_RESOURCE; - } else { - /* Update the current descriptor */ - CURR_TFD_SET (p_tx_next_desc_curr, tx_queue); - return ETH_OK; - } -} - -/******************************************************************************* - * eth_tx_return_desc - Free all used Tx descriptors - * - * DESCRIPTION: - * This routine returns the transmitted packet information to the caller. - * It uses the 'first' index to support Tx desc return in case a transmit - * of a packet spanned over multiple buffer still in process. - * In case the Tx queue was in "resource error" condition, where there are - * no available Tx resources, the function resets the resource error flag. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Tx ring 'first' and 'used' indexes are updated. - * - * RETURN: - * ETH_ERROR in case the routine can not access Tx desc ring. - * ETH_RETRY in case there is transmission in process. - * ETH_END_OF_JOB if the routine has nothing to release. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO * - p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_TX_DESC *p_tx_desc_used = NULL; - volatile ETH_TX_DESC *p_tx_desc_first = NULL; - unsigned int command_status; - - - /* Get the Tx Desc ring indexes */ - USED_TFD_GET (p_tx_desc_used, tx_queue); - FIRST_TFD_GET (p_tx_desc_first, tx_queue); - - - /* Sanity check */ - if (p_tx_desc_used == NULL) - return ETH_ERROR; - - command_status = p_tx_desc_used->cmd_sts; - - /* Still transmitting... */ - if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - return ETH_RETRY; - } - - /* Stop release. About to overlap the current available Tx descriptor */ - if ((p_tx_desc_used == p_tx_desc_first) && - (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) { - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - return ETH_END_OF_JOB; - } - - /* Pass the packet information to the caller */ - p_pkt_info->cmd_sts = command_status; - p_pkt_info->return_info = p_tx_desc_used->return_info; - p_tx_desc_used->return_info = 0; - - /* Update the next descriptor to release. */ - USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue); - - /* Any Tx return cancels the Tx resource error status */ - if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) - p_eth_port_ctrl->tx_resource_err[tx_queue] = false; - - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - - return ETH_OK; - -} - -/******************************************************************************* - * eth_port_receive - Get received information from Rx ring. - * - * DESCRIPTION: - * This routine returns the received data to the caller. There is no - * data copying during routine operation. All information is returned - * using pointer to packet information struct passed from the caller. - * If the routine exhausts Rx ring resources then the resource error flag - * is set. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Rx ring current and used indexes are updated. - * - * RETURN: - * ETH_ERROR in case the routine can not access Rx desc ring. - * ETH_QUEUE_FULL if Rx ring resources are exhausted. - * ETH_END_OF_JOB if there is no received data. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_RX_DESC *p_rx_curr_desc; - volatile ETH_RX_DESC *p_rx_next_curr_desc; - volatile ETH_RX_DESC *p_rx_used_desc; - unsigned int command_status; - - /* Do not process Rx ring in case of Rx ring resource error */ - if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) { - printf ("\nRx Queue is full ...\n"); - return ETH_QUEUE_FULL; - } - - /* Get the Rx Desc ring 'curr and 'used' indexes */ - CURR_RFD_GET (p_rx_curr_desc, rx_queue); - USED_RFD_GET (p_rx_used_desc, rx_queue); - - /* Sanity check */ - if (p_rx_curr_desc == NULL) - return ETH_ERROR; - - /* The following parameters are used to save readings from memory */ - p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue); - command_status = p_rx_curr_desc->cmd_sts; - - /* Nothing to receive... */ - if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { -/* DP(printf("Rx: command_status: %08x\n", command_status)); */ - D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); -/* DP(printf("\nETH_END_OF_JOB ...\n"));*/ - return ETH_END_OF_JOB; - } - - p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET; - p_pkt_info->cmd_sts = command_status; - p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET; - p_pkt_info->return_info = p_rx_curr_desc->return_info; - p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */ - - /* Clean the return info field to indicate that the packet has been */ - /* moved to the upper layers */ - p_rx_curr_desc->return_info = 0; - - /* Update 'curr' in data structure */ - CURR_RFD_SET (p_rx_next_curr_desc, rx_queue); - - /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */ - if (p_rx_next_curr_desc == p_rx_used_desc) - p_eth_port_ctrl->rx_resource_err[rx_queue] = true; - - D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); - CPU_PIPE_FLUSH; - return ETH_OK; -} - -/******************************************************************************* - * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. - * - * DESCRIPTION: - * This routine returns a Rx buffer back to the Rx ring. It retrieves the - * next 'used' descriptor and attached the returned buffer to it. - * In case the Rx ring was in "resource error" condition, where there are - * no available Rx resources, the function resets the resource error flag. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * PKT_INFO *p_pkt_info Information on the returned buffer. - * - * OUTPUT: - * New available Rx resource in Rx descriptor ring. - * - * RETURN: - * ETH_ERROR in case the routine can not access Rx desc ring. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO * - p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */ - - /* Get 'used' Rx descriptor */ - USED_RFD_GET (p_used_rx_desc, rx_queue); - - /* Sanity check */ - if (p_used_rx_desc == NULL) - return ETH_ERROR; - - p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; - p_used_rx_desc->return_info = p_pkt_info->return_info; - p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt; - p_used_rx_desc->buf_size = MV64360_RX_BUFFER_SIZE; /* Reset Buffer size */ - - /* Flush the write pipe */ - CPU_PIPE_FLUSH; - - /* Return the descriptor to DMA ownership */ - p_used_rx_desc->cmd_sts = - ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; - - /* Flush descriptor and CPU pipe */ - D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0); - CPU_PIPE_FLUSH; - - /* Move the used descriptor pointer to the next descriptor */ - USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue); - - /* Any Rx return cancels the Rx resource error status */ - if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) - p_eth_port_ctrl->rx_resource_err[rx_queue] = false; - - return ETH_OK; -} - -/******************************************************************************* - * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path - * - * DESCRIPTION: - * This routine sets the RX coalescing interrupt mechanism parameter. - * This parameter is a timeout counter, that counts in 64 t_clk - * chunks ; that when timeout event occurs a maskable interrupt - * occurs. - * The parameter is calculated using the tClk of the MV-643xx chip - * , and the required delay of the interrupt in usec. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet port number - * unsigned int t_clk t_clk of the MV-643xx chip in HZ units - * unsigned int delay Delay in usec - * - * OUTPUT: - * Interrupt coalescing mechanism value is set in MV-643xx chip. - * - * RETURN: - * The interrupt coalescing value set in the gigE port. - * - *******************************************************************************/ -#if 0 /* FIXME */ -static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num, - unsigned int t_clk, - unsigned int delay) -{ - unsigned int coal; - - coal = ((t_clk / 1000000) * delay) / 64; - /* Set RX Coalescing mechanism */ - MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num), - ((coal & 0x3fff) << 8) | - (MV_REG_READ - (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num)) - & 0xffc000ff)); - return coal; -} - -#endif -/******************************************************************************* - * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path - * - * DESCRIPTION: - * This routine sets the TX coalescing interrupt mechanism parameter. - * This parameter is a timeout counter, that counts in 64 t_clk - * chunks ; that when timeout event occurs a maskable interrupt - * occurs. - * The parameter is calculated using the t_cLK frequency of the - * MV-643xx chip and the required delay in the interrupt in uSec - * - * INPUT: - * ETH_PORT eth_port_num Ethernet port number - * unsigned int t_clk t_clk of the MV-643xx chip in HZ units - * unsigned int delay Delay in uSeconds - * - * OUTPUT: - * Interrupt coalescing mechanism value is set in MV-643xx chip. - * - * RETURN: - * The interrupt coalescing value set in the gigE port. - * - *******************************************************************************/ -#if 0 /* FIXME */ -static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num, - unsigned int t_clk, - unsigned int delay) -{ - unsigned int coal; - - coal = ((t_clk / 1000000) * delay) / 64; - /* Set TX Coalescing mechanism */ - MV_REG_WRITE (MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num), - coal << 4); - return coal; -} -#endif - -/******************************************************************************* - * eth_b_copy - Copy bytes from source to destination - * - * DESCRIPTION: - * This function supports the eight bytes limitation on Tx buffer size. - * The routine will zero eight bytes starting from the destination address - * followed by copying bytes from the source address to the destination. - * - * INPUT: - * unsigned int src_addr 32 bit source address. - * unsigned int dst_addr 32 bit destination address. - * int byte_count Number of bytes to copy. - * - * OUTPUT: - * See description. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, - int byte_count) -{ - /* Zero the dst_addr area */ - *(unsigned int *) dst_addr = 0x0; - - while (byte_count != 0) { - *(char *) dst_addr = *(char *) src_addr; - dst_addr++; - src_addr++; - byte_count--; - } -} diff --git a/board/esd/cpci750/mv_eth.h b/board/esd/cpci750/mv_eth.h deleted file mode 100644 index c04fb58..0000000 --- a/board/esd/cpci750/mv_eth.h +++ /dev/null @@ -1,819 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus <ingo.assmus@keymile.com> - * - * based on - Driver for MV64360X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mv_eth.h - header file for the polled mode GT ethernet driver - */ - -#ifndef __DB64360_ETH_H__ -#define __DB64360_ETH_H__ - -#include <asm/types.h> -#include <asm/io.h> -#include <asm/byteorder.h> -#include <common.h> -#include <net.h> -#include "mv_regs.h" -#include <asm/errno.h> - - -/************************************************************************* -************************************************************************** -************************************************************************** -* The first part is the high level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ -/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */ -#ifndef MAX_SKB_FRAGS -#define MAX_SKB_FRAGS 0 -#endif - -/* Port attributes */ -/*#define MAX_RX_QUEUE_NUM 8*/ -/*#define MAX_TX_QUEUE_NUM 8*/ -#define MAX_RX_QUEUE_NUM 1 -#define MAX_TX_QUEUE_NUM 1 - - -/* Use one TX queue and one RX queue */ -#define MV64360_TX_QUEUE_NUM 1 -#define MV64360_RX_QUEUE_NUM 1 - -/* - * Number of RX / TX descriptors on RX / TX rings. - * Note that allocating RX descriptors is done by allocating the RX - * ring AND a preallocated RX buffers (skb's) for each descriptor. - * The TX descriptors only allocates the TX descriptors ring, - * with no pre allocated TX buffers (skb's are allocated by higher layers. - */ - -/* Default TX ring size is 10 descriptors */ -#ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE -#define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE -#else -#define MV64360_TX_QUEUE_SIZE 4 -#endif - -/* Default RX ring size is 4 descriptors */ -#ifdef CONFIG_MV64360_ETH_RXQUEUE_SIZE -#define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE -#else -#define MV64360_RX_QUEUE_SIZE 4 -#endif - -#ifdef CONFIG_RX_BUFFER_SIZE -#define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE -#else -#define MV64360_RX_BUFFER_SIZE 1600 -#endif - -#ifdef CONFIG_TX_BUFFER_SIZE -#define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE -#else -#define MV64360_TX_BUFFER_SIZE 1600 -#endif - - -/* - * Network device statistics. Akin to the 2.0 ether stats but - * with byte counters. - */ - -struct net_device_stats -{ - unsigned long rx_packets; /* total packets received */ - unsigned long tx_packets; /* total packets transmitted */ - unsigned long rx_bytes; /* total bytes received */ - unsigned long tx_bytes; /* total bytes transmitted */ - unsigned long rx_errors; /* bad packets received */ - unsigned long tx_errors; /* packet transmit problems */ - unsigned long rx_dropped; /* no space in linux buffers */ - unsigned long tx_dropped; /* no space available in linux */ - unsigned long multicast; /* multicast packets received */ - unsigned long collisions; - - /* detailed rx_errors: */ - unsigned long rx_length_errors; - unsigned long rx_over_errors; /* receiver ring buff overflow */ - unsigned long rx_crc_errors; /* recved pkt with crc error */ - unsigned long rx_frame_errors; /* recv'd frame alignment error */ - unsigned long rx_fifo_errors; /* recv'r fifo overrun */ - unsigned long rx_missed_errors; /* receiver missed packet */ - - /* detailed tx_errors */ - unsigned long tx_aborted_errors; - unsigned long tx_carrier_errors; - unsigned long tx_fifo_errors; - unsigned long tx_heartbeat_errors; - unsigned long tx_window_errors; - - /* for cslip etc */ - unsigned long rx_compressed; - unsigned long tx_compressed; -}; - - -/* Private data structure used for ethernet device */ -struct mv64360_eth_priv { - unsigned int port_num; - struct net_device_stats *stats; - -/* to buffer area aligned */ - char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */ - char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */ - - /* Size of Tx Ring per queue */ - unsigned int tx_ring_size [MAX_TX_QUEUE_NUM]; - - - /* Size of Rx Ring per queue */ - unsigned int rx_ring_size [MAX_RX_QUEUE_NUM]; - - /* Magic Number for Ethernet running */ - unsigned int eth_running; - -}; - - -int mv64360_eth_init (struct eth_device *dev); -int mv64360_eth_stop (struct eth_device *dev); -int mv64360_eth_start_xmit(struct eth_device *dev, void *packet, int length); -int mv64360_eth_open (struct eth_device *dev); - - -/************************************************************************* -************************************************************************** -************************************************************************** -* The second part is the low level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ - - -/******************************************************************************** - * Header File for : MV-643xx network interface header - * - * DESCRIPTION: - * This header file contains macros typedefs and function declaration for - * the Marvell Gig Bit Ethernet Controller. - * - * DEPENDENCIES: - * None. - * - *******************************************************************************/ - - -#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY -#ifdef CONFIG_MV64360_SRAM_CACHEABLE -/* In case SRAM is cacheable but not cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) \ -{ \ - __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ -} -#else -/* In case SRAM is cache coherent or non-cacheable */ -#define D_CACHE_FLUSH_LINE(addr, offset) ; -#endif -#else -#ifdef CONFIG_NOT_COHERENT_CACHE -/* In case of descriptors on DDR but not cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) \ -{ \ - __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ -} -#else -/* In case of descriptors on DDR and cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) ; -#endif /* CONFIG_NOT_COHERENT_CACHE */ -#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */ - - -#define CPU_PIPE_FLUSH \ -{ \ - __asm__ __volatile__ ("eieio"); \ -} - - -/* defines */ - -/* Default port configuration value */ -#define PORT_CONFIG_VALUE \ - ETH_UNICAST_NORMAL_MODE | \ - ETH_DEFAULT_RX_QUEUE_0 | \ - ETH_DEFAULT_RX_ARP_QUEUE_0 | \ - ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \ - ETH_RECEIVE_BC_IF_IP | \ - ETH_RECEIVE_BC_IF_ARP | \ - ETH_CAPTURE_TCP_FRAMES_DIS | \ - ETH_CAPTURE_UDP_FRAMES_DIS | \ - ETH_DEFAULT_RX_TCP_QUEUE_0 | \ - ETH_DEFAULT_RX_UDP_QUEUE_0 | \ - ETH_DEFAULT_RX_BPDU_QUEUE_0 - -/* Default port extend configuration value */ -#define PORT_CONFIG_EXTEND_VALUE \ - ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \ - ETH_PARTITION_DISABLE - - -/* Default sdma control value */ -#ifdef CONFIG_NOT_COHERENT_CACHE -#define PORT_SDMA_CONFIG_VALUE \ - ETH_RX_BURST_SIZE_16_64BIT | \ - GT_ETH_IPG_INT_RX(0) | \ - ETH_TX_BURST_SIZE_16_64BIT; -#else -#define PORT_SDMA_CONFIG_VALUE \ - ETH_RX_BURST_SIZE_4_64BIT | \ - GT_ETH_IPG_INT_RX(0) | \ - ETH_TX_BURST_SIZE_4_64BIT; -#endif - -#define GT_ETH_IPG_INT_RX(value) \ - ((value & 0x3fff) << 8) - -/* Default port serial control value */ -#define PORT_SERIAL_CONTROL_VALUE \ - ETH_FORCE_LINK_PASS | \ - ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \ - ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ - ETH_ADV_SYMMETRIC_FLOW_CTRL | \ - ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ - ETH_FORCE_BP_MODE_NO_JAM | \ - BIT9 | \ - ETH_DO_NOT_FORCE_LINK_FAIL | \ - ETH_RETRANSMIT_16_ETTEMPTS | \ - ETH_ENABLE_AUTO_NEG_SPEED_GMII | \ - ETH_DTE_ADV_0 | \ - ETH_DISABLE_AUTO_NEG_BYPASS | \ - ETH_AUTO_NEG_NO_CHANGE | \ - ETH_MAX_RX_PACKET_1552BYTE | \ - ETH_CLR_EXT_LOOPBACK | \ - ETH_SET_FULL_DUPLEX_MODE | \ - ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX; - -#define RX_BUFFER_MAX_SIZE 0xFFFF -#define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */ - -#define RX_BUFFER_MIN_SIZE 0x8 -#define TX_BUFFER_MIN_SIZE 0x8 - -/* Tx WRR confoguration macros */ -#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */ -#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */ -#define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */ - -/* MAC accepet/reject macros */ -#define ACCEPT_MAC_ADDR 0 -#define REJECT_MAC_ADDR 1 - -/* Size of a Tx/Rx descriptor used in chain list data structure */ -#define RX_DESC_ALIGNED_SIZE 0x20 -#define TX_DESC_ALIGNED_SIZE 0x20 - -/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */ -#define TX_BUF_OFFSET_IN_DESC 0x18 -/* Buffer offset from buffer pointer */ -#define RX_BUF_OFFSET 0x2 - -/* Gap define */ -#define ETH_BAR_GAP 0x8 -#define ETH_SIZE_REG_GAP 0x8 -#define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4 -#define ETH_PORT_ACCESS_CTRL_GAP 0x4 - -/* Gigabit Ethernet Unit Global Registers */ - -/* MIB Counters register definitions */ -#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0 -#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4 -#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8 -#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc -#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10 -#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14 -#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18 -#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c -#define ETH_MIB_FRAMES_64_OCTETS 0x20 -#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24 -#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28 -#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c -#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30 -#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 -#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38 -#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c -#define ETH_MIB_GOOD_FRAMES_SENT 0x40 -#define ETH_MIB_EXCESSIVE_COLLISION 0x44 -#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48 -#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c -#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50 -#define ETH_MIB_FC_SENT 0x54 -#define ETH_MIB_GOOD_FC_RECEIVED 0x58 -#define ETH_MIB_BAD_FC_RECEIVED 0x5c -#define ETH_MIB_UNDERSIZE_RECEIVED 0x60 -#define ETH_MIB_FRAGMENTS_RECEIVED 0x64 -#define ETH_MIB_OVERSIZE_RECEIVED 0x68 -#define ETH_MIB_JABBER_RECEIVED 0x6c -#define ETH_MIB_MAC_RECEIVE_ERROR 0x70 -#define ETH_MIB_BAD_CRC_EVENT 0x74 -#define ETH_MIB_COLLISION 0x78 -#define ETH_MIB_LATE_COLLISION 0x7c - -/* Port serial status reg (PSR) */ -#define ETH_INTERFACE_GMII_MII 0 -#define ETH_INTERFACE_PCM BIT0 -#define ETH_LINK_IS_DOWN 0 -#define ETH_LINK_IS_UP BIT1 -#define ETH_PORT_AT_HALF_DUPLEX 0 -#define ETH_PORT_AT_FULL_DUPLEX BIT2 -#define ETH_RX_FLOW_CTRL_DISABLED 0 -#define ETH_RX_FLOW_CTRL_ENBALED BIT3 -#define ETH_GMII_SPEED_100_10 0 -#define ETH_GMII_SPEED_1000 BIT4 -#define ETH_MII_SPEED_10 0 -#define ETH_MII_SPEED_100 BIT5 -#define ETH_NO_TX 0 -#define ETH_TX_IN_PROGRESS BIT7 -#define ETH_BYPASS_NO_ACTIVE 0 -#define ETH_BYPASS_ACTIVE BIT8 -#define ETH_PORT_NOT_AT_PARTITION_STATE 0 -#define ETH_PORT_AT_PARTITION_STATE BIT9 -#define ETH_PORT_TX_FIFO_NOT_EMPTY 0 -#define ETH_PORT_TX_FIFO_EMPTY BIT10 - - -/* These macros describes the Port configuration reg (Px_cR) bits */ -#define ETH_UNICAST_NORMAL_MODE 0 -#define ETH_UNICAST_PROMISCUOUS_MODE BIT0 -#define ETH_DEFAULT_RX_QUEUE_0 0 -#define ETH_DEFAULT_RX_QUEUE_1 BIT1 -#define ETH_DEFAULT_RX_QUEUE_2 BIT2 -#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1) -#define ETH_DEFAULT_RX_QUEUE_4 BIT3 -#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1) -#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2) -#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1) -#define ETH_DEFAULT_RX_ARP_QUEUE_0 0 -#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4 -#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5 -#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4) -#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6 -#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4) -#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5) -#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4) -#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0 -#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7 -#define ETH_RECEIVE_BC_IF_IP 0 -#define ETH_REJECT_BC_IF_IP BIT8 -#define ETH_RECEIVE_BC_IF_ARP 0 -#define ETH_REJECT_BC_IF_ARP BIT9 -#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12 -#define ETH_CAPTURE_TCP_FRAMES_DIS 0 -#define ETH_CAPTURE_TCP_FRAMES_EN BIT14 -#define ETH_CAPTURE_UDP_FRAMES_DIS 0 -#define ETH_CAPTURE_UDP_FRAMES_EN BIT15 -#define ETH_DEFAULT_RX_TCP_QUEUE_0 0 -#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16 -#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17 -#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16) -#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18 -#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16) -#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17) -#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16) -#define ETH_DEFAULT_RX_UDP_QUEUE_0 0 -#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19 -#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20 -#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19) -#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21 -#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19) -#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20) -#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19) -#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0 -#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22 -#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23 -#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22) -#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24 -#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22) -#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23) -#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22) - - -/* These macros describes the Port configuration extend reg (Px_cXR) bits*/ -#define ETH_CLASSIFY_EN BIT0 -#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0 -#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1 -#define ETH_PARTITION_DISABLE 0 -#define ETH_PARTITION_ENABLE BIT2 - - -/* Tx/Rx queue command reg (RQCR/TQCR)*/ -#define ETH_QUEUE_0_ENABLE BIT0 -#define ETH_QUEUE_1_ENABLE BIT1 -#define ETH_QUEUE_2_ENABLE BIT2 -#define ETH_QUEUE_3_ENABLE BIT3 -#define ETH_QUEUE_4_ENABLE BIT4 -#define ETH_QUEUE_5_ENABLE BIT5 -#define ETH_QUEUE_6_ENABLE BIT6 -#define ETH_QUEUE_7_ENABLE BIT7 -#define ETH_QUEUE_0_DISABLE BIT8 -#define ETH_QUEUE_1_DISABLE BIT9 -#define ETH_QUEUE_2_DISABLE BIT10 -#define ETH_QUEUE_3_DISABLE BIT11 -#define ETH_QUEUE_4_DISABLE BIT12 -#define ETH_QUEUE_5_DISABLE BIT13 -#define ETH_QUEUE_6_DISABLE BIT14 -#define ETH_QUEUE_7_DISABLE BIT15 - - -/* These macros describes the Port Sdma configuration reg (SDCR) bits */ -#define ETH_RIFB BIT0 -#define ETH_RX_BURST_SIZE_1_64BIT 0 -#define ETH_RX_BURST_SIZE_2_64BIT BIT1 -#define ETH_RX_BURST_SIZE_4_64BIT BIT2 -#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1) -#define ETH_RX_BURST_SIZE_16_64BIT BIT3 -#define ETH_BLM_RX_NO_SWAP BIT4 -#define ETH_BLM_RX_BYTE_SWAP 0 -#define ETH_BLM_TX_NO_SWAP BIT5 -#define ETH_BLM_TX_BYTE_SWAP 0 -#define ETH_DESCRIPTORS_BYTE_SWAP BIT6 -#define ETH_DESCRIPTORS_NO_SWAP 0 -#define ETH_TX_BURST_SIZE_1_64BIT 0 -#define ETH_TX_BURST_SIZE_2_64BIT BIT22 -#define ETH_TX_BURST_SIZE_4_64BIT BIT23 -#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22) -#define ETH_TX_BURST_SIZE_16_64BIT BIT24 - - -/* These macros describes the Port serial control reg (PSCR) bits */ -#define ETH_SERIAL_PORT_DISABLE 0 -#define ETH_SERIAL_PORT_ENABLE BIT0 -#define ETH_FORCE_LINK_PASS BIT1 -#define ETH_DO_NOT_FORCE_LINK_PASS 0 -#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0 -#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2 -#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0 -#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3 -#define ETH_ADV_NO_FLOW_CTRL 0 -#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4 -#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0 -#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5 -#define ETH_FORCE_BP_MODE_NO_JAM 0 -#define ETH_FORCE_BP_MODE_JAM_TX BIT7 -#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8 -#define ETH_FORCE_LINK_FAIL 0 -#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10 -#define ETH_RETRANSMIT_16_ETTEMPTS 0 -#define ETH_RETRANSMIT_FOREVER BIT11 -#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13 -#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0 -#define ETH_DTE_ADV_0 0 -#define ETH_DTE_ADV_1 BIT14 -#define ETH_DISABLE_AUTO_NEG_BYPASS 0 -#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15 -#define ETH_AUTO_NEG_NO_CHANGE 0 -#define ETH_RESTART_AUTO_NEG BIT16 -#define ETH_MAX_RX_PACKET_1518BYTE 0 -#define ETH_MAX_RX_PACKET_1522BYTE BIT17 -#define ETH_MAX_RX_PACKET_1552BYTE BIT18 -#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17) -#define ETH_MAX_RX_PACKET_9192BYTE BIT19 -#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17) -#define ETH_SET_EXT_LOOPBACK BIT20 -#define ETH_CLR_EXT_LOOPBACK 0 -#define ETH_SET_FULL_DUPLEX_MODE BIT21 -#define ETH_SET_HALF_DUPLEX_MODE 0 -#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22 -#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0 -#define ETH_SET_GMII_SPEED_TO_10_100 0 -#define ETH_SET_GMII_SPEED_TO_1000 BIT23 -#define ETH_SET_MII_SPEED_TO_10 0 -#define ETH_SET_MII_SPEED_TO_100 BIT24 - - -/* SMI reg */ -#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */ -#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */ -#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */ -#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */ - -/* SDMA command status fields macros */ - -/* Tx & Rx descriptors status */ -#define ETH_ERROR_SUMMARY (BIT0) - -/* Tx & Rx descriptors command */ -#define ETH_BUFFER_OWNED_BY_DMA (BIT31) - -/* Tx descriptors status */ -#define ETH_LC_ERROR (0 ) -#define ETH_UR_ERROR (BIT1 ) -#define ETH_RL_ERROR (BIT2 ) -#define ETH_LLC_SNAP_FORMAT (BIT9 ) - -/* Rx descriptors status */ -#define ETH_CRC_ERROR (0 ) -#define ETH_OVERRUN_ERROR (BIT1 ) -#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 ) -#define ETH_RESOURCE_ERROR ((BIT2 | BIT1)) -#define ETH_VLAN_TAGGED (BIT19) -#define ETH_BPDU_FRAME (BIT20) -#define ETH_TCP_FRAME_OVER_IP_V_4 (0 ) -#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21) -#define ETH_OTHER_FRAME_TYPE (BIT22) -#define ETH_LAYER_2_IS_ETH_V_2 (BIT23) -#define ETH_FRAME_TYPE_IP_V_4 (BIT24) -#define ETH_FRAME_HEADER_OK (BIT25) -#define ETH_RX_LAST_DESC (BIT26) -#define ETH_RX_FIRST_DESC (BIT27) -#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28) -#define ETH_RX_ENABLE_INTERRUPT (BIT29) -#define ETH_LAYER_4_CHECKSUM_OK (BIT30) - -/* Rx descriptors byte count */ -#define ETH_FRAME_FRAGMENTED (BIT2) - -/* Tx descriptors command */ -#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10) -#define ETH_FRAME_SET_TO_VLAN (BIT15) -#define ETH_TCP_FRAME (0 ) -#define ETH_UDP_FRAME (BIT16) -#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17) -#define ETH_GEN_IP_V_4_CHECKSUM (BIT18) -#define ETH_ZERO_PADDING (BIT19) -#define ETH_TX_LAST_DESC (BIT20) -#define ETH_TX_FIRST_DESC (BIT21) -#define ETH_GEN_CRC (BIT22) -#define ETH_TX_ENABLE_INTERRUPT (BIT23) -#define ETH_AUTO_MODE (BIT30) - -/* Address decode parameters */ -/* Ethernet Base Address Register bits */ -#define EBAR_TARGET_DRAM 0x00000000 -#define EBAR_TARGET_DEVICE 0x00000001 -#define EBAR_TARGET_CBS 0x00000002 -#define EBAR_TARGET_PCI0 0x00000003 -#define EBAR_TARGET_PCI1 0x00000004 -#define EBAR_TARGET_CUNIT 0x00000005 -#define EBAR_TARGET_AUNIT 0x00000006 -#define EBAR_TARGET_GUNIT 0x00000007 - -/* Window attributes */ -#define EBAR_ATTR_DRAM_CS0 0x00000E00 -#define EBAR_ATTR_DRAM_CS1 0x00000D00 -#define EBAR_ATTR_DRAM_CS2 0x00000B00 -#define EBAR_ATTR_DRAM_CS3 0x00000700 - -/* DRAM Target interface */ -#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000 -#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000 -#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000 - -/* Device Bus Target interface */ -#define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00 -#define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00 -#define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00 -#define EBAR_ATTR_DEVICE_DEVCS3 0x00001700 -#define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00 - -/* PCI Target interface */ -#define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000 -#define EBAR_ATTR_PCI_NO_SWAP 0x00000100 -#define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200 -#define EBAR_ATTR_PCI_WORD_SWAP 0x00000300 -#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000 -#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400 -#define EBAR_ATTR_PCI_IO_SPACE 0x00000000 -#define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800 -#define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000 -#define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000 - -/* CPU 60x bus or internal SRAM interface */ -#define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000 -#define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100 -#define EBAR_ATTR_CBS_SRAM 0x00000000 -#define EBAR_ATTR_CBS_CPU_BUS 0x00000800 - -/* Window access control */ -#define EWIN_ACCESS_NOT_ALLOWED 0 -#define EWIN_ACCESS_READ_ONLY BIT0 -#define EWIN_ACCESS_FULL (BIT1 | BIT0) -#define EWIN0_ACCESS_MASK 0x0003 -#define EWIN1_ACCESS_MASK 0x000C -#define EWIN2_ACCESS_MASK 0x0030 -#define EWIN3_ACCESS_MASK 0x00C0 - -/* typedefs */ - -typedef enum _eth_port -{ - ETH_0 = 0, - ETH_1 = 1, - ETH_2 = 2 -}ETH_PORT; - -typedef enum _eth_func_ret_status -{ - ETH_OK, /* Returned as expected. */ - ETH_ERROR, /* Fundamental error. */ - ETH_RETRY, /* Could not process request. Try later. */ - ETH_END_OF_JOB, /* Ring has nothing to process. */ - ETH_QUEUE_FULL, /* Ring resource error. */ - ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */ -}ETH_FUNC_RET_STATUS; - -typedef enum _eth_queue -{ - ETH_Q0 = 0, - ETH_Q1 = 1, - ETH_Q2 = 2, - ETH_Q3 = 3, - ETH_Q4 = 4, - ETH_Q5 = 5, - ETH_Q6 = 6, - ETH_Q7 = 7 -} ETH_QUEUE; - -typedef enum _addr_win -{ - ETH_WIN0, - ETH_WIN1, - ETH_WIN2, - ETH_WIN3, - ETH_WIN4, - ETH_WIN5 -} ETH_ADDR_WIN; - -typedef enum _eth_target -{ - ETH_TARGET_DRAM , - ETH_TARGET_DEVICE, - ETH_TARGET_CBS , - ETH_TARGET_PCI0 , - ETH_TARGET_PCI1 -}ETH_TARGET; - -typedef struct _eth_rx_desc -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short buf_size ; /* Buffer size */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int next_desc_ptr; /* Next descriptor pointer */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} ETH_RX_DESC; - - -typedef struct _eth_tx_desc -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short l4i_chk ; /* CPU provided TCP Checksum */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int next_desc_ptr; /* Next descriptor pointer */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} ETH_TX_DESC; - -/* Unified struct for Rx and Tx operations. The user is not required to */ -/* be familier with neither Tx nor Rx descriptors. */ -typedef struct _pkt_info -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} PKT_INFO; - - -typedef struct _eth_win_param -{ - ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */ - ETH_TARGET target; /* System targets. See ETH_TARGET enum */ - unsigned short attributes; /* BAR attributes. See above macros. */ - unsigned int base_addr; /* Window base address in unsigned int form */ - unsigned int high_addr; /* Window high address in unsigned int form */ - unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */ - bool enable; /* Enable/disable access to the window. */ - unsigned short access_ctrl; /* Access ctrl register. see above macros */ -} ETH_WIN_PARAM; - - -/* Ethernet port specific infomation */ - -typedef struct _eth_port_ctrl -{ - ETH_PORT port_num; /* User Ethernet port number */ - int port_phy_addr; /* User phy address of Ethrnet port */ - unsigned char port_mac_addr[6]; /* User defined port MAC address. */ - unsigned int port_config; /* User port configuration value */ - unsigned int port_config_extend; /* User port config extend value */ - unsigned int port_sdma_config; /* User port SDMA config value */ - unsigned int port_serial_control; /* User port serial control value */ - unsigned int port_tx_queue_command; /* Port active Tx queues summary */ - unsigned int port_rx_queue_command; /* Port active Rx queues summary */ - - /* User function to cast virtual address to CPU bus address */ - unsigned int (*port_virt_to_phys)(unsigned int addr); - /* User scratch pad for user specific data structures */ - void *port_private; - - bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */ - bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */ - - /* Tx/Rx rings managment indexes fields. For driver use */ - - /* Next available Rx resource */ - volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM]; - /* Returning Rx resource */ - volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM]; - - /* Next available Tx resource */ - volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM]; - /* Returning Tx resource */ - volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM]; - /* An extra Tx index to support transmit of multiple buffers per packet */ - volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM]; - - /* Tx/Rx rings size and base variables fields. For driver use */ - - volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM]; - unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM]; - char *p_rx_buffer_base[MAX_RX_QUEUE_NUM]; - - volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM]; - unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM]; - char *p_tx_buffer_base[MAX_TX_QUEUE_NUM]; - -} ETH_PORT_INFO; - - -/* ethernet.h API list */ - -/* Port operation control routines */ -static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl); -static void eth_port_reset(ETH_PORT eth_port_num); -static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl); - - -/* Port MAC address routines */ -static void eth_port_uc_addr_set (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue); -#if 0 /* FIXME */ -static void eth_port_mc_addr (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue, - int option); -#endif - -/* PHY and MIB routines */ -static bool ethernet_phy_reset(ETH_PORT eth_port_num); - -static bool eth_port_write_smi_reg(ETH_PORT eth_port_num, - unsigned int phy_reg, - unsigned int value); - -static bool eth_port_read_smi_reg(ETH_PORT eth_port_num, - unsigned int phy_reg, - unsigned int* value); - -static void eth_clear_mib_counters(ETH_PORT eth_port_num); - -/* Port data flow control routines */ -static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO *p_pkt_info); - - -static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - int tx_desc_num, - int tx_buff_size, - unsigned int tx_desc_base_addr, - unsigned int tx_buff_base_addr); - -static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - int rx_desc_num, - int rx_buff_size, - unsigned int rx_desc_base_addr, - unsigned int rx_buff_base_addr); - -#endif /* MV64360_ETH_ */ diff --git a/board/esd/cpci750/mv_regs.h b/board/esd/cpci750/mv_regs.h deleted file mode 100644 index 9a54a97..0000000 --- a/board/esd/cpci750/mv_regs.h +++ /dev/null @@ -1,1108 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus <ingo.assmus@keymile.com> - * - * based on - Driver for MV64360X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/******************************************************************************** -* gt64360r.h - GT-64360 Internal registers definition file. -* -* DESCRIPTION: -* None. -* -* DEPENDENCIES: -* None. -* -*******************************************************************************/ - -#ifndef __INCmv_regsh -#define __INCmv_regsh - -#define MV64360 - -/* Supported by the Atlantis */ -#define MV64360_INCLUDE_PCI_1 -#define MV64360_INCLUDE_PCI_0_ARBITER -#define MV64360_INCLUDE_PCI_1_ARBITER -#define MV64360_INCLUDE_SNOOP_SUPPORT -#define MV64360_INCLUDE_P2P -#define MV64360_INCLUDE_ETH_PORT_2 -#define MV64360_INCLUDE_CPU_MAPPING -#define MV64360_INCLUDE_MPSC - -/* Not supported features */ -#undef INCLUDE_CNTMR_4_7 -#undef INCLUDE_DMA_4_7 - -/****************************************/ -/* Processor Address Space */ -/****************************************/ - -/* DDR SDRAM BAR and size registers */ - -#define MV64360_CS_0_BASE_ADDR 0x008 -#define MV64360_CS_0_SIZE 0x010 -#define MV64360_CS_1_BASE_ADDR 0x208 -#define MV64360_CS_1_SIZE 0x210 -#define MV64360_CS_2_BASE_ADDR 0x018 -#define MV64360_CS_2_SIZE 0x020 -#define MV64360_CS_3_BASE_ADDR 0x218 -#define MV64360_CS_3_SIZE 0x220 - -/* Devices BAR and size registers */ - -#define MV64360_DEV_CS0_BASE_ADDR 0x028 -#define MV64360_DEV_CS0_SIZE 0x030 -#define MV64360_DEV_CS1_BASE_ADDR 0x228 -#define MV64360_DEV_CS1_SIZE 0x230 -#define MV64360_DEV_CS2_BASE_ADDR 0x248 -#define MV64360_DEV_CS2_SIZE 0x250 -#define MV64360_DEV_CS3_BASE_ADDR 0x038 -#define MV64360_DEV_CS3_SIZE 0x040 -#define MV64360_BOOTCS_BASE_ADDR 0x238 -#define MV64360_BOOTCS_SIZE 0x240 - -/* PCI 0 BAR and size registers */ - -#define MV64360_PCI_0_IO_BASE_ADDR 0x048 -#define MV64360_PCI_0_IO_SIZE 0x050 -#define MV64360_PCI_0_MEMORY0_BASE_ADDR 0x058 -#define MV64360_PCI_0_MEMORY0_SIZE 0x060 -#define MV64360_PCI_0_MEMORY1_BASE_ADDR 0x080 -#define MV64360_PCI_0_MEMORY1_SIZE 0x088 -#define MV64360_PCI_0_MEMORY2_BASE_ADDR 0x258 -#define MV64360_PCI_0_MEMORY2_SIZE 0x260 -#define MV64360_PCI_0_MEMORY3_BASE_ADDR 0x280 -#define MV64360_PCI_0_MEMORY3_SIZE 0x288 - -/* PCI 1 BAR and size registers */ -#define MV64360_PCI_1_IO_BASE_ADDR 0x090 -#define MV64360_PCI_1_IO_SIZE 0x098 -#define MV64360_PCI_1_MEMORY0_BASE_ADDR 0x0a0 -#define MV64360_PCI_1_MEMORY0_SIZE 0x0a8 -#define MV64360_PCI_1_MEMORY1_BASE_ADDR 0x0b0 -#define MV64360_PCI_1_MEMORY1_SIZE 0x0b8 -#define MV64360_PCI_1_MEMORY2_BASE_ADDR 0x2a0 -#define MV64360_PCI_1_MEMORY2_SIZE 0x2a8 -#define MV64360_PCI_1_MEMORY3_BASE_ADDR 0x2b0 -#define MV64360_PCI_1_MEMORY3_SIZE 0x2b8 - -/* SRAM base address */ -#define MV64360_INTEGRATED_SRAM_BASE_ADDR 0x268 - -/* internal registers space base address */ -#define MV64360_INTERNAL_SPACE_BASE_ADDR 0x068 - -/* Enables the CS , DEV_CS , PCI 0 and PCI 1 - windows above */ -#define MV64360_BASE_ADDR_ENABLE 0x278 - -/****************************************/ -/* PCI remap registers */ -/****************************************/ - /* PCI 0 */ -#define MV64360_PCI_0_IO_ADDR_REMAP 0x0f0 -#define MV64360_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8 -#define MV64360_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320 -#define MV64360_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100 -#define MV64360_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328 -#define MV64360_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8 -#define MV64360_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330 -#define MV64360_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300 -#define MV64360_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338 - /* PCI 1 */ -#define MV64360_PCI_1_IO_ADDR_REMAP 0x108 -#define MV64360_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110 -#define MV64360_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340 -#define MV64360_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118 -#define MV64360_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348 -#define MV64360_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310 -#define MV64360_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350 -#define MV64360_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318 -#define MV64360_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358 - -#define MV64360_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0 -#define MV64360_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8 -#define MV64360_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0 -#define MV64360_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8 -#define MV64360_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0 -#define MV64360_CPU_GE_HEADERS_RETARGET_BASE 0x3d8 -#define MV64360_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0 -#define MV64360_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8 - -/****************************************/ -/* CPU Control Registers */ -/****************************************/ - -#define MV64360_CPU_CONFIG 0x000 -#define MV64360_CPU_MODE 0x120 -#define MV64360_CPU_MASTER_CONTROL 0x160 -#define MV64360_CPU_CROSS_BAR_CONTROL_LOW 0x150 -#define MV64360_CPU_CROSS_BAR_CONTROL_HIGH 0x158 -#define MV64360_CPU_CROSS_BAR_TIMEOUT 0x168 - -/****************************************/ -/* SMP RegisterS */ -/****************************************/ - -#define MV64360_SMP_WHO_AM_I 0x200 -#define MV64360_SMP_CPU0_DOORBELL 0x214 -#define MV64360_SMP_CPU0_DOORBELL_CLEAR 0x21C -#define MV64360_SMP_CPU1_DOORBELL 0x224 -#define MV64360_SMP_CPU1_DOORBELL_CLEAR 0x22C -#define MV64360_SMP_CPU0_DOORBELL_MASK 0x234 -#define MV64360_SMP_CPU1_DOORBELL_MASK 0x23C -#define MV64360_SMP_SEMAPHOR0 0x244 -#define MV64360_SMP_SEMAPHOR1 0x24c -#define MV64360_SMP_SEMAPHOR2 0x254 -#define MV64360_SMP_SEMAPHOR3 0x25c -#define MV64360_SMP_SEMAPHOR4 0x264 -#define MV64360_SMP_SEMAPHOR5 0x26c -#define MV64360_SMP_SEMAPHOR6 0x274 -#define MV64360_SMP_SEMAPHOR7 0x27c - -/****************************************/ -/* CPU Sync Barrier Register */ -/****************************************/ - -#define MV64360_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0 -#define MV64360_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8 -#define MV64360_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0 -#define MV64360_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8 - -/****************************************/ -/* CPU Access Protect */ -/****************************************/ - -#define MV64360_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180 -#define MV64360_CPU_PROTECT_WINDOW_0_SIZE 0x188 -#define MV64360_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190 -#define MV64360_CPU_PROTECT_WINDOW_1_SIZE 0x198 -#define MV64360_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0 -#define MV64360_CPU_PROTECT_WINDOW_2_SIZE 0x1a8 -#define MV64360_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0 -#define MV64360_CPU_PROTECT_WINDOW_3_SIZE 0x1b8 - - -/****************************************/ -/* CPU Error Report */ -/****************************************/ - -#define MV64360_CPU_ERROR_ADDR_LOW 0x070 -#define MV64360_CPU_ERROR_ADDR_HIGH 0x078 -#define MV64360_CPU_ERROR_DATA_LOW 0x128 -#define MV64360_CPU_ERROR_DATA_HIGH 0x130 -#define MV64360_CPU_ERROR_PARITY 0x138 -#define MV64360_CPU_ERROR_CAUSE 0x140 -#define MV64360_CPU_ERROR_MASK 0x148 - -/****************************************/ -/* CPU Interface Debug Registers */ -/****************************************/ - -#define MV64360_PUNIT_SLAVE_DEBUG_LOW 0x360 -#define MV64360_PUNIT_SLAVE_DEBUG_HIGH 0x368 -#define MV64360_PUNIT_MASTER_DEBUG_LOW 0x370 -#define MV64360_PUNIT_MASTER_DEBUG_HIGH 0x378 -#define MV64360_PUNIT_MMASK 0x3e4 - -/****************************************/ -/* Integrated SRAM Registers */ -/****************************************/ - -#define MV64360_SRAM_CONFIG 0x380 -#define MV64360_SRAM_TEST_MODE 0X3F4 -#define MV64360_SRAM_ERROR_CAUSE 0x388 -#define MV64360_SRAM_ERROR_ADDR 0x390 -#define MV64360_SRAM_ERROR_ADDR_HIGH 0X3F8 -#define MV64360_SRAM_ERROR_DATA_LOW 0x398 -#define MV64360_SRAM_ERROR_DATA_HIGH 0x3a0 -#define MV64360_SRAM_ERROR_DATA_PARITY 0x3a8 - -/****************************************/ -/* SDRAM Configuration */ -/****************************************/ - -#define MV64360_SDRAM_CONFIG 0x1400 -#define MV64360_D_UNIT_CONTROL_LOW 0x1404 -#define MV64360_D_UNIT_CONTROL_HIGH 0x1424 -#define MV64360_SDRAM_TIMING_CONTROL_LOW 0x1408 -#define MV64360_SDRAM_TIMING_CONTROL_HIGH 0x140c -#define MV64360_SDRAM_ADDR_CONTROL 0x1410 -#define MV64360_SDRAM_OPEN_PAGES_CONTROL 0x1414 -#define MV64360_SDRAM_OPERATION 0x1418 -#define MV64360_SDRAM_MODE 0x141c -#define MV64360_EXTENDED_DRAM_MODE 0x1420 -#define MV64360_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430 -#define MV64360_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434 -#define MV64360_SDRAM_CROSS_BAR_TIMEOUT 0x1438 -#define MV64360_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0 -#define MV64360_SDRAM_DATA_PADS_CALIBRATION 0x14c4 - -/****************************************/ -/* SDRAM Error Report */ -/****************************************/ - -#define MV64360_SDRAM_ERROR_DATA_LOW 0x1444 -#define MV64360_SDRAM_ERROR_DATA_HIGH 0x1440 -#define MV64360_SDRAM_ERROR_ADDR 0x1450 -#define MV64360_SDRAM_RECEIVED_ECC 0x1448 -#define MV64360_SDRAM_CALCULATED_ECC 0x144c -#define MV64360_SDRAM_ECC_CONTROL 0x1454 -#define MV64360_SDRAM_ECC_ERROR_COUNTER 0x1458 - -/******************************************/ -/* Controlled Delay Line (CDL) Registers */ -/******************************************/ - -#define MV64360_DFCDL_CONFIG0 0x1480 -#define MV64360_DFCDL_CONFIG1 0x1484 -#define MV64360_DLL_WRITE 0x1488 -#define MV64360_DLL_READ 0x148c -#define MV64360_SRAM_ADDR 0x1490 -#define MV64360_SRAM_DATA0 0x1494 -#define MV64360_SRAM_DATA1 0x1498 -#define MV64360_SRAM_DATA2 0x149c -#define MV64360_DFCL_PROBE 0x14a0 - -/******************************************/ -/* Debug Registers */ -/******************************************/ - -#define MV64360_DUNIT_DEBUG_LOW 0x1460 -#define MV64360_DUNIT_DEBUG_HIGH 0x1464 -#define MV64360_DUNIT_MMASK 0X1b40 - -/****************************************/ -/* Device Parameters */ -/****************************************/ - -#define MV64360_DEVICE_BANK0_PARAMETERS 0x45c -#define MV64360_DEVICE_BANK1_PARAMETERS 0x460 -#define MV64360_DEVICE_BANK2_PARAMETERS 0x464 -#define MV64360_DEVICE_BANK3_PARAMETERS 0x468 -#define MV64360_DEVICE_BOOT_BANK_PARAMETERS 0x46c -#define MV64360_DEVICE_INTERFACE_CONTROL 0x4c0 -#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8 -#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc -#define MV64360_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4 - -/****************************************/ -/* Device interrupt registers */ -/****************************************/ - -#define MV64360_DEVICE_INTERRUPT_CAUSE 0x4d0 -#define MV64360_DEVICE_INTERRUPT_MASK 0x4d4 -#define MV64360_DEVICE_ERROR_ADDR 0x4d8 -#define MV64360_DEVICE_ERROR_DATA 0x4dc -#define MV64360_DEVICE_ERROR_PARITY 0x4e0 - -/****************************************/ -/* Device debug registers */ -/****************************************/ - -#define MV64360_DEVICE_DEBUG_LOW 0x4e4 -#define MV64360_DEVICE_DEBUG_HIGH 0x4e8 -#define MV64360_RUNIT_MMASK 0x4f0 - -/****************************************/ -/* PCI Slave Address Decoding registers */ -/****************************************/ - -#define MV64360_PCI_0_CS_0_BANK_SIZE 0xc08 -#define MV64360_PCI_1_CS_0_BANK_SIZE 0xc88 -#define MV64360_PCI_0_CS_1_BANK_SIZE 0xd08 -#define MV64360_PCI_1_CS_1_BANK_SIZE 0xd88 -#define MV64360_PCI_0_CS_2_BANK_SIZE 0xc0c -#define MV64360_PCI_1_CS_2_BANK_SIZE 0xc8c -#define MV64360_PCI_0_CS_3_BANK_SIZE 0xd0c -#define MV64360_PCI_1_CS_3_BANK_SIZE 0xd8c -#define MV64360_PCI_0_DEVCS_0_BANK_SIZE 0xc10 -#define MV64360_PCI_1_DEVCS_0_BANK_SIZE 0xc90 -#define MV64360_PCI_0_DEVCS_1_BANK_SIZE 0xd10 -#define MV64360_PCI_1_DEVCS_1_BANK_SIZE 0xd90 -#define MV64360_PCI_0_DEVCS_2_BANK_SIZE 0xd18 -#define MV64360_PCI_1_DEVCS_2_BANK_SIZE 0xd98 -#define MV64360_PCI_0_DEVCS_3_BANK_SIZE 0xc14 -#define MV64360_PCI_1_DEVCS_3_BANK_SIZE 0xc94 -#define MV64360_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14 -#define MV64360_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94 -#define MV64360_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c -#define MV64360_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c -#define MV64360_PCI_0_P2P_MEM1_BAR_SIZE 0xd20 -#define MV64360_PCI_1_P2P_MEM1_BAR_SIZE 0xda0 -#define MV64360_PCI_0_P2P_I_O_BAR_SIZE 0xd24 -#define MV64360_PCI_1_P2P_I_O_BAR_SIZE 0xda4 -#define MV64360_PCI_0_CPU_BAR_SIZE 0xd28 -#define MV64360_PCI_1_CPU_BAR_SIZE 0xda8 -#define MV64360_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00 -#define MV64360_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80 -#define MV64360_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c -#define MV64360_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c -#define MV64360_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c -#define MV64360_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc -#define MV64360_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48 -#define MV64360_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8 -#define MV64360_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48 -#define MV64360_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8 -#define MV64360_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c -#define MV64360_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc -#define MV64360_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c -#define MV64360_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc -#define MV64360_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04 -#define MV64360_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84 -#define MV64360_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08 -#define MV64360_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88 -#define MV64360_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C -#define MV64360_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C -#define MV64360_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10 -#define MV64360_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90 -#define MV64360_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50 -#define MV64360_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0 -#define MV64360_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50 -#define MV64360_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0 -#define MV64360_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58 -#define MV64360_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8 -#define MV64360_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54 -#define MV64360_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4 -#define MV64360_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54 -#define MV64360_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4 -#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c -#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc -#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60 -#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0 -#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64 -#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4 -#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68 -#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8 -#define MV64360_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c -#define MV64360_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec -#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70 -#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0 -#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74 -#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4 -#define MV64360_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00 -#define MV64360_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80 -#define MV64360_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38 -#define MV64360_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8 -#define MV64360_PCI_0_ADDR_DECODE_CONTROL 0xd3c -#define MV64360_PCI_1_ADDR_DECODE_CONTROL 0xdbc -#define MV64360_PCI_0_HEADERS_RETARGET_CONTROL 0xF40 -#define MV64360_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0 -#define MV64360_PCI_0_HEADERS_RETARGET_BASE 0xF44 -#define MV64360_PCI_1_HEADERS_RETARGET_BASE 0xFc4 -#define MV64360_PCI_0_HEADERS_RETARGET_HIGH 0xF48 -#define MV64360_PCI_1_HEADERS_RETARGET_HIGH 0xFc8 - -/***********************************/ -/* PCI Control Register Map */ -/***********************************/ - -#define MV64360_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20 -#define MV64360_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0 -#define MV64360_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C -#define MV64360_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C -#define MV64360_PCI_0_COMMAND 0xc00 -#define MV64360_PCI_1_COMMAND 0xc80 -#define MV64360_PCI_0_MODE 0xd00 -#define MV64360_PCI_1_MODE 0xd80 -#define MV64360_PCI_0_RETRY 0xc04 -#define MV64360_PCI_1_RETRY 0xc84 -#define MV64360_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04 -#define MV64360_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84 -#define MV64360_PCI_0_MSI_TRIGGER_TIMER 0xc38 -#define MV64360_PCI_1_MSI_TRIGGER_TIMER 0xcb8 -#define MV64360_PCI_0_ARBITER_CONTROL 0x1d00 -#define MV64360_PCI_1_ARBITER_CONTROL 0x1d80 -#define MV64360_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08 -#define MV64360_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88 -#define MV64360_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c -#define MV64360_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c -#define MV64360_PCI_0_CROSS_BAR_TIMEOUT 0x1d04 -#define MV64360_PCI_1_CROSS_BAR_TIMEOUT 0x1d84 -#define MV64360_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18 -#define MV64360_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98 -#define MV64360_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10 -#define MV64360_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90 -#define MV64360_PCI_0_P2P_CONFIG 0x1d14 -#define MV64360_PCI_1_P2P_CONFIG 0x1d94 - -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50 -#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54 -#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58 - -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0 -#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 -#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8 - -/****************************************/ -/* PCI Configuration Access Registers */ -/****************************************/ - -#define MV64360_PCI_0_CONFIG_ADDR 0xcf8 -#define MV64360_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc -#define MV64360_PCI_1_CONFIG_ADDR 0xc78 -#define MV64360_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c -#define MV64360_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34 -#define MV64360_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4 - -/****************************************/ -/* PCI Error Report Registers */ -/****************************************/ - -#define MV64360_PCI_0_SERR_MASK 0xc28 -#define MV64360_PCI_1_SERR_MASK 0xca8 -#define MV64360_PCI_0_ERROR_ADDR_LOW 0x1d40 -#define MV64360_PCI_1_ERROR_ADDR_LOW 0x1dc0 -#define MV64360_PCI_0_ERROR_ADDR_HIGH 0x1d44 -#define MV64360_PCI_1_ERROR_ADDR_HIGH 0x1dc4 -#define MV64360_PCI_0_ERROR_ATTRIBUTE 0x1d48 -#define MV64360_PCI_1_ERROR_ATTRIBUTE 0x1dc8 -#define MV64360_PCI_0_ERROR_COMMAND 0x1d50 -#define MV64360_PCI_1_ERROR_COMMAND 0x1dd0 -#define MV64360_PCI_0_ERROR_CAUSE 0x1d58 -#define MV64360_PCI_1_ERROR_CAUSE 0x1dd8 -#define MV64360_PCI_0_ERROR_MASK 0x1d5c -#define MV64360_PCI_1_ERROR_MASK 0x1ddc - -/****************************************/ -/* PCI Debug Registers */ -/****************************************/ - -#define MV64360_PCI_0_MMASK 0X1D24 -#define MV64360_PCI_1_MMASK 0X1DA4 - -/*********************************************/ -/* PCI Configuration, Function 0, Registers */ -/*********************************************/ - -#define MV64360_PCI_DEVICE_AND_VENDOR_ID 0x000 -#define MV64360_PCI_STATUS_AND_COMMAND 0x004 -#define MV64360_PCI_CLASS_CODE_AND_REVISION_ID 0x008 -#define MV64360_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C - -#define MV64360_PCI_SCS_0_BASE_ADDR_LOW 0x010 -#define MV64360_PCI_SCS_0_BASE_ADDR_HIGH 0x014 -#define MV64360_PCI_SCS_1_BASE_ADDR_LOW 0x018 -#define MV64360_PCI_SCS_1_BASE_ADDR_HIGH 0x01C -#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020 -#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024 -#define MV64360_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c -#define MV64360_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 -#define MV64360_PCI_CAPABILTY_LIST_POINTER 0x034 -#define MV64360_PCI_INTERRUPT_PIN_AND_LINE 0x03C - /* capability list */ -#define MV64360_PCI_POWER_MANAGEMENT_CAPABILITY 0x040 -#define MV64360_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 -#define MV64360_PCI_VPD_ADDR 0x048 -#define MV64360_PCI_VPD_DATA 0x04c -#define MV64360_PCI_MSI_MESSAGE_CONTROL 0x050 -#define MV64360_PCI_MSI_MESSAGE_ADDR 0x054 -#define MV64360_PCI_MSI_MESSAGE_UPPER_ADDR 0x058 -#define MV64360_PCI_MSI_MESSAGE_DATA 0x05c -#define MV64360_PCI_X_COMMAND 0x060 -#define MV64360_PCI_X_STATUS 0x064 -#define MV64360_PCI_COMPACT_PCI_HOT_SWAP 0x068 - -/***********************************************/ -/* PCI Configuration, Function 1, Registers */ -/***********************************************/ - -#define MV64360_PCI_SCS_2_BASE_ADDR_LOW 0x110 -#define MV64360_PCI_SCS_2_BASE_ADDR_HIGH 0x114 -#define MV64360_PCI_SCS_3_BASE_ADDR_LOW 0x118 -#define MV64360_PCI_SCS_3_BASE_ADDR_HIGH 0x11c -#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120 -#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124 - -/***********************************************/ -/* PCI Configuration, Function 2, Registers */ -/***********************************************/ - -#define MV64360_PCI_DEVCS_0_BASE_ADDR_LOW 0x210 -#define MV64360_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214 -#define MV64360_PCI_DEVCS_1_BASE_ADDR_LOW 0x218 -#define MV64360_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c -#define MV64360_PCI_DEVCS_2_BASE_ADDR_LOW 0x220 -#define MV64360_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224 - -/***********************************************/ -/* PCI Configuration, Function 3, Registers */ -/***********************************************/ - -#define MV64360_PCI_DEVCS_3_BASE_ADDR_LOW 0x310 -#define MV64360_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314 -#define MV64360_PCI_BOOT_CS_BASE_ADDR_LOW 0x318 -#define MV64360_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c -#define MV64360_PCI_CPU_BASE_ADDR_LOW 0x220 -#define MV64360_PCI_CPU_BASE_ADDR_HIGH 0x224 - -/***********************************************/ -/* PCI Configuration, Function 4, Registers */ -/***********************************************/ - -#define MV64360_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410 -#define MV64360_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414 -#define MV64360_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418 -#define MV64360_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c -#define MV64360_PCI_P2P_I_O_BASE_ADDR 0x420 -#define MV64360_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424 - -/****************************************/ -/* Messaging Unit Registers (I20) */ -/****************************************/ - -#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010 -#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C -#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020 -#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024 -#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028 -#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C -#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030 -#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034 -#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040 -#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044 -#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050 -#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054 -#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060 -#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064 -#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068 -#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C -#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070 -#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074 -#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8 -#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC - -#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090 -#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C -#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0 -#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4 -#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8 -#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC -#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0 -#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4 -#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0 -#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4 -#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0 -#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4 -#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0 -#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4 -#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8 -#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC -#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0 -#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4 -#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078 -#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C - -#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10 -#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C -#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20 -#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24 -#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28 -#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C -#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30 -#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34 -#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40 -#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44 -#define MV64360_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50 -#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54 -#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60 -#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64 -#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68 -#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C -#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70 -#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74 -#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8 -#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC -#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90 -#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98 -#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C -#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0 -#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4 -#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8 -#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC -#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0 -#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4 -#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0 -#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4 -#define MV64360_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0 -#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4 -#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0 -#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4 -#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8 -#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC -#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0 -#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4 -#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78 -#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C - -/****************************************/ -/* Ethernet Unit Registers */ -/****************************************/ - -#define MV64360_ETH_PHY_ADDR_REG 0x2000 -#define MV64360_ETH_SMI_REG 0x2004 -#define MV64360_ETH_UNIT_DEFAULT_ADDR_REG 0x2008 -#define MV64360_ETH_UNIT_DEFAULTID_REG 0x200c -#define MV64360_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080 -#define MV64360_ETH_UNIT_INTERRUPT_MASK_REG 0x2084 -#define MV64360_ETH_UNIT_INTERNAL_USE_REG 0x24fc -#define MV64360_ETH_UNIT_ERROR_ADDR_REG 0x2094 -#define MV64360_ETH_BAR_0 0x2200 -#define MV64360_ETH_BAR_1 0x2208 -#define MV64360_ETH_BAR_2 0x2210 -#define MV64360_ETH_BAR_3 0x2218 -#define MV64360_ETH_BAR_4 0x2220 -#define MV64360_ETH_BAR_5 0x2228 -#define MV64360_ETH_SIZE_REG_0 0x2204 -#define MV64360_ETH_SIZE_REG_1 0x220c -#define MV64360_ETH_SIZE_REG_2 0x2214 -#define MV64360_ETH_SIZE_REG_3 0x221c -#define MV64360_ETH_SIZE_REG_4 0x2224 -#define MV64360_ETH_SIZE_REG_5 0x222c -#define MV64360_ETH_HEADERS_RETARGET_BASE_REG 0x2230 -#define MV64360_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234 -#define MV64360_ETH_HIGH_ADDR_REMAP_REG_0 0x2280 -#define MV64360_ETH_HIGH_ADDR_REMAP_REG_1 0x2284 -#define MV64360_ETH_HIGH_ADDR_REMAP_REG_2 0x2288 -#define MV64360_ETH_HIGH_ADDR_REMAP_REG_3 0x228c -#define MV64360_ETH_BASE_ADDR_ENABLE_REG 0x2290 -#define MV64360_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2)) -#define MV64360_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7)) -#define MV64360_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10)) -#define MV64360_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10)) -#define MV64360_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10)) -#define MV64360_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10)) -#define MV64360_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10)) -#define MV64360_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10)) -#define MV64360_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10)) -#define MV64360_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10)) -#define MV64360_ETH_DSCP_0(port) (0x2420 + (port<<10)) -#define MV64360_ETH_DSCP_1(port) (0x2424 + (port<<10)) -#define MV64360_ETH_DSCP_2(port) (0x2428 + (port<<10)) -#define MV64360_ETH_DSCP_3(port) (0x242c + (port<<10)) -#define MV64360_ETH_DSCP_4(port) (0x2430 + (port<<10)) -#define MV64360_ETH_DSCP_5(port) (0x2434 + (port<<10)) -#define MV64360_ETH_DSCP_6(port) (0x2438 + (port<<10)) -#define MV64360_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10)) -#define MV64360_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10)) -#define MV64360_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10)) -#define MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10)) -#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10)) -#define MV64360_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10)) -#define MV64360_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10)) -#define MV64360_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10)) -#define MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10)) -#define MV64360_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10)) -#define MV64360_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10)) -#define MV64360_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10)) -#define MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10)) -#define MV64360_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10)) -#define MV64360_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10) -#define MV64360_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10)) -#define MV64360_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10)) -#define MV64360_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10)) -#define MV64360_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10)) -#define MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10)) -#define MV64360_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10)) -#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10)) -#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10)) -#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10)) -#define MV64360_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10)) -#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10)) -#define MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10)) -#define MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10)) -#define MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10)) - -/*******************************************/ -/* CUNIT Registers */ -/*******************************************/ - - /* Address Decoding Register Map */ - -#define MV64360_CUNIT_BASE_ADDR_REG0 0xf200 -#define MV64360_CUNIT_BASE_ADDR_REG1 0xf208 -#define MV64360_CUNIT_BASE_ADDR_REG2 0xf210 -#define MV64360_CUNIT_BASE_ADDR_REG3 0xf218 -#define MV64360_CUNIT_SIZE0 0xf204 -#define MV64360_CUNIT_SIZE1 0xf20c -#define MV64360_CUNIT_SIZE2 0xf214 -#define MV64360_CUNIT_SIZE3 0xf21c -#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240 -#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244 -#define MV64360_CUNIT_BASE_ADDR_ENABLE_REG 0xf250 -#define MV64360_MPSC0_ACCESS_PROTECTION_REG 0xf254 -#define MV64360_MPSC1_ACCESS_PROTECTION_REG 0xf258 -#define MV64360_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C - - /* Error Report Registers */ - -#define MV64360_CUNIT_INTERRUPT_CAUSE_REG 0xf310 -#define MV64360_CUNIT_INTERRUPT_MASK_REG 0xf314 -#define MV64360_CUNIT_ERROR_ADDR 0xf318 - - /* Cunit Control Registers */ - -#define MV64360_CUNIT_ARBITER_CONTROL_REG 0xf300 -#define MV64360_CUNIT_CONFIG_REG 0xb40c -#define MV64360_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304 - - /* Cunit Debug Registers */ - -#define MV64360_CUNIT_DEBUG_LOW 0xf340 -#define MV64360_CUNIT_DEBUG_HIGH 0xf344 -#define MV64360_CUNIT_MMASK 0xf380 - - /* Cunit Base Address Enable Window Bits*/ -#define MV64360_CUNIT_BASE_ADDR_WIN_0_BIT 0x0 -#define MV64360_CUNIT_BASE_ADDR_WIN_1_BIT 0x1 -#define MV64360_CUNIT_BASE_ADDR_WIN_2_BIT 0x2 -#define MV64360_CUNIT_BASE_ADDR_WIN_3_BIT 0x3 - - /* MPSCs Clocks Routing Registers */ - -#define MV64360_MPSC_ROUTING_REG 0xb400 -#define MV64360_MPSC_RX_CLOCK_ROUTING_REG 0xb404 -#define MV64360_MPSC_TX_CLOCK_ROUTING_REG 0xb408 - - /* MPSCs Interrupts Registers */ - -#define MV64360_MPSC_CAUSE_REG(port) (0xb804 + (port<<3)) -#define MV64360_MPSC_MASK_REG(port) (0xb884 + (port<<3)) - -#define MV64360_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12)) -#define MV64360_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12)) -#define MV64360_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG1(port) (0x800c + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG5(port) (0x801c + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG9(port) (0x802c + (port<<12)) -#define MV64360_MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12)) - - /* MPSC0 Registers */ - - -/***************************************/ -/* SDMA Registers */ -/***************************************/ - -#define MV64360_SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13)) -#define MV64360_SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13)) -#define MV64360_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13)) -#define MV64360_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13)) -#define MV64360_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13)) - -#define MV64360_SDMA_CAUSE_REG 0xb800 -#define MV64360_SDMA_MASK_REG 0xb880 - - -/****************************************/ -/* SDMA Address Space Targets */ -/****************************************/ - -#define MV64360_SDMA_DRAM_CS_0_TARGET 0x0e00 -#define MV64360_SDMA_DRAM_CS_1_TARGET 0x0d00 -#define MV64360_SDMA_DRAM_CS_2_TARGET 0x0b00 -#define MV64360_SDMA_DRAM_CS_3_TARGET 0x0700 - -#define MV64360_SDMA_DEV_CS_0_TARGET 0x1e01 -#define MV64360_SDMA_DEV_CS_1_TARGET 0x1d01 -#define MV64360_SDMA_DEV_CS_2_TARGET 0x1b01 -#define MV64360_SDMA_DEV_CS_3_TARGET 0x1701 - -#define MV64360_SDMA_BOOT_CS_TARGET 0x0f00 - -#define MV64360_SDMA_SRAM_TARGET 0x0003 -#define MV64360_SDMA_60X_BUS_TARGET 0x4003 - -#define MV64360_PCI_0_TARGET 0x0003 -#define MV64360_PCI_1_TARGET 0x0004 - - -/* Devices BAR and size registers */ - -#define MV64360_DEV_CS0_BASE_ADDR 0x028 -#define MV64360_DEV_CS0_SIZE 0x030 -#define MV64360_DEV_CS1_BASE_ADDR 0x228 -#define MV64360_DEV_CS1_SIZE 0x230 -#define MV64360_DEV_CS2_BASE_ADDR 0x248 -#define MV64360_DEV_CS2_SIZE 0x250 -#define MV64360_DEV_CS3_BASE_ADDR 0x038 -#define MV64360_DEV_CS3_SIZE 0x040 -#define MV64360_BOOTCS_BASE_ADDR 0x238 -#define MV64360_BOOTCS_SIZE 0x240 - -/* SDMA Window access protection */ -#define MV64360_SDMA_WIN_ACCESS_NOT_ALLOWED 0 -#define MV64360_SDMA_WIN_ACCESS_READ_ONLY 1 -#define MV64360_SDMA_WIN_ACCESS_FULL 2 - -/* BRG Interrupts */ - -#define MV64360_BRG_CONFIG_REG(brg) (0xb200 + (brg<<3)) -#define MV64360_BRG_BAUDE_TUNING_REG(brg) (0xb204 + (brg<<3)) -#define MV64360_BRG_CAUSE_REG 0xb834 -#define MV64360_BRG_MASK_REG 0xb8b4 - -/****************************************/ -/* DMA Channel Control */ -/****************************************/ - -#define MV64360_DMA_CHANNEL0_CONTROL 0x840 -#define MV64360_DMA_CHANNEL0_CONTROL_HIGH 0x880 -#define MV64360_DMA_CHANNEL1_CONTROL 0x844 -#define MV64360_DMA_CHANNEL1_CONTROL_HIGH 0x884 -#define MV64360_DMA_CHANNEL2_CONTROL 0x848 -#define MV64360_DMA_CHANNEL2_CONTROL_HIGH 0x888 -#define MV64360_DMA_CHANNEL3_CONTROL 0x84C -#define MV64360_DMA_CHANNEL3_CONTROL_HIGH 0x88C - - -/****************************************/ -/* IDMA Registers */ -/****************************************/ - -#define MV64360_DMA_CHANNEL0_BYTE_COUNT 0x800 -#define MV64360_DMA_CHANNEL1_BYTE_COUNT 0x804 -#define MV64360_DMA_CHANNEL2_BYTE_COUNT 0x808 -#define MV64360_DMA_CHANNEL3_BYTE_COUNT 0x80C -#define MV64360_DMA_CHANNEL0_SOURCE_ADDR 0x810 -#define MV64360_DMA_CHANNEL1_SOURCE_ADDR 0x814 -#define MV64360_DMA_CHANNEL2_SOURCE_ADDR 0x818 -#define MV64360_DMA_CHANNEL3_SOURCE_ADDR 0x81c -#define MV64360_DMA_CHANNEL0_DESTINATION_ADDR 0x820 -#define MV64360_DMA_CHANNEL1_DESTINATION_ADDR 0x824 -#define MV64360_DMA_CHANNEL2_DESTINATION_ADDR 0x828 -#define MV64360_DMA_CHANNEL3_DESTINATION_ADDR 0x82C -#define MV64360_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830 -#define MV64360_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834 -#define MV64360_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838 -#define MV64360_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C -#define MV64360_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870 -#define MV64360_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874 -#define MV64360_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878 -#define MV64360_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C - - /* IDMA Address Decoding Base Address Registers */ - -#define MV64360_DMA_BASE_ADDR_REG0 0xa00 -#define MV64360_DMA_BASE_ADDR_REG1 0xa08 -#define MV64360_DMA_BASE_ADDR_REG2 0xa10 -#define MV64360_DMA_BASE_ADDR_REG3 0xa18 -#define MV64360_DMA_BASE_ADDR_REG4 0xa20 -#define MV64360_DMA_BASE_ADDR_REG5 0xa28 -#define MV64360_DMA_BASE_ADDR_REG6 0xa30 -#define MV64360_DMA_BASE_ADDR_REG7 0xa38 - - /* IDMA Address Decoding Size Address Register */ - -#define MV64360_DMA_SIZE_REG0 0xa04 -#define MV64360_DMA_SIZE_REG1 0xa0c -#define MV64360_DMA_SIZE_REG2 0xa14 -#define MV64360_DMA_SIZE_REG3 0xa1c -#define MV64360_DMA_SIZE_REG4 0xa24 -#define MV64360_DMA_SIZE_REG5 0xa2c -#define MV64360_DMA_SIZE_REG6 0xa34 -#define MV64360_DMA_SIZE_REG7 0xa3C - - /* IDMA Address Decoding High Address Remap and Access - Protection Registers */ - -#define MV64360_DMA_HIGH_ADDR_REMAP_REG0 0xa60 -#define MV64360_DMA_HIGH_ADDR_REMAP_REG1 0xa64 -#define MV64360_DMA_HIGH_ADDR_REMAP_REG2 0xa68 -#define MV64360_DMA_HIGH_ADDR_REMAP_REG3 0xa6C -#define MV64360_DMA_BASE_ADDR_ENABLE_REG 0xa80 -#define MV64360_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70 -#define MV64360_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74 -#define MV64360_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78 -#define MV64360_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c -#define MV64360_DMA_ARBITER_CONTROL 0x860 -#define MV64360_DMA_CROSS_BAR_TIMEOUT 0x8d0 - - /* IDMA Headers Retarget Registers */ - -#define MV64360_DMA_HEADERS_RETARGET_CONTROL 0xa84 -#define MV64360_DMA_HEADERS_RETARGET_BASE 0xa88 - - /* IDMA Interrupt Register */ - -#define MV64360_DMA_INTERRUPT_CAUSE_REG 0x8c0 -#define MV64360_DMA_INTERRUPT_CAUSE_MASK 0x8c4 -#define MV64360_DMA_ERROR_ADDR 0x8c8 -#define MV64360_DMA_ERROR_SELECT 0x8cc - - /* IDMA Debug Register ( for internal use ) */ - -#define MV64360_DMA_DEBUG_LOW 0x8e0 -#define MV64360_DMA_DEBUG_HIGH 0x8e4 -#define MV64360_DMA_SPARE 0xA8C - -/****************************************/ -/* Timer_Counter */ -/****************************************/ - -#define MV64360_TIMER_COUNTER0 0x850 -#define MV64360_TIMER_COUNTER1 0x854 -#define MV64360_TIMER_COUNTER2 0x858 -#define MV64360_TIMER_COUNTER3 0x85C -#define MV64360_TIMER_COUNTER_0_3_CONTROL 0x864 -#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 -#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c - -/****************************************/ -/* Watchdog registers */ -/****************************************/ - -#define MV64360_WATCHDOG_CONFIG_REG 0xb410 -#define MV64360_WATCHDOG_VALUE_REG 0xb414 - -/****************************************/ -/* I2C Registers */ -/****************************************/ - -#define MV64360_I2C_SLAVE_ADDR 0xc000 -#define MV64360_I2C_EXTENDED_SLAVE_ADDR 0xc010 -#define MV64360_I2C_DATA 0xc004 -#define MV64360_I2C_CONTROL 0xc008 -#define MV64360_I2C_STATUS_BAUDE_RATE 0xc00C -#define MV64360_I2C_SOFT_RESET 0xc01c - -/****************************************/ -/* GPP Interface Registers */ -/****************************************/ - -#define MV64360_GPP_IO_CONTROL 0xf100 -#define MV64360_GPP_LEVEL_CONTROL 0xf110 -#define MV64360_GPP_VALUE 0xf104 -#define MV64360_GPP_INTERRUPT_CAUSE 0xf108 -#define MV64360_GPP_INTERRUPT_MASK0 0xf10c -#define MV64360_GPP_INTERRUPT_MASK1 0xf114 -#define MV64360_GPP_VALUE_SET 0xf118 -#define MV64360_GPP_VALUE_CLEAR 0xf11c - -/****************************************/ -/* Interrupt Controller Registers */ -/****************************************/ - -/****************************************/ -/* Interrupts */ -/****************************************/ - -#define MV64360_MAIN_INTERRUPT_CAUSE_LOW 0x004 -#define MV64360_MAIN_INTERRUPT_CAUSE_HIGH 0x00c -#define MV64360_CPU_INTERRUPT0_MASK_LOW 0x014 -#define MV64360_CPU_INTERRUPT0_MASK_HIGH 0x01c -#define MV64360_CPU_INTERRUPT0_SELECT_CAUSE 0x024 -#define MV64360_CPU_INTERRUPT1_MASK_LOW 0x034 -#define MV64360_CPU_INTERRUPT1_MASK_HIGH 0x03c -#define MV64360_CPU_INTERRUPT1_SELECT_CAUSE 0x044 -#define MV64360_INTERRUPT0_MASK_0_LOW 0x054 -#define MV64360_INTERRUPT0_MASK_0_HIGH 0x05c -#define MV64360_INTERRUPT0_SELECT_CAUSE 0x064 -#define MV64360_INTERRUPT1_MASK_0_LOW 0x074 -#define MV64360_INTERRUPT1_MASK_0_HIGH 0x07c -#define MV64360_INTERRUPT1_SELECT_CAUSE 0x084 - -/****************************************/ -/* MPP Interface Registers */ -/****************************************/ - -#define MV64360_MPP_CONTROL0 0xf000 -#define MV64360_MPP_CONTROL1 0xf004 -#define MV64360_MPP_CONTROL2 0xf008 -#define MV64360_MPP_CONTROL3 0xf00c - -/****************************************/ -/* Serial Initialization registers */ -/****************************************/ - -#define MV64360_SERIAL_INIT_LAST_DATA 0xf324 -#define MV64360_SERIAL_INIT_CONTROL 0xf328 -#define MV64360_SERIAL_INIT_STATUS 0xf32c - - -#endif /* __INCgt64360rh */ diff --git a/board/esd/cpci750/pci.c b/board/esd/cpci750/pci.c deleted file mode 100644 index 59f170a..0000000 --- a/board/esd/cpci750/pci.c +++ /dev/null @@ -1,1028 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* PCI.c - PCI functions */ - - -#include <common.h> -#ifdef CONFIG_PCI -#include <pci.h> - -#include "../../Marvell/include/pci.h" - -#undef DEBUG -#undef IDE_SET_NATIVE_MODE -static unsigned int local_buses[] = { 0, 0 }; - -static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = { - {0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 }, - {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 }, -}; - -#ifdef CONFIG_USE_CPCIDVI -typedef struct { - unsigned int base; - unsigned int init; -} GT_CPCIDVI_ROM_T; - -static GT_CPCIDVI_ROM_T gt_cpcidvi_rom = {0, 0}; -#endif - -#ifdef DEBUG -static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE }; -static void gt_pci_bus_mode_display (PCI_HOST host) -{ - unsigned int mode; - - - mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4; - switch (mode) { - case 0: - printf ("PCI %d bus mode: Conventional PCI\n", host); - break; - case 1: - printf ("PCI %d bus mode: 66 MHz PCIX\n", host); - break; - case 2: - printf ("PCI %d bus mode: 100 MHz PCIX\n", host); - break; - case 3: - printf ("PCI %d bus mode: 133 MHz PCIX\n", host); - break; - default: - printf ("Unknown BUS %d\n", mode); - } -} -#endif - -static const unsigned int pci_p2p_configuration_reg[] = { - PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION -}; - -static const unsigned int pci_configuration_address[] = { - PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS -}; - -static const unsigned int pci_configuration_data[] = { - PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, - PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER -}; - -static const unsigned int pci_error_cause_reg[] = { - PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE -}; - -static const unsigned int pci_arbiter_control[] = { - PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL -}; - -static const unsigned int pci_address_space_en[] = { - PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE -}; - -static const unsigned int pci_snoop_control_base_0_low[] = { - PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW -}; -static const unsigned int pci_snoop_control_top_0[] = { - PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0 -}; - -static const unsigned int pci_access_control_base_0_low[] = { - PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW -}; -static const unsigned int pci_access_control_top_0[] = { - PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0 -}; - -static const unsigned int pci_scs_bank_size[2][4] = { - {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE, - PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE}, - {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE, - PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE} -}; - -static const unsigned int pci_p2p_configuration[] = { - PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION -}; - - -/******************************************************************** -* pciWriteConfigReg - Write to a PCI configuration register -* - Make sure the GT is configured as a master before writing -* to another device on the PCI. -* - The function takes care of Big/Little endian conversion. -* -* -* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec -* (or any other PCI device spec) -* pciDevNum: The device number needs to be addressed. -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum, unsigned int data) -{ - volatile unsigned int DataForAddrReg; - unsigned int functionNum; - unsigned int busNum = 0; - unsigned int addr; - - if (pciDevNum > 32) /* illegal device Number */ - return; - if (pciDevNum == SELF) { /* configure our configuration space. */ - pciDevNum = - (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & - 0x1f; - busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & - 0xff0000; - } - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xfc; - DataForAddrReg = - (regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); - GT_REG_READ (pci_configuration_address[host], &addr); - if (addr != DataForAddrReg) - return; - GT_REG_WRITE (pci_configuration_data[host], data); -} - -/******************************************************************** -* pciReadConfigReg - Read from a PCI0 configuration register -* - Make sure the GT is configured as a master before reading -* from another device on the PCI. -* - The function takes care of Big/Little endian conversion. -* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec) -* pciDevNum: The device number needs to be addressed. -* RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum) -{ - volatile unsigned int DataForAddrReg; - unsigned int data; - unsigned int functionNum; - unsigned int busNum = 0; - - if (pciDevNum > 32) /* illegal device Number */ - return 0xffffffff; - if (pciDevNum == SELF) { /* configure our configuration space. */ - pciDevNum = - (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & - 0x1f; - busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & - 0xff0000; - } - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xfc; - DataForAddrReg = - (regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); - GT_REG_READ (pci_configuration_address[host], &data); - if (data != DataForAddrReg) - return 0xffffffff; - GT_REG_READ (pci_configuration_data[host], &data); - return data; -} - -/******************************************************************** -* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where -* the agent is placed on another Bus. For more -* information read P2P in the PCI spec. -* -* Inputs: unsigned int regOffset - The register offset as it apears in the -* GT spec (or any other PCI device spec). -* unsigned int pciDevNum - The device number needs to be addressed. -* unsigned int busNum - On which bus does the Target agent connect -* to. -* unsigned int data - data to be written. -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -* The configuration Address is configure as type-I (bits[1:0] = '01') due to -* PCI spec referring to P2P. -* -*********************************************************************/ -void pciOverBridgeWriteConfigReg (PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum, unsigned int data) -{ - unsigned int DataForReg; - unsigned int functionNum; - - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - busNum = busNum << 16; - if (pciDevNum == SELF) { /* This board */ - DataForReg = (regOffset | pciDevNum | functionNum) | BIT0; - } else { - DataForReg = (regOffset | pciDevNum | functionNum | busNum) | - BIT31 | BIT0; - } - GT_REG_WRITE (pci_configuration_address[host], DataForReg); - GT_REG_WRITE (pci_configuration_data[host], data); -} - - -/******************************************************************** -* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where -* the agent target locate on another PCI bus. -* - Make sure the GT is configured as a master -* before reading from another device on the PCI. -* - The function takes care of Big/Little endian -* conversion. -* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec). (configuration register offset.) -* pciDevNum: The device number needs to be addressed. -* busNum: the Bus number where the agent is place. -* RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -unsigned int pciOverBridgeReadConfigReg (PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum) -{ - unsigned int DataForReg; - unsigned int data; - unsigned int functionNum; - - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - busNum = busNum << 16; - if (pciDevNum == SELF) { /* This board */ - DataForReg = (regOffset | pciDevNum | functionNum) | BIT31; - } else { /* agent on another bus */ - - DataForReg = (regOffset | pciDevNum | functionNum | busNum) | - BIT0 | BIT31; - } - GT_REG_WRITE (pci_configuration_address[host], DataForReg); - GT_REG_READ (pci_configuration_data[host], &data); - return data; -} - - -/******************************************************************** -* pciGetRegOffset - Gets the register offset for this region config. -* -* INPUT: Bus, Region - The bus and region we ask for its base address. -* OUTPUT: N/A -* RETURNS: PCI register base address -*********************************************************************/ -static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region) -{ - switch (host) { - case PCI_HOST0: - switch (region) { - case PCI_IO: - return PCI_0I_O_LOW_DECODE_ADDRESS; - case PCI_REGION0: - return PCI_0MEMORY0_LOW_DECODE_ADDRESS; - case PCI_REGION1: - return PCI_0MEMORY1_LOW_DECODE_ADDRESS; - case PCI_REGION2: - return PCI_0MEMORY2_LOW_DECODE_ADDRESS; - case PCI_REGION3: - return PCI_0MEMORY3_LOW_DECODE_ADDRESS; - } - case PCI_HOST1: - switch (region) { - case PCI_IO: - return PCI_1I_O_LOW_DECODE_ADDRESS; - case PCI_REGION0: - return PCI_1MEMORY0_LOW_DECODE_ADDRESS; - case PCI_REGION1: - return PCI_1MEMORY1_LOW_DECODE_ADDRESS; - case PCI_REGION2: - return PCI_1MEMORY2_LOW_DECODE_ADDRESS; - case PCI_REGION3: - return PCI_1MEMORY3_LOW_DECODE_ADDRESS; - } - } - return PCI_0MEMORY0_LOW_DECODE_ADDRESS; -} - -static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region) -{ - switch (host) { - case PCI_HOST0: - switch (region) { - case PCI_IO: - return PCI_0I_O_ADDRESS_REMAP; - case PCI_REGION0: - return PCI_0MEMORY0_ADDRESS_REMAP; - case PCI_REGION1: - return PCI_0MEMORY1_ADDRESS_REMAP; - case PCI_REGION2: - return PCI_0MEMORY2_ADDRESS_REMAP; - case PCI_REGION3: - return PCI_0MEMORY3_ADDRESS_REMAP; - } - case PCI_HOST1: - switch (region) { - case PCI_IO: - return PCI_1I_O_ADDRESS_REMAP; - case PCI_REGION0: - return PCI_1MEMORY0_ADDRESS_REMAP; - case PCI_REGION1: - return PCI_1MEMORY1_ADDRESS_REMAP; - case PCI_REGION2: - return PCI_1MEMORY2_ADDRESS_REMAP; - case PCI_REGION3: - return PCI_1MEMORY3_ADDRESS_REMAP; - } - } - return PCI_0MEMORY0_ADDRESS_REMAP; -} - -/******************************************************************** -* pciGetBaseAddress - Gets the base address of a PCI. -* - If the PCI size is 0 then this base address has no meaning!!! -* -* -* INPUT: Bus, Region - The bus and region we ask for its base address. -* OUTPUT: N/A -* RETURNS: PCI base address. -*********************************************************************/ -unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region) -{ - unsigned int regBase; - unsigned int regEnd; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, ®Base); - GT_REG_READ (regOffset + 8, ®End); - - if (regEnd <= regBase) - return 0xffffffff; /* ERROR !!! */ - - regBase = regBase << 16; - return regBase; -} - -bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase, - unsigned int bankBase, unsigned int bankLength) -{ - unsigned int low = 0xfff; - unsigned int high = 0x0; - unsigned int regOffset = pciGetRegOffset (host, region); - unsigned int remapOffset = pciGetRemapOffset (host, region); - - if (bankLength != 0) { - low = (bankBase >> 16) & 0xffff; - high = ((bankBase + bankLength) >> 16) - 1; - } - - GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */ - GT_REG_WRITE (regOffset + 8, high); - - if (bankLength != 0) { /* must do AFTER writing maps */ - GT_REG_WRITE (remapOffset, remapBase >> 16); /* sorry, 32 bits only. - dont support upper 32 - in this driver */ - } - return true; -} - -unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region) -{ - unsigned int low; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, &low); - return (low & 0xffff) << 16; -} - -unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region) -{ - unsigned int low, high; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, &low); - GT_REG_READ (regOffset + 8, &high); - return ((high & 0xffff) + 1) << 16; -} - - -/* ronen - 7/Dec/03*/ -/******************************************************************** -* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS. -* Inputs: one of the PCI BAR -*********************************************************************/ -void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR) -{ - RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR); -} - -void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR) -{ - SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR); -} - -/******************************************************************** -* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave. -* -* Inputs: base and size of PCI SCS -*********************************************************************/ -void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank, - unsigned int pciDramBase, unsigned int pciDramSize) -{ - /*ronen different function for 3rd bank. */ - unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8; - - pciDramBase = pciDramBase & 0xfffff000; - pciDramBase = pciDramBase | (pciReadConfigReg (host, - PCI_SCS_0_BASE_ADDRESS - + offset, - SELF) & 0x00000fff); - pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF, - pciDramBase); - if (pciDramSize == 0) - pciDramSize++; - GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1); - gtPciEnableInternalBAR (host, bank); -} - -/******************************************************************** -* pciSetRegionFeatures - This function modifys one of the 8 regions with -* feature bits given as an input. -* - Be advised to check the spec before modifying them. -* Inputs: PCI_PROTECT_REGION region - one of the eight regions. -* unsigned int features - See file: pci.h there are defintion for those -* region features. -* unsigned int baseAddress - The region base Address. -* unsigned int topAddress - The region top Address. -* Returns: false if one of the parameters is erroneous true otherwise. -*********************************************************************/ -bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region, - unsigned int features, unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int accessLow; - unsigned int accessHigh; - unsigned int accessTop = baseAddress + regionLength; - - if (regionLength == 0) { /* close the region. */ - pciDisableAccessRegion (host, region); - return true; - } - /* base Address is store is bits [11:0] */ - accessLow = (baseAddress & 0xfff00000) >> 20; - /* All the features are update according to the defines in pci.h (to be on - the safe side we disable bits: [11:0] */ - accessLow = accessLow | (features & 0xfffff000); - /* write to the Low Access Region register */ - GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, - accessLow); - - accessHigh = (accessTop & 0xfff00000) >> 20; - - /* write to the High Access Region register */ - GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, - accessHigh - 1); - return true; -} - -/******************************************************************** -* pciDisableAccessRegion - Disable The given Region by writing MAX size -* to its low Address and MIN size to its high Address. -* -* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled. -* Returns: N/A. -*********************************************************************/ -void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region) -{ - /* writing back the registers default values. */ - GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, - 0x01001fff); - GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0); -} - -/******************************************************************** -* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism. -* -* Inputs: N/A -* Returns: true. -*********************************************************************/ -bool pciArbiterEnable (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31); - return true; -} - -/******************************************************************** -* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism. -* -* Inputs: N/A -* Returns: true -*********************************************************************/ -bool pciArbiterDisable (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff); - return true; -} - -/******************************************************************** -* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low) -* -* Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent. -* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent. -* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent. -* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent. -* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent. -* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent. -* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent. -* Returns: true -*********************************************************************/ -bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent, - PCI_AGENT_PRIO externalAgent0, - PCI_AGENT_PRIO externalAgent1, - PCI_AGENT_PRIO externalAgent2, - PCI_AGENT_PRIO externalAgent3, - PCI_AGENT_PRIO externalAgent4, - PCI_AGENT_PRIO externalAgent5) -{ - unsigned int regData; - unsigned int writeData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - writeData = (internalAgent << 7) + (externalAgent0 << 8) + - (externalAgent1 << 9) + (externalAgent2 << 10) + - (externalAgent3 << 11) + (externalAgent4 << 12) + - (externalAgent5 << 13); - regData = (regData & 0xffffc07f) | writeData; - GT_REG_WRITE (pci_arbiter_control[host], regData & regData); - return true; -} - -/******************************************************************** -* pciParkingDisable - Park on last option disable, with this function you can -* disable the park on last mechanism for each agent. -* disabling this option for all agents results parking -* on the internal master. -* -* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent. -* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. -* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. -* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. -* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. -* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. -* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. -* Returns: true -*********************************************************************/ -bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent, - PCI_AGENT_PARK externalAgent0, - PCI_AGENT_PARK externalAgent1, - PCI_AGENT_PARK externalAgent2, - PCI_AGENT_PARK externalAgent3, - PCI_AGENT_PARK externalAgent4, - PCI_AGENT_PARK externalAgent5) -{ - unsigned int regData; - unsigned int writeData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - writeData = (internalAgent << 14) + (externalAgent0 << 15) + - (externalAgent1 << 16) + (externalAgent2 << 17) + - (externalAgent3 << 18) + (externalAgent4 << 19) + - (externalAgent5 << 20); - regData = (regData & ~(0x7f << 14)) | writeData; - GT_REG_WRITE (pci_arbiter_control[host], regData); - return true; -} - -/******************************************************************** -* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to -* respond to grant assertion within a window specified in -* the input value: 'brokenValue'. -* -* Inputs: unsigned char brokenValue - A value which limits the Master to hold the -* grant without asserting frame. -* Returns: Error for illegal broken value otherwise true. -*********************************************************************/ -bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue) -{ - unsigned int data; - unsigned int regData; - - if (brokenValue > 0xf) - return false; /* brokenValue must be 4 bit */ - data = brokenValue << 3; - GT_REG_READ (pci_arbiter_control[host], ®Data); - regData = (regData & 0xffffff87) | data; - GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1); - return true; -} - -/******************************************************************** -* pciDisableBrokenAgentDetection - This function disable the Broken agent -* Detection mechanism. -* NOTE: This operation may cause a dead lock on the -* pci0 arbitration. -* -* Inputs: N/A -* Returns: true. -*********************************************************************/ -bool pciDisableBrokenAgentDetection (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - regData = regData & 0xfffffffd; - GT_REG_WRITE (pci_arbiter_control[host], regData); - return true; -} - -/******************************************************************** -* pciP2PConfig - This function set the PCI_n P2P configurate. -* For more information on the P2P read PCI spec. -* -* Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower -* Boundry. -* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper -* Boundry. -* unsigned int busNum - The CPI bus number to which the PCI interface -* is connected. -* unsigned int devNum - The PCI interface's device number. -* -* Returns: true. -*********************************************************************/ -bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow, - unsigned int SecondBusHigh, - unsigned int busNum, unsigned int devNum) -{ - unsigned int regData; - - regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) | - ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24); - GT_REG_WRITE (pci_p2p_configuration[host], regData); - return true; -} - -/******************************************************************** -* pciSetRegionSnoopMode - This function modifys one of the 4 regions which -* supports Cache Coherency in the PCI_n interface. -* Inputs: region - One of the four regions. -* snoopType - There is four optional Types: -* 1. No Snoop. -* 2. Snoop to WT region. -* 3. Snoop to WB region. -* 4. Snoop & Invalidate to WB region. -* baseAddress - Base Address of this region. -* regionLength - Region length. -* Returns: false if one of the parameters is wrong otherwise return true. -*********************************************************************/ -bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region, - PCI_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int snoopXbaseAddress; - unsigned int snoopXtopAddress; - unsigned int data; - unsigned int snoopHigh = baseAddress + regionLength; - - if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB)) - return false; - snoopXbaseAddress = - pci_snoop_control_base_0_low[host] + 0x10 * region; - snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region; - if (regionLength == 0) { /* closing the region */ - GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff); - GT_REG_WRITE (snoopXtopAddress, 0); - return true; - } - baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ - data = (baseAddress >> 20) | snoopType << 12; - GT_REG_WRITE (snoopXbaseAddress, data); - snoopHigh = (snoopHigh & 0xfff00000) >> 20; - GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1); - return true; -} - -static int gt_read_config_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, u32 * value) -{ - int bus = PCI_BUS (dev); - - if ((bus == local_buses[0]) || (bus == local_buses[1])) { - *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, - offset | (PCI_FUNC(dev) << 8), - PCI_DEV (dev)); - } else { - *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->cfg_addr, - offset | (PCI_FUNC(dev) << 8), - PCI_DEV (dev), bus); - } - - return 0; -} - -static int gt_write_config_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, u32 value) -{ - int bus = PCI_BUS (dev); - - if ((bus == local_buses[0]) || (bus == local_buses[1])) { - pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, - offset | (PCI_FUNC(dev) << 8), - PCI_DEV (dev), value); - } else { - pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr, - offset | (PCI_FUNC(dev) << 8), - PCI_DEV (dev), bus, - value); - } - return 0; -} - - -static void gt_setup_ide (struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *entry) -{ - static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 }; - u32 bar_response, bar_value; - int bar; - - if (CPCI750_SLAVE_TEST != 0) - return; - - for (bar = 0; bar < 6; bar++) { - /*ronen different function for 3rd bank. */ - unsigned int offset = - (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8; - - pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset, - 0x0); - pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset, - &bar_response); - - pciauto_region_allocate (bar_response & - PCI_BASE_ADDRESS_SPACE_IO ? hose-> - pci_io : hose->pci_mem, ide_bar[bar], - &bar_value); - - pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + bar * 4, - bar_value); - } -} - -#ifdef CONFIG_USE_CPCIDVI -static void gt_setup_cpcidvi (struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *entry) -{ - u32 bar_value, pci_response; - - if (CPCI750_SLAVE_TEST != 0) - return; - - pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response); - pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff); - pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pci_response); - pciauto_region_allocate (hose->pci_mem, 0x01000000, &bar_value); - pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, (bar_value & 0xffffff00)); - pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, 0x0); - pciauto_region_allocate (hose->pci_mem, 0x40000, &bar_value); - pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, (bar_value & 0xffffff00) | 0x01); - gt_cpcidvi_rom.base = bar_value & 0xffffff00; - gt_cpcidvi_rom.init = 1; -} - -unsigned char gt_cpcidvi_in8(unsigned int offset) -{ - unsigned char data; - - if (gt_cpcidvi_rom.init == 0) { - return(0); - } - data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base); - return(data); -} - -void gt_cpcidvi_out8(unsigned int offset, unsigned char data) -{ - unsigned int off; - - if (gt_cpcidvi_rom.init == 0) { - return; - } - off = data; - off = ((off << 3) & 0x7f8) + (offset & 0x4) + 0x3e000 + gt_cpcidvi_rom.base; - in8(off); - return; -} -#endif - -/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */ -/* and is curently not called *. */ -#if 0 -static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char pin, irq; - - pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin); - - if (pin == 1) { /* only allow INT A */ - irq = pci_irq_swizzle[(PCI_HOST) hose-> - cfg_addr][PCI_DEV (dev)]; - if (irq) - pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq); - } -} -#endif - -struct pci_config_table gt_config_table[] = { -#ifdef CONFIG_USE_CPCIDVI - {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030, PCI_CLASS_DISPLAY_VGA, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_cpcidvi}, -#endif - {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide}, - {} -}; - -struct pci_controller pci0_hose = { -/* fixup_irq: gt_fixup_irq, */ - config_table:gt_config_table, -}; - -struct pci_controller pci1_hose = { -/* fixup_irq: gt_fixup_irq, */ - config_table:gt_config_table, -}; - -void pci_init_board (void) -{ - unsigned int command; - unsigned int slave; -#ifdef CONFIG_PCI_PNP - unsigned int bar; -#endif -#ifdef DEBUG - gt_pci_bus_mode_display (PCI_HOST0); -#endif -#ifdef CONFIG_USE_CPCIDVI - gt_cpcidvi_rom.init = 0; - gt_cpcidvi_rom.base = 0; -#endif - - slave = CPCI750_SLAVE_TEST; - - pci0_hose.config_table = gt_config_table; - pci1_hose.config_table = gt_config_table; - -#ifdef CONFIG_USE_CPCIDVI - gt_config_table[0].config_device = gt_setup_cpcidvi; -#endif - gt_config_table[1].config_device = gt_setup_ide; - - pci0_hose.first_busno = 0; - pci0_hose.last_busno = 0xff; - local_buses[0] = pci0_hose.first_busno; - - /* PCI memory space */ - pci_set_region (pci0_hose.regions + 0, - CONFIG_SYS_PCI0_0_MEM_SPACE, - CONFIG_SYS_PCI0_0_MEM_SPACE, - CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (pci0_hose.regions + 1, - CONFIG_SYS_PCI0_IO_SPACE_PCI, - CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO); - - pci_set_ops (&pci0_hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - gt_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - gt_write_config_dword); - pci0_hose.region_count = 2; - - pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0; - - pci_register_hose (&pci0_hose); - if (slave == 0) { - pciArbiterEnable (PCI_HOST0); - pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1); - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - -#ifdef CONFIG_PCI_PNP - pciauto_config_init(&pci0_hose); - pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar); -#endif -#ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Bus Dev VenId DevId Class Int\n"); -#endif - pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose, - pci0_hose.first_busno); - -#ifdef DEBUG - gt_pci_bus_mode_display (PCI_HOST1); -#endif - } else { - pciArbiterDisable (PCI_HOST0); - pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1); - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - pci0_hose.last_busno = pci0_hose.first_busno; - } - pci1_hose.first_busno = pci0_hose.last_busno + 1; - pci1_hose.last_busno = 0xff; - pci1_hose.current_busno = pci1_hose.first_busno; - local_buses[1] = pci1_hose.first_busno; - - /* PCI memory space */ - pci_set_region (pci1_hose.regions + 0, - CONFIG_SYS_PCI1_0_MEM_SPACE, - CONFIG_SYS_PCI1_0_MEM_SPACE, - CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (pci1_hose.regions + 1, - CONFIG_SYS_PCI1_IO_SPACE_PCI, - CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); - - pci_set_ops (&pci1_hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - gt_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - gt_write_config_dword); - - pci1_hose.region_count = 2; - - pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1; - - pci_register_hose (&pci1_hose); - - pciArbiterEnable (PCI_HOST1); - pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1); - - command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); - -#ifdef CONFIG_PCI_PNP - pciauto_config_init(&pci1_hose); - pciauto_region_allocate(pci1_hose.pci_io, 0x400, &bar); -#endif - pci1_hose.last_busno = pci_hose_scan_bus (&pci1_hose, pci1_hose.first_busno); - - command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); - -} -#endif /* of CONFIG_PCI */ diff --git a/board/esd/cpci750/sdram_init.c b/board/esd/cpci750/sdram_init.c deleted file mode 100644 index 89f94aa..0000000 --- a/board/esd/cpci750/sdram_init.c +++ /dev/null @@ -1,1702 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * adaption for the Marvell DB64360 Board - * Ingo Assmus (ingo.assmus@keymile.com) - * - * adaption for the cpci750 Board - * Reinhard Arlt (reinhard.arlt@esd-electronics.com) - *************************************************************************/ - - -/* sdram_init.c - automatic memory sizing */ - -#include <common.h> -#include <74xx_7xx.h> -#include "../../Marvell/include/memory.h" -#include "../../Marvell/include/pci.h" -#include "../../Marvell/include/mv_gen_reg.h" -#include <net.h> - -#include "eth.h" -#include "mpsc.h" -#include "../../Marvell/common/i2c.h" -#include "64360.h" -#include "mv_regs.h" - -DECLARE_GLOBAL_DATA_PTR; - -int set_dfcdlInit(void); /* setup delay line of Mv64360 */ - -/* ------------------------------------------------------------------------- */ - -int -memory_map_bank(unsigned int bankNo, - unsigned int bankBase, - unsigned int bankLength) -{ -#ifdef MAP_PCI - PCI_HOST host; -#endif - - -#ifdef DEBUG - if (bankLength > 0) { - printf("mapping bank %d at %08x - %08x\n", - bankNo, bankBase, bankBase + bankLength - 1); - } else { - printf("unmapping bank %d\n", bankNo); - } -#endif - - memoryMapBank(bankNo, bankBase, bankLength); - -#ifdef MAP_PCI - for (host=PCI_HOST0;host<=PCI_HOST1;host++) { - const int features= - PREFETCH_ENABLE | - DELAYED_READ_ENABLE | - AGGRESSIVE_PREFETCH | - READ_LINE_AGGRESSIVE_PREFETCH | - READ_MULTI_AGGRESSIVE_PREFETCH | - MAX_BURST_4 | - PCI_NO_SWAP; - - pciMapMemoryBank(host, bankNo, bankBase, bankLength); - - pciSetRegionSnoopMode(host, bankNo, PCI_SNOOP_WB, bankBase, - bankLength); - - pciSetRegionFeatures(host, bankNo, features, bankBase, bankLength); - } -#endif - return 0; -} - -#define GB (1 << 30) - -/* much of this code is based on (or is) the code in the pip405 port */ -/* thanks go to the authors of said port - Josh */ - -/* structure to store the relevant information about an sdram bank */ -typedef struct sdram_info { - uchar drb_size; - uchar registered, ecc; - uchar tpar; - uchar tras_clocks; - uchar burst_len; - uchar banks, slot; -} sdram_info_t; - -/* Typedefs for 'gtAuxilGetDIMMinfo' function */ - -typedef enum _memoryType {SDRAM, DDR} MEMORY_TYPE; - -typedef enum _voltageInterface {TTL_5V_TOLERANT, LVTTL, HSTL_1_5V, - SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN, - } VOLTAGE_INTERFACE; - -typedef enum _max_CL_supported_DDR {DDR_CL_1=1, DDR_CL_1_5=2, DDR_CL_2=4, DDR_CL_2_5=8, DDR_CL_3=16, DDR_CL_3_5=32, DDR_CL_FAULT} MAX_CL_SUPPORTED_DDR; -typedef enum _max_CL_supported_SD {SD_CL_1=1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7, SD_FAULT} MAX_CL_SUPPORTED_SD; - - -/* SDRAM/DDR information struct */ -typedef struct _gtMemoryDimmInfo { - MEMORY_TYPE memoryType; - unsigned int numOfRowAddresses; - unsigned int numOfColAddresses; - unsigned int numOfModuleBanks; - unsigned int dataWidth; - VOLTAGE_INTERFACE voltageInterface; - unsigned int errorCheckType; /* ECC , PARITY.. */ - unsigned int sdramWidth; /* 4,8,16 or 32 */ ; - unsigned int errorCheckDataWidth; /* 0 - no, 1 - Yes */ - unsigned int minClkDelay; - unsigned int burstLengthSupported; - unsigned int numOfBanksOnEachDevice; - unsigned int suportedCasLatencies; - unsigned int RefreshInterval; - unsigned int maxCASlatencySupported_LoP; /* LoP left of point (measured in ns) */ - unsigned int maxCASlatencySupported_RoP; /* RoP right of point (measured in ns) */ - MAX_CL_SUPPORTED_DDR maxClSupported_DDR; - MAX_CL_SUPPORTED_SD maxClSupported_SD; - unsigned int moduleBankDensity; - /* module attributes (true for yes) */ - bool bufferedAddrAndControlInputs; - bool registeredAddrAndControlInputs; - bool onCardPLL; - bool bufferedDQMBinputs; - bool registeredDQMBinputs; - bool differentialClockInput; - bool redundantRowAddressing; - - /* module general attributes */ - bool suportedAutoPreCharge; - bool suportedPreChargeAll; - bool suportedEarlyRasPreCharge; - bool suportedWrite1ReadBurst; - bool suported5PercentLowVCC; - bool suported5PercentUpperVCC; - /* module timing parameters */ - unsigned int minRasToCasDelay; - unsigned int minRowActiveRowActiveDelay; - unsigned int minRasPulseWidth; - unsigned int minRowPrechargeTime; /* measured in ns */ - - int addrAndCommandHoldTime; /* LoP left of point (measured in ns) */ - int addrAndCommandSetupTime; /* (measured in ns/100) */ - int dataInputSetupTime; /* LoP left of point (measured in ns) */ - int dataInputHoldTime; /* LoP left of point (measured in ns) */ -/* tAC times for highest 2nd and 3rd highest CAS Latency values */ - unsigned int clockToDataOut_LoP; /* LoP left of point (measured in ns) */ - unsigned int clockToDataOut_RoP; /* RoP right of point (measured in ns) */ - unsigned int clockToDataOutMinus1_LoP; /* LoP left of point (measured in ns) */ - unsigned int clockToDataOutMinus1_RoP; /* RoP right of point (measured in ns) */ - unsigned int clockToDataOutMinus2_LoP; /* LoP left of point (measured in ns) */ - unsigned int clockToDataOutMinus2_RoP; /* RoP right of point (measured in ns) */ - - unsigned int minimumCycleTimeAtMaxCasLatancy_LoP; /* LoP left of point (measured in ns) */ - unsigned int minimumCycleTimeAtMaxCasLatancy_RoP; /* RoP right of point (measured in ns) */ - - unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */ - unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns) */ - - unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */ - unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns) */ - - /* Parameters calculated from - the extracted DIMM information */ - unsigned int size; - unsigned int deviceDensity; /* 16,64,128,256 or 512 Mbit */ - unsigned int numberOfDevices; - uchar drb_size; /* DRAM size in n*64Mbit */ - uchar slot; /* Slot Number this module is inserted in */ - uchar spd_raw_data[128]; /* Content of SPD-EEPROM copied 1:1 */ -#ifdef DEBUG - uchar manufactura[8]; /* Content of SPD-EEPROM Byte 64-71 */ - uchar modul_id[18]; /* Content of SPD-EEPROM Byte 73-90 */ - uchar vendor_data[27]; /* Content of SPD-EEPROM Byte 99-125 */ - unsigned long modul_serial_no; /* Content of SPD-EEPROM Byte 95-98 */ - unsigned int manufac_date; /* Content of SPD-EEPROM Byte 93-94 */ - unsigned int modul_revision; /* Content of SPD-EEPROM Byte 91-92 */ - uchar manufac_place; /* Content of SPD-EEPROM Byte 72 */ - -#endif -} AUX_MEM_DIMM_INFO; - - -/* - * translate ns.ns/10 coding of SPD timing values - * into 10 ps unit values - */ -static inline unsigned short -NS10to10PS(unsigned char spd_byte) -{ - unsigned short ns, ns10; - - /* isolate upper nibble */ - ns = (spd_byte >> 4) & 0x0F; - /* isolate lower nibble */ - ns10 = (spd_byte & 0x0F); - - return(ns*100 + ns10*10); -} - -/* - * translate ns coding of SPD timing values - * into 10 ps unit values - */ -static inline unsigned short -NSto10PS(unsigned char spd_byte) -{ - return(spd_byte*100); -} - -/* This code reads the SPD chip on the sdram and populates - * the array which is passed in with the relevant information */ -/* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */ -static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) -{ - uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; - int ret; - unsigned int i, j, density = 1, devicesForErrCheck = 0; - -#ifdef DEBUG - unsigned int k; -#endif - unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp; - int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint; - uchar supp_cal, cal_val; - ulong memclk, tmemclk; - ulong tmp; - uchar trp_clocks = 0, tras_clocks; - uchar data[128]; - - memclk = gd->bus_clk; - tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ - - memset (data, 0, sizeof (data)); - - - ret = 0; - - debug("before i2c read\n"); - - ret = i2c_read (addr, 0, 2, data, 128); - - debug("after i2c read\n"); - - if ((data[64] != 'e') || (data[65] != 's') || (data[66] != 'd') - || (data[67] != '-') || (data[68] != 'g') || (data[69] != 'm') - || (data[70] != 'b') || (data[71] != 'h')) { - ret = -1; - } - - if ((ret != 0) && (slot == 0)) { - memset (data, 0, sizeof (data)); - data[0] = 0x80; - data[1] = 0x08; - data[2] = 0x07; - data[3] = 0x0c; - data[4] = 0x09; - data[5] = 0x01; - data[6] = 0x48; - data[7] = 0x00; - data[8] = 0x04; - data[9] = 0x75; - data[10] = 0x80; - data[11] = 0x02; - data[12] = 0x80; - data[13] = 0x10; - data[14] = 0x08; - data[15] = 0x01; - data[16] = 0x0e; - data[17] = 0x04; - data[18] = 0x0c; - data[19] = 0x01; - data[20] = 0x02; - data[21] = 0x20; - data[22] = 0x00; - data[23] = 0xa0; - data[24] = 0x80; - data[25] = 0x00; - data[26] = 0x00; - data[27] = 0x50; - data[28] = 0x3c; - data[29] = 0x50; - data[30] = 0x32; - data[31] = 0x10; - data[32] = 0xb0; - data[33] = 0xb0; - data[34] = 0x60; - data[35] = 0x60; - data[64] = 'e'; - data[65] = 's'; - data[66] = 'd'; - data[67] = '-'; - data[68] = 'g'; - data[69] = 'm'; - data[70] = 'b'; - data[71] = 'h'; - ret = 0; - } - - /* zero all the values */ - memset (dimmInfo, 0, sizeof (*dimmInfo)); - - /* copy the SPD content 1:1 into the dimmInfo structure */ - for (i = 0; i <= 127; i++) { - dimmInfo->spd_raw_data[i] = data[i]; - } - - if (ret) { - debug("No DIMM in slot %d [err = %x]\n", slot, ret); - return 0; - } else - dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */ - -#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT - - for (i = 0; i <= 127; i++) { - printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i], - data[i]); - } - -#endif -#ifdef DEBUG - /* find Manufacturer of Dimm Module */ - for (i = 0; i < sizeof (dimmInfo->manufactura); i++) { - dimmInfo->manufactura[i] = data[64 + i]; - } - printf ("\nThis RAM-Module is produced by: %s\n", - dimmInfo->manufactura); - - /* find Manul-ID of Dimm Module */ - for (i = 0; i < sizeof (dimmInfo->modul_id); i++) { - dimmInfo->modul_id[i] = data[73 + i]; - } - printf ("The Module-ID of this RAM-Module is: %s\n", - dimmInfo->modul_id); - - /* find Vendor-Data of Dimm Module */ - for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) { - dimmInfo->vendor_data[i] = data[99 + i]; - } - printf ("Vendor Data of this RAM-Module is: %s\n", - dimmInfo->vendor_data); - - /* find modul_serial_no of Dimm Module */ - dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95]))); - printf ("Serial No. of this RAM-Module is: %ld (%lx)\n", - dimmInfo->modul_serial_no, dimmInfo->modul_serial_no); - - /* find Manufac-Data of Dimm Module */ - dimmInfo->manufac_date = (*((unsigned int *) (&data[93]))); - printf ("Manufactoring Date of this RAM-Module is: %d.%d\n", data[93], data[94]); /*dimmInfo->manufac_date */ - - /* find modul_revision of Dimm Module */ - dimmInfo->modul_revision = (*((unsigned int *) (&data[91]))); - printf ("Module Revision of this RAM-Module is: %d.%d\n", data[91], data[92]); /* dimmInfo->modul_revision */ - - /* find manufac_place of Dimm Module */ - dimmInfo->manufac_place = (*((unsigned char *) (&data[72]))); - printf ("manufac_place of this RAM-Module is: %d\n", - dimmInfo->manufac_place); - -#endif -/*------------------------------------------------------------------------------------------------------------------------------*/ -/* calculate SPD checksum */ -/*------------------------------------------------------------------------------------------------------------------------------*/ -#if 0 /* test-only */ - spd_checksum = 0; - - for (i = 0; i <= 62; i++) { - spd_checksum += data[i]; - } - - if ((spd_checksum & 0xff) != data[63]) { - printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]); - hang (); - } - - else - printf ("SPD Checksum ok!\n"); -#endif /* test-only */ - -/*------------------------------------------------------------------------------------------------------------------------------*/ - for (i = 2; i <= 35; i++) { - switch (i) { - case 2: /* Memory type (DDR / SDRAM) */ - dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM; -#ifdef DEBUG - if (dimmInfo->memoryType == 0) - debug("Dram_type in slot %d is: SDRAM\n", - dimmInfo->slot); - if (dimmInfo->memoryType == 1) - debug("Dram_type in slot %d is: DDRAM\n", - dimmInfo->slot); -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 3: /* Number Of Row Addresses */ - dimmInfo->numOfRowAddresses = data[i]; - debug("Module Number of row addresses: %d\n", - dimmInfo->numOfRowAddresses); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 4: /* Number Of Column Addresses */ - dimmInfo->numOfColAddresses = data[i]; - debug("Module Number of col addresses: %d\n", - dimmInfo->numOfColAddresses); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 5: /* Number Of Module Banks */ - dimmInfo->numOfModuleBanks = data[i]; - debug("Number of Banks on Mod. : %d\n", - dimmInfo->numOfModuleBanks); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 6: /* Data Width */ - dimmInfo->dataWidth = data[i]; - debug("Module Data Width: %d\n", - dimmInfo->dataWidth); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 8: /* Voltage Interface */ - switch (data[i]) { - case 0x0: - dimmInfo->voltageInterface = TTL_5V_TOLERANT; - debug("Module is TTL_5V_TOLERANT\n"); - break; - case 0x1: - dimmInfo->voltageInterface = LVTTL; - debug("Module is LVTTL\n"); - break; - case 0x2: - dimmInfo->voltageInterface = HSTL_1_5V; - debug("Module is TTL_5V_TOLERANT\n"); - break; - case 0x3: - dimmInfo->voltageInterface = SSTL_3_3V; - debug("Module is HSTL_1_5V\n"); - break; - case 0x4: - dimmInfo->voltageInterface = SSTL_2_5V; - debug("Module is SSTL_2_5V\n"); - break; - default: - dimmInfo->voltageInterface = VOLTAGE_UNKNOWN; - debug("Module is VOLTAGE_UNKNOWN\n"); - break; - } - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 9: /* Minimum Cycle Time At Max CasLatancy */ - shift = (dimmInfo->memoryType == DDR) ? 4 : 2; - mult = (dimmInfo->memoryType == DDR) ? 10 : 25; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf : 0x03; - leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; - rightOfPoint = (data[i] & maskRightOfPoint) * mult; - dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP = - leftOfPoint; - dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP = - rightOfPoint; - debug("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n", - leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 10: /* Clock To Data Out */ - div = (dimmInfo->memoryType == DDR) ? 100 : 10; - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - dimmInfo->clockToDataOut_LoP = leftOfPoint; - dimmInfo->clockToDataOut_RoP = rightOfPoint; - debug("Clock To Data Out: %d.%2d [ns]\n", - leftOfPoint, rightOfPoint); - /*dimmInfo->clockToDataOut */ - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - -#ifdef CONFIG_MV64360_ECC - case 11: /* Error Check Type */ - dimmInfo->errorCheckType = data[i]; - debug("Error Check Type (0=NONE): %d\n", - dimmInfo->errorCheckType); - break; -#endif /* of ifdef CONFIG_MV64360_ECC */ -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 12: /* Refresh Interval */ - dimmInfo->RefreshInterval = data[i]; - debug("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n", - dimmInfo->RefreshInterval); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 13: /* Sdram Width */ - dimmInfo->sdramWidth = data[i]; - debug("Sdram Width: %d\n", - dimmInfo->sdramWidth); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 14: /* Error Check Data Width */ - dimmInfo->errorCheckDataWidth = data[i]; - debug("Error Check Data Width: %d\n", - dimmInfo->errorCheckDataWidth); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 15: /* Minimum Clock Delay */ - dimmInfo->minClkDelay = data[i]; - debug("Minimum Clock Delay: %d\n", - dimmInfo->minClkDelay); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 16: /* Burst Length Supported */ - /******-******-******-******* - * bit3 | bit2 | bit1 | bit0 * - *******-******-******-******* - burst length = * 8 | 4 | 2 | 1 * - ***************************** - - If for example bit0 and bit2 are set, the burst - length supported are 1 and 4. */ - - dimmInfo->burstLengthSupported = data[i]; -#ifdef DEBUG - debug("Burst Length Supported: "); - if (dimmInfo->burstLengthSupported & 0x01) - debug("1, "); - if (dimmInfo->burstLengthSupported & 0x02) - debug("2, "); - if (dimmInfo->burstLengthSupported & 0x04) - debug("4, "); - if (dimmInfo->burstLengthSupported & 0x08) - debug("8, "); - debug(" Bit \n"); -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 17: /* Number Of Banks On Each Device */ - dimmInfo->numOfBanksOnEachDevice = data[i]; - debug("Number Of Banks On Each Chip: %d\n", - dimmInfo->numOfBanksOnEachDevice); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 18: /* Suported Cas Latencies */ - - /* DDR: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | TBD | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * - ********************************************************* - SDRAM: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * - ********************************************************/ - dimmInfo->suportedCasLatencies = data[i]; -#ifdef DEBUG - debug("Suported Cas Latencies: (CL) "); - if (dimmInfo->memoryType == 0) { /* SDRAM */ - for (k = 0; k <= 7; k++) { - if (dimmInfo-> - suportedCasLatencies & (1 << k)) - debug("%d, ", - k + 1); - } - - } else { /* DDR-RAM */ - - if (dimmInfo->suportedCasLatencies & 1) - debug("1, "); - if (dimmInfo->suportedCasLatencies & 2) - debug("1.5, "); - if (dimmInfo->suportedCasLatencies & 4) - debug("2, "); - if (dimmInfo->suportedCasLatencies & 8) - debug("2.5, "); - if (dimmInfo->suportedCasLatencies & 16) - debug("3, "); - if (dimmInfo->suportedCasLatencies & 32) - debug("3.5, "); - - } - debug("\n"); -#endif - /* Calculating MAX CAS latency */ - for (j = 7; j > 0; j--) { - if (((dimmInfo-> - suportedCasLatencies >> j) & 0x1) == - 1) { - switch (dimmInfo->memoryType) { - case DDR: - /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */ - switch (j) { - case 7: - debug("Max. Cas Latencies (DDR): ERROR !!!\n"); - dimmInfo-> - maxClSupported_DDR - = - DDR_CL_FAULT; - hang (); - break; - case 6: - debug("Max. Cas Latencies (DDR): ERROR !!!\n"); - dimmInfo-> - maxClSupported_DDR - = - DDR_CL_FAULT; - hang (); - break; - case 5: - debug("Max. Cas Latencies (DDR): 3.5 clk's\n"); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_3_5; - break; - case 4: - debug("Max. Cas Latencies (DDR): 3 clk's \n"); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_3; - break; - case 3: - debug("Max. Cas Latencies (DDR): 2.5 clk's \n"); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_2_5; - break; - case 2: - debug("Max. Cas Latencies (DDR): 2 clk's \n"); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_2; - break; - case 1: - debug("Max. Cas Latencies (DDR): 1.5 clk's \n"); - dimmInfo-> - maxClSupported_DDR - = DDR_CL_1_5; - break; - } - dimmInfo-> - maxCASlatencySupported_LoP - = - 1 + - (int) (5 * j / 10); - if (((5 * j) % 10) != 0) - dimmInfo-> - maxCASlatencySupported_RoP - = 5; - else - dimmInfo-> - maxCASlatencySupported_RoP - = 0; - debug("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", - dimmInfo-> - maxCASlatencySupported_LoP, - dimmInfo-> - maxCASlatencySupported_RoP); - break; - case SDRAM: - /* CAS latency 1, 2, 3, 4, 5, 6, 7 */ - dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */ - debug("Max. Cas Latencies (SD): %d\n", - dimmInfo-> - maxClSupported_SD); - dimmInfo-> - maxCASlatencySupported_LoP - = j; - dimmInfo-> - maxCASlatencySupported_RoP - = 0; - debug("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", - dimmInfo-> - maxCASlatencySupported_LoP, - dimmInfo-> - maxCASlatencySupported_RoP); - break; - } - break; - } - } - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 21: /* Buffered Address And Control Inputs */ - debug("\nModul Attributes (SPD Byte 21): \n"); - dimmInfo->bufferedAddrAndControlInputs = - data[i] & BIT0; - dimmInfo->registeredAddrAndControlInputs = - (data[i] & BIT1) >> 1; - dimmInfo->onCardPLL = (data[i] & BIT2) >> 2; - dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3; - dimmInfo->registeredDQMBinputs = - (data[i] & BIT4) >> 4; - dimmInfo->differentialClockInput = - (data[i] & BIT5) >> 5; - dimmInfo->redundantRowAddressing = - (data[i] & BIT6) >> 6; - - if (dimmInfo->bufferedAddrAndControlInputs == 1) - debug(" - Buffered Address/Control Input: Yes \n"); - else - debug(" - Buffered Address/Control Input: No \n"); - - if (dimmInfo->registeredAddrAndControlInputs == 1) - debug(" - Registered Address/Control Input: Yes \n"); - else - debug(" - Registered Address/Control Input: No \n"); - - if (dimmInfo->onCardPLL == 1) - debug(" - On-Card PLL (clock): Yes \n"); - else - debug(" - On-Card PLL (clock): No \n"); - - if (dimmInfo->bufferedDQMBinputs == 1) - debug(" - Bufferd DQMB Inputs: Yes \n"); - else - debug(" - Bufferd DQMB Inputs: No \n"); - - if (dimmInfo->registeredDQMBinputs == 1) - debug(" - Registered DQMB Inputs: Yes \n"); - else - debug(" - Registered DQMB Inputs: No \n"); - - if (dimmInfo->differentialClockInput == 1) - debug(" - Differential Clock Input: Yes \n"); - else - debug(" - Differential Clock Input: No \n"); - - if (dimmInfo->redundantRowAddressing == 1) - debug(" - redundant Row Addressing: Yes \n"); - else - debug(" - redundant Row Addressing: No \n"); - - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 22: /* Suported AutoPreCharge */ - debug("\nModul Attributes (SPD Byte 22): \n"); - dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0; - dimmInfo->suportedAutoPreCharge = - (data[i] & BIT1) >> 1; - dimmInfo->suportedPreChargeAll = - (data[i] & BIT2) >> 2; - dimmInfo->suportedWrite1ReadBurst = - (data[i] & BIT3) >> 3; - dimmInfo->suported5PercentLowVCC = - (data[i] & BIT4) >> 4; - dimmInfo->suported5PercentUpperVCC = - (data[i] & BIT5) >> 5; - - if (dimmInfo->suportedEarlyRasPreCharge == 1) - debug(" - Early Ras Precharge: Yes \n"); - else - debug(" - Early Ras Precharge: No \n"); - - if (dimmInfo->suportedAutoPreCharge == 1) - debug(" - AutoPreCharge: Yes \n"); - else - debug(" - AutoPreCharge: No \n"); - - if (dimmInfo->suportedPreChargeAll == 1) - debug(" - Precharge All: Yes \n"); - else - debug(" - Precharge All: No \n"); - - if (dimmInfo->suportedWrite1ReadBurst == 1) - debug(" - Write 1/ReadBurst: Yes \n"); - else - debug(" - Write 1/ReadBurst: No \n"); - - if (dimmInfo->suported5PercentLowVCC == 1) - debug(" - lower VCC tolerance: 5 Percent \n"); - else - debug(" - lower VCC tolerance: 10 Percent \n"); - - if (dimmInfo->suported5PercentUpperVCC == 1) - debug(" - upper VCC tolerance: 5 Percent \n"); - else - debug(" - upper VCC tolerance: 10 Percent \n"); - - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 23: /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ - shift = (dimmInfo->memoryType == DDR) ? 4 : 2; - mult = (dimmInfo->memoryType == DDR) ? 10 : 25; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf : 0x03; - leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; - rightOfPoint = (data[i] & maskRightOfPoint) * mult; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP = - leftOfPoint; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP = - rightOfPoint; - debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", - leftOfPoint, rightOfPoint); - /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 24: /* Clock To Data Out 2nd highest Cas Latency Value */ - div = (dimmInfo->memoryType == DDR) ? 100 : 10; - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint; - dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint; - debug("Clock To Data Out (2nd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 25: /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ - shift = (dimmInfo->memoryType == DDR) ? 4 : 2; - mult = (dimmInfo->memoryType == DDR) ? 10 : 25; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0xf : 0x03; - leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; - rightOfPoint = (data[i] & maskRightOfPoint) * mult; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP = - leftOfPoint; - dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP = - rightOfPoint; - debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", - leftOfPoint, rightOfPoint); - /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 26: /* Clock To Data Out 3rd highest Cas Latency Value */ - div = (dimmInfo->memoryType == DDR) ? 100 : 10; - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint; - dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint; - debug("Clock To Data Out (3rd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 27: /* Minimum Row Precharge Time */ - shift = (dimmInfo->memoryType == DDR) ? 2 : 0; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; - leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (data[i] & maskRightOfPoint) * 25; - - dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint); /* measured in n times 10ps Intervals */ - trp_clocks = - (dimmInfo->minRowPrechargeTime + - (tmemclk - 1)) / tmemclk; - debug("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n", - tmemclk, tmemclk / 100, tmemclk % 100); - debug("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 28: /* Minimum Row Active to Row Active Time */ - shift = (dimmInfo->memoryType == DDR) ? 2 : 0; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; - leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (data[i] & maskRightOfPoint) * 25; - - dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - debug("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 29: /* Minimum Ras-To-Cas Delay */ - shift = (dimmInfo->memoryType == DDR) ? 2 : 0; - maskLeftOfPoint = - (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; - maskRightOfPoint = - (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; - leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (data[i] & maskRightOfPoint) * 25; - - dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - debug("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 30: /* Minimum Ras Pulse Width */ - dimmInfo->minRasPulseWidth = data[i]; - tras_clocks = - (NSto10PS (data[i]) + - (tmemclk - 1)) / tmemclk; - debug("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n", - dimmInfo->minRasPulseWidth, tras_clocks); - - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 31: /* Module Bank Density */ - dimmInfo->moduleBankDensity = data[i]; - debug("Module Bank Density: %d\n", - dimmInfo->moduleBankDensity); -#ifdef DEBUG - debug("*** Offered Densities (more than 1 = Multisize-Module): "); - { - if (dimmInfo->moduleBankDensity & 1) - debug("4MB, "); - if (dimmInfo->moduleBankDensity & 2) - debug("8MB, "); - if (dimmInfo->moduleBankDensity & 4) - debug("16MB, "); - if (dimmInfo->moduleBankDensity & 8) - debug("32MB, "); - if (dimmInfo->moduleBankDensity & 16) - debug("64MB, "); - if (dimmInfo->moduleBankDensity & 32) - debug("128MB, "); - if ((dimmInfo->moduleBankDensity & 64) - || (dimmInfo->moduleBankDensity & 128)) { - debug("ERROR, "); - hang (); - } - } - debug("\n"); -#endif - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 32: /* Address And Command Setup Time (measured in ns/1000) */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->addrAndCommandSetupTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - debug("Address And Command Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 33: /* Address And Command Hold Time */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->addrAndCommandHoldTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - debug("Address And Command Hold Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 34: /* Data Input Setup Time */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->dataInputSetupTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - debug("Data Input Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - - case 35: /* Data Input Hold Time */ - sign = 1; - switch (dimmInfo->memoryType) { - case DDR: - time_tmp = - (((data[i] & 0xf0) >> 4) * 10) + - ((data[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - break; - case SDRAM: - leftOfPoint = (data[i] & 0xf0) >> 4; - if (leftOfPoint > 7) { - leftOfPoint = data[i] & 0x70 >> 4; - sign = -1; - } - rightOfPoint = (data[i] & 0x0f); - break; - } - dimmInfo->dataInputHoldTime = - (leftOfPoint * 100 + rightOfPoint) * sign; - debug("Data Input Hold Time [ns]: %d.%d\n\n", - sign * leftOfPoint, rightOfPoint); - break; -/*------------------------------------------------------------------------------------------------------------------------------*/ - } - } - /* calculating the sdram density */ - for (i = 0; - i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses; - i++) { - density = density * 2; - } - dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice * - dimmInfo->sdramWidth; - dimmInfo->numberOfDevices = - (dimmInfo->dataWidth / dimmInfo->sdramWidth) * - dimmInfo->numOfModuleBanks; - devicesForErrCheck = - (dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth; - if ((dimmInfo->errorCheckType == 0x1) - || (dimmInfo->errorCheckType == 0x2) - || (dimmInfo->errorCheckType == 0x3)) { - dimmInfo->size = - (dimmInfo->deviceDensity / 8) * - (dimmInfo->numberOfDevices - devicesForErrCheck); - } else { - dimmInfo->size = - (dimmInfo->deviceDensity / 8) * - dimmInfo->numberOfDevices; - } - - /* compute the module DRB size */ - tmp = (1 << - (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses)); - tmp *= dimmInfo->numOfModuleBanks; - tmp *= dimmInfo->sdramWidth; - tmp = tmp >> 24; /* div by 0x4000000 (64M) */ - dimmInfo->drb_size = (uchar) tmp; - debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size); - - /* try a CAS latency of 3 first... */ - - /* bit 1 is CL2, bit 2 is CL3 */ - supp_cal = (dimmInfo->suportedCasLatencies & 0x1c) >> 1; - - cal_val = 0; - if (supp_cal & 8) { - if (NS10to10PS (data[9]) <= tmemclk) - cal_val = 6; - } - if (supp_cal & 4) { - if (NS10to10PS (data[9]) <= tmemclk) - cal_val = 5; - } - - /* then 2... */ - if (supp_cal & 2) { - if (NS10to10PS (data[23]) <= tmemclk) - cal_val = 4; - } - - debug("cal_val = %d\n", cal_val * 5); - - /* bummer, did't work... */ - if (cal_val == 0) { - debug("Couldn't find a good CAS latency\n"); - hang (); - return 0; - } - - return true; -} - -/* sets up the GT properly with information passed in */ -int setup_sdram (AUX_MEM_DIMM_INFO * info) -{ - ulong tmp; - ulong tmp_sdram_mode = 0; /* 0x141c */ - ulong tmp_dunit_control_low = 0; /* 0x1404 */ - uint sdram_config_reg = CONFIG_SYS_SDRAM_CONFIG; - int i; - - /* sanity checking */ - if (!info->numOfModuleBanks) { - printf ("setup_sdram called with 0 banks\n"); - return 1; - } - - /* delay line */ - - /* Program the GT with the discovered data */ - if (info->registeredAddrAndControlInputs == true) - debug("Module is registered, but we do not support registered Modules !!!\n"); - - /* delay line */ - set_dfcdlInit (); /* may be its not needed */ - debug("Delay line set done\n"); - - /* set SDRAM mode NOP */ /* To_do check it */ - GT_REG_WRITE (SDRAM_OPERATION, 0x5); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - debug("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"); - } - -#ifdef CONFIG_MV64360_ECC - if ((info->errorCheckType == 0x2) && (CPCI750_ECC_TEST)) { - /* DRAM has ECC, so turn it on */ - sdram_config_reg |= BIT18; - debug("Enabling ECC\n"); - } -#endif /* of ifdef CONFIG_MV64360_ECC */ - - /* SDRAM configuration */ - GT_REG_WRITE(SDRAM_CONFIG, sdram_config_reg); - debug("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG)); - - /* SDRAM open pages controll keep open as much as I can */ - GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0); - debug("sdram_open_pages_controll 0x1414: %08x\n", - GTREGREAD (SDRAM_OPEN_PAGES_CONTROL)); - - - /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ - tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */ - if (tmp == 0) - debug("Core Signals are sync (by HW-Setting)!!!\n"); - else - debug("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"); - - /* SDRAM set CAS Lentency according to SPD information */ - switch (info->memoryType) { - case SDRAM: - debug("### SD-RAM not supported yet !!!\n"); - hang (); - /* ToDo fill SD-RAM if needed !!!!! */ - break; - - case DDR: - debug("### SET-CL for DDR-RAM\n"); - - switch (info->maxClSupported_DDR) { - case DDR_CL_3: - tmp_dunit_control_low = 0x3c000000; /* Read-Data sampled on falling edge of Clk */ - tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */ - debug("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - break; - - case DDR_CL_2_5: - if (tmp == 1) { /* clocks sync */ - tmp_dunit_control_low = 0x24000000; /* Read-Data sampled on falling edge of Clk */ - tmp_sdram_mode = 0x62; /* CL=2,5 Burstlength = 4 */ - debug("Max. CL is 2,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } else { /* clk sync. bypassed */ - - tmp_dunit_control_low = 0x03000000; /* Read-Data sampled on rising edge of Clk */ - tmp_sdram_mode = 0x62; /* CL=2,5 Burstlength = 4 */ - debug("Max. CL is 2,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } - break; - - case DDR_CL_2: - if (tmp == 1) { /* Sync */ - tmp_dunit_control_low = 0x03000000; /* Read-Data sampled on rising edge of Clk */ - tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */ - debug("Max. CL is 2s CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } else { /* Not sync. */ - - tmp_dunit_control_low = 0x3b000000; /* Read-Data sampled on rising edge of Clk */ - tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */ - debug("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } - break; - - case DDR_CL_1_5: - if (tmp == 1) { /* Sync */ - tmp_dunit_control_low = 0x23000000; /* Read-Data sampled on falling edge of Clk */ - tmp_sdram_mode = 0x52; /* CL=1,5 Burstlength = 4 */ - debug("Max. CL is 1,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } else { /* not sync */ - - tmp_dunit_control_low = 0x1a000000; /* Read-Data sampled on rising edge of Clk */ - tmp_sdram_mode = 0x52; /* CL=1,5 Burstlength = 4 */ - debug("Max. CL is 1,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low); - } - break; - - default: - printf ("Max. CL is out of range %d\n", - info->maxClSupported_DDR); - hang (); - break; - } - break; - } - - /* Write results of CL detection procedure */ - GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode); - /* set SDRAM mode SetCommand 0x1418 */ - GT_REG_WRITE (SDRAM_OPERATION, 0x3); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); - } - - - /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ - tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */ - if (tmp != 1) { /*clocks are not sync */ - /* asyncmode */ - GT_REG_WRITE (D_UNIT_CONTROL_LOW, - (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) | - 0x18110780 | tmp_dunit_control_low); - } else { - /* syncmode */ - GT_REG_WRITE (D_UNIT_CONTROL_LOW, - (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) | - 0x00110000 | tmp_dunit_control_low); - } - - /* set SDRAM mode SetCommand 0x1418 */ - GT_REG_WRITE (SDRAM_OPERATION, 0x3); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - debug("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"); - } - -/*------------------------------------------------------------------------------ */ - - - /* bank parameters */ - /* SDRAM address decode register */ - /* program this with the default value */ - tmp = 0x02; - - - debug("drb_size (n*64Mbit): %d\n", info->drb_size); - switch (info->drb_size) { - case 1: /* 64 Mbit */ - case 2: /* 128 Mbit */ - debug("RAM-Device_size 64Mbit or 128Mbit)\n"); - tmp |= (0x00 << 4); - break; - case 4: /* 256 Mbit */ - case 8: /* 512 Mbit */ - debug("RAM-Device_size 256Mbit or 512Mbit)\n"); - tmp |= (0x01 << 4); - break; - case 16: /* 1 Gbit */ - case 32: /* 2 Gbit */ - debug("RAM-Device_size 1Gbit or 2Gbit)\n"); - tmp |= (0x02 << 4); - break; - default: - printf ("Error in dram size calculation\n"); - debug("Assume: RAM-Device_size 1Gbit or 2Gbit)\n"); - tmp |= (0x02 << 4); - return 1; - } - - /* SDRAM bank parameters */ - /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */ - debug("setting up slot %d config with: %08lx \n", info->slot, tmp); - GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp); - -/* ------------------------------------------------------------------------------ */ - - debug("setting up sdram_timing_control_low with: %08x \n", - 0x11511220); - GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220); - - -/* ------------------------------------------------------------------------------ */ - - /* SDRAM configuration */ - tmp = GTREGREAD (SDRAM_CONFIG); - - if (info->registeredAddrAndControlInputs - || info->registeredDQMBinputs) { - tmp |= (1 << 17); - debug("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n", - info->registeredAddrAndControlInputs, - info->registeredDQMBinputs); - } - - /* Use buffer 1 to return read data to the CPU - * Page 426 MV64360 */ - tmp |= (1 << 26); - debug("Before Buffer assignment - sdram_conf: %08x\n", - GTREGREAD (SDRAM_CONFIG)); - debug("After Buffer assignment - sdram_conf: %08x\n", - GTREGREAD (SDRAM_CONFIG)); - - /* SDRAM timing To_do: */ - - - tmp = GTREGREAD (SDRAM_TIMING_CONTROL_HIGH); - debug("# sdram_timing_control_high is : %08lx \n", tmp); - - /* SDRAM address decode register */ - /* program this with the default value */ - tmp = GTREGREAD (SDRAM_ADDR_CONTROL); - debug("SDRAM address control (before: decode): %08x ", - GTREGREAD (SDRAM_ADDR_CONTROL)); - GT_REG_WRITE (SDRAM_ADDR_CONTROL, (tmp | 0x2)); - debug("SDRAM address control (after: decode): %08x\n", - GTREGREAD (SDRAM_ADDR_CONTROL)); - - /* set the SDRAM configuration for each bank */ - -/* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */ - { - int l, l1; - - i = info->slot; - debug("\n*** Running a MRS cycle for bank %d ***\n", i); - - /* map the bank */ - memory_map_bank (i, 0, GB / 4); -#if 1 /* test only */ - - tmp = GTREGREAD (SDRAM_MODE); - GT_REG_WRITE (EXTENDED_DRAM_MODE, 0x0); - GT_REG_WRITE (SDRAM_OPERATION, 0x4); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); - } - - GT_REG_WRITE (SDRAM_MODE, tmp | 0x80); - GT_REG_WRITE (SDRAM_OPERATION, 0x3); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); - } - l1 = 0; - for (l=0;l<200;l++) - l1 += GTREGREAD (SDRAM_OPERATION); - - GT_REG_WRITE (SDRAM_MODE, tmp); - GT_REG_WRITE (SDRAM_OPERATION, 0x3); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); - } - - /* switch back to normal operation mode */ - GT_REG_WRITE (SDRAM_OPERATION, 0x5); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); - } - -#endif /* test only */ - /* unmap the bank */ - memory_map_bank (i, 0, 0); - } - - return 0; -} - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ -long int -dram_size(long int *base, long int maxsize) -{ - volatile long int *addr, *b=base; - long int cnt, val, save1, save2; - -#define STARTVAL (1<<20) /* start test at 1M */ - for (cnt = STARTVAL/sizeof(long); cnt < maxsize/sizeof(long); cnt <<= 1) { - addr = base + cnt; /* pointer arith! */ - - save1 = *addr; /* save contents of addr */ - save2 = *b; /* save contents of base */ - - *addr=cnt; /* write cnt to addr */ - *b=0; /* put null at base */ - - /* check at base address */ - if ((*b) != 0) { - *addr=save1; /* restore *addr */ - *b=save2; /* restore *b */ - return (0); - } - val = *addr; /* read *addr */ - val = *addr; /* read *addr */ - - *addr=save1; - *b=save2; - - if (val != cnt) { - debug("Found %08x at Address %08x (failure)\n", (unsigned int)val, (unsigned int) addr); - /* fix boundary condition.. STARTVAL means zero */ - if(cnt==STARTVAL/sizeof(long)) cnt=0; - return (cnt * sizeof(long)); - } - } - return maxsize; -} - -#ifdef CONFIG_MV64360_ECC -/* - * mv_dma_is_channel_active: - * Checks if a engine is busy. - */ -int mv_dma_is_channel_active(int engine) -{ - ulong data; - - data = GTREGREAD(MV64360_DMA_CHANNEL0_CONTROL + 4 * engine); - if (data & BIT14) /* activity status */ - return 1; - - return 0; -} - -/* - * mv_dma_set_memory_space: - * Set a DMA memory window for the DMA's address decoding map. - */ -int mv_dma_set_memory_space(ulong mem_space, ulong mem_space_target, - ulong mem_space_attr, ulong base_address, - ulong size) -{ - ulong temp; - - /* The base address must be aligned to the size. */ - if (base_address % size != 0) - return 0; - - if (size >= 0x10000) { - size &= 0xffff0000; - base_address = (base_address & 0xffff0000); - /* Set the new attributes */ - GT_REG_WRITE(MV64360_DMA_BASE_ADDR_REG0 + mem_space * 8, - (base_address | mem_space_target | - mem_space_attr)); - GT_REG_WRITE((MV64360_DMA_SIZE_REG0 + mem_space * 8), - (size - 1) & 0xffff0000); - temp = GTREGREAD(MV64360_DMA_BASE_ADDR_ENABLE_REG); - GT_REG_WRITE(DMA_BASE_ADDR_ENABLE_REG, - (temp & ~(BIT0 << mem_space))); - return 1; - } - - return 0; -} - - -/* - * mv_dma_transfer: - * Transfer data from source_addr to dest_addr on one of the 4 DMA channels. - */ -int mv_dma_transfer(int engine, ulong source_addr, - ulong dest_addr, ulong bytes, ulong command) -{ - ulong eng_off_reg; /* Engine Offset Register */ - - if (bytes > 0xffff) - command = command | BIT31; /* DMA_16M_DESCRIPTOR_MODE */ - - command = command | ((command >> 6) & 0x7); - eng_off_reg = engine * 4; - GT_REG_WRITE(MV64360_DMA_CHANNEL0_BYTE_COUNT + eng_off_reg, - bytes); - GT_REG_WRITE(MV64360_DMA_CHANNEL0_SOURCE_ADDR + eng_off_reg, - source_addr); - GT_REG_WRITE(MV64360_DMA_CHANNEL0_DESTINATION_ADDR + eng_off_reg, - dest_addr); - command |= BIT12 /* DMA_CHANNEL_ENABLE */ - | BIT9; /* DMA_NON_CHAIN_MODE */ - - /* Activate DMA engine By writting to mv_dma_control_register */ - GT_REG_WRITE(MV64360_DMA_CHANNEL0_CONTROL + eng_off_reg, command); - - return 1; -} -#endif /* of ifdef CONFIG_MV64360_ECC */ - -/* ppcboot interface function to SDRAM init - this is where all the - * controlling logic happens */ -phys_size_t -initdram(int board_type) -{ - int checkbank[4] = { [0 ... 3] = 0 }; - ulong realsize, total, check; - AUX_MEM_DIMM_INFO dimmInfo1; - AUX_MEM_DIMM_INFO dimmInfo2; - int bank_no, nhr; -#ifdef CONFIG_MV64360_ECC - ulong dest, mem_space_attr; -#endif /* of ifdef CONFIG_MV64360_ECC */ - - /* first, use the SPD to get info about the SDRAM/ DDRRAM */ - - /* check the NHR bit and skip mem init if it's already done */ - nhr = get_hid0() & (1 << 16); - - if (nhr) { - printf("Skipping SD- DDRRAM setup due to NHR bit being set\n"); - } else { - /* DIMM0 */ - (void)check_dimm(0, &dimmInfo1); - - /* DIMM1 */ - (void)check_dimm(1, &dimmInfo2); - - memory_map_bank(0, 0, 0); - memory_map_bank(1, 0, 0); - memory_map_bank(2, 0, 0); - memory_map_bank(3, 0, 0); - - if (dimmInfo1.numOfModuleBanks && setup_sdram(&dimmInfo1)) { - printf("Setup for DIMM1 failed.\n"); - } - - if (dimmInfo2.numOfModuleBanks && setup_sdram(&dimmInfo2)) { - printf("Setup for DIMM2 failed.\n"); - } - - /* set the NHR bit */ - set_hid0(get_hid0() | (1 << 16)); - } - /* next, size the SDRAM banks */ - - realsize = total = 0; - check = GB/4; - if (dimmInfo1.numOfModuleBanks > 0) {checkbank[0] = 1; printf("-- DIMM1 has 1 bank\n");} - if (dimmInfo1.numOfModuleBanks > 1) {checkbank[1] = 1; printf("-- DIMM1 has 2 banks\n");} - if (dimmInfo1.numOfModuleBanks > 2) - printf("Error, SPD claims DIMM1 has >2 banks\n"); - - if (dimmInfo2.numOfModuleBanks > 0) {checkbank[2] = 1; printf("-- DIMM2 has 1 bank\n");} - if (dimmInfo2.numOfModuleBanks > 1) {checkbank[3] = 1; printf("-- DIMM2 has 2 banks\n");} - if (dimmInfo2.numOfModuleBanks > 2) - printf("Error, SPD claims DIMM2 has >2 banks\n"); - - for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) { - /* skip over banks that are not populated */ - if (! checkbank[bank_no]) - continue; - - if ((total + check) > CONFIG_SYS_GT_REGS) - check = CONFIG_SYS_GT_REGS - total; - - memory_map_bank(bank_no, total, check); - realsize = dram_size((long int *)total, check); - memory_map_bank(bank_no, total, realsize); - -#ifdef CONFIG_MV64360_ECC - if (((dimmInfo1.errorCheckType != 0) && - ((dimmInfo2.errorCheckType != 0) || - (dimmInfo2.numOfModuleBanks == 0))) && - (CPCI750_ECC_TEST)) { - printf("ECC Initialization of Bank %d:", bank_no); - mem_space_attr = ((~(BIT0 << bank_no)) & 0xf) << 8; - mv_dma_set_memory_space(0, 0, mem_space_attr, total, - realsize); - for (dest = total; dest < total + realsize; - dest += _8M) { - mv_dma_transfer(0, total, dest, _8M, - BIT8 | /* DMA_DTL_128BYTES */ - BIT3 | /* DMA_HOLD_SOURCE_ADDR */ - BIT11); /* DMA_BLOCK_TRANSFER_MODE */ - while (mv_dma_is_channel_active(0)) - ; - } - printf(" PASS\n"); - } -#endif /* of ifdef CONFIG_MV64360_ECC */ - - total += realsize; - } - -/* Setup Ethernet DMA Adress window to DRAM Area */ - return(total); -} - -/* *************************************************************************************** -! * SDRAM INIT * -! * This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb * -! * This procedure fits only the Atlantis * -! * * -! *************************************************************************************** */ - - -/* *************************************************************************************** -! * DFCDL initialize MV643xx Design Considerations * -! * * -! *************************************************************************************** */ -int set_dfcdlInit (void) -{ - int i; - unsigned int dfcdl_word = 0x0000014f; - - for (i = 0; i < 64; i++) { - GT_REG_WRITE (SRAM_DATA0, dfcdl_word); - } - GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000); /* enable dynamic delay line updating */ - - - return (0); -} - -int do_show_ecc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned int ecc_counter; - unsigned int ecc_addr; - - GT_REG_READ(0x1458, &ecc_counter); - GT_REG_READ(0x1450, &ecc_addr); - GT_REG_WRITE(0x1450, 0); - - printf("Error Counter since Reset: %8d\n", ecc_counter); - printf("Last error address :0x%08x (" , ecc_addr & 0xfffffff8); - if (ecc_addr & 0x01) - printf("double"); - else - printf("single"); - printf(" bit) at DDR-RAM CS#%d\n", ((ecc_addr & 0x6) >> 1)); - - return 0; -} - - -U_BOOT_CMD( - show_ecc, 1, 1, do_show_ecc, - "Show Marvell MV64360 ECC Info", - "Show Marvell MV64360 ECC Counter and last error." -); diff --git a/board/esd/cpci750/serial.c b/board/esd/cpci750/serial.c deleted file mode 100644 index 6c2cf21..0000000 --- a/board/esd/cpci750/serial.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * modified for marvell db64360 eval board by - * Ingo Assmus <ingo.assmus@keymile.com> - * - * modified for cpci750 board by - * Reinhard Arlt <reinhard.arlt@esd-electronics.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * serial.c - serial support for esd cpci750 board - */ - -/* supports the MPSC */ - -#include <common.h> -#include <command.h> -#include <serial.h> -#include <linux/compiler.h> - -#include "../../Marvell/include/memory.h" - -#include "mpsc.h" - -DECLARE_GLOBAL_DATA_PTR; - -static int cpci750_serial_init(void) -{ - mpsc_init (gd->baudrate); - - return (0); -} - -static void cpci750_serial_putc(const char c) -{ - if (c == '\n') - mpsc_putchar ('\r'); - - mpsc_putchar (c); -} - -static int cpci750_serial_getc(void) -{ - return mpsc_getchar (); -} - -static int cpci750_serial_tstc(void) -{ - return mpsc_test_char (); -} - -static void cpci750_serial_setbrg(void) -{ - galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate); -} - -static struct serial_device cpci750_serial_drv = { - .name = "cpci750_serial", - .start = cpci750_serial_init, - .stop = NULL, - .setbrg = cpci750_serial_setbrg, - .putc = cpci750_serial_putc, - .puts = default_serial_puts, - .getc = cpci750_serial_getc, - .tstc = cpci750_serial_tstc, -}; - -void cpci750_serial_initialize(void) -{ - serial_register(&cpci750_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &cpci750_serial_drv; -} - -#if defined(CONFIG_CMD_KGDB) -void kgdb_serial_init (void) -{ -} - -void putDebugChar (int c) -{ - serial_putc (c); -} - -void putDebugStr (const char *str) -{ - serial_puts (str); -} - -int getDebugChar (void) -{ - return serial_getc (); -} - -void kgdb_interruptible (int yes) -{ - return; -} -#endif diff --git a/board/exmeritus/hww1u1a/Kconfig b/board/exmeritus/hww1u1a/Kconfig deleted file mode 100644 index 7a76b43..0000000 --- a/board/exmeritus/hww1u1a/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_HWW1U1A - -config SYS_BOARD - default "hww1u1a" - -config SYS_VENDOR - default "exmeritus" - -config SYS_CONFIG_NAME - default "HWW1U1A" - -endif diff --git a/board/exmeritus/hww1u1a/MAINTAINERS b/board/exmeritus/hww1u1a/MAINTAINERS deleted file mode 100644 index b37f10b..0000000 --- a/board/exmeritus/hww1u1a/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -HWW1U1A BOARD -#M: Kyle Moffett <Kyle.D.Moffett@boeing.com> -S: Orphan (since 2014-06) -F: board/exmeritus/hww1u1a/ -F: include/configs/HWW1U1A.h -F: configs/HWW1U1A_defconfig diff --git a/board/exmeritus/hww1u1a/Makefile b/board/exmeritus/hww1u1a/Makefile deleted file mode 100644 index d0cd878..0000000 --- a/board/exmeritus/hww1u1a/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright 2007-2009 Freescale Semiconductor, Inc. -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += hww1u1a.o -obj-y += law.o -obj-y += tlb.o -obj-$(CONFIG_DDR_SPD) += ddr.o diff --git a/board/exmeritus/hww1u1a/ddr.c b/board/exmeritus/hww1u1a/ddr.c deleted file mode 100644 index e1f6865..0000000 --- a/board/exmeritus/hww1u1a/ddr.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright 2009-2010 eXMeritus, A Boeing Company - * Copyright 2008-2009 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include <common.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * We only support one DIMM, so according to the P2020 docs we should - * set the options as follows: - */ - popts->cs_local_opts[0].odt_rd_cfg = 0; - popts->cs_local_opts[0].odt_wr_cfg = 4; - popts->cs_local_opts[1].odt_rd_cfg = 0; - popts->cs_local_opts[1].odt_wr_cfg = 0; - popts->half_strength_driver_enable = 0; - - /* Manually configured for our static clock rate */ - popts->clk_adjust = 4; - popts->cpo_override = 4; - popts->write_data_delay = 2; - popts->twot_en = 0; -} diff --git a/board/exmeritus/hww1u1a/gpios.h b/board/exmeritus/hww1u1a/gpios.h deleted file mode 100644 index 499880f..0000000 --- a/board/exmeritus/hww1u1a/gpios.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright 2010 eXMeritus, A Boeing Company - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm/mpc85xx_gpio.h> - -/* Common CPU A/B GPIOs (GPIO8-GPIO15 and IRQ4-IRQ6) */ -#define GPIO_CPU_ID (1UL << (31 - 8)) -#define GPIO_BLUE_LED (1UL << (31 - 9)) -#define GPIO_DIMM_RESET (1UL << (31 - 10)) -#define GPIO_USB_RESET (1UL << (31 - 11)) -#define GPIO_UNUSED_12 (1UL << (31 - 12)) -#define GPIO_GETH0_RESET (1UL << (31 - 13)) -#define GPIO_RS422_RE (1UL << (31 - 14)) -#define GPIO_RS422_DE (1UL << (31 - 15)) -#define IRQ_I2CINT (1UL << (31 - 20)) -#define IRQ_FANINT (1UL << (31 - 21)) -#define IRQ_DIMM_EVENT (1UL << (31 - 22)) - -#define GPIO_RESETS (GPIO_DIMM_RESET|GPIO_USB_RESET|GPIO_GETH0_RESET) - -/* CPU A GPIOS (GPIO0-GPIO7 and IRQ0-IRQ3) */ -#define GPIO_CPUA_UNUSED_0 (1UL << (31 - 0)) -#define GPIO_CPUA_CPU_READY (1UL << (31 - 1)) -#define GPIO_CPUA_DEBUG_LED2 (1UL << (31 - 2)) -#define GPIO_CPUA_DEBUG_LED1 (1UL << (31 - 3)) -#define GPIO_CPUA_TDIS2B (1UL << (31 - 4)) /* MAC 2 TX B */ -#define GPIO_CPUA_TDIS2A (1UL << (31 - 5)) /* MAC 2 TX A */ -#define GPIO_CPUA_TDIS1B (1UL << (31 - 6)) /* MAC 1 TX B */ -#define GPIO_CPUA_TDIS1A (1UL << (31 - 7)) /* MAC 1 TX A */ -#define IRQ_CPUA_UNUSED_0 (1UL << (31 - 16)) -#define IRQ_CPUA_UNUSED_1 (1UL << (31 - 17)) -#define IRQ_CPUA_UNUSED_2 (1UL << (31 - 18)) -#define IRQ_CPUA_UNUSED_3 (1UL << (31 - 19)) - -/* CPU B GPIOS (GPIO0-GPIO7 and IRQ0-IRQ3) */ -#define GPIO_CPUB_RMUX_SEL1B (1UL << (31 - 0)) -#define GPIO_CPUB_RMUX_SEL0B (1UL << (31 - 1)) -#define GPIO_CPUB_RMUX_SEL1A (1UL << (31 - 2)) -#define GPIO_CPUB_RMUX_SEL0A (1UL << (31 - 3)) -#define GPIO_CPUB_UNUSED_4 (1UL << (31 - 4)) -#define GPIO_CPUB_CPU_READY (1UL << (31 - 5)) -#define GPIO_CPUB_DEBUG_LED2 (1UL << (31 - 6)) -#define GPIO_CPUB_DEBUG_LED1 (1UL << (31 - 7)) -#define IRQ_CPUB_SD_1A (1UL << (31 - 16)) -#define IRQ_CPUB_SD_2B (1UL << (31 - 17)) -#define IRQ_CPUB_SD_2A (1UL << (31 - 18)) -#define IRQ_CPUB_SD_1B (1UL << (31 - 19)) - -/* If it isn't CPU A then it's CPU B */ -static inline unsigned int hww1u1a_is_cpu_a(void) -{ - return !mpc85xx_gpio_get(GPIO_CPU_ID); -} diff --git a/board/exmeritus/hww1u1a/hww1u1a.c b/board/exmeritus/hww1u1a/hww1u1a.c deleted file mode 100644 index 643ece1..0000000 --- a/board/exmeritus/hww1u1a/hww1u1a.c +++ /dev/null @@ -1,268 +0,0 @@ -/* - * Copyright 2009-2011 eXMeritus, A Boeing Company - * Copyright 2007-2009 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/cache.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_pci.h> -#include <fsl_ddr_sdram.h> -#include <asm/io.h> -#include <miiphy.h> -#include <libfdt.h> -#include <linux/ctype.h> -#include <fdt_support.h> -#include <fsl_mdio.h> -#include <tsec.h> -#include <asm/fsl_law.h> -#include <netdev.h> -#include <malloc.h> -#include <i2c.h> -#include <pca953x.h> - -#include "gpios.h" - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - unsigned int gpio_high = 0; - unsigned int gpio_low = 0; - unsigned int gpio_in = 0; - unsigned int i; - struct ccsr_ddr __iomem *ddr; - - puts("Board: HWW-1U-1A "); - - /* - * First just figure out which CPU we're on, then use that to - * configure the lists of other GPIOs to be programmed. - */ - mpc85xx_gpio_set_in(GPIO_CPU_ID); - if (hww1u1a_is_cpu_a()) { - puts("CPU A\n"); - - /* We want to turn on some LEDs */ - gpio_high |= GPIO_CPUA_CPU_READY; - gpio_low |= GPIO_CPUA_DEBUG_LED1; - gpio_low |= GPIO_CPUA_DEBUG_LED2; - - /* Disable the unused transmitters */ - gpio_low |= GPIO_CPUA_TDIS1A; - gpio_high |= GPIO_CPUA_TDIS1B; - gpio_low |= GPIO_CPUA_TDIS2A; - gpio_high |= GPIO_CPUA_TDIS2B; - } else { - puts("CPU B\n"); - - /* We want to turn on some LEDs */ - gpio_high |= GPIO_CPUB_CPU_READY; - gpio_low |= GPIO_CPUB_DEBUG_LED1; - gpio_low |= GPIO_CPUB_DEBUG_LED2; - - /* Enable the appropriate receivers */ - gpio_high |= GPIO_CPUB_RMUX_SEL0A; - gpio_high |= GPIO_CPUB_RMUX_SEL0B; - gpio_low |= GPIO_CPUB_RMUX_SEL1A; - gpio_low |= GPIO_CPUB_RMUX_SEL1B; - } - - /* These GPIOs are common */ - gpio_in |= IRQ_I2CINT | IRQ_FANINT | IRQ_DIMM_EVENT; - gpio_low |= GPIO_RS422_RE; - gpio_high |= GPIO_RS422_DE; - - /* Ok, now go ahead and program all of those in one go */ - mpc85xx_gpio_set(gpio_high|gpio_low|gpio_in, - gpio_high|gpio_low, - gpio_high); - - /* - * If things have been taken out of reset early (for example, by one - * of the BDI3000 debuggers), then we need to put them back in reset - * and delay a while before we continue. - */ - if (mpc85xx_gpio_get(GPIO_RESETS)) { - ddr = (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; - - puts("Debugger detected... extra device reset enabled!\n"); - - /* Put stuff into reset and disable the DDR controller */ - mpc85xx_gpio_set_low(GPIO_RESETS); - out_be32(&ddr->sdram_cfg, 0x00000000); - - puts(" Waiting 1 sec for reset..."); - for (i = 0; i < 10; i++) { - udelay(100000); - puts("."); - } - puts("\n"); - } - - /* Now bring everything back out of reset again */ - mpc85xx_gpio_set_high(GPIO_RESETS); - return 0; -} - -/* - * This little shell function just returns whether or not it's CPU A. - * It can be used to select the right device-tree when booting, etc. - */ -int do_hww1u1a_test_cpu_a(cmd_tbl_t *cmdtp, int flag, - int argc, char * const argv[]) -{ - if (argc > 1) - cmd_usage(cmdtp); - - if (hww1u1a_is_cpu_a()) - return 0; - else - return 1; -} -U_BOOT_CMD( - test_cpu_a, 1, 0, do_hww1u1a_test_cpu_a, - "Test if this is CPU A (versus B) on the eXMeritus HWW-1U-1A board", - "" -); - -/* Create a prompt-like string: "uboot@HOSTNAME% " */ -#define PROMPT_PREFIX "uboot@exm" -#define PROMPT_SUFFIX "% " - -/* This function returns a PS1 prompt based on the serial number */ -static char *hww1u1a_prompt; -const char *hww1u1a_get_ps1(void) -{ - unsigned long len, i, j; - const char *serialnr; - - /* If our prompt was already set, just use that */ - if (hww1u1a_prompt) - return hww1u1a_prompt; - - /* Use our serial number if present, otherwise a default */ - serialnr = getenv("serial#"); - if (!serialnr || !serialnr[0]) - serialnr = "999999-X"; - - /* - * We will turn the serial number into a hostname by: - * (A) Delete all non-alphanumerics. - * (B) Lowercase all letters. - * (C) Prefix "exm". - * (D) Suffix "a" for CPU A and "b" for CPU B. - */ - for (i = 0, len = 0; serialnr[i]; i++) { - if (isalnum(serialnr[i])) - len++; - } - - len += sizeof(PROMPT_PREFIX PROMPT_SUFFIX) + 1; /* Includes NUL */ - hww1u1a_prompt = malloc(len); - if (!hww1u1a_prompt) - return PROMPT_PREFIX "UNKNOWN(ENOMEM)" PROMPT_SUFFIX; - - /* Now actually fill it in */ - i = 0; - - /* Handle the prefix */ - for (j = 0; j < sizeof(PROMPT_PREFIX) - 1; j++) - hww1u1a_prompt[i++] = PROMPT_PREFIX[j]; - - /* Now the serial# part of the hostname */ - for (j = 0; serialnr[j]; j++) - if (isalnum(serialnr[j])) - hww1u1a_prompt[i++] = tolower(serialnr[j]); - - /* Now the CPU id ("a" or "b") */ - hww1u1a_prompt[i++] = hww1u1a_is_cpu_a() ? 'a' : 'b'; - - /* Finally the suffix */ - for (j = 0; j < sizeof(PROMPT_SUFFIX); j++) - hww1u1a_prompt[i++] = PROMPT_SUFFIX[j]; - - /* This should all have added up, but just in case */ - hww1u1a_prompt[len - 1] = '\0'; - - /* Now we're done */ - return hww1u1a_prompt; -} - -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - int flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap bootflash region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - if (flash_esel == -1) { - /* very unlikely unless something is messed up */ - puts("Error: Could not find TLB for FLASH BASE\n"); - flash_esel = 2; /* give our best effort to continue */ - } else { - /* invalidate existing TLB entry for FLASH */ - disable_tlb(flash_esel); - } - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_256M, 1); - - return 0; -} - -int board_eth_init(bd_t *bis) -{ - struct tsec_info_struct tsec_info[4]; - struct fsl_pq_mdio_info mdio_info; - - SET_STD_TSEC_INFO(tsec_info[0], 1); - SET_STD_TSEC_INFO(tsec_info[1], 2); - SET_STD_TSEC_INFO(tsec_info[2], 3); - - if (hww1u1a_is_cpu_a()) - tsec_info[2].phyaddr = TSEC3_PHY_ADDR_CPUA; - else - tsec_info[2].phyaddr = TSEC3_PHY_ADDR_CPUB; - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - fsl_pq_mdio_init(bis, &mdio_info); - - tsec_eth_init(bis, tsec_info, 3); - return pci_eth_init(bis); -} - -void ft_board_setup(void *blob, bd_t *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = getenv_bootm_low(); - size = getenv_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - - FT_FSL_PCI_SETUP; -} diff --git a/board/exmeritus/hww1u1a/law.c b/board/exmeritus/hww1u1a/law.c deleted file mode 100644 index c7dc58d..0000000 --- a/board/exmeritus/hww1u1a/law.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright 2008-2009 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/exmeritus/hww1u1a/tlb.c b/board/exmeritus/hww1u1a/tlb.c deleted file mode 100644 index 7f5a36f..0000000 --- a/board/exmeritus/hww1u1a/tlb.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright 2009-2010 eXMeritus, A Boeing Company - * Copyright 2008-2009 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 0 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 0 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Boot page */ - SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, - CONFIG_BPTR_VIRT_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, - CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - - /* - * W**G* - FLASH (Will be *I*G* after relocation to RAM) - * - * This maps both SPI FLASH chips (128MByte per chip) - */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * *I*G* - PCI memory - * - * We have 1.5GB total PCI-E memory space to map and we want to use - * the minimum possible number of TLB entries. Since Book-E TLB - * entries are sized in powers of 4, we use 1GB + 256MB + 256MB. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, - CONFIG_SYS_PCIE3_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_1G, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, - CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, - CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), - - /* - * *I*G* - PCI I/O - * - * This one entry covers all 3 64k PCI-E I/O windows - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, - CONFIG_SYS_PCIE3_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_256K, 1), -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc5121ads/README b/board/freescale/mpc5121ads/README index defcd6b..741bc40 100644 --- a/board/freescale/mpc5121ads/README +++ b/board/freescale/mpc5121ads/README @@ -1,7 +1,7 @@ To configure for the current (Rev 3.x) ADS5121 - make ads5121_config + make mpc5121ads_config This will automatically include PCI, the Real Time CLock, add backup flash ability and set the correct frequency and memory configuration. To configure for the older Rev 2 ADS5121 type (this will not have PCI) - make ads5121_rev2_config + make mpc5121ads_rev2_config diff --git a/board/hymod/Kconfig b/board/hymod/Kconfig deleted file mode 100644 index fa162eb..0000000 --- a/board/hymod/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_HYMOD - -config SYS_BOARD - default "hymod" - -config SYS_CONFIG_NAME - default "hymod" - -endif diff --git a/board/hymod/MAINTAINERS b/board/hymod/MAINTAINERS deleted file mode 100644 index e27fe97..0000000 --- a/board/hymod/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -HYMOD BOARD -M: Murray Jensen <Murray.Jensen@csiro.au> -S: Maintained -F: board/hymod/ -F: include/configs/hymod.h -F: configs/hymod_defconfig diff --git a/board/hymod/Makefile b/board/hymod/Makefile deleted file mode 100644 index b9080b0..0000000 --- a/board/hymod/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = hymod.o flash.o bsp.o eeprom.o fetch.o input.o env.o diff --git a/board/hymod/bsp.c b/board/hymod/bsp.c deleted file mode 100644 index e54640f..0000000 --- a/board/hymod/bsp.c +++ /dev/null @@ -1,387 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * hacked for Hymod FPGA support by Murray.Jensen@csiro.au, 29-Jan-01 - */ - -#include <common.h> -#include <command.h> -#include <net.h> -#include <asm/iopin_8260.h> - -DECLARE_GLOBAL_DATA_PTR; - -/*----------------------------------------------------------------------- - * Board Special Commands: FPGA load/store, EEPROM erase - */ - -#if defined(CONFIG_CMD_BSP) - -#define LOAD_SUCCESS 0 -#define LOAD_FAIL_NOCONF 1 -#define LOAD_FAIL_NOINIT 2 -#define LOAD_FAIL_NODONE 3 - -#define STORE_SUCCESS 0 - -/* - * Programming the Hymod FPGAs - * - * The 8260 io port config table is set up so that the INIT pin is - * held Low (Open Drain output 0) - this will delay the automatic - * Power-On config until INIT is released (by making it an input). - * - * If the FPGA has been programmed before, then the assertion of PROGRAM - * will initiate configuration (i.e. it begins clearing the RAM). - * - * When the FPGA is ready to receive configuration data (either after - * releasing INIT after Power-On, or after asserting PROGRAM), it will - * pull INIT high. - * - * Notes from Paul Dunn: - * - * 1. program pin should be forced low for >= 300ns - * (about 20 bus clock cycles minimum). - * - * 2. then wait for init to go high, which signals - * that the FPGA has cleared its internal memory - * and is ready to load - * - * 3. perform load writes of entire config file - * - * 4. wait for done to go high, which should be - * within a few bus clock cycles. If done has not - * gone high after reasonable period, then load - * has not worked (wait several ms?) - */ - -int -fpga_load(int mezz, const uchar *addr, ulong size) -{ - hymod_conf_t *cp = &gd->bd->bi_hymod_conf; - xlx_info_t *fp; - xlx_iopins_t *fpgaio; - volatile uchar *fpgabase; - volatile uint cnt; - const uchar *eaddr = addr + size; - int result; - - if (mezz) - fp = &cp->mezz.xlx[0]; - else - fp = &cp->main.xlx[0]; - - if (!fp->mmap.prog.exists) - return (LOAD_FAIL_NOCONF); - - fpgabase = (uchar *)fp->mmap.prog.base; - fpgaio = &fp->iopins; - - /* set enable HIGH if required */ - if (fpgaio->enable_pin.flag) - iopin_set_high (&fpgaio->enable_pin); - - /* ensure INIT is released (set it to be an input) */ - iopin_set_in (&fpgaio->init_pin); - - /* toggle PROG Low then High (will already be Low after Power-On) */ - iopin_set_low (&fpgaio->prog_pin); - udelay (1); /* minimum 300ns - 1usec should do it */ - iopin_set_high (&fpgaio->prog_pin); - - /* wait for INIT High */ - cnt = 0; - while (!iopin_is_high (&fpgaio->init_pin)) - if (++cnt == 10000000) { - result = LOAD_FAIL_NOINIT; - goto done; - } - - /* write configuration data */ - while (addr < eaddr) - *fpgabase = *addr++; - - /* wait for DONE High */ - cnt = 0; - while (!iopin_is_high (&fpgaio->done_pin)) - if (++cnt == 100000000) { - result = LOAD_FAIL_NODONE; - goto done; - } - - /* success */ - result = LOAD_SUCCESS; - - done: - - if (fpgaio->enable_pin.flag) - iopin_set_low (&fpgaio->enable_pin); - - return (result); -} - -/* ------------------------------------------------------------------------- */ -int -do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - uchar *addr, *save_addr; - ulong size; - int mezz, arg, result; - - switch (argc) { - - case 0: - case 1: - break; - - case 2: - if (strcmp (argv[1], "info") == 0) { - printf ("\nHymod FPGA Info...\n"); - printf ("\t\t\t\tAddress\t\tSize\n"); - printf ("\tMain Configuration:\t0x%08x\t%d\n", - FPGA_MAIN_CFG_BASE, FPGA_MAIN_CFG_SIZE); - printf ("\tMain Register:\t\t0x%08x\t%d\n", - FPGA_MAIN_REG_BASE, FPGA_MAIN_REG_SIZE); - printf ("\tMain Port:\t\t0x%08x\t%d\n", - FPGA_MAIN_PORT_BASE, FPGA_MAIN_PORT_SIZE); - printf ("\tMezz Configuration:\t0x%08x\t%d\n", - FPGA_MEZZ_CFG_BASE, FPGA_MEZZ_CFG_SIZE); - return 0; - } - break; - - case 3: - if (strcmp (argv[1], "store") == 0) { - addr = (uchar *) simple_strtoul (argv[2], NULL, 16); - - save_addr = addr; -#if 0 - /* fpga readback unimplemented */ - while (more readback data) - *addr++ = *fpga; - result = error ? STORE_FAIL_XXX : STORE_SUCCESS; -#else - result = STORE_SUCCESS; -#endif - - if (result == STORE_SUCCESS) { - printf ("SUCCEEDED (%d bytes)\n", - addr - save_addr); - return 0; - } else - printf ("FAILED (%d bytes)\n", - addr - save_addr); - return 1; - } - break; - - case 4: - if (strcmp (argv[1], "tftp") == 0) { - copy_filename (BootFile, argv[2], sizeof (BootFile)); - load_addr = simple_strtoul (argv[3], NULL, 16); - NetBootFileXferSize = 0; - - if (NetLoop(TFTPGET) <= 0) { - printf ("tftp transfer failed - aborting " - "fgpa load\n"); - return 1; - } - - if (NetBootFileXferSize == 0) { - printf ("can't determine file size - " - "aborting fpga load\n"); - return 1; - } - - printf ("File transfer succeeded - " - "beginning fpga load..."); - - result = fpga_load (0, (uchar *) load_addr, - NetBootFileXferSize); - - if (result == LOAD_SUCCESS) { - printf ("SUCCEEDED\n"); - return 0; - } else if (result == LOAD_FAIL_NOCONF) - printf ("FAILED (no CONF)\n"); - else if (result == LOAD_FAIL_NOINIT) - printf ("FAILED (no INIT)\n"); - else - printf ("FAILED (no DONE)\n"); - return 1; - - } - /* fall through ... */ - - case 5: - if (strcmp (argv[1], "load") == 0) { - if (argc == 5) { - if (strcmp (argv[2], "main") == 0) - mezz = 0; - else if (strcmp (argv[2], "mezz") == 0) - mezz = 1; - else { - printf ("FPGA type must be either " - "`main' or `mezz'\n"); - return 1; - } - arg = 3; - } else { - mezz = 0; - arg = 2; - } - - addr = (uchar *) simple_strtoul (argv[arg++], NULL, 16); - size = (ulong) simple_strtoul (argv[arg], NULL, 16); - - result = fpga_load (mezz, addr, size); - - if (result == LOAD_SUCCESS) { - printf ("SUCCEEDED\n"); - return 0; - } else if (result == LOAD_FAIL_NOCONF) - printf ("FAILED (no CONF)\n"); - else if (result == LOAD_FAIL_NOINIT) - printf ("FAILED (no INIT)\n"); - else - printf ("FAILED (no DONE)\n"); - return 1; - } - break; - - default: - break; - } - - return cmd_usage(cmdtp); -} -U_BOOT_CMD( - fpga, 6, 1, do_fpga, - "FPGA sub-system", - "load [type] addr size\n" - " - write the configuration data at memory address `addr',\n" - " size `size' bytes, into the FPGA of type `type' (either\n" - " `main' or `mezz', default `main'). e.g.\n" - " `fpga load 100000 7d8f'\n" - " loads the main FPGA with config data at address 100000\n" - " HEX, size 7d8f HEX (32143 DEC) bytes\n" - "fpga tftp file addr\n" - " - transfers `file' from the tftp server into memory at\n" - " address `addr', then writes the entire file contents\n" - " into the main FPGA\n" - "fpga store addr\n" - " - read configuration data from the main FPGA (the mezz\n" - " FPGA is write-only), into address `addr'. There must be\n" - " enough memory available at `addr' to hold all the config\n" - " data - the size of which is determined by VC:???\n" - "fpga info\n" - " - print information about the Hymod FPGA, namely the\n" - " memory addresses at which the four FPGA local bus\n" - " address spaces appear in the physical address space" -); -/* ------------------------------------------------------------------------- */ -int -do_eecl (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - uchar data[HYMOD_EEPROM_SIZE]; - uint addr = CONFIG_SYS_I2C_EEPROM_ADDR; - - switch (argc) { - - case 1: - addr |= HYMOD_EEOFF_MAIN; - break; - - case 2: - if (strcmp (argv[1], "main") == 0) { - addr |= HYMOD_EEOFF_MAIN; - break; - } - if (strcmp (argv[1], "mezz") == 0) { - addr |= HYMOD_EEOFF_MEZZ; - break; - } - /* fall through ... */ - - default: - return cmd_usage(cmdtp); - } - - memset (data, 0, HYMOD_EEPROM_SIZE); - - eeprom_write (addr, 0, data, HYMOD_EEPROM_SIZE); - - return 0; -} -U_BOOT_CMD( - eeclear, 1, 0, do_eecl, - "Clear the eeprom on a Hymod board", - "[type]\n" - " - write zeroes into the EEPROM on the board of type `type'\n" - " (`type' is either `main' or `mezz' - default `main')\n" - " Note: the EEPROM write enable jumper must be installed" -); - -/* ------------------------------------------------------------------------- */ - -int -do_htest (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ -#if 0 - int rc; -#endif -#ifdef CONFIG_ETHER_LOOPBACK_TEST - extern void eth_loopback_test (void); -#endif /* CONFIG_ETHER_LOOPBACK_TEST */ - - printf ("HYMOD tests - ensure loopbacks etc. are connected\n\n"); - -#if 0 - /* Load FPGA with test program */ - - printf ("Loading test FPGA program ..."); - - rc = fpga_load (0, test_bitfile, sizeof (test_bitfile)); - - switch (rc) { - - case LOAD_SUCCESS: - printf (" SUCCEEDED\n"); - break; - - case LOAD_FAIL_NOCONF: - printf (" FAILED (no configuration space defined)\n"); - return 1; - - case LOAD_FAIL_NOINIT: - printf (" FAILED (timeout - no INIT signal seen)\n"); - return 1; - - case LOAD_FAIL_NODONE: - printf (" FAILED (timeout - no DONE signal seen)\n"); - return 1; - - default: - printf (" FAILED (unknown return code from fpga_load\n"); - return 1; - } - - /* run Local Bus <=> Xilinx tests */ - - /* tell Xilinx to run ZBT Ram, High Speed serial and Mezzanine tests */ - - /* run SDRAM test */ -#endif - -#ifdef CONFIG_ETHER_LOOPBACK_TEST - /* run Ethernet test */ - eth_loopback_test (); -#endif /* CONFIG_ETHER_LOOPBACK_TEST */ - - return 0; -} - -#endif diff --git a/board/hymod/config.mk b/board/hymod/config.mk deleted file mode 100644 index 2eeea50..0000000 --- a/board/hymod/config.mk +++ /dev/null @@ -1,14 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# HYMOD boards -# - -PLATFORM_CPPFLAGS += -I$(srctree) - -OBJCOPYFLAGS = --remove-section=.ppcenv diff --git a/board/hymod/eeprom.c b/board/hymod/eeprom.c deleted file mode 100644 index ffb0df1..0000000 --- a/board/hymod/eeprom.c +++ /dev/null @@ -1,678 +0,0 @@ -/* - * (C) Copyright 2001 - * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8260.h> - -/* imports from fetch.c */ -extern int fetch_and_parse (char *, ulong, int (*)(uchar *, uchar *)); - -/* imports from input.c */ -extern int hymod_get_serno (const char *); - -/* this is relative to the root of the server's tftp directory */ -static char *def_bddb_cfgdir = "/hymod/bddb"; - -static int -hymod_eeprom_load (int which, hymod_eeprom_t *ep) -{ - unsigned dev_addr = CONFIG_SYS_I2C_EEPROM_ADDR | \ - (which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN); - unsigned offset = 0; - uchar data[HYMOD_EEPROM_MAXLEN], *dp, *edp; - hymod_eehdr_t hdr; - ulong len, crc; - - memset (ep, 0, sizeof *ep); - - eeprom_read (dev_addr, offset, (uchar *)&hdr, sizeof (hdr)); - offset += sizeof (hdr); - - if (hdr.id != HYMOD_EEPROM_ID || hdr.ver > HYMOD_EEPROM_VER || - (len = hdr.len) > HYMOD_EEPROM_MAXLEN) - return (0); - - eeprom_read (dev_addr, offset, data, len); - offset += len; - - eeprom_read (dev_addr, offset, (uchar *)&crc, sizeof (ulong)); - offset += sizeof (ulong); - - if (crc32 (crc32 (0, (uchar *)&hdr, sizeof hdr), data, len) != crc) - return (0); - - ep->ver = hdr.ver; - dp = data; edp = dp + len; - - for (;;) { - ulong rtyp; - uchar rlen, *rdat; - - rtyp = *dp++; - if ((rtyp & 0x80) == 0) - rlen = *dp++; - else { - uchar islarge = rtyp & 0x40; - - rtyp = ((rtyp & 0x3f) << 8) | *dp++; - if (islarge) { - rtyp = (rtyp << 8) | *dp++; - rtyp = (rtyp << 8) | *dp++; - } - - rlen = *dp++; - rlen = (rlen << 8) | *dp++; - if (islarge) { - rlen = (rlen << 8) | *dp++; - rlen = (rlen << 8) | *dp++; - } - } - - if (rtyp == 0) - break; - - rdat = dp; - dp += rlen; - - if (dp > edp) /* error? */ - break; - - switch (rtyp) { - - case HYMOD_EEREC_SERNO: /* serial number */ - if (rlen == sizeof (ulong)) - ep->serno = \ - ((ulong)rdat[0] << 24) | \ - ((ulong)rdat[1] << 16) | \ - ((ulong)rdat[2] << 8) | \ - (ulong)rdat[3]; - break; - - case HYMOD_EEREC_DATE: /* date */ - if (rlen == sizeof (hymod_date_t)) { - ep->date.year = ((ushort)rdat[0] << 8) | \ - (ushort)rdat[1]; - ep->date.month = rdat[2]; - ep->date.day = rdat[3]; - } - break; - - case HYMOD_EEREC_BATCH: /* batch */ - if (rlen <= HYMOD_MAX_BATCH) - memcpy (ep->batch, rdat, ep->batchlen = rlen); - break; - - case HYMOD_EEREC_TYPE: /* board type */ - if (rlen == 1) - ep->bdtype = *rdat; - break; - - case HYMOD_EEREC_REV: /* board revision */ - if (rlen == 1) - ep->bdrev = *rdat; - break; - - case HYMOD_EEREC_SDRAM: /* sdram size(s) */ - if (rlen > 0 && rlen <= HYMOD_MAX_SDRAM) { - int i; - - for (i = 0; i < rlen; i++) - ep->sdramsz[i] = rdat[i]; - ep->nsdram = rlen; - } - break; - - case HYMOD_EEREC_FLASH: /* flash size(s) */ - if (rlen > 0 && rlen <= HYMOD_MAX_FLASH) { - int i; - - for (i = 0; i < rlen; i++) - ep->flashsz[i] = rdat[i]; - ep->nflash = rlen; - } - break; - - case HYMOD_EEREC_ZBT: /* zbt ram size(s) */ - if (rlen > 0 && rlen <= HYMOD_MAX_ZBT) { - int i; - - for (i = 0; i < rlen; i++) - ep->zbtsz[i] = rdat[i]; - ep->nzbt = rlen; - } - break; - - case HYMOD_EEREC_XLXTYP: /* xilinx fpga type(s) */ - if (rlen > 0 && rlen <= HYMOD_MAX_XLX) { - int i; - - for (i = 0; i < rlen; i++) - ep->xlx[i].type = rdat[i]; - ep->nxlx = rlen; - } - break; - - case HYMOD_EEREC_XLXSPD: /* xilinx fpga speed(s) */ - if (rlen > 0 && rlen <= HYMOD_MAX_XLX) { - int i; - - for (i = 0; i < rlen; i++) - ep->xlx[i].speed = rdat[i]; - } - break; - - case HYMOD_EEREC_XLXTMP: /* xilinx fpga temperature(s) */ - if (rlen > 0 && rlen <= HYMOD_MAX_XLX) { - int i; - - for (i = 0; i < rlen; i++) - ep->xlx[i].temp = rdat[i]; - } - break; - - case HYMOD_EEREC_XLXGRD: /* xilinx fpga grade(s) */ - if (rlen > 0 && rlen <= HYMOD_MAX_XLX) { - int i; - - for (i = 0; i < rlen; i++) - ep->xlx[i].grade = rdat[i]; - } - break; - - case HYMOD_EEREC_CPUTYP: /* CPU type */ - if (rlen == 1) - ep->mpc.type = *rdat; - break; - - case HYMOD_EEREC_CPUSPD: /* CPU speed */ - if (rlen == 1) - ep->mpc.cpuspd = *rdat; - break; - - case HYMOD_EEREC_CPMSPD: /* CPM speed */ - if (rlen == 1) - ep->mpc.cpmspd = *rdat; - break; - - case HYMOD_EEREC_BUSSPD: /* bus speed */ - if (rlen == 1) - ep->mpc.busspd = *rdat; - break; - - case HYMOD_EEREC_HSTYPE: /* hs-serial chip type */ - if (rlen == 1) - ep->hss.type = *rdat; - break; - - case HYMOD_EEREC_HSCHIN: /* num hs-serial input chans */ - if (rlen == 1) - ep->hss.nchin = *rdat; - break; - - case HYMOD_EEREC_HSCHOUT: /* num hs-serial output chans */ - if (rlen == 1) - ep->hss.nchout = *rdat; - break; - - default: /* ignore */ - break; - } - } - - return (1); -} - -/* maps an ascii "name=value" into a binary eeprom data record */ -typedef - struct _eerec_map { - char *name; - uint type; - uchar *(*handler) \ - (struct _eerec_map *, uchar *, uchar *, uchar *); - uint length; - uint maxlen; - } -eerec_map_t; - -static uchar * -uint_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp) -{ - char *eval; - ulong lval; - - lval = simple_strtol ((char *)val, &eval, 10); - - if ((uchar *)eval == val || *eval != '\0') { - printf ("%s rec (%s) is not a valid uint\n", rp->name, val); - return (NULL); - } - - if (dp + 2 + rp->length > edp) { - printf ("can't fit %s rec into eeprom\n", rp->name); - return (NULL); - } - - *dp++ = rp->type; - *dp++ = rp->length; - - switch (rp->length) { - - case 1: - if (lval >= 256) { - printf ("%s rec value (%lu) out of range (0-255)\n", - rp->name, lval); - return (NULL); - } - *dp++ = lval; - break; - - case 2: - if (lval >= 65536) { - printf ("%s rec value (%lu) out of range (0-65535)\n", - rp->name, lval); - return (NULL); - } - *dp++ = lval >> 8; - *dp++ = lval; - break; - - case 4: - *dp++ = lval >> 24; - *dp++ = lval >> 16; - *dp++ = lval >> 8; - *dp++ = lval; - break; - - default: - printf ("huh? rp->length not 1, 2 or 4! (%d)\n", rp->length); - return (NULL); - } - - return (dp); -} - -static uchar * -date_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp) -{ - hymod_date_t date; - char *p = (char *)val; - char *ep; - ulong lval; - - lval = simple_strtol (p, &ep, 10); - if (ep == p || *ep++ != '-') { -bad_date: - printf ("%s rec (%s) is not a valid date\n", rp->name, val); - return (NULL); - } - if (lval >= 65536) - goto bad_date; - date.year = lval; - - lval = simple_strtol (p = ep, &ep, 10); - if (ep == p || *ep++ != '-' || lval == 0 || lval > 12) - goto bad_date; - date.month = lval; - - lval = simple_strtol (p = ep, &ep, 10); - if (ep == p || *ep != '\0' || lval == 0 || lval > 31) - goto bad_date; - date.day = lval; - - if (dp + 2 + rp->length > edp) { - printf ("can't fit %s rec into eeprom\n", rp->name); - return (NULL); - } - - *dp++ = rp->type; - *dp++ = rp->length; - *dp++ = date.year >> 8; - *dp++ = date.year; - *dp++ = date.month; - *dp++ = date.day; - - return (dp); -} - -static uchar * -string_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp) -{ - uint len; - - if ((len = strlen ((char *)val)) > rp->maxlen) { - printf ("%s rec (%s) string is too long (%d>%d)\n", - rp->name, val, len, rp->maxlen); - return (NULL); - } - - if (dp + 2 + len > edp) { - printf ("can't fit %s rec into eeprom\n", rp->name); - return (NULL); - } - - *dp++ = rp->type; - *dp++ = len; - memcpy (dp, val, len); - dp += len; - - return (dp); -} - -static uchar * -bytes_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp) -{ - uchar bytes[HYMOD_MAX_BYTES], nbytes, *p; - char *ep; - - for (nbytes = 0, p = val; *p != '\0'; p = (uchar *)ep) { - ulong lval; - - lval = simple_strtol ((char *)p, &ep, 10); - if ((uchar *)ep == p || (*ep != '\0' && *ep != ',') || \ - lval >= 256) { - printf ("%s rec (%s) byte array has invalid uint\n", - rp->name, val); - return (NULL); - } - if (nbytes >= HYMOD_MAX_BYTES) { - printf ("%s rec (%s) byte array too long\n", - rp->name, val); - return (NULL); - } - bytes[nbytes++] = lval; - - if (*ep != '\0') - ep++; - } - - if (dp + 2 + nbytes > edp) { - printf ("can't fit %s rec into eeprom\n", rp->name); - return (NULL); - } - - *dp++ = rp->type; - *dp++ = nbytes; - memcpy (dp, bytes, nbytes); - dp += nbytes; - - return (dp); -} - -static eerec_map_t eerec_map[] = { - /* name type handler len max */ - { "serno", HYMOD_EEREC_SERNO, uint_handler, 4, 0 }, - { "date", HYMOD_EEREC_DATE, date_handler, 4, 0 }, - { "batch", HYMOD_EEREC_BATCH, string_handler, 0, HYMOD_MAX_BATCH }, - { "type", HYMOD_EEREC_TYPE, uint_handler, 1, 0 }, - { "rev", HYMOD_EEREC_REV, uint_handler, 1, 0 }, - { "sdram", HYMOD_EEREC_SDRAM, bytes_handler, 0, HYMOD_MAX_SDRAM }, - { "flash", HYMOD_EEREC_FLASH, bytes_handler, 0, HYMOD_MAX_FLASH }, - { "zbt", HYMOD_EEREC_ZBT, bytes_handler, 0, HYMOD_MAX_ZBT }, - { "xlxtyp", HYMOD_EEREC_XLXTYP, bytes_handler, 0, HYMOD_MAX_XLX }, - { "xlxspd", HYMOD_EEREC_XLXSPD, bytes_handler, 0, HYMOD_MAX_XLX }, - { "xlxtmp", HYMOD_EEREC_XLXTMP, bytes_handler, 0, HYMOD_MAX_XLX }, - { "xlxgrd", HYMOD_EEREC_XLXGRD, bytes_handler, 0, HYMOD_MAX_XLX }, - { "cputyp", HYMOD_EEREC_CPUTYP, uint_handler, 1, 0 }, - { "cpuspd", HYMOD_EEREC_CPUSPD, uint_handler, 1, 0 }, - { "cpmspd", HYMOD_EEREC_CPMSPD, uint_handler, 1, 0 }, - { "busspd", HYMOD_EEREC_BUSSPD, uint_handler, 1, 0 }, - { "hstype", HYMOD_EEREC_HSTYPE, uint_handler, 1, 0 }, - { "hschin", HYMOD_EEREC_HSCHIN, uint_handler, 1, 0 }, - { "hschout", HYMOD_EEREC_HSCHOUT, uint_handler, 1, 0 }, -}; - -static int neerecs = sizeof eerec_map / sizeof eerec_map[0]; - -static uchar data[HYMOD_EEPROM_SIZE], *sdp, *dp, *edp; - -static int -eerec_callback (uchar *name, uchar *val) -{ - eerec_map_t *rp; - - for (rp = eerec_map; rp < &eerec_map[neerecs]; rp++) - if (strcmp ((char *)name, rp->name) == 0) - break; - - if (rp >= &eerec_map[neerecs]) - return (0); - - if ((dp = (*rp->handler) (rp, val, dp, edp)) == NULL) - return (0); - - return (1); -} - -static int -hymod_eeprom_fetch(int which, char *filename, ulong addr) -{ - unsigned dev_addr = CONFIG_SYS_I2C_EEPROM_ADDR | \ - (which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN); - hymod_eehdr_t *hp = (hymod_eehdr_t *)&data[0]; - ulong crc; - - memset (hp, 0, sizeof *hp); - hp->id = HYMOD_EEPROM_ID; - hp->ver = HYMOD_EEPROM_VER; - - dp = sdp = (uchar *)(hp + 1); - edp = dp + HYMOD_EEPROM_MAXLEN; - - if (fetch_and_parse (filename, addr, eerec_callback) == 0) - return (0); - - hp->len = dp - sdp; - - crc = crc32 (0, data, dp - data); - memcpy (dp, &crc, sizeof (ulong)); - dp += sizeof (ulong); - - eeprom_write (dev_addr, 0, data, dp - data); - - return (1); -} - -static char *type_vals[] = { - "NONE", "IO", "CLP", "DSP", "INPUT", "ALT-INPUT", "DISPLAY" -}; - -static char *xlxtyp_vals[] = { - "NONE", "XCV300E", "XCV400E", "XCV600E" -}; - -static char *xlxspd_vals[] = { - "NONE", "6", "7", "8" -}; - -static char *xlxtmp_vals[] = { - "NONE", "COM", "IND" -}; - -static char *xlxgrd_vals[] = { - "NONE", "NORMAL", "ENGSAMP" -}; - -static char *cputyp_vals[] = { - "NONE", "MPC8260" -}; - -static char *clk_vals[] = { - "NONE", "33", "66", "100", "133", "166", "200" -}; - -static char *hstype_vals[] = { - "NONE", "AMCC-S2064A" -}; - -static void -print_mem (char *l, char *s, uchar n, uchar a[]) -{ - if (n > 0) { - if (n == 1) - printf ("%s%dMB %s", s, 1 << (a[0] - 20), l); - else { - ulong t = 0; - int i; - - for (i = 0; i < n; i++) - t += 1 << (a[i] - 20); - - printf ("%s%luMB %s (%d banks:", s, t, l, n); - - for (i = 0; i < n; i++) - printf ("%dMB%s", - 1 << (a[i] - 20), - (i == n - 1) ? ")" : ","); - } - } - else - printf ("%sNO %s", s, l); -} - -void -hymod_eeprom_print (hymod_eeprom_t *ep) -{ - int i; - - printf (" Hymod %s board, rev %03d\n", - type_vals[ep->bdtype], ep->bdrev); - - printf (" serial #: %010lu, date %04d-%02d-%02d", - ep->serno, ep->date.year, ep->date.month, ep->date.day); - if (ep->batchlen > 0) - printf (", batch \"%.*s\"", ep->batchlen, ep->batch); - puts ("\n"); - - switch (ep->bdtype) { - - case HYMOD_BDTYPE_IO: - case HYMOD_BDTYPE_CLP: - case HYMOD_BDTYPE_DSP: - printf (" Motorola %s CPU, speeds: %s/%s/%s", - cputyp_vals[ep->mpc.type], clk_vals[ep->mpc.cpuspd], - clk_vals[ep->mpc.cpmspd], clk_vals[ep->mpc.busspd]); - - print_mem ("SDRAM", ", ", ep->nsdram, ep->sdramsz); - - print_mem ("FLASH", ", ", ep->nflash, ep->flashsz); - - puts ("\n"); - - print_mem ("ZBT", " ", ep->nzbt, ep->zbtsz); - - if (ep->nxlx > 0) { - hymod_xlx_t *xp; - - if (ep->nxlx == 1) { - xp = &ep->xlx[0]; - printf (", Xilinx %s FPGA (%s/%s/%s)", - xlxtyp_vals[xp->type], - xlxspd_vals[xp->speed], - xlxtmp_vals[xp->temp], - xlxgrd_vals[xp->grade]); - } - else { - printf (", %d Xilinx FPGAs (", ep->nxlx); - for (i = 0; i < ep->nxlx; i++) { - xp = &ep->xlx[i]; - printf ("%s[%s/%s/%s]%s", - xlxtyp_vals[xp->type], - xlxspd_vals[xp->speed], - xlxtmp_vals[xp->temp], - xlxgrd_vals[xp->grade], - (i == ep->nxlx - 1) ? ")" : ", "); - } - } - } - else - puts(", NO FPGAs"); - - puts ("\n"); - - if (ep->hss.type > 0) - printf (" High Speed Serial: " - "%s, %d input%s, %d output%s\n", - hstype_vals[ep->hss.type], - ep->hss.nchin, - (ep->hss.nchin == 1 ? "" : "s"), - ep->hss.nchout, - (ep->hss.nchout == 1 ? "" : "s")); - break; - - case HYMOD_BDTYPE_INPUT: - case HYMOD_BDTYPE_ALTINPUT: - case HYMOD_BDTYPE_DISPLAY: - break; - - default: - /* crap! */ - printf (" UNKNOWN BOARD TYPE: %d\n", ep->bdtype); - break; - } -} - -int -hymod_eeprom_read (int which, hymod_eeprom_t *ep) -{ - char *label = which ? "mezzanine" : "main"; - unsigned dev_addr = CONFIG_SYS_I2C_EEPROM_ADDR | \ - (which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN); - char filename[50], prompt[50], *dir; - int serno, count = 0, rc; - - rc = eeprom_probe (dev_addr, 0); - - if (rc > 0) { - printf ("*** probe for eeprom failed with code %d\n", rc); - return (0); - } - - if (rc < 0) - return (rc); - - sprintf (prompt, "Enter %s board serial number: ", label); - - if ((dir = getenv ("bddb_cfgdir")) == NULL) - dir = def_bddb_cfgdir; - - for (;;) { - int rc; - - if (hymod_eeprom_load (which, ep)) - return (1); - - printf ("*** %s board EEPROM contents are %sinvalid\n", - label, count == 0 ? "" : "STILL "); - - puts ("*** will fetch from server (Ctrl-C to abort)\n"); - - serno = hymod_get_serno (prompt); - - if (serno < 0) { - if (serno == -1) - puts ("\n*** interrupted!"); - else - puts ("\n*** timeout!"); - puts (" - ignoring eeprom contents\n"); - return (0); - } - - sprintf (filename, "%s/%010d.cfg", dir, serno); - - printf ("*** fetching %s board EEPROM contents from server\n", - label); - - rc = hymod_eeprom_fetch (which, filename, CONFIG_SYS_LOAD_ADDR); - - if (rc == 0) { - puts ("*** fetch failed - ignoring eeprom contents\n"); - return (0); - } - - count++; - } -} diff --git a/board/hymod/env.c b/board/hymod/env.c deleted file mode 100644 index 66c5115..0000000 --- a/board/hymod/env.c +++ /dev/null @@ -1,221 +0,0 @@ -/* - * (C) Copyright 2003 - * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <linux/ctype.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* imports from fetch.c */ -extern int fetch_and_parse (char *, ulong, int (*)(uchar *, uchar *)); - -/* this is relative to the root of the server's tftp directory */ -static char *def_global_env_path = "/hymod/global_env"; - -static int -env_callback (uchar *name, uchar *value) -{ - hymod_conf_t *cp = &gd->bd->bi_hymod_conf; - char ov[CONFIG_SYS_CBSIZE], nv[CONFIG_SYS_CBSIZE], *p, *q, *nn, c, *curver, *newver; - int override = 1, append = 0, remove = 0, nnl, ovl, nvl; - - nn = (char *)name; - - if (*nn == '-') { - override = 0; - nn++; - } - - while (isblank(*nn)) - nn++; - - if ((nnl = strlen (nn)) == 0) { - printf ("Empty name in global env file\n"); - return (0); - } - - if ((c = nn[nnl - 1]) == '+' || c == '-') { - if (c == '+') - append = 1; - else - remove = 1; - nn[--nnl] = '\0'; - } - - while (nnl > 0 && isblank(nn[nnl - 1])) - nn[--nnl] = '\0'; - if (nnl == 0) { - printf ("Empty name in global env file\n"); - return (0); - } - - p = (char *)value; - q = nv; - - while (isblank(*p)) - p++; - - nvl = strlen (p); - while (nvl > 0 && isblank(p[nvl - 1])) - p[--nvl] = '\0'; - - while ((*q = *p++) != '\0') { - if (*q == '%') { - switch (*p++) { - - case '\0': /* whoops - back up */ - p--; - break; - - case '%': /* a single percent character */ - q++; - break; - - case 's': /* main board serial number as string */ - q += sprintf (q, "%010lu", - cp->main.eeprom.serno); - break; - - case 'S': /* main board serial number as number */ - q += sprintf (q, "%lu", cp->main.eeprom.serno); - break; - - default: /* ignore any others */ - break; - } - } - else - q++; - } - - if ((nvl = q - nv) == 0) { - setenv (nn, NULL); - return (1); - } - - if ((curver = getenv ("global_env_version")) == NULL) - curver = "unknown"; - - if ((newver = getenv ("new_genv_version")) == NULL || \ - strcmp (curver, newver) == 0) { - if (strcmp (nn, "version") == 0) - setenv ("new_genv_version", nv); - return (1); - } - - if ((p = getenv (nn)) != NULL) { - - strcpy (ov, p); - ovl = strlen (ov); - - if (append) { - - if (strstr (ov, nv) == NULL) { - - printf ("Appending '%s' to env var '%s'\n", - nv, nn); - - while (nvl >= 0) { - nv[ovl + 1 + nvl] = nv[nvl]; - nvl--; - } - - nv[ovl] = ' '; - - while (--ovl >= 0) - nv[ovl] = ov[ovl]; - - setenv (nn, nv); - } - - return (1); - } - - if (remove) { - - if (strstr (ov, nv) != NULL) { - - printf ("Removing '%s' from env var '%s'\n", - nv, nn); - - while ((p = strstr (ov, nv)) != NULL) { - q = p + nvl; - if (*q == ' ') - q++; - strcpy(p, q); - } - - setenv (nn, ov); - } - - return (1); - } - - if (!override || strcmp (ov, nv) == 0) - return (1); - - printf ("Re-setting env cmd '%s' from '%s' to '%s'\n", - nn, ov, nv); - } - else - printf ("Setting env cmd '%s' to '%s'\n", nn, nv); - - setenv (nn, nv); - return (1); -} - -void -hymod_check_env (void) -{ - char *p, *path, *curver, *newver; - int firsttime = 0, needsave = 0; - - if (getenv ("global_env_loaded") == NULL) { - puts ("*** global environment has never been loaded\n"); - puts ("*** fetching from server"); - firsttime = 1; - } - else if ((p = getenv ("always_check_env")) != NULL && - strcmp (p, "yes") == 0) - puts ("*** checking for updated global environment"); - else - return; - - puts (" (Control-C to Abort)\n"); - - if ((path = getenv ("global_env_path")) == NULL || *path == '\0') - path = def_global_env_path; - - if (fetch_and_parse (path, CONFIG_SYS_LOAD_ADDR, env_callback) == 0) { - puts ("*** Fetch of global environment failed!\n"); - return; - } - - if ((newver = getenv ("new_genv_version")) == NULL) { - puts ("*** Version number not set - contents ignored!\n"); - return; - } - - if ((curver = getenv ("global_env_version")) == NULL || \ - strcmp (curver, newver) != 0) { - setenv ("global_env_version", newver); - needsave = 1; - } - else - printf ("*** Global environment up-to-date (ver %s)\n", curver); - - setenv ("new_genv_version", NULL); - - if (firsttime) { - setenv ("global_env_loaded", "yes"); - needsave = 1; - } - - if (needsave) - puts ("\n*** Remember to run the 'saveenv' " - "command to save the changes\n\n"); -} diff --git a/board/hymod/fetch.c b/board/hymod/fetch.c deleted file mode 100644 index da9373f..0000000 --- a/board/hymod/fetch.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * (C) Copyright 2001 - * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <net.h> - -/* imports from input.c */ -extern int hymod_get_ethaddr (void); - -int -fetch_and_parse (char *fn, ulong addr, int (*cback)(uchar *, uchar *)) -{ - char *ethaddr; - uchar *fp, *efp; - int rc, count = 0; - - while ((ethaddr = getenv ("ethaddr")) == NULL || *ethaddr == '\0') { - - printf ("*** Ethernet address is%s not set\n", - count == 0 ? "" : " STILL"); - - if ((rc = hymod_get_ethaddr ()) < 0) { - if (rc == -1) - puts ("\n*** interrupted!"); - else - puts ("\n*** timeout!"); - printf (" - fetch of '%s' aborted\n", fn); - return (0); - } - - count++; - } - - copy_filename (BootFile, fn, sizeof (BootFile)); - load_addr = addr; - NetBootFileXferSize = 0; - - if (NetLoop(TFTPGET) == 0) { - printf ("tftp transfer of file '%s' failed\n", fn); - return (0); - } - - if (NetBootFileXferSize == 0) { - printf ("can't determine size of file '%s'\n", fn); - return (0); - } - - fp = (uchar *)load_addr; - efp = fp + NetBootFileXferSize; - - do { - uchar *name, *value; - - if (*fp == '#' || *fp == '\n') { - /* skip this line */ - while (fp < efp && *fp++ != '\n') - ; - continue; - } - - name = fp; - - while (fp < efp && *fp != '=' && *fp != '\n') - fp++; - if (fp >= efp) - break; - if (*fp == '\n') { - fp++; - continue; - } - *fp++ = '\0'; - - value = fp; - - while (fp < efp && *fp != '\n') - fp++; - if (fp[-1] == '\r') - fp[-1] = '\0'; - *fp++ = '\0'; /* ok if we go off the end here */ - - if ((*cback)(name, value) == 0) - return (0); - - } while (fp < efp); - - return (1); -} diff --git a/board/hymod/flash.c b/board/hymod/flash.c deleted file mode 100644 index 02e519c..0000000 --- a/board/hymod/flash.c +++ /dev/null @@ -1,490 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Hacked for the Hymod board by Murray.Jensen@csiro.au, 20-Oct-00 - */ - -#include <common.h> -#include <mpc8260.h> -#include <board/hymod/flash.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Protection Flags: - */ -#define FLAG_PROTECT_SET 0x01 -#define FLAG_PROTECT_CLEAR 0x02 - -/*----------------------------------------------------------------------- - */ - -/* - * probe for flash bank at address "base" and store info about it - * in the flash_info entry "fip". Fatal error if nothing there. - */ -static void -bank_probe (flash_info_t *fip, volatile bank_addr_t base) -{ - volatile bank_addr_t addr; - bank_word_t word; - int i; - - /* reset the flash */ - *base = BANK_CMD_RST; - - /* put flash into read id mode */ - *base = BANK_CMD_RD_ID; - - /* check the manufacturer id - must be intel */ - word = *BANK_REG_MAN_CODE (base); - if (word != BANK_FILL_WORD (INTEL_MANUFACT&0xff)) - panic ("\nbad manufacturer's code (0x%08lx) at addr 0x%08lx", - (unsigned long)word, (unsigned long)base); - - /* check the device id */ - word = *BANK_REG_DEV_CODE (base); - switch (word) { - - case BANK_FILL_WORD (INTEL_ID_28F320J5&0xff): - fip->flash_id = FLASH_MAN_INTEL | FLASH_28F320J5; - fip->sector_count = 32; - break; - - case BANK_FILL_WORD (INTEL_ID_28F640J5&0xff): - fip->flash_id = FLASH_MAN_INTEL | FLASH_28F640J5; - fip->sector_count = 64; - break; - - case BANK_FILL_WORD (INTEL_ID_28F320J3A&0xff): - fip->flash_id = FLASH_MAN_INTEL | FLASH_28F320J3A; - fip->sector_count = 32; - break; - - case BANK_FILL_WORD (INTEL_ID_28F640J3A&0xff): - fip->flash_id = FLASH_MAN_INTEL | FLASH_28F640J3A; - fip->sector_count = 64; - break; - - case BANK_FILL_WORD (INTEL_ID_28F128J3A&0xff): - fip->flash_id = FLASH_MAN_INTEL | FLASH_28F128J3A; - fip->sector_count = 128; - break; - - default: - panic ("\nbad device code (0x%08lx) at addr 0x%08lx", - (unsigned long)word, (unsigned long)base); - } - - if (fip->sector_count >= CONFIG_SYS_MAX_FLASH_SECT) - panic ("\ntoo many sectors (%d) in flash at address 0x%08lx", - fip->sector_count, (unsigned long)base); - - addr = base; - for (i = 0; i < fip->sector_count; i++) { - fip->start[i] = (unsigned long)addr; - fip->protect[i] = 0; - addr = BANK_ADDR_NEXT_BLK (addr); - } - - fip->size = (bank_size_t)addr - (bank_size_t)base; - - /* reset the flash */ - *base = BANK_CMD_RST; -} - -static void -bank_reset (flash_info_t *info, int sect) -{ - volatile bank_addr_t addr = (bank_addr_t)info->start[sect]; - -#ifdef FLASH_DEBUG - printf ("writing reset cmd to addr 0x%08lx\n", (unsigned long)addr); -#endif - - *addr = BANK_CMD_RST; -} - -static void -bank_erase_init (flash_info_t *info, int sect) -{ - volatile bank_addr_t addr = (bank_addr_t)info->start[sect]; - int flag; - -#ifdef FLASH_DEBUG - printf ("erasing sector %d, addr = 0x%08lx\n", - sect, (unsigned long)addr); -#endif - - /* Disable intrs which might cause a timeout here */ - flag = disable_interrupts (); - -#ifdef FLASH_DEBUG - printf ("writing erase cmd to addr 0x%08lx\n", (unsigned long)addr); -#endif - *addr = BANK_CMD_ERASE1; - *addr = BANK_CMD_ERASE2; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); -} - -static int -bank_erase_poll (flash_info_t *info, int sect) -{ - volatile bank_addr_t addr = (bank_addr_t)info->start[sect]; - bank_word_t stat = *addr; - -#ifdef FLASH_DEBUG - printf ("checking status at addr 0x%08lx [0x%08lx]\n", - (unsigned long)addr, (unsigned long)stat); -#endif - - if ((stat & BANK_STAT_RDY) == BANK_STAT_RDY) { - if ((stat & BANK_STAT_ERR) != 0) { - printf ("failed on sector %d [0x%08lx] at " - "address 0x%08lx\n", sect, - (unsigned long)stat, (unsigned long)addr); - *addr = BANK_CMD_CLR_STAT; - return (-1); - } - else - return (1); - } - else - return (0); -} - -static int -bank_write_word (volatile bank_addr_t addr, bank_word_t value) -{ - bank_word_t stat; - ulong start; - int flag, retval; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = BANK_CMD_PROG; - - *addr = value; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - retval = 0; - - /* data polling for D7 */ - start = get_timer (0); - do { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - retval = 1; - goto done; - } - stat = *addr; - } while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY); - - if ((stat & BANK_STAT_ERR) != 0) { - printf ("flash program failed [0x%08lx] at address 0x%08lx\n", - (unsigned long)stat, (unsigned long)addr); - *addr = BANK_CMD_CLR_STAT; - retval = 3; - } - -done: - /* reset to read mode */ - *addr = BANK_CMD_RST; - - return (retval); -} - -/*----------------------------------------------------------------------- - */ - -unsigned long -flash_init (void) -{ - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - bank_probe (&flash_info[0], (bank_addr_t)CONFIG_SYS_FLASH_BASE); - - /* - * protect monitor and environment sectors - */ - -#if CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE - (void)flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#if defined(CONFIG_SYS_FLASH_ENV_ADDR) - (void)flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_ENV_ADDR, -#if defined(CONFIG_SYS_FLASH_ENV_BUF) - CONFIG_SYS_FLASH_ENV_ADDR + CONFIG_SYS_FLASH_ENV_BUF - 1, -#else - CONFIG_SYS_FLASH_ENV_ADDR + CONFIG_SYS_FLASH_ENV_SIZE - 1, -#endif - &flash_info[0]); -#endif - - return flash_info[0].size; -} - -/*----------------------------------------------------------------------- - */ -void -flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J5: printf ("28F320J5 (32 Mbit, 2 x 16bit)\n"); - break; - case FLASH_28F640J5: printf ("28F640J5 (64 Mbit, 2 x 16bit)\n"); - break; - case FLASH_28F320J3A: printf ("28F320J3A (32 Mbit, 2 x 16bit)\n"); - break; - case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 2 x 16bit)\n"); - break; - case FLASH_28F128J3A: printf ("28F320J3A (128 Mbit, 2 x 16bit)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ - -/*----------------------------------------------------------------------- - */ - -int -flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int prot, sect, haderr; - ulong start, now, last; - int rcode = 0; - -#ifdef FLASH_DEBUG - printf ("\nflash_erase: erase %d sectors (%d to %d incl.) from\n" - " Bank # %d: ", s_last - s_first + 1, s_first, s_last, - (info - flash_info) + 1); - flash_print_info (info); -#endif - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sector%s will not be erased\n", - prot, (prot > 1 ? "s" : "")); - } - - start = get_timer (0); - last = 0; - haderr = 0; - - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - ulong estart; - int sectdone; - - bank_erase_init (info, sect); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - estart = get_timer (start); - - do { - now = get_timer (start); - - if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout (sect %d)\n", sect); - haderr = 1; - rcode = 1; - break; - } - -#ifndef FLASH_DEBUG - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } -#endif - - sectdone = bank_erase_poll (info, sect); - - if (sectdone < 0) { - haderr = 1; - rcode = 1; - break; - } - - } while (!sectdone); - - if (haderr) - break; - } - } - - if (haderr > 0) - printf (" failed\n"); - else - printf (" done\n"); - - /* reset to read mode */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - bank_reset (info, sect); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 3 - Program failed - */ -static int -write_word (flash_info_t *info, ulong dest, ulong data) -{ - /* Check if Flash is (sufficiently) erased */ - if ((*(ulong *)dest & data) != data) - return (2); - - return (bank_write_word ((bank_addr_t)dest, (bank_word_t)data)); -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 3 - Program failed - */ - -int -write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word (info, wp, data)); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/hymod/flash.h b/board/hymod/flash.h deleted file mode 100644 index 6ea2823..0000000 --- a/board/hymod/flash.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * (C) Copyright 2000 - * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*************** DEFINES for Intel StrataFlash FLASH chip ********************/ - -/* Commands */ -#define ISF_CMD_RST 0xFF /* reset flash */ -#define ISF_CMD_RD_ID 0x90 /* read the id and lock bits */ -#define ISF_CMD_RD_QUERY 0x98 /* read device capabilities */ -#define ISF_CMD_RD_STAT 0x70 /* read the status register */ -#define ISF_CMD_CLR_STAT 0x50 /* clear the staus register */ -#define ISF_CMD_WR_BUF 0xE8 /* clear the staus register */ -#define ISF_CMD_PROG 0x40 /* program word command */ -#define ISF_CMD_ERASE1 0x20 /* 1st word for block erase */ -#define ISF_CMD_ERASE2 0xD0 /* 2nd word for block erase */ -#define ISF_CMD_ERASE_SUSP 0xB0 /* suspend block erase */ -#define ISF_CMD_LOCK 0x60 /* 1st word for all lock cmds */ -#define ISF_CMD_SET_LOCK_BLK 0x01 /* 2nd wrd set block lock bit */ -#define ISF_CMD_SET_LOCK_MSTR 0xF1 /* 2nd wrd set master lck bit */ -#define ISF_CMD_CLR_LOCK_BLK 0xD0 /* 2nd wrd clear blk lck bit */ - -/* status register bits */ -#define ISF_STAT_DPS 0x02 /* Device Protect Status */ -#define ISF_STAT_VPPS 0x08 /* VPP Status */ -#define ISF_STAT_PSLBS 0x10 /* Program+Set Lock Bit Stat */ -#define ISF_STAT_ECLBS 0x20 /* Erase+Clr Lock Bit Stat */ -#define ISF_STAT_ESS 0x40 /* Erase Suspend Status */ -#define ISF_STAT_RDY 0x80 /* WSM Mach Status, 1=rdy */ - -#define ISF_STAT_ERR (ISF_STAT_VPPS | ISF_STAT_DPS | \ - ISF_STAT_ECLBS | ISF_STAT_PSLBS) - -/* register addresses, valid only following an ISF_CMD_RD_ID command */ -#define ISF_REG_MAN_CODE 0x00 /* manufacturer code */ -#define ISF_REG_DEV_CODE 0x01 /* device code */ -#define ISF_REG_BLK_LCK 0x02 /* block lock configuration */ -#define ISF_REG_MST_LCK 0x03 /* master lock configuration */ - -/********************** DEFINES for Hymod Flash ******************************/ - -/* - * this code requires that the flash on any Hymod board appear as a bank - * of two (identical) 16bit Intel StrataFlash chips with 64Kword erase - * sectors (or blocks), running in x16 bit mode and connected side-by-side - * to make a 32-bit wide bus. - */ - -typedef unsigned long bank_word_t; -typedef bank_word_t bank_blk_t[64 * 1024]; - -#define BANK_FILL_WORD(b) (((bank_word_t)(b) << 16) | (bank_word_t)(b)) - -#ifdef EXAMPLE - -/* theoretically the following examples should also work */ - -/* one flash chip in x8 mode with 128Kword sectors and 8bit bus */ -typedef unsigned char bank_word_t; -typedef bank_word_t bank_blk_t[128 * 1024]; -#define BANK_FILL_WORD(b) ((bank_word_t)(b)) - -/* four flash chips in x16 mode with 32Kword sectors and 64bit bus */ -typedef unsigned long long bank_word_t; -typedef bank_word_t bank_blk_t[32 * 1024]; -#define BANK_FILL_WORD(b) ( \ - ((bank_word_t)(b) << 48) \ - ((bank_word_t)(b) << 32) \ - ((bank_word_t)(b) << 16) \ - ((bank_word_t)(b) << 0) \ - ) - -#endif /* EXAMPLE */ - -/* the sizes of these two types should probably be the same */ -typedef bank_word_t *bank_addr_t; -typedef unsigned long bank_size_t; - -/* align bank addresses and sizes to bank word boundaries */ -#define BANK_ADDR_WORD_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ - & ~(sizeof (bank_word_t) - 1))) -#define BANK_SIZE_WORD_ALIGN(s) (((bank_size_t)(s) + sizeof (bank_word_t) - 1) \ - & ~(sizeof (bank_word_t) - 1)) - -/* align bank addresses and sizes to bank block boundaries */ -#define BANK_ADDR_BLK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ - & ~(sizeof (bank_blk_t) - 1))) -#define BANK_SIZE_BLK_ALIGN(s) (((bank_size_t)(s) + sizeof (bank_blk_t) - 1) \ - & ~(sizeof (bank_blk_t) - 1)) - -/* add an offset to a bank address */ -#define BANK_ADDR_OFFSET(a, o) ((bank_addr_t)((bank_size_t)(a) + \ - (bank_size_t)(o))) - -/* adjust a bank address to start of next word, block or bank */ -#define BANK_ADDR_NEXT_WORD(a) BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \ - sizeof (bank_word_t)) -#define BANK_ADDR_NEXT_BLK(a) BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \ - sizeof (bank_blk_t)) - -/* get bank address of register r given a bank base address a and block num b */ -#define BANK_ADDR_REG(a, b, r) BANK_ADDR_OFFSET(BANK_ADDR_OFFSET((a), \ - (bank_size_t)(b) * sizeof (bank_blk_t)), \ - (bank_size_t)(r) * sizeof (bank_word_t)) - -/* make a bank word value for each StrataFlash value */ - -/* Commands */ -#define BANK_CMD_RST BANK_FILL_WORD(ISF_CMD_RST) -#define BANK_CMD_RD_ID BANK_FILL_WORD(ISF_CMD_RD_ID) -#define BANK_CMD_RD_STAT BANK_FILL_WORD(ISF_CMD_RD_STAT) -#define BANK_CMD_CLR_STAT BANK_FILL_WORD(ISF_CMD_CLR_STAT) -#define BANK_CMD_ERASE1 BANK_FILL_WORD(ISF_CMD_ERASE1) -#define BANK_CMD_ERASE2 BANK_FILL_WORD(ISF_CMD_ERASE2) -#define BANK_CMD_PROG BANK_FILL_WORD(ISF_CMD_PROG) -#define BANK_CMD_LOCK BANK_FILL_WORD(ISF_CMD_LOCK) -#define BANK_CMD_SET_LOCK_BLK BANK_FILL_WORD(ISF_CMD_SET_LOCK_BLK) -#define BANK_CMD_SET_LOCK_MSTR BANK_FILL_WORD(ISF_CMD_SET_LOCK_MSTR) -#define BANK_CMD_CLR_LOCK_BLK BANK_FILL_WORD(ISF_CMD_CLR_LOCK_BLK) - -/* status register bits */ -#define BANK_STAT_DPS BANK_FILL_WORD(ISF_STAT_DPS) -#define BANK_STAT_PSS BANK_FILL_WORD(ISF_STAT_PSS) -#define BANK_STAT_VPPS BANK_FILL_WORD(ISF_STAT_VPPS) -#define BANK_STAT_PSLBS BANK_FILL_WORD(ISF_STAT_PSLBS) -#define BANK_STAT_ECLBS BANK_FILL_WORD(ISF_STAT_ECLBS) -#define BANK_STAT_ESS BANK_FILL_WORD(ISF_STAT_ESS) -#define BANK_STAT_RDY BANK_FILL_WORD(ISF_STAT_RDY) - -#define BANK_STAT_ERR BANK_FILL_WORD(ISF_STAT_ERR) - -/* make a bank register address for each StrataFlash register address */ - -#define BANK_REG_MAN_CODE(a) BANK_ADDR_REG((a), 0, ISF_REG_MAN_CODE) -#define BANK_REG_DEV_CODE(a) BANK_ADDR_REG((a), 0, ISF_REG_DEV_CODE) -#define BANK_REG_BLK_LCK(a, b) BANK_ADDR_REG((a), (b), ISF_REG_BLK_LCK) -#define BANK_REG_MST_LCK(a) BANK_ADDR_REG((a), 0, ISF_REG_MST_LCK) diff --git a/board/hymod/global_env b/board/hymod/global_env deleted file mode 100644 index ac12fd7..0000000 --- a/board/hymod/global_env +++ /dev/null @@ -1,145 +0,0 @@ -# DONT FORGET TO CHANGE THE "version" VAR BELOW IF YOU MAKE CHANGES TO THIS FILE - -# (C) Copyright 2001 -# Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au> -# -# SPDX-License-Identifier: GPL-2.0+ - -# -# global_env -# -# file used by Hymod boards to initialise the u-boot non-volatile -# environment when u-boot is first run (it determines this by the -# absence of the environment variable "global_env_loaded") -# -# format of this file is: -# -# 1. blank lines and lines beginning with '#' are ignored -# 2. all other lines must have the form <name>=<value> -# 3. if a percent appears anywhere, it is replaced like so: -# -# %s serial number of the main board (10 digit zero filled) -# %S serial number of the main board (plain number) -# %% a percentage character -# ... otherwise the %x is discarded -# -# if first character in <name> is a dash ('-'), then an existing env var -# will not be overwritten (the dash is removed). i.e. it is only set if -# it does not exist -# -# if last character in <name> is a plus ('+'), then <value> will be appended -# to any existing env var (the plus is ignored). Duplicates of <value> are -# removed. -# -# similarly, if the last character in <name> is a minus ('-'), then any -# occurences of <value> in the current value of <name> will removed (the -# minus is ignored). -# -# leading and trailing whitespace is removed in both <name> and <value> -# (after processing any initial or final plus/minus in <name>). -# - -# MISCELLANEOUS PARAMETERS - -# version must always come first -version=4 - -# set the ip address based on the main board serial number -ipaddr=192.168.1.%S -serverip=192.168.1.254 - -# stop auto execute after tftp (not a very good name really) -autostart=no - -# setting this to "yes" forces the global_env file to be loaded and processed -# if the current version is different to the version in the file -always_check_env=no - -# BOOTING COMMANDS AND PARAMETERS - -# command to run when "auto-booting" -bootcmd=bootm 40080000 - -# how long the "countdown" to automatically running "bootcmd" is -bootdelay=2 - -# how long before it "times out" console input and attempts to run "bootcmd" -bootretry=5 - -# arguments passed to the boot program (i.e. linux kernel) via register 6 -# the linux kernel (v2.4) uses the following registers: -# r3 - address of board information structure -# r4 - address of initial ramdisk image (0 means no initrd) -# r5 - size of initial ramdisk image -# r6 - address of command line string --bootargs=root=/dev/mtdblock5 rootfstype=squashfs ro - -# these four are for hymod linux integrated into our Sun network -bootargs+=serialno=%S -bootargs+=nisclient nisdomain=mlb.dmt.csiro.au nissrvadr=138.194.112.4 -bootargs+=nfsclient -bootargs+=automount - -# start a web server by default -bootargs+=webserver - -# give negotiation time to finish -bootargs+=netsleep=5 - -# then our ciscos don't pass packets for 25-30 secs after that, so -# pinging the server until it responds prevents network connections -# from failing... -bootargs+=netping - -# these are old bootargs - we don't need them anymore -bootargs-=preload=unix,i2c-cpm,i2c-dev -bootargs-=ramdisk_size=32768 -bootargs-=ramdisk_size=24576 - -# FLASH MANIPULATION COMMANDS - -# -# 16M flash, 64 x 256K sectors, mapped at address 0x40000000 -# -# Sector(s) Address Size Description -# -# 0 - 0 0x40000000 256K boot code -# 1 - 1 0x40040000 256K non volatile environment -# 2 - 4 0x40080000 768K linux kernel image -# 5 - 7 0x40140000 768K alternate linux kernel image -# 8 - 47 0x40200000 10M linux initial ramdisk image -# 48 - 63 0x40c00000 4M ramdisk image for applications -# - -fetchboot=tftp 100000 /hymod/u-boot.bin -eraseboot=protect off 1:0 ; erase 1:0 ; protect on 1:0 -copyboot=protect off 1:0 ; cp.b 100000 40000000 40000 ; protect on 1:0 -cmpboot=cmp.b 100000 40000000 40000 -newboot=run fetchboot eraseboot copyboot cmpboot - -fetchlinux=tftp 100000 /hymod/linux.bin -eraselinux=erase 1:2-4 -copylinux=cp.b 100000 40080000 ${filesize} -cmplinux=cmp.b 100000 40080000 ${filesize} -newlinux=run fetchlinux eraselinux copylinux cmplinux - -fetchaltlinux=tftp 100000 /hymod/altlinux.bin -erasealtlinux=erase 1:5-7 -copyaltlinux=cp.b 100000 40140000 ${filesize} -cmpaltlinux=cmp.b 100000 40140000 ${filesize} -newaltlinux=run fetchaltlinux erasealtlinux copyaltlinux cmpaltlinux - -fetchroot=tftp 100000 /hymod/root.bin -eraseroot=erase 1:8-47 -copyroot=cp.b 100000 40200000 ${filesize} -cmproot=cmp.b 100000 40200000 ${filesize} -newroot=run fetchroot eraseroot copyroot cmproot - -fetchard=tftp 100000 /hymod/apprd.bin -eraseard=erase 1:48-63 -copyard=cp.b 100000 40c00000 ${filesize} -cmpard=cmp.b 100000 40c00000 ${filesize} -newapprd=run fetchard eraseard copyard cmpard - -# pass above map to linux mtd driver -bootargs+=mtdparts=phys:256k(u-boot),256k(u-boot-env),768k(linux),768k(altlinux),10m(root),4m(hymod) diff --git a/board/hymod/hymod.c b/board/hymod/hymod.c deleted file mode 100644 index 0183f78..0000000 --- a/board/hymod/hymod.c +++ /dev/null @@ -1,521 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Hacked for the Hymod board by Murray.Jensen@csiro.au, 20-Oct-00 - */ - -#include <common.h> -#include <bootretry.h> -#include <cli.h> -#include <mpc8260.h> -#include <mpc8260_irq.h> -#include <ioports.h> -#include <i2c.h> -#include <asm/iopin_8260.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - -/* imports from eeprom.c */ -extern int hymod_eeprom_read (int, hymod_eeprom_t *); -extern void hymod_eeprom_print (hymod_eeprom_t *); - -/* imports from env.c */ -extern void hymod_check_env (void); - -/* ------------------------------------------------------------------------- */ - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { - /* cnf par sor dir odr dat */ - { 1, 1, 1, 0, 0, 0 }, /* PA31: FCC1 MII COL */ - { 1, 1, 1, 0, 0, 0 }, /* PA30: FCC1 MII CRS */ - { 1, 1, 1, 1, 0, 0 }, /* PA29: FCC1 MII TX_ER */ - { 1, 1, 1, 1, 0, 0 }, /* PA28: FCC1 MII TX_EN */ - { 1, 1, 1, 0, 0, 0 }, /* PA27: FCC1 MII RX_DV */ - { 1, 1, 1, 0, 0, 0 }, /* PA26: FCC1 MII RX_ER */ - { 1, 0, 0, 1, 0, 0 }, /* PA25: FCC2 MII MDIO */ - { 1, 0, 0, 1, 0, 0 }, /* PA24: FCC2 MII MDC */ - { 1, 0, 0, 1, 0, 0 }, /* PA23: FCC3 MII MDIO */ - { 1, 0, 0, 1, 0, 0 }, /* PA22: FCC3 MII MDC */ - { 1, 1, 0, 1, 0, 0 }, /* PA21: FCC1 MII TxD[3] */ - { 1, 1, 0, 1, 0, 0 }, /* PA20: FCC1 MII TxD[2] */ - { 1, 1, 0, 1, 0, 0 }, /* PA19: FCC1 MII TxD[1] */ - { 1, 1, 0, 1, 0, 0 }, /* PA18: FCC1 MII TxD[0] */ - { 1, 1, 0, 0, 0, 0 }, /* PA17: FCC1 MII RxD[3] */ - { 1, 1, 0, 0, 0, 0 }, /* PA16: FCC1 MII RxD[2] */ - { 1, 1, 0, 0, 0, 0 }, /* PA15: FCC1 MII RxD[1] */ - { 1, 1, 0, 0, 0, 0 }, /* PA14: FCC1 MII RxD[0] */ - { 1, 0, 0, 1, 0, 0 }, /* PA13: FCC1 MII MDIO */ - { 1, 0, 0, 1, 0, 0 }, /* PA12: FCC1 MII MDC */ - { 1, 0, 0, 1, 0, 0 }, /* PA11: SEL_CD */ - { 1, 0, 0, 0, 0, 0 }, /* PA10: FLASH STS1 */ - { 1, 0, 0, 0, 0, 0 }, /* PA09: FLASH STS0 */ - { 1, 0, 0, 0, 0, 0 }, /* PA08: FLASH ~PE */ - { 1, 0, 0, 0, 0, 0 }, /* PA07: WATCH ~HRESET */ - { 1, 0, 0, 0, 1, 0 }, /* PA06: VC DONE */ - { 1, 0, 0, 1, 1, 0 }, /* PA05: VC INIT */ - { 1, 0, 0, 1, 0, 0 }, /* PA04: VC ~PROG */ - { 1, 0, 0, 1, 0, 0 }, /* PA03: VM ENABLE */ - { 1, 0, 0, 0, 1, 0 }, /* PA02: VM DONE */ - { 1, 0, 0, 1, 1, 0 }, /* PA01: VM INIT */ - { 1, 0, 0, 1, 0, 0 } /* PA00: VM ~PROG */ - }, - - /* Port B configuration */ - { - /* cnf par sor dir odr dat */ - { 1, 1, 0, 1, 0, 0 }, /* PB31: FCC2 MII TX_ER */ - { 1, 1, 0, 0, 0, 0 }, /* PB30: FCC2 MII RX_DV */ - { 1, 1, 1, 1, 0, 0 }, /* PB29: FCC2 MII TX_EN */ - { 1, 1, 0, 0, 0, 0 }, /* PB28: FCC2 MII RX_ER */ - { 1, 1, 0, 0, 0, 0 }, /* PB27: FCC2 MII COL */ - { 1, 1, 0, 0, 0, 0 }, /* PB26: FCC2 MII CRS */ - { 1, 1, 0, 1, 0, 0 }, /* PB25: FCC2 MII TxD[3] */ - { 1, 1, 0, 1, 0, 0 }, /* PB24: FCC2 MII TxD[2] */ - { 1, 1, 0, 1, 0, 0 }, /* PB23: FCC2 MII TxD[1] */ - { 1, 1, 0, 1, 0, 0 }, /* PB22: FCC2 MII TxD[0] */ - { 1, 1, 0, 0, 0, 0 }, /* PB21: FCC2 MII RxD[0] */ - { 1, 1, 0, 0, 0, 0 }, /* PB20: FCC2 MII RxD[1] */ - { 1, 1, 0, 0, 0, 0 }, /* PB19: FCC2 MII RxD[2] */ - { 1, 1, 0, 0, 0, 0 }, /* PB18: FCC2 MII RxD[3] */ - { 1, 1, 0, 0, 0, 0 }, /* PB17: FCC3 MII RX_DV */ - { 1, 1, 0, 0, 0, 0 }, /* PB16: FCC3 MII RX_ER */ - { 1, 1, 0, 1, 0, 0 }, /* PB15: FCC3 MII TX_ER */ - { 1, 1, 0, 1, 0, 0 }, /* PB14: FCC3 MII TX_EN */ - { 1, 1, 0, 0, 0, 0 }, /* PB13: FCC3 MII COL */ - { 1, 1, 0, 0, 0, 0 }, /* PB12: FCC3 MII CRS */ - { 1, 1, 0, 0, 0, 0 }, /* PB11: FCC3 MII RxD[3] */ - { 1, 1, 0, 0, 0, 0 }, /* PB10: FCC3 MII RxD[2] */ - { 1, 1, 0, 0, 0, 0 }, /* PB09: FCC3 MII RxD[1] */ - { 1, 1, 0, 0, 0, 0 }, /* PB08: FCC3 MII RxD[0] */ - { 1, 1, 0, 1, 0, 0 }, /* PB07: FCC3 MII TxD[3] */ - { 1, 1, 0, 1, 0, 0 }, /* PB06: FCC3 MII TxD[2] */ - { 1, 1, 0, 1, 0, 0 }, /* PB05: FCC3 MII TxD[1] */ - { 1, 1, 0, 1, 0, 0 }, /* PB04: FCC3 MII TxD[0] */ - { 0, 0, 0, 0, 0, 0 }, /* PB03: pin doesn't exist */ - { 0, 0, 0, 0, 0, 0 }, /* PB02: pin doesn't exist */ - { 0, 0, 0, 0, 0, 0 }, /* PB01: pin doesn't exist */ - { 0, 0, 0, 0, 0, 0 } /* PB00: pin doesn't exist */ - }, - - /* Port C configuration */ - { - /* cnf par sor dir odr dat */ - { 1, 0, 0, 0, 0, 0 }, /* PC31: MEZ ~IACK */ - { 0, 0, 0, 0, 0, 0 }, /* PC30: ? */ - { 1, 1, 0, 0, 0, 0 }, /* PC29: CLK SCCx */ - { 1, 1, 0, 0, 0, 0 }, /* PC28: CLK4 */ - { 1, 1, 0, 0, 0, 0 }, /* PC27: CLK SCCF */ - { 1, 1, 0, 0, 0, 0 }, /* PC26: CLK 32K */ - { 1, 1, 0, 0, 0, 0 }, /* PC25: BRG4/CLK7 */ - { 0, 0, 0, 0, 0, 0 }, /* PC24: ? */ - { 1, 1, 0, 0, 0, 0 }, /* PC23: CLK SCCx */ - { 1, 1, 0, 0, 0, 0 }, /* PC22: FCC1 MII RX_CLK */ - { 1, 1, 0, 0, 0, 0 }, /* PC21: FCC1 MII TX_CLK */ - { 1, 1, 0, 0, 0, 0 }, /* PC20: CLK SCCF */ - { 1, 1, 0, 0, 0, 0 }, /* PC19: FCC2 MII RX_CLK */ - { 1, 1, 0, 0, 0, 0 }, /* PC18: FCC2 MII TX_CLK */ - { 1, 1, 0, 0, 0, 0 }, /* PC17: FCC3 MII RX_CLK */ - { 1, 1, 0, 0, 0, 0 }, /* PC16: FCC3 MII TX_CLK */ - { 1, 0, 0, 0, 0, 0 }, /* PC15: SCC1 UART ~CTS */ - { 1, 0, 0, 0, 0, 0 }, /* PC14: SCC1 UART ~CD */ - { 1, 0, 0, 0, 0, 0 }, /* PC13: SCC2 UART ~CTS */ - { 1, 0, 0, 0, 0, 0 }, /* PC12: SCC2 UART ~CD */ - { 1, 0, 0, 1, 0, 0 }, /* PC11: SCC1 UART ~DTR */ - { 1, 0, 0, 1, 0, 0 }, /* PC10: SCC1 UART ~DSR */ - { 1, 0, 0, 1, 0, 0 }, /* PC09: SCC2 UART ~DTR */ - { 1, 0, 0, 1, 0, 0 }, /* PC08: SCC2 UART ~DSR */ - { 1, 0, 0, 0, 0, 0 }, /* PC07: TEMP ~ALERT */ - { 1, 0, 0, 0, 0, 0 }, /* PC06: FCC3 INT */ - { 1, 0, 0, 0, 0, 0 }, /* PC05: FCC2 INT */ - { 1, 0, 0, 0, 0, 0 }, /* PC04: FCC1 INT */ - { 0, 1, 1, 1, 0, 0 }, /* PC03: SDMA IDMA2 ~DACK */ - { 0, 1, 1, 0, 0, 0 }, /* PC02: SDMA IDMA2 ~DONE */ - { 0, 1, 0, 0, 0, 0 }, /* PC01: SDMA IDMA2 ~DREQ */ - { 1, 1, 0, 1, 0, 0 } /* PC00: BRG7 */ - }, - - /* Port D configuration */ - { - /* cnf par sor dir odr dat */ - { 1, 1, 0, 0, 0, 0 }, /* PD31: SCC1 UART RxD */ - { 1, 1, 1, 1, 0, 0 }, /* PD30: SCC1 UART TxD */ - { 1, 0, 0, 1, 0, 0 }, /* PD29: SCC1 UART ~RTS */ - { 1, 1, 0, 0, 0, 0 }, /* PD28: SCC2 UART RxD */ - { 1, 1, 0, 1, 0, 0 }, /* PD27: SCC2 UART TxD */ - { 1, 0, 0, 1, 0, 0 }, /* PD26: SCC2 UART ~RTS */ - { 1, 0, 0, 0, 0, 0 }, /* PD25: SCC1 UART ~RI */ - { 1, 0, 0, 0, 0, 0 }, /* PD24: SCC2 UART ~RI */ - { 1, 0, 0, 1, 0, 0 }, /* PD23: CLKGEN PD */ - { 1, 0, 0, 0, 0, 0 }, /* PD22: USER3 */ - { 1, 0, 0, 0, 0, 0 }, /* PD21: USER2 */ - { 1, 0, 0, 0, 0, 0 }, /* PD20: USER1 */ - { 1, 1, 1, 0, 0, 0 }, /* PD19: SPI ~SEL */ - { 1, 1, 1, 0, 0, 0 }, /* PD18: SPI CLK */ - { 1, 1, 1, 0, 0, 0 }, /* PD17: SPI MOSI */ - { 1, 1, 1, 0, 0, 0 }, /* PD16: SPI MISO */ - { 1, 1, 1, 0, 1, 0 }, /* PD15: I2C SDA */ - { 1, 1, 1, 0, 1, 0 }, /* PD14: I2C SCL */ - { 1, 0, 0, 1, 0, 1 }, /* PD13: TEMP ~STDBY */ - { 1, 0, 0, 1, 0, 1 }, /* PD12: FCC3 ~RESET */ - { 1, 0, 0, 1, 0, 1 }, /* PD11: FCC2 ~RESET */ - { 1, 0, 0, 1, 0, 1 }, /* PD10: FCC1 ~RESET */ - { 1, 0, 0, 0, 0, 0 }, /* PD09: PD9 */ - { 1, 0, 0, 0, 0, 0 }, /* PD08: PD8 */ - { 1, 0, 0, 1, 0, 1 }, /* PD07: PD7 */ - { 1, 0, 0, 1, 0, 1 }, /* PD06: PD6 */ - { 1, 0, 0, 1, 0, 1 }, /* PD05: PD5 */ - { 1, 0, 0, 1, 0, 1 }, /* PD04: PD4 */ - { 0, 0, 0, 0, 0, 0 }, /* PD03: pin doesn't exist */ - { 0, 0, 0, 0, 0, 0 }, /* PD02: pin doesn't exist */ - { 0, 0, 0, 0, 0, 0 }, /* PD01: pin doesn't exist */ - { 0, 0, 0, 0, 0, 0 } /* PD00: pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* - * AMI FS6377 Clock Generator configuration table - * - * the "fs6377_regs[]" table entries correspond to FS6377 registers - * 0 - 15 (total of 16 bytes). - * - * the data is written to the FS6377 via the i2c bus using address in - * "fs6377_addr" (address is 7 bits - R/W bit not included). - * - * The fs6377 has four clock outputs: A, B, C and D. - * - * Outputs C and D can each provide two different clock outputs C1/D1 or - * C2/D2 depending on the state of the SEL_CD input which is connected to - * the MPC8260 I/O port pin PA11. PA11 output (SEL_CD input) low (or 0) - * selects C1/D1 and PA11 output (SEL_CD input) high (or 1) selects C2/D2. - * - * PA11 defaults to output low (or 0) in the i/o port config table above. - * - * Output A provides a 100MHz for the High Speed Serial chips. Output B - * provides a 3.6864MHz clock for more accurate asynchronous serial bit - * rates. Output C is routed to the mezzanine connector but is currently - * unused - both C1 and C2 are set to 16MHz. Output D is used by both the - * alt-input and display mezzanine boards for their video chips. The - * alt-input board requires a clock of 24.576MHz and this is available on - * D1 (PA11=SEL_CD=0). The display board requires a clock of 27MHz and this - * is available on D2 (PA11=SEL_CD=1). - * - * So the default is a clock suitable for the alt-input board. PA11 is toggled - * later in misc_init_r(), if a display board is detected. - */ - -uchar fs6377_addr = 0x5c; - -uchar fs6377_regs[16] = { - 12, 75, 64, 25, 144, 128, 25, 192, - 0, 16, 135, 192, 224, 64, 64, 192 -}; - -/* ------------------------------------------------------------------------- */ - -/* - * special board initialisation, after clocks and timebase have been - * set up but before environment and serial are initialised. - * - * added so that very early initialisations can be done using the i2c - * driver (which requires the clocks, to calculate the dividers, and - * the timebase, for udelay()) - */ - -int -board_postclk_init (void) -{ - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - /* - * Initialise the FS6377 clock chip - * - * the secondary address is the register number from where to - * start the write - I want to write all the registers - * - * don't bother checking return status - we have no console yet - * to print it on, nor any RAM to store it in - it will be obvious - * if this doesn't work - */ - (void) i2c_write (fs6377_addr, 0, 1, fs6377_regs, - sizeof (fs6377_regs)); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: Hardwired to HYMOD - */ - -int -checkboard (void) -{ - puts ("Board: HYMOD\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * miscellaneous (early - while running in flash) initialisations. - */ - -#define _NOT_USED_ 0xFFFFFFFF - -uint upmb_table[] = { - /* Read Single Beat (RSS) - offset 0x00 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Read Burst (RBS) - offset 0x08 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Write Single Beat (WSS) - offset 0x18 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Write Burst (WSS) - offset 0x20 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Refresh Timer (PTS) - offset 0x30 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Exception Condition (EXS) - offset 0x3c */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_ -}; - -uint upmc_table[] = { - /* Read Single Beat (RSS) - offset 0x00 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Read Burst (RBS) - offset 0x08 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Write Single Beat (WSS) - offset 0x18 */ - 0xF0E00000, 0xF0A00000, 0x00A00000, 0x30A00000, - 0xF0F40007, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Write Burst (WSS) - offset 0x20 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Refresh Timer (PTS) - offset 0x30 */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* Exception Condition (EXS) - offset 0x3c */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_ -}; - -int -misc_init_f (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - - printf ("UPMs: "); - - upmconfig (UPMB, upmb_table, sizeof upmb_table / sizeof upmb_table[0]); - memctl->memc_mbmr = CONFIG_SYS_MBMR; - - upmconfig (UPMC, upmc_table, sizeof upmc_table / sizeof upmc_table[0]); - memctl->memc_mcmr = CONFIG_SYS_MCMR; - - printf ("configured\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t -initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0, *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8); - ulong psdmr = CONFIG_SYS_PSDMR; - int i; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; - - return (CONFIG_SYS_SDRAM_SIZE << 20); -} - -/* ------------------------------------------------------------------------- */ -/* miscellaneous initialisations after relocation into ram (misc_init_r) */ -/* */ -/* loads the data in the main board and mezzanine board eeproms into */ -/* the hymod configuration struct stored in the board information area. */ -/* */ -/* if the contents of either eeprom is invalid, prompts for a serial */ -/* number (and an ethernet address if required) then fetches a file */ -/* containing information to be stored in the eeprom from the tftp server */ -/* (the file name is based on the serial number and a built-in path) */ - -int -last_stage_init (void) -{ - hymod_conf_t *cp = &gd->bd->bi_hymod_conf; - int rc; - - /* - * we use the cli_readline() function, but we also want - * command timeout enabled - */ - bootretry_init_cmd_timeout(); - - memset ((void *) cp, 0, sizeof (*cp)); - - /* set up main board config info */ - - rc = hymod_eeprom_read (0, &cp->main.eeprom); - - puts ("EEPROM:main..."); - if (rc < 0) - puts ("NOT PRESENT\n"); - else if (rc == 0) - puts ("INVALID\n"); - else { - cp->main.eeprom.valid = 1; - - printf ("OK (ver %u)\n", cp->main.eeprom.ver); - hymod_eeprom_print (&cp->main.eeprom); - - /* - * hard-wired assumption here: all hymod main boards will have - * one xilinx fpga, with the interrupt line connected to IRQ2 - * - * One day, this might be based on the board type - */ - - cp->main.xlx[0].mmap.prog.exists = 1; - cp->main.xlx[0].mmap.prog.size = FPGA_MAIN_CFG_SIZE; - cp->main.xlx[0].mmap.prog.base = FPGA_MAIN_CFG_BASE; - - cp->main.xlx[0].mmap.reg.exists = 1; - cp->main.xlx[0].mmap.reg.size = FPGA_MAIN_REG_SIZE; - cp->main.xlx[0].mmap.reg.base = FPGA_MAIN_REG_BASE; - - cp->main.xlx[0].mmap.port.exists = 1; - cp->main.xlx[0].mmap.port.size = FPGA_MAIN_PORT_SIZE; - cp->main.xlx[0].mmap.port.base = FPGA_MAIN_PORT_BASE; - - cp->main.xlx[0].iopins.prog_pin.port = FPGA_MAIN_PROG_PORT; - cp->main.xlx[0].iopins.prog_pin.pin = FPGA_MAIN_PROG_PIN; - cp->main.xlx[0].iopins.prog_pin.flag = 1; - cp->main.xlx[0].iopins.init_pin.port = FPGA_MAIN_INIT_PORT; - cp->main.xlx[0].iopins.init_pin.pin = FPGA_MAIN_INIT_PIN; - cp->main.xlx[0].iopins.init_pin.flag = 1; - cp->main.xlx[0].iopins.done_pin.port = FPGA_MAIN_DONE_PORT; - cp->main.xlx[0].iopins.done_pin.pin = FPGA_MAIN_DONE_PIN; - cp->main.xlx[0].iopins.done_pin.flag = 1; -#ifdef FPGA_MAIN_ENABLE_PORT - cp->main.xlx[0].iopins.enable_pin.port = FPGA_MAIN_ENABLE_PORT; - cp->main.xlx[0].iopins.enable_pin.pin = FPGA_MAIN_ENABLE_PIN; - cp->main.xlx[0].iopins.enable_pin.flag = 1; -#endif - - cp->main.xlx[0].irq = FPGA_MAIN_IRQ; - } - - /* set up mezzanine board config info */ - - rc = hymod_eeprom_read (1, &cp->mezz.eeprom); - - puts ("EEPROM:mezz..."); - if (rc < 0) - puts ("NOT PRESENT\n"); - else if (rc == 0) - puts ("INVALID\n"); - else { - cp->main.eeprom.valid = 1; - - printf ("OK (ver %u)\n", cp->mezz.eeprom.ver); - hymod_eeprom_print (&cp->mezz.eeprom); - } - - cp->crc = crc32 (0, (unsigned char *)cp, offsetof (hymod_conf_t, crc)); - - hymod_check_env (); - - return (0); -} - -#ifdef CONFIG_SHOW_ACTIVITY -void board_show_activity (ulong timebase) -{ -#ifdef CONFIG_SYS_HYMOD_DBLEDS - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile iop8260_t *iop = &immr->im_ioport; - static int shift = 0; - - if ((timestamp % CONFIG_SYS_HZ) == 0) { - if (++shift > 3) - shift = 0; - iop->iop_pdatd = - (iop->iop_pdatd & ~0x0f000000) | (1 << (24 + shift)); - } -#endif /* CONFIG_SYS_HYMOD_DBLEDS */ -} - -void show_activity(int arg) -{ -} -#endif /* CONFIG_SHOW_ACTIVITY */ diff --git a/board/hymod/hymod.h b/board/hymod/hymod.h deleted file mode 100644 index 7024d8a..0000000 --- a/board/hymod/hymod.h +++ /dev/null @@ -1,305 +0,0 @@ -/* - * (C) Copyright 2001 - * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _HYMOD_H_ -#define _HYMOD_H_ - -#ifdef CONFIG_MPC8260 -#include <asm/iopin_8260.h> -#endif - -/* - * hymod configuration data - passed by boot code via the board information - * structure (only U-Boot has support for this at the moment) - * - * there are three types of data passed up from the boot monitor. the first - * (type hymod_eeprom_t) is the eeprom data that was read off both the main - * (or mother) board and the mezzanine board (if any). this data defines how - * many Xilinx fpgas are on each board, and their types (among other things). - * the second type of data (type xlx_mmap_t, one per Xilinx fpga) defines where - * in the physical address space the various Xilinx fpga access regions have - * been mapped by the boot rom. the third type of data (type xlx_iopins_t, - * one per Xilinx fpga) defines which io port pins are connected to the various - * signals required to program a Xilinx fpga. - * - * A ram/flash "bank" refers to memory controlled by the same chip select. - * - * the eeprom contents are defined as in technical note #2 - basically, - * a header, zero or more records in no particular order, and a 32 bit crc - * a record is 1 or more type bytes, a length byte and "length" bytes. - */ - -#define HYMOD_EEPROM_ID 0xAA /* eeprom id byte */ -#define HYMOD_EEPROM_VER 1 /* eeprom contents version (0-127) */ -#define HYMOD_EEPROM_SIZE 256 /* number of bytes in the eeprom */ - -/* eeprom header */ -typedef - struct { - unsigned char id; /* eeprom id byte */ - unsigned char :1; - unsigned char ver:7; /* eeprom contents version number */ - unsigned long len; /* total # of bytes btw hdr and crc */ - } -hymod_eehdr_t; - -/* maximum number of bytes available for eeprom data records */ -#define HYMOD_EEPROM_MAXLEN (HYMOD_EEPROM_SIZE \ - - sizeof (hymod_eehdr_t) \ - - sizeof (unsigned long)) - -/* eeprom data record */ -typedef - union { - struct { - unsigned char topbit:1; - unsigned char type:7; - unsigned char len; - unsigned char data[1]; /* variable length */ - } small; - struct { - unsigned short topbit:1; - unsigned short nxtbit:1; - unsigned short type:14; - unsigned short len; - unsigned char data[1]; /* variable length */ - } medium; - struct { - unsigned long topbit:1; - unsigned long nxtbit:1; - unsigned long type:30; - unsigned long len; - unsigned char data[1]; /* variable length */ - } large; - } -hymod_eerec_t; - -#define HYMOD_EEOFF_MAIN 0x00 /* i2c addr offset for main eeprom */ -#define HYMOD_EEOFF_MEZZ 0x04 /* i2c addr offset for mezz eepomr */ - -/* eeprom record types */ -#define HYMOD_EEREC_SERNO 1 /* serial number */ -#define HYMOD_EEREC_DATE 2 /* date */ -#define HYMOD_EEREC_BATCH 3 /* batch id */ -#define HYMOD_EEREC_TYPE 4 /* board type */ -#define HYMOD_EEREC_REV 5 /* revision number */ -#define HYMOD_EEREC_SDRAM 6 /* sdram sizes */ -#define HYMOD_EEREC_FLASH 7 /* flash sizes */ -#define HYMOD_EEREC_ZBT 8 /* zbt ram sizes */ -#define HYMOD_EEREC_XLXTYP 9 /* Xilinx fpga types */ -#define HYMOD_EEREC_XLXSPD 10 /* Xilinx fpga speeds */ -#define HYMOD_EEREC_XLXTMP 11 /* Xilinx fpga temperatures */ -#define HYMOD_EEREC_XLXGRD 12 /* Xilinx fpga grades */ -#define HYMOD_EEREC_CPUTYP 13 /* Motorola CPU type */ -#define HYMOD_EEREC_CPUSPD 14 /* CPU speed */ -#define HYMOD_EEREC_BUSSPD 15 /* bus speed */ -#define HYMOD_EEREC_CPMSPD 16 /* CPM speed */ -#define HYMOD_EEREC_HSTYPE 17 /* high-speed serial chip type */ -#define HYMOD_EEREC_HSCHIN 18 /* high-speed serial input channels */ -#define HYMOD_EEREC_HSCHOUT 19 /* high-speed serial output channels */ - -/* some dimensions */ -#define HYMOD_MAX_BATCH 32 /* max no. of bytes in batch id */ -#define HYMOD_MAX_SDRAM 4 /* max sdram "banks" on any board */ -#define HYMOD_MAX_FLASH 4 /* max flash "banks" on any board */ -#define HYMOD_MAX_ZBT 16 /* max ZBT rams on any board */ -#define HYMOD_MAX_XLX 4 /* max Xilinx fpgas on any board */ - -#define HYMOD_MAX_BYTES 16 /* enough to store any bytes array */ - -/* board types */ -#define HYMOD_BDTYPE_NONE 0 /* information not present */ -#define HYMOD_BDTYPE_IO 1 /* I/O main board */ -#define HYMOD_BDTYPE_CLP 2 /* CLP main board */ -#define HYMOD_BDTYPE_DSP 3 /* DSP main board */ -#define HYMOD_BDTYPE_INPUT 4 /* video input mezzanine board */ -#define HYMOD_BDTYPE_ALTINPUT 5 /* video input mezzanine board */ -#define HYMOD_BDTYPE_DISPLAY 6 /* video display mezzanine board */ -#define HYMOD_BDTYPE_MAX 7 /* first invalid value */ - -/* Xilinx fpga types */ -#define HYMOD_XTYP_NONE 0 /* information not present */ -#define HYMOD_XTYP_XCV300E 1 /* Xilinx Virtex 300 */ -#define HYMOD_XTYP_XCV400E 2 /* Xilinx Virtex 400 */ -#define HYMOD_XTYP_XCV600E 3 /* Xilinx Virtex 600 */ -#define HYMOD_XTYP_MAX 4 /* first invalid value */ - -/* Xilinx fpga speeds */ -#define HYMOD_XSPD_NONE 0 /* information not present */ -#define HYMOD_XSPD_SIX 1 -#define HYMOD_XSPD_SEVEN 2 -#define HYMOD_XSPD_EIGHT 3 -#define HYMOD_XSPD_MAX 4 /* first invalid value */ - -/* Xilinx fpga temperatures */ -#define HYMOD_XTMP_NONE 0 /* information not present */ -#define HYMOD_XTMP_COM 1 -#define HYMOD_XTMP_IND 2 -#define HYMOD_XTMP_MAX 3 /* first invalid value */ - -/* Xilinx fpga grades */ -#define HYMOD_XTMP_NONE 0 /* information not present */ -#define HYMOD_XTMP_NORMAL 1 -#define HYMOD_XTMP_ENGSAMP 2 -#define HYMOD_XTMP_MAX 3 /* first invalid value */ - -/* CPU types */ -#define HYMOD_CPUTYPE_NONE 0 /* information not present */ -#define HYMOD_CPUTYPE_MPC8260 1 /* Motorola MPC8260 embedded powerpc */ -#define HYMOD_CPUTYPE_MAX 2 /* first invalid value */ - -/* CPU/BUS/CPM clock speeds */ -#define HYMOD_CLKSPD_NONE 0 /* information not present */ -#define HYMOD_CLKSPD_33MHZ 1 -#define HYMOD_CLKSPD_66MHZ 2 -#define HYMOD_CLKSPD_100MHZ 3 -#define HYMOD_CLKSPD_133MHZ 4 -#define HYMOD_CLKSPD_166MHZ 5 -#define HYMOD_CLKSPD_200MHZ 6 -#define HYMOD_CLKSPD_MAX 7 /* first invalid value */ - -/* high speed serial chip types */ -#define HYMOD_HSSTYPE_NONE 0 /* information not present */ -#define HYMOD_HSSTYPE_AMCC52064 1 -#define HYMOD_HSSTYPE_MAX 2 /* first invalid value */ - -/* a date (yyyy-mm-dd) */ -typedef - struct { - unsigned short year; - unsigned char month; - unsigned char day; - } -hymod_date_t; - -/* describes a Xilinx fpga */ -typedef - struct { - unsigned char type; /* chip type */ - unsigned char speed; /* chip speed rating */ - unsigned char temp; /* chip temperature rating */ - unsigned char grade; /* chip grade */ - } -hymod_xlx_t; - -/* describes a Motorola embedded processor */ -typedef - struct { - unsigned char type; /* CPU type */ - unsigned char cpuspd; /* speed of the PowerPC core */ - unsigned char busspd; /* speed of the system and 60x bus */ - unsigned char cpmspd; /* speed of the CPM co-processor */ - } -hymod_mpc_t; - -/* info about high-speed (1Gbit) serial interface */ -typedef - struct { - unsigned char type; /* high-speed serial chip type */ - unsigned char nchin; /* number of input channels mounted */ - unsigned char nchout; /* number of output channels mounted */ - } -hymod_hss_t; - -/* - * this defines the contents of the serial eeprom that exists on every - * hymod board, including mezzanine boards (the serial eeprom will be - * faked for early development boards that don't have one) - */ - -typedef - struct { - unsigned char valid:1; /* contents of this struct is valid */ - unsigned char ver:7; /* eeprom contents version */ - unsigned char bdtype; /* board type */ - unsigned char bdrev; /* board revision */ - unsigned char batchlen; /* length of batch string below */ - unsigned long serno; /* serial number */ - hymod_date_t date; /* manufacture date */ - unsigned char batch[32]; /* manufacturer specific batch id */ - unsigned char nsdram; /* # of ram "banks" */ - unsigned char nflash; /* # of flash "banks" */ - unsigned char nzbt; /* # of ZBT rams */ - unsigned char nxlx; /* # of Xilinx fpgas */ - unsigned char sdramsz[HYMOD_MAX_SDRAM]; /* log2 of sdram size */ - unsigned char flashsz[HYMOD_MAX_FLASH]; /* log2 of flash size */ - unsigned char zbtsz[HYMOD_MAX_ZBT]; /* log2 of ZBT ram size */ - hymod_xlx_t xlx[HYMOD_MAX_XLX]; /* Xilinx fpga info */ - hymod_mpc_t mpc; /* Motorola MPC CPU info */ - hymod_hss_t hss; /* high-speed serial info */ - } -hymod_eeprom_t; - -/* - * this defines a region in the processor's physical address space - */ -typedef - struct { - unsigned long exists:1; /* 1 if the region exists, 0 if not */ - unsigned long size:31; /* size in bytes */ - unsigned long base; /* base address */ - } -xlx_prgn_t; - -/* - * this defines where the various Xilinx fpga access regions are mapped - * into the physical address space of the processor - */ -typedef - struct { - xlx_prgn_t prog; /* program access region */ - xlx_prgn_t reg; /* register access region */ - xlx_prgn_t port; /* port access region */ - } -xlx_mmap_t; - -/* - * this defines which 8260 i/o port pins are connected to the various - * signals required for programming a Xilinx fpga - */ -typedef - struct { - iopin_t prog_pin; /* assert for >= 300ns to program */ - iopin_t init_pin; /* goes high when fpga is cleared */ - iopin_t done_pin; /* goes high when program is done */ - iopin_t enable_pin; /* some fpgas need enabling */ - } -xlx_iopins_t; - -/* all info about one Xilinx chip */ -typedef - struct { - xlx_mmap_t mmap; - xlx_iopins_t iopins; - unsigned long irq:8; /* h/w intr req number for this fpga */ - } -xlx_info_t; - -/* all info about one hymod board */ -typedef - struct { - hymod_eeprom_t eeprom; - xlx_info_t xlx[HYMOD_MAX_XLX]; - } -hymod_board_t; - -/* - * this defines the configuration information of a hymod board-set - * (main board + possible mezzanine board). In future, there may be - * more than one mezzanine board (stackable?) - if so, add a "mezz2" - * field, and so on... or make mezz an array? - */ -typedef - struct { - unsigned long ver:8; /* version control */ - hymod_board_t main; /* main board info */ - hymod_board_t mezz; /* mezzanine board info */ - unsigned long crc; /* ensures kernel and boot prom agree */ - } -hymod_conf_t; - -#endif /* _HYMOD_H_ */ diff --git a/board/hymod/input.c b/board/hymod/input.c deleted file mode 100644 index a9035d3..0000000 --- a/board/hymod/input.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * (C) Copyright 2003 - * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <bootretry.h> -#include <cli.h> - -int -hymod_get_serno (const char *prompt) -{ - for (;;) { - int n, serno; - char *p; - - bootretry_reset_cmd_timeout(); - - n = cli_readline(prompt); - - if (n < 0) - return (n); - - if (n == 0) - continue; - - serno = (int) simple_strtol (console_buffer, &p, 10); - - if (p > console_buffer && *p == '\0' && serno > 0) - return (serno); - - printf ("Invalid number (%s) - please re-enter\n", - console_buffer); - } -} - -int -hymod_get_ethaddr (void) -{ - for (;;) { - int n; - - bootretry_reset_cmd_timeout(); - - n = cli_readline("Enter board ethernet address: "); - - if (n < 0) - return (n); - - if (n == 0) - continue; - - if (n == 17) { - int i; - char *p, *q; - - /* see if it looks like an ethernet address */ - - p = console_buffer; - - for (i = 0; i < 6; i++) { - char term = (i == 5 ? '\0' : ':'); - - (void)simple_strtol (p, &q, 16); - - if ((q - p) != 2 || *q++ != term) - break; - - p = q; - } - - if (i == 6) { - /* it looks ok - set it */ - printf ("Setting ethernet addr to %s\n", - console_buffer); - - setenv ("ethaddr", console_buffer); - - puts ("Remember to do a 'saveenv' to " - "make it permanent\n"); - - return (0); - } - } - - printf ("Invalid ethernet addr (%s) - please re-enter\n", - console_buffer); - } -} diff --git a/board/hymod/u-boot.lds b/board/hymod/u-boot.lds deleted file mode 100644 index 1dfd2b2..0000000 --- a/board/hymod/u-boot.lds +++ /dev/null @@ -1,132 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8260/start.o (.text) -/* - common/dlmalloc.o (.text) - arch/powerpc/lib/ppcstring.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - lib/zlib.o (.text) - - . = env_offset; -*/ - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - . = ALIGN(256 * 1024); - .ppcenv : - { - common/env_embedded.o (.ppcenv) - } - . = ALIGN(4); - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/hymod/u-boot.lds.debug b/board/hymod/u-boot.lds.debug deleted file mode 100644 index b9c84c7..0000000 --- a/board/hymod/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/icu862/Kconfig b/board/icu862/Kconfig deleted file mode 100644 index da11d7b..0000000 --- a/board/icu862/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_ICU862 - -config SYS_BOARD - default "icu862" - -config SYS_CONFIG_NAME - default "ICU862" - -endif diff --git a/board/icu862/MAINTAINERS b/board/icu862/MAINTAINERS deleted file mode 100644 index 7fe16d1..0000000 --- a/board/icu862/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -ICU862 BOARD -M: Wolfgang Denk <wd@denx.de> -S: Maintained -F: board/icu862/ -F: include/configs/ICU862.h -F: configs/ICU862_defconfig -F: configs/ICU862_100MHz_defconfig diff --git a/board/icu862/Makefile b/board/icu862/Makefile deleted file mode 100644 index 263f21b..0000000 --- a/board/icu862/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = icu862.o flash.o pcmcia.o diff --git a/board/icu862/flash.c b/board/icu862/flash.c deleted file mode 100644 index a84ab99..0000000 --- a/board/icu862/flash.c +++ /dev/null @@ -1,575 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, - size_b0 >> 20); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, - &flash_info[0]); -#endif - - /* ICU862 Board has only one Flash Bank */ - flash_info[0].size = size_b0; - - return size_b0; - -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM033C)) { - /* set sector offsets for uniform sector type */ - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00040000); - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - puts ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: puts ("AMD "); break; - case FLASH_MAN_FUJ: puts ("FUJITSU "); break; - case FLASH_MAN_BM: puts ("BRIGHT MICRO "); break; - default: puts ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: puts ("29F040/29LV040 (4 Mbit, uniform sectors)\n"); - break; - case FLASH_AM400B: puts ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: puts ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: puts ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: puts ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: puts ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: puts ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: puts ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: puts ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AM033C: puts ("AM29LV033C (32 Mbit)\n"); - break; - default: puts ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - puts (" Sector Start Addresses:"); - - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) { - puts ("\n "); - } - - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - - puts ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; -#if 0 - ulong base = (ulong)addr; -#endif - uchar value; - - /* Write auto select command: read Manufacturer ID */ -#if 0 - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; -#else - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x90909090; -#endif - - value = addr[0]; - - switch (value + (value << 16)) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - value = addr[1]; /* device ID */ - - switch ((unsigned long)value) { - case AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - case AMD_ID_LV033C: - info->flash_id += FLASH_AM033C; - info->sector_count = 64; - info->size = 0x01000000; - break; /* => 16Mb */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - -#if 0 - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } -#else - flash_get_offsets ((ulong)addr, &flash_info[0]); -#endif - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); -#if 1 - /* We don't know why it happens, but on ICU Board * - * for AMD29033C flash we need to resend the command of * - * reading flash protection for upper 8 Mb of flash */ - if ( i == 32 ) { - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x90909090; - } -#endif - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; -#if 0 - *addr = 0x00F000F0; /* reset bank */ -#else - *addr = 0xF0F0F0F0; /* reset bank */ -#endif - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - puts ("- missing\n"); - } else { - puts ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - puts ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - puts ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - -#if 0 - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; -#else - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x80808080; - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; -#endif - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); -#if 0 - addr[0] = 0x00300030; -#else - addr[0] = 0x30303030; -#endif - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); -#if 0 - while ((addr[0] & 0x00800080) != 0x00800080) -#else - while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF) -#endif - { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - puts ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; -#if 0 - addr[0] = 0x00F000F0; /* reset bank */ -#else - addr[0] = 0xF0F0F0F0; /* reset bank */ -#endif - - puts (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - -#if 0 - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; -#else - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0xA0A0A0A0; -#endif - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); -#if 0 - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) -#else - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) -#endif - { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/icu862/icu862.c b/board/icu862/icu862.c deleted file mode 100644 index 4c0e919..0000000 --- a/board/icu862/icu862.c +++ /dev/null @@ -1,199 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <config.h> -#include <mpc8xx.h> - -/* - * Memory Controller Using - * - * CS0 - Flash memory (0x40000000) - * CS1 - SDRAM (0x00000000} - * CS2 - S/UNI Ultra ATM155 - * CS3 - IDT 77106 ATM25 - * CS4 - DSP HPI - * CS5 - E1/T1 Interface device - * CS6 - PCMCIA device - * CS7 - PCMCIA device - */ - -/* ------------------------------------------------------------------------- */ - -#define _not_used_ 0xffffffff - -const uint sdram_table[] = { - /* single read. (offset 0 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, - 0x1ff77c47, - - /* MRS initialization (offset 5) */ - - 0x1ff77c34, 0xefeabc34, 0x1fb57c35, - - /* burst read. (offset 8 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, - 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* single write. (offset 18 in upm RAM) */ - 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* burst write. (offset 20 in upm RAM) */ - 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, - 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* refresh. (offset 30 in upm RAM) */ - 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* exception. (offset 3c in upm RAM) */ - 0x7ffffc07, _not_used_, _not_used_, _not_used_ -}; - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: ICU862 Board\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size8, size9; - long int size_b0 = 0; - unsigned long reg; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; - - memctl->memc_mar = 0x00000088; - - /* - * Map controller bank 1 to the SDRAM bank at - * preliminary address - these have to be modified after the - * SDRAM size has been determined. - */ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay (200); - memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */ - udelay (200); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE1_PRELIM, - SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE1_PRELIM, - SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size_b0 = size9; -/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ - } else { /* back to 8 columns */ - size_b0 = size8; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; - udelay (500); -/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ - } - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type, both banks - * For types > 128 MBit leave it at the current (fast) rate - */ - if ((size_b0 < 0x02000000)) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; - udelay (1000); - } - - /* - * Final mapping - */ - - memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - - udelay (10000); - - return (size_b0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} diff --git a/board/icu862/pcmcia.c b/board/icu862/pcmcia.c deleted file mode 100644 index dbe3c3c..0000000 --- a/board/icu862/pcmcia.c +++ /dev/null @@ -1,262 +0,0 @@ -#include <common.h> -#include <mpc8xx.h> -#include <pcmcia.h> - -#undef CONFIG_PCMCIA - -#if defined(CONFIG_CMD_PCMCIA) -#define CONFIG_PCMCIA -#endif - -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) -#define CONFIG_PCMCIA -#endif - -#ifdef CONFIG_PCMCIA - -#define PCMCIA_BOARD_MSG "ICU862" - -static void cfg_port_B (void) -{ - volatile cpm8xx_t *cp; - uint reg; - - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); - - /* - * Configure Port B for TPS2205 PC-Card Power-Interface Switch - * - * Switch off all voltages, assert shutdown - */ - reg = cp->cp_pbdat; - reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */ - TPS2205_VCC3 | TPS2205_VCC5 | /* VAVCC => Hi-Z */ - TPS2205_SHDN); /* enable switch */ - cp->cp_pbdat = reg; - - cp->cp_pbpar &= ~(TPS2205_INPUTS | TPS2205_OUTPUTS); - - reg = cp->cp_pbdir & ~(TPS2205_INPUTS); - cp->cp_pbdir = reg | TPS2205_OUTPUTS; - - debug ("Set Port B: PAR: %08x DIR: %08x DAT: %08x\n", - cp->cp_pbpar, cp->cp_pbdir, cp->cp_pbdat); -} - -int pcmcia_hardware_enable(int slot) -{ - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - volatile sysconf8xx_t *sysp; - uint reg, pipr, mask; - int i; - - debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - udelay(10000); - - sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); - - /* Configure Port B for TPS2205 PC-Card Power-Interface Switch */ - cfg_port_B (); - - /* - * Configure SIUMCR to enable PCMCIA port B - * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) - */ - sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ - - /* clear interrupt state, and disable interrupts */ - pcmp->pcmc_pscr = PCMCIA_MASK(_slot_); - pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); - - /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - /* - * Make sure there is a card in the slot, then configure the interface. - */ - udelay(10000); - debug ("[%d] %s: PIPR(%p)=0x%x\n", - __LINE__,__FUNCTION__, - &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); - if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { - printf (" No Card found\n"); - return (1); - } - - /* - * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z - */ - mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); - pipr = pcmp->pcmc_pipr; - debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", - pipr, - (reg&PCMCIA_VS1(slot))?"n":"ff", - (reg&PCMCIA_VS2(slot))?"n":"ff"); - - reg = cp->cp_pbdat; - if ((pipr & mask) == mask) { - reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */ - TPS2205_VCC3); /* 3V off */ - reg &= ~(TPS2205_VCC5); /* 5V on */ - puts (" 5.0V card found: "); - } else { - reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */ - TPS2205_VCC5); /* 5V off */ - reg &= ~(TPS2205_VCC3); /* 3V on */ - puts (" 3.3V card found: "); - } - - debug ("\nPB DAT: %08x -> 3.3V %s 5.0V %s VPP_PGM %s VPP_VCC %s\n", - reg, - (reg & TPS2205_VCC3) ? "off" : "on", - (reg & TPS2205_VCC5) ? "off" : "on", - (reg & TPS2205_VPP_PGM) ? "off" : "on", - (reg & TPS2205_VPP_VCC) ? "off" : "on" ); - - cp->cp_pbdat = reg; - - /* Wait 500 ms; use this to check for over-current */ - for (i=0; i<5000; ++i) { - if ((cp->cp_pbdat & TPS2205_OC) == 0) { - printf (" *** Overcurrent - Safety shutdown ***\n"); - cp->cp_pbdat &= ~(TPS2205_SHDN); - return (1); - } - udelay (100); - } - - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - - udelay(250000); /* some cards need >150 ms to come up :-( */ - - debug ("# hardware_enable done\n"); - - return (0); -} - - -#if defined(CONFIG_CMD_PCMCIA) -int pcmcia_hardware_disable(int slot) -{ - volatile immap_t *immap; - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - u_long reg; - - debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - - immap = (immap_t *)CONFIG_SYS_IMMR; - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - - /* Shut down */ - cp->cp_pbdat &= ~(TPS2205_SHDN); - - /* Configure PCMCIA General Control Register */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - - udelay(10000); - - return (0); -} -#endif - - -int pcmcia_voltage_set(int slot, int vcc, int vpp) -{ - volatile cpm8xx_t *cp; - volatile pcmconf8xx_t *pcmp; - u_long reg; - - debug ("voltage_set: " - PCMCIA_BOARD_MSG - " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", - 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - /* - * Disable PCMCIA buffers (isolate the interface) - * and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - /* - * Configure Port C pins for - * 5 Volts Enable and 3 Volts enable, - * Turn all power pins to Hi-Z - */ - debug ("PCMCIA power OFF\n"); - cfg_port_B (); /* Enables switch, but all in Hi-Z */ - - reg = cp->cp_pbdat; - - switch(vcc) { - case 0: break; /* Switch off */ - case 33: reg &= ~TPS2205_VCC3; break; /* Switch on 3.3V */ - case 50: reg &= ~TPS2205_VCC5; break; /* Switch on 5.0V */ - default: goto done; - } - - /* Checking supported voltages */ - - debug ("PIPR: 0x%x --> %s\n", - pcmp->pcmc_pipr, - (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); - - cp->cp_pbdat = reg; - -#ifdef DEBUG -{ - char *s; - - if ((reg & TPS2205_VCC3) == 0) { - s = "at 3.3V"; - } else if ((reg & TPS2205_VCC5) == 0) { - s = "at 5.0V"; - } else { - s = "down"; - } - printf ("PCMCIA powered %s\n", s); -} -#endif - -done: - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX(_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX(_slot_) = reg; - udelay(500); - - debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", - slot+'A'); - return (0); -} - -#endif /* CONFIG_PCMCIA */ diff --git a/board/icu862/u-boot.lds b/board/icu862/u-boot.lds deleted file mode 100644 index 00f63d2..0000000 --- a/board/icu862/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2001-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/icu862/u-boot.lds.debug b/board/icu862/u-boot.lds.debug deleted file mode 100644 index c7c6116..0000000 --- a/board/icu862/u-boot.lds.debug +++ /dev/null @@ -1,122 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/ids/ids8247/Kconfig b/board/ids/ids8247/Kconfig deleted file mode 100644 index bbab727..0000000 --- a/board/ids/ids8247/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_IDS8247 - -config SYS_BOARD - default "ids8247" - -config SYS_VENDOR - default "ids" - -config SYS_CONFIG_NAME - default "IDS8247" - -endif diff --git a/board/ids/ids8247/MAINTAINERS b/board/ids/ids8247/MAINTAINERS deleted file mode 100644 index 3173cdf..0000000 --- a/board/ids/ids8247/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -IDS8247 BOARD -M: Heiko Schocher <hs@denx.de> -S: Maintained -F: board/ids/ids8247/ -F: include/configs/IDS8247.h -F: configs/IDS8247_defconfig diff --git a/board/ids/ids8247/Makefile b/board/ids/ids8247/Makefile deleted file mode 100644 index 99c47b6..0000000 --- a/board/ids/ids8247/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2005 -# Heiko Schocher, DENX Software Engineering, <hs@denx.de> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = ids8247.o diff --git a/board/ids/ids8247/ids8247.c b/board/ids/ids8247/ids8247.c deleted file mode 100644 index 1b2d0e0..0000000 --- a/board/ids/ids8247/ids8247.c +++ /dev/null @@ -1,390 +0,0 @@ -/* - * (C) Copyright 2005 - * Heiko Schocher, DENX Software Engineering, <hs@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ioports.h> -#include <mpc8260.h> - -#if defined(CONFIG_OF_LIBFDT) -#include <libfdt.h> -#include <libfdt_env.h> -#include <fdt_support.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */ - /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */ - /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */ - /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */ - /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */ - /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */ - /* PA25 */ { 0, 0, 0, 0, 1, 0 }, /* 8247_P0 */ -#if defined(CONFIG_SYS_I2C_SOFT) - /* PA24 */ { 1, 0, 0, 0, 1, 1 }, /* I2C_SDA2 */ - /* PA23 */ { 1, 0, 0, 1, 1, 1 }, /* I2C_SCL2 */ -#else /* normal I/O port pins */ - /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */ - /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */ -#endif - /* PA22 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DCD */ - /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */ - /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */ - /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */ - /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */ - /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */ - /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */ - /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */ - /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */ - /* PA13 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_RTS */ - /* PA12 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_CTS */ - /* PA11 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_DTR */ - /* PA10 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DSR */ - /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_OUT */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_IN */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */ - /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */ - /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDC */ - /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 1, 0, 0, 0, 0 }, /* SCC3_RX */ - /* PD24 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_TX */ - /* PD23 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_RTS */ - /* PD22 */ { 0, 1, 0, 0, 0, 0 }, /* SCC4_RXD */ - /* PD21 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_TXD */ - /* PD20 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_RTS */ - /* PD19 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_SEL */ - /* PD18 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_CLK */ - /* PD17 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MOSI */ - /* PD16 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MISO */ -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA1 */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL1 */ -#else /* normal I/O port pins */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* PD15 */ - /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* PD14 */ -#endif - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */ - /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */ - /* PD7 */ { 1, 0, 0, 1, 0, 1 }, /* MII_MDIO */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* Check Board Identity: - */ -int checkboard (void) -{ - puts ("Board: IDS 8247\n"); - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, - ulong orx, volatile uchar * base) -{ - volatile uchar c = 0xff; - volatile uint *sdmr_ptr; - volatile uint *orx_ptr; - ulong maxsize, size; - int i; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff))/* / 2*/; - - sdmr_ptr = &memctl->memc_psdmr; - orx_ptr = &memctl->memc_or2; - - *orx_ptr = orx; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - *sdmr_ptr = sdmr | PSDMR_OP_PREA; - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ - - *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *base = c; - - size = get_ram_size((long *)base, maxsize); - *orx_ptr = orx | ~(size - 1); - - return (size); -} - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - - long psize; - - psize = 16 * 1024 * 1024; - - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - -#ifndef CONFIG_SYS_RAMBOOT - /* 60x SDRAM setup: - */ - psize = try_init (memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR2, - (uchar *) CONFIG_SYS_SDRAM_BASE); -#endif /* CONFIG_SYS_RAMBOOT */ - - icache_enable (); - - return (psize); -} - -int misc_init_r (void) -{ - gd->bd->bi_flashstart = 0xff800000; - return 0; -} - -#if defined(CONFIG_CMD_NAND) -#include <nand.h> -#include <linux/mtd/mtd.h> -#include <asm/io.h> - -static u8 hwctl; - -static void ids_nand_hwctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - - if (ctrl & NAND_CTRL_CHANGE) { - if ( ctrl & NAND_CLE ) { - hwctl |= 0x1; - writeb(0x00, (this->IO_ADDR_W + 0x0a)); - } else { - hwctl &= ~0x1; - writeb(0x00, (this->IO_ADDR_W + 0x08)); - } - if ( ctrl & NAND_ALE ) { - hwctl |= 0x2; - writeb(0x00, (this->IO_ADDR_W + 0x09)); - } else { - hwctl &= ~0x2; - writeb(0x00, (this->IO_ADDR_W + 0x08)); - } - if ( (ctrl & NAND_NCE) != NAND_NCE) - writeb(0x00, (this->IO_ADDR_W + 0x0c)); - else - writeb(0x00, (this->IO_ADDR_W + 0x08)); - } - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); - -} - -static u_char ids_nand_read_byte(struct mtd_info *mtd) -{ - struct nand_chip *this = mtd->priv; - - return readb(this->IO_ADDR_R); -} - -static void ids_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) -{ - struct nand_chip *nand = mtd->priv; - int i; - - for (i = 0; i < len; i++) { - if (hwctl & 0x1) - writeb(buf[i], (nand->IO_ADDR_W + 0x02)); - else if (hwctl & 0x2) - writeb(buf[i], (nand->IO_ADDR_W + 0x01)); - else - writeb(buf[i], nand->IO_ADDR_W); - } -} - -static void ids_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) -{ - struct nand_chip *this = mtd->priv; - int i; - - for (i = 0; i < len; i++) { - buf[i] = readb(this->IO_ADDR_R); - } -} - -static int ids_nand_dev_ready(struct mtd_info *mtd) -{ - /* constant delay (see also tR in the datasheet) */ - udelay(12); - return 1; -} - -int board_nand_init(struct nand_chip *nand) -{ - nand->ecc.mode = NAND_ECC_SOFT; - - /* Reference hardware control function */ - nand->cmd_ctrl = ids_nand_hwctrl; - nand->read_byte = ids_nand_read_byte; - nand->write_buf = ids_nand_write_buf; - nand->read_buf = ids_nand_read_buf; - nand->dev_ready = ids_nand_dev_ready; - nand->chip_delay = 12; - - return 0; -} - -#endif /* CONFIG_CMD_NAND */ - -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup( blob, bd); -} -#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/prodrive/p3mx/64460.h b/board/prodrive/p3mx/64460.h deleted file mode 100644 index 9cf7fee..0000000 --- a/board/prodrive/p3mx/64460.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus <ingo.assmus@keymile.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * main board support/init for the Galileo Eval board DB64460. - */ - -#ifndef __64460_H__ -#define __64460_H__ - -/* CPU Configuration bits */ -#define CPU_CONF_ADDR_MISS_EN (1 << 8) -#define CPU_CONF_SINGLE_CPU (1 << 11) -#define CPU_CONF_ENDIANESS (1 << 12) -#define CPU_CONF_PIPELINE (1 << 13) -#define CPU_CONF_STOP_RETRY (1 << 17) -#define CPU_CONF_MULTI_DECODE (1 << 18) -#define CPU_CONF_DP_VALID (1 << 19) -#define CPU_CONF_PERR_PROP (1 << 22) -#define CPU_CONF_AACK_DELAY_2 (1 << 25) -#define CPU_CONF_AP_VALID (1 << 26) -#define CPU_CONF_REMAP_WR_DIS (1 << 27) - -/* CPU Master Control bits */ -#define CPU_MAST_CTL_ARB_EN (1 << 8) -#define CPU_MAST_CTL_MASK_BR_1 (1 << 9) -#define CPU_MAST_CTL_M_WR_TRIG (1 << 10) -#define CPU_MAST_CTL_M_RD_TRIG (1 << 11) -#define CPU_MAST_CTL_CLEAN_BLK (1 << 12) -#define CPU_MAST_CTL_FLUSH_BLK (1 << 13) - -#endif /* __64460_H__ */ diff --git a/board/prodrive/p3mx/Kconfig b/board/prodrive/p3mx/Kconfig deleted file mode 100644 index 28fb8bb..0000000 --- a/board/prodrive/p3mx/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_P3MX - -config SYS_BOARD - default "p3mx" - -config SYS_VENDOR - default "prodrive" - -config SYS_CONFIG_NAME - default "p3mx" - -endif diff --git a/board/prodrive/p3mx/MAINTAINERS b/board/prodrive/p3mx/MAINTAINERS deleted file mode 100644 index e60fdb6..0000000 --- a/board/prodrive/p3mx/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -P3MX BOARD -M: Stefan Roese <sr@denx.de> -S: Maintained -F: board/prodrive/p3mx/ -F: include/configs/p3mx.h -F: configs/p3m7448_defconfig -F: configs/p3m750_defconfig diff --git a/board/prodrive/p3mx/Makefile b/board/prodrive/p3mx/Makefile deleted file mode 100644 index 6ddda22..0000000 --- a/board/prodrive/p3mx/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = misc.o -obj-y += p3mx.o mpsc.o mv_eth.o pci.o sdram_init.o serial.o \ - ../../Marvell/common/i2c.o ../../Marvell/common/memory.o diff --git a/board/prodrive/p3mx/eth.h b/board/prodrive/p3mx/eth.h deleted file mode 100644 index d5fe3cb..0000000 --- a/board/prodrive/p3mx/eth.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * eth.h - header file for the polled mode GT ethernet driver - */ - -#ifndef __EVB64360_ETH_H__ -#define __EVB64360_ETH_H__ - -#include <asm/types.h> -#include <asm/io.h> -#include <asm/byteorder.h> -#include <common.h> - - -int db64360_eth0_poll(void); -int db64360_eth0_transmit(unsigned int s, volatile char *p); -void db64360_eth0_disable(void); -bool network_start(bd_t *bis); - -int mv6446x_eth_initialize(bd_t *); - -#endif /* __EVB64360_ETH_H__ */ diff --git a/board/prodrive/p3mx/misc.S b/board/prodrive/p3mx/misc.S deleted file mode 100644 index 233fd83..0000000 --- a/board/prodrive/p3mx/misc.S +++ /dev/null @@ -1,245 +0,0 @@ -#include <config.h> -#include <74xx_7xx.h> -#include "version.h" - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#include <asm/cache.h> -#include <asm/mmu.h> - -#include "../../Marvell/include/mv_gen_reg.h" - -#ifdef CONFIG_ECC - /* Galileo specific asm code for initializing ECC */ - .globl board_relocate_rom -board_relocate_rom: - mflr r7 - /* update the location of the GT registers */ - lis r11, CONFIG_SYS_GT_REGS@h - /* if we're using ECC, we must use the DMA engine to copy ourselves */ - bl start_idma_transfer_0 - bl wait_for_idma_0 - bl stop_idma_engine_0 - - mtlr r7 - blr - - .globl board_init_ecc -board_init_ecc: - mflr r7 - /* NOTE: r10 still contains the location we've been relocated to - * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */ - - /* now that we're running from ram, init the rest of main memory - * for ECC use */ - lis r8, CONFIG_SYS_MONITOR_LEN@h - ori r8, r8, CONFIG_SYS_MONITOR_LEN@l - - divw r3, r10, r8 - - /* set up the counter, and init the starting address */ - mtctr r3 - li r12, 0 - - /* bytes per transfer */ - mr r5, r8 -about_to_init_ecc: -1: mr r3, r12 - mr r4, r12 - bl start_idma_transfer_0 - bl wait_for_idma_0 - bl stop_idma_engine_0 - add r12, r12, r8 - bdnz 1b - - mtlr r7 - blr - - /* r3: dest addr - * r4: source addr - * r5: byte count - * r11: gt regbase - * trashes: r6, r5 - */ -start_idma_transfer_0: - /* set the byte count, including the OWN bit */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_BYTE_COUNT - stwbrx r5, 0, (r6) - - /* set the source address */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS - stwbrx r4, 0, (r6) - - /* set the dest address */ - mr r6, r11 - ori r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS - stwbrx r3, 0, (r6) - - /* set the next record pointer */ - li r5, 0 - mr r6, r11 - ori r6, r6, CHANNEL0NEXT_RECORD_POINTER - stwbrx r5, 0, (r6) - - /* set the low control register */ - /* bit 9 is NON chained mode, bit 31 is new style descriptors. - bit 12 is channel enable */ - ori r5, r5, (1 << 12) | (1 << 12) | (1 << 11) - /* 15 shifted by 16 (oris) == bit 31 */ - oris r5, r5, (1 << 15) - mr r6, r11 - ori r6, r6, CHANNEL0CONTROL - stwbrx r5, 0, (r6) - - blr - - /* this waits for the bytecount to return to zero, indicating - * that the trasfer is complete */ -wait_for_idma_0: - mr r5, r11 - lis r6, 0xff - ori r6, r6, 0xffff - ori r5, r5, CHANNEL0_DMA_BYTE_COUNT -1: lwbrx r4, 0, (r5) - and. r4, r4, r6 - bne 1b - - blr - - /* this turns off channel 0 of the idma engine */ -stop_idma_engine_0: - /* shut off the DMA engine */ - li r5, 0 - mr r6, r11 - ori r6, r6, CHANNEL0CONTROL - stwbrx r5, 0, (r6) - - blr -#endif - -#ifdef CONFIG_SYS_BOARD_ASM_INIT - /* NOTE: trashes r3-r7 */ - .globl board_asm_init -board_asm_init: - /* just move the GT registers to where they belong */ - lis r3, CONFIG_SYS_DFL_GT_REGS@h - ori r3, r3, CONFIG_SYS_DFL_GT_REGS@l - lis r4, CONFIG_SYS_GT_REGS@h - ori r4, r4, CONFIG_SYS_GT_REGS@l - li r5, INTERNAL_SPACE_DECODE - - /* test to see if we've already moved */ - lwbrx r6, r5, r4 - andi. r6, r6, 0xffff - /* check loading of R7 is: 0x0F80 should: 0xf800: DONE */ -/* rlwinm r7, r4, 8, 16, 31 - rlwinm r7, r4, 12, 16, 31 */ /* original */ - rlwinm r7, r4, 16, 16, 31 - /* -----------------------------------------------------*/ - cmp cr0, r7, r6 - beqlr - - /* nope, have to move the registers */ - lwbrx r6, r5, r3 - andis. r6, r6, 0xffff - or r6, r6, r7 - stwbrx r6, r5, r3 - - /* now, poll for the change */ -1: lwbrx r7, r5, r4 - cmp cr0, r7, r6 - bne 1b - - lis r3, CONFIG_SYS_INT_SRAM_BASE@h - ori r3, r3, CONFIG_SYS_INT_SRAM_BASE@l - rlwinm r3, r3, 16, 16, 31 - lis r4, CONFIG_SYS_GT_REGS@h - ori r4, r4, CONFIG_SYS_GT_REGS@l - li r5, INTEGRATED_SRAM_BASE_ADDR - stwbrx r3, r5, r4 - -2: lwbrx r6, r5, r4 - cmp cr0, r3, r6 - bne 2b - - /* done! */ - blr -#endif - -/* For use of the debug LEDs */ - .global led_on0_relocated -led_on0_relocated: - xor r21, r21, r21 - xor r18, r18, r18 - lis r18, 0xFC80 - ori r18, r18, 0x8000 -/* stw r21, 0x0(r18) */ - sync - blr - - .global led_off0_relocated -led_off0_relocated: - xor r21, r21, r21 - xor r18, r18, r18 - lis r18, 0xFC81 - ori r18, r18, 0x4000 -/* stw r21, 0x0(r18) */ - sync - blr - - .global led_on0 -led_on0: - xor r18, r18, r18 - lis r18, 0x1c80 - ori r18, r18, 0x8000 -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_off0 -led_off0: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0x4000 -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_on1 -led_on1: - xor r18, r18, r18 - lis r18, 0x1c80 - ori r18, r18, 0xc000 -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_off1 -led_off1: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0x8000 -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_on2 -led_on2: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0x0000 -/* stw r18, 0x0(r18) */ - sync - blr - - .global led_off2 -led_off2: - xor r18, r18, r18 - lis r18, 0x1c81 - ori r18, r18, 0xc000 -/* stw r18, 0x0(r18) */ - sync - blr diff --git a/board/prodrive/p3mx/mpsc.c b/board/prodrive/p3mx/mpsc.c deleted file mode 100644 index 97d0909..0000000 --- a/board/prodrive/p3mx/mpsc.c +++ /dev/null @@ -1,997 +0,0 @@ -/* - * (C) Copyright 2001 - * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * changes for Marvell DB64460 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com> - * - ************************************************************************/ - -/* - * mpsc.c - driver for console over the MPSC. - */ - - -#include <common.h> -#include <config.h> -#include <asm/cache.h> - -#include <malloc.h> -#include "mpsc.h" - -#include "mv_regs.h" - -#include "../../Marvell/include/memory.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* Define this if you wish to use the MPSC as a register based UART. - * This will force the serial port to not use the SDMA engine at all. - */ -#undef CONFIG_MPSC_DEBUG_PORT - - -int (*mpsc_putchar) (char ch) = mpsc_putchar_early; -char (*mpsc_getchar) (void) = mpsc_getchar_debug; -int (*mpsc_test_char) (void) = mpsc_test_char_debug; - - -static volatile unsigned int *rx_desc_base = NULL; -static unsigned int rx_desc_index = 0; -static volatile unsigned int *tx_desc_base = NULL; -static unsigned int tx_desc_index = 0; - -/* local function declarations */ -static int galmpsc_connect (int channel, int connect); -static int galmpsc_route_rx_clock (int channel, int brg); -static int galmpsc_route_tx_clock (int channel, int brg); -static int galmpsc_write_config_regs (int mpsc, int mode); -static int galmpsc_config_channel_regs (int mpsc); -static int galmpsc_set_char_length (int mpsc, int value); -static int galmpsc_set_stop_bit_length (int mpsc, int value); -static int galmpsc_set_parity (int mpsc, int value); -static int galmpsc_enter_hunt (int mpsc); -static int galmpsc_set_brkcnt (int mpsc, int value); -static int galmpsc_set_tcschar (int mpsc, int value); -static int galmpsc_set_snoop (int mpsc, int value); -static int galmpsc_shutdown (int mpsc); - -static int galsdma_set_RFT (int channel); -static int galsdma_set_SFM (int channel); -static int galsdma_set_rxle (int channel); -static int galsdma_set_txle (int channel); -static int galsdma_set_burstsize (int channel, unsigned int value); -static int galsdma_set_RC (int channel, unsigned int value); - -static int galbrg_set_CDV (int channel, int value); -static int galbrg_enable (int channel); -static int galbrg_disable (int channel); -static int galbrg_set_clksrc (int channel, int value); -static int galbrg_set_CUV (int channel, int value); - -static void galsdma_enable_rx (void); -static int galsdma_set_mem_space (unsigned int memSpace, - unsigned int memSpaceTarget, - unsigned int memSpaceAttr, - unsigned int baseAddress, - unsigned int size); - - -#define SOFTWARE_CACHE_MANAGEMENT - -#ifdef SOFTWARE_CACHE_MANAGEMENT -#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));} -#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));} -#else -#define FLUSH_DCACHE(a,b) -#define FLUSH_AND_INVALIDATE_DCACHE(a,b) -#define INVALIDATE_DCACHE(a,b) -#endif - -#ifdef CONFIG_MPSC_DEBUG_PORT -static void mpsc_debug_init (void) -{ - - volatile unsigned int temp; - - /* Clear the CFR (CHR4) */ - /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */ - temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP)); - temp &= 0xffffff00; - temp |= BIT29; - GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP), - temp); - - /* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */ - temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP)); - temp |= (BIT12 | BIT15); - GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP), - temp); - - /* Set int mask */ - temp = GTREGREAD (GALMPSC_0_INT_MASK); - temp |= BIT6; - GT_REG_WRITE (GALMPSC_0_INT_MASK, temp); -} -#endif - -char mpsc_getchar_debug (void) -{ - volatile int temp; - volatile unsigned int cause; - - cause = GTREGREAD (GALMPSC_0_INT_CAUSE); - while ((cause & BIT6) == 0) { - cause = GTREGREAD (GALMPSC_0_INT_CAUSE); - } - - temp = GTREGREAD (GALMPSC_CHANNELREG_10 + - (CHANNEL * GALMPSC_REG_GAP)); - /* By writing 1's to the set bits, the register is cleared */ - GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP), - temp); - GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6); - return (temp >> 16) & 0xff; -} - -/* special function for running out of flash. doesn't modify any - * global variables [josh] */ -int mpsc_putchar_early (char ch) -{ - int mpsc = CHANNEL; - int temp = - GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - galmpsc_set_tcschar (mpsc, ch); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), - temp | 0x200); - -#define MAGIC_FACTOR (10*1000000) - - udelay (MAGIC_FACTOR / gd->baudrate); - return 0; -} - -/* This is used after relocation, see serial.c and mpsc_init2 */ -static int mpsc_putchar_sdma (char ch) -{ - volatile unsigned int *p; - unsigned int temp; - - - /* align the descriptor */ - p = tx_desc_base; - memset ((void *) p, 0, 8 * sizeof (unsigned int)); - - /* fill one 64 bit buffer */ - /* word swap, pad with 0 */ - p[4] = 0; /* x */ - p[5] = (unsigned int) ch; /* x */ - - /* CHANGED completely according to GT64260A dox - NTL */ - p[0] = 0x00010001; /* 0 */ - p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* 4 */ - p[2] = 0; /* 8 */ - p[3] = (unsigned int) &p[4]; /* c */ - -#if 0 - p[9] = DESC_FIRST | DESC_LAST; - p[10] = (unsigned int) &p[0]; - p[11] = (unsigned int) &p[12]; -#endif - - FLUSH_DCACHE (&p[0], &p[8]); - - GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &p[0]); - GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &p[0]); - - temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF)); - temp |= (TX_DEMAND | TX_STOP); - GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp); - - INVALIDATE_DCACHE (&p[1], &p[2]); - - while (p[1] & DESC_OWNER_BIT) { - udelay (100); - INVALIDATE_DCACHE (&p[1], &p[2]); - } - return 0; -} - -char mpsc_getchar_sdma (void) -{ - static unsigned int done = 0; - volatile char ch; - unsigned int len = 0, idx = 0, temp; - - volatile unsigned int *p; - - - do { - p = &rx_desc_base[rx_desc_index * 8]; - - INVALIDATE_DCACHE (&p[0], &p[1]); - /* Wait for character */ - while (p[1] & DESC_OWNER_BIT) { - udelay (100); - INVALIDATE_DCACHE (&p[0], &p[1]); - } - - /* Handle error case */ - if (p[1] & (1 << 15)) { - printf ("oops, error: %08x\n", p[1]); - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + - (CHANNEL * GALMPSC_REG_GAP)); - temp |= (1 << 23); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + - (CHANNEL * GALMPSC_REG_GAP), temp); - - /* Can't poll on abort bit, so we just wait. */ - udelay (100); - - galsdma_enable_rx (); - } - - /* Number of bytes left in this descriptor */ - len = p[0] & 0xffff; - - if (len) { - /* Where to look */ - idx = 5; - if (done > 3) - idx = 4; - if (done > 7) - idx = 7; - if (done > 11) - idx = 6; - - INVALIDATE_DCACHE (&p[idx], &p[idx + 1]); - ch = p[idx] & 0xff; - done++; - } - - if (done < len) { - /* this descriptor has more bytes still - * shift down the char we just read, and leave the - * buffer in place for the next time around - */ - p[idx] = p[idx] >> 8; - FLUSH_DCACHE (&p[idx], &p[idx + 1]); - } - - if (done == len) { - /* nothing left in this descriptor. - * go to next one - */ - p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; - p[0] = 0x00100000; - FLUSH_DCACHE (&p[0], &p[1]); - /* Next descriptor */ - rx_desc_index = (rx_desc_index + 1) % RX_DESC; - done = 0; - } - } while (len == 0); /* galileo bug.. len might be zero */ - - return ch; -} - - -int mpsc_test_char_debug (void) -{ - if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0) - return 0; - else { - return 1; - } -} - - -int mpsc_test_char_sdma (void) -{ - volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8]; - - INVALIDATE_DCACHE (&p[1], &p[2]); - - if (p[1] & DESC_OWNER_BIT) - return 0; - else - return 1; -} - -int mpsc_init (int baud) -{ - /* BRG CONFIG */ - galbrg_set_baudrate (CHANNEL, baud); - galbrg_set_clksrc (CHANNEL, 8); /* set source=Tclk */ - galbrg_set_CUV (CHANNEL, 0); /* set up CountUpValue */ - galbrg_enable (CHANNEL); /* Enable BRG */ - - /* Set up clock routing */ - galmpsc_connect (CHANNEL, GALMPSC_CONNECT); /* connect it */ - - galmpsc_route_rx_clock (CHANNEL, CHANNEL); /* chosse BRG0 for Rx */ - galmpsc_route_tx_clock (CHANNEL, CHANNEL); /* chose BRG0 for Tx */ - - /* reset MPSC state */ - galmpsc_shutdown (CHANNEL); - - /* SDMA CONFIG */ - galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8); /* in 64 bit words (8 bytes) */ - galsdma_set_txle (CHANNEL); - galsdma_set_rxle (CHANNEL); - galsdma_set_RC (CHANNEL, 0xf); - galsdma_set_SFM (CHANNEL); - galsdma_set_RFT (CHANNEL); - - /* MPSC CONFIG */ - galmpsc_write_config_regs (CHANNEL, GALMPSC_UART); - galmpsc_config_channel_regs (CHANNEL); - galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8); /* 8 */ - galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE); /* N */ - galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */ - -#ifdef CONFIG_MPSC_DEBUG_PORT - mpsc_debug_init (); -#endif - - /* COMM_MPSC CONFIG */ -#ifdef SOFTWARE_CACHE_MANAGEMENT - galmpsc_set_snoop (CHANNEL, 0); /* disable snoop */ -#else - galmpsc_set_snoop (CHANNEL, 1); /* enable snoop */ -#endif - - return 0; -} - - -void mpsc_sdma_init (void) -{ - /* Setup SDMA channel0 SDMA_CONFIG_REG*/ - GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff); - - /* Enable MPSC-Window0 for DRAM Bank 0 */ - if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT, - MV64460_SDMA_DRAM_CS_0_TARGET, - 0, - memoryGetBankBaseAddress(0), - memoryGetBankSize(0)) != true) - printf ("%s: SDMA_Window0 memory setup failed !!! \n", - __FUNCTION__); - - - /* Enable MPSC-Window1 for DRAM Bank 1 */ - if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_1_BIT, - MV64460_SDMA_DRAM_CS_1_TARGET, - 0, - memoryGetBankBaseAddress(1), - memoryGetBankSize(1)) != true) - printf ("%s: SDMA_Window1 memory setup failed !!! \n", - __FUNCTION__); - - - /* Disable MPSC-Window2 */ - if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_2_BIT, - MV64460_SDMA_DRAM_CS_2_TARGET, - 0, - memoryGetBankBaseAddress(2), - memoryGetBankSize(2)) != true) - printf ("%s: SDMA_Window2 memory setup failed !!! \n", - __FUNCTION__); - - - /* Disable MPSC-Window3 */ - if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_3_BIT, - MV64460_SDMA_DRAM_CS_3_TARGET, - 0, - memoryGetBankBaseAddress(3), - memoryGetBankSize(3)) != true) - printf ("%s: SDMA_Window3 memory setup failed !!! \n", - __FUNCTION__); - - /* Setup MPSC0 access mode Window0 full access */ - GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG, - (MV64460_SDMA_WIN_ACCESS_FULL << - (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); - - /* Setup MPSC1 access mode Window1 full access */ - GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG, - (MV64460_SDMA_WIN_ACCESS_FULL << - (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); - - /* Setup MPSC internal address space base address */ - GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS); - - /* no high address remap*/ - GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00); - GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00); - - /* clear interrupt cause register for MPSC (fault register)*/ - GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00); -} - - -void mpsc_init2 (void) -{ - int i; - -#ifndef CONFIG_MPSC_DEBUG_PORT - mpsc_putchar = mpsc_putchar_sdma; - mpsc_getchar = mpsc_getchar_sdma; - mpsc_test_char = mpsc_test_char_sdma; -#endif - /* RX descriptors */ - rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) * - sizeof (unsigned int)); - - /* align descriptors */ - rx_desc_base = (unsigned int *) - (((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0); - - rx_desc_index = 0; - - memset ((void *) rx_desc_base, 0, - (RX_DESC * 8) * sizeof (unsigned int)); - - for (i = 0; i < RX_DESC; i++) { - rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4]; /* Buffer */ - rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8]; /* Next descriptor */ - rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* Command & control */ - rx_desc_base[i * 8] = 0x00100000; - } - rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0]; - - FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]); - GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF), - (unsigned int) &rx_desc_base[0]); - - /* TX descriptors */ - tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) * - sizeof (unsigned int)); - - /* align descriptors */ - tx_desc_base = (unsigned int *) - (((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0); - - tx_desc_index = -1; - - memset ((void *) tx_desc_base, 0, - (TX_DESC * 8) * sizeof (unsigned int)); - - for (i = 0; i < TX_DESC; i++) { - tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323; - tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323; - tx_desc_base[i * 8 + 3] = - (unsigned int) &tx_desc_base[i * 8 + 4]; - tx_desc_base[i * 8 + 2] = - (unsigned int) &tx_desc_base[(i + 1) * 8]; - tx_desc_base[i * 8 + 1] = - DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; - - /* set sbytecnt and shadow byte cnt to 1 */ - tx_desc_base[i * 8] = 0x00010001; - } - tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0]; - - FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]); - - udelay (100); - - galsdma_enable_rx (); - - return; -} - -int galbrg_set_baudrate (int channel, int rate) -{ - int clock; - - galbrg_disable (channel); /*ok */ - -#ifdef ZUMA_NTL - /* from tclk */ - clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; -#else - clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; -#endif - - galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */ - - galbrg_enable (channel); - - gd->baudrate = rate; - - return 0; -} - -/* ------------------------------------------------------------------ */ - -/* Below are all the private functions that no one else needs */ - -static int galbrg_set_CDV (int channel, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFFF0000; - temp |= (value & 0x0000FFFF); - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_enable (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp |= 0x00010000; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_disable (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFFEFFFF; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} - -static int galbrg_set_clksrc (int channel, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp &= 0xFFC3FFFF; /* Bit 18 - 21 (MV 64260 18-22) */ - temp |= (value << 18); - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - return 0; -} - -static int galbrg_set_CUV (int channel, int value) -{ - /* set CountUpValue */ - GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value); - - return 0; -} - -#if 0 -static int galbrg_reset (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); - temp |= 0x20000; - GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); - - return 0; -} -#endif - -static int galsdma_set_RFT (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000001; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_SFM (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000002; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_rxle (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000040; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_txle (int channel) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp |= 0x00000080; - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_RC (int channel, unsigned int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp &= ~0x0000003c; - temp |= (value << 2); - GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), - temp); - - return 0; -} - -static int galsdma_set_burstsize (int channel, unsigned int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); - temp &= 0xFFFFCFFF; - switch (value) { - case 8: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x3 << 12))); - break; - - case 4: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x2 << 12))); - break; - - case 2: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x1 << 12))); - break; - - case 1: - GT_REG_WRITE (GALSDMA_0_CONF_REG + - (channel * GALSDMA_REG_DIFF), - (temp | (0x0 << 12))); - break; - - default: - return -1; - break; - } - - return 0; -} - -static int galmpsc_connect (int channel, int connect) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_ROUTING_REGISTER); - - if ((channel == 0) && connect) - temp &= ~0x00000007; - else if ((channel == 1) && connect) - temp &= ~(0x00000007 << 6); - else if ((channel == 0) && !connect) - temp |= 0x00000007; - else - temp |= (0x00000007 << 6); - - /* Just in case... */ - temp &= 0x3fffffff; - - GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp); - - return 0; -} - -static int galmpsc_route_rx_clock (int channel, int brg) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_RxC_ROUTE); - - if (channel == 0) { - temp &= ~0x0000000F; - temp |= brg; - } else { - temp &= ~0x00000F00; - temp |= (brg << 8); - } - - GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp); - - return 0; -} - -static int galmpsc_route_tx_clock (int channel, int brg) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_TxC_ROUTE); - - if (channel == 0) { - temp &= ~0x0000000F; - temp |= brg; - } else { - temp &= ~0x00000F00; - temp |= (brg << 8); - } - - GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp); - - return 0; -} - -static int galmpsc_write_config_regs (int mpsc, int mode) -{ - if (mode == GALMPSC_UART) { - /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */ - GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP), - 0x000004c4); - - /* Main config reg High (32x Rx/Tx clock mode, width=8bits */ - GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP), - 0x024003f8); - /* 22 2222 1111 */ - /* 54 3210 9876 */ - /* 0000 0010 0000 0000 */ - /* 1 */ - /* 098 7654 3210 */ - /* 0000 0011 1111 1000 */ - } else - return -1; - - return 0; -} - -static int galmpsc_config_channel_regs (int mpsc) -{ - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1); - GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0); - GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0); - - galmpsc_set_brkcnt (mpsc, 0x3); - galmpsc_set_tcschar (mpsc, 0xab); - - return 0; -} - -static int galmpsc_set_brkcnt (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP)); - temp &= 0x0000FFFF; - temp |= (value << 16); - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_tcschar (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFF0000; - temp |= value; - GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_char_length (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFFCFFF; - temp |= (value << 12); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_stop_bit_length (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP)); - temp &= 0xFFFFBFFF; - temp |= (value << 14); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_set_parity (int mpsc, int value) -{ - unsigned int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - if (value != -1) { - temp &= 0xFFF3FFF3; - temp |= ((value << 18) | (value << 2)); - temp |= ((value << 17) | (value << 1)); - } else { - temp &= 0xFFF1FFF1; - } - - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - return 0; -} - -static int galmpsc_enter_hunt (int mpsc) -{ - int temp; - - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - temp |= 0x80000000; - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) & - MPSC_ENTER_HUNT) { - udelay (1); - } - return 0; -} - - -static int galmpsc_shutdown (int mpsc) -{ - unsigned int temp; - - /* cause RX abort (clears RX) */ - temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); - temp |= MPSC_RX_ABORT | MPSC_TX_ABORT; - temp &= ~MPSC_ENTER_HUNT; - GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); - - GT_REG_WRITE (GALSDMA_0_COM_REG, 0); - GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT); - - /* shut down the MPSC */ - GT_REG_WRITE (GALMPSC_MCONF_LOW, 0); - GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0); - GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0); - - udelay (100); - - /* shut down the sdma engines. */ - /* reset config to default */ - GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc); - - udelay (100); - - /* clear the SDMA current and first TX and RX pointers */ - GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0); - GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0); - GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0); - - udelay (100); - - return 0; -} - -static void galsdma_enable_rx (void) -{ - int temp; - - /* Enable RX processing */ - temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF)); - temp |= RX_ENABLE; - GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp); - - galmpsc_enter_hunt (CHANNEL); -} - -static int galmpsc_set_snoop (int mpsc, int value) -{ - int reg = - mpsc ? MPSC_1_ADDRESS_CONTROL_LOW : - MPSC_0_ADDRESS_CONTROL_LOW; - int temp = GTREGREAD (reg); - - if (value) - temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30); - else - temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30)); - GT_REG_WRITE (reg, temp); - return 0; -} - -/******************************************************************************* -* galsdma_set_mem_space - Set MV64460 IDMA memory decoding map. -* -* DESCRIPTION: -* the MV64460 SDMA has its own address decoding map that is de-coupled -* from the CPU interface address decoding windows. The SDMA channels -* share four address windows. Each region can be individually configured -* by this function by associating it to a target interface and setting -* base and size values. -* -* NOTE!!! -* The size must be in 64Kbyte granularity. -* The base address must be aligned to the size. -* The size must be a series of 1s followed by a series of zeros -* -* OUTPUT: -* None. -* -* RETURN: -* true for success, false otherwise. -* -*******************************************************************************/ - -static int galsdma_set_mem_space (unsigned int memSpace, - unsigned int memSpaceTarget, - unsigned int memSpaceAttr, - unsigned int baseAddress, unsigned int size) -{ - unsigned int temp; - - if (size == 0) { - GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG, - 1 << memSpace); - return true; - } - - /* The base address must be aligned to the size. */ - if (baseAddress % size != 0) { - return false; - } - if (size < 0x10000) { - return false; - } - - /* Align size and base to 64K */ - baseAddress &= 0xffff0000; - size &= 0xffff0000; - temp = size >> 16; - - /* Checking that the size is a sequence of '1' followed by a - sequence of '0' starting from LSB to MSB. */ - while ((temp > 0) && (temp & 0x1)) { - temp = temp >> 1; - } - - if (temp != 0) { - GT_REG_WRITE (MV64460_CUNIT_BASE_ADDR_REG0 + memSpace * 8, - (baseAddress | memSpaceTarget | memSpaceAttr)); - GT_REG_WRITE ((MV64460_CUNIT_SIZE0 + memSpace * 8), - (size - 1) & 0xffff0000); - GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG, - 1 << memSpace); - } else { - /* An invalid size was specified */ - return false; - } - return true; -} diff --git a/board/prodrive/p3mx/mpsc.h b/board/prodrive/p3mx/mpsc.h deleted file mode 100644 index 241f28a..0000000 --- a/board/prodrive/p3mx/mpsc.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * (C) Copyright 2001 - * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com> - * - ************************************************************************/ - - -/* - * mpsc.h - header file for MPSC in uart mode (console driver) - */ - -#ifndef __MPSC_H__ -#define __MPSC_H__ - -/* include actual Galileo defines */ -#include "../../Marvell/include/mv_gen_reg.h" - -/* driver related defines */ - -int mpsc_init(int baud); -void mpsc_sdma_init(void); -void mpsc_init2(void); -int galbrg_set_baudrate(int channel, int rate); - -int mpsc_putchar_early(char ch); -char mpsc_getchar_debug(void); -int mpsc_test_char_debug(void); - -int mpsc_test_char_sdma(void); - -extern int (*mpsc_putchar)(char ch); -extern char (*mpsc_getchar)(void); -extern int (*mpsc_test_char)(void); - -#define CHANNEL CONFIG_MPSC_PORT - -#define TX_DESC 5 -#define RX_DESC 20 - -#define DESC_FIRST 0x00010000 -#define DESC_LAST 0x00020000 -#define DESC_OWNER_BIT 0x80000000 - -#define TX_DEMAND 0x00800000 -#define TX_STOP 0x00010000 -#define RX_ENABLE 0x00000080 - -#define SDMA_RX_ABORT (1 << 15) -#define SDMA_TX_ABORT (1 << 31) -#define MPSC_TX_ABORT (1 << 7) -#define MPSC_RX_ABORT (1 << 23) -#define MPSC_ENTER_HUNT (1 << 31) - -/* MPSC defines */ - -#define GALMPSC_CONNECT 0x1 -#define GALMPSC_DISCONNECT 0x0 - -#define GALMPSC_UART 0x1 - -#define GALMPSC_STOP_BITS_1 0x0 -#define GALMPSC_STOP_BITS_2 0x1 -#define GALMPSC_CHAR_LENGTH_8 0x3 -#define GALMPSC_CHAR_LENGTH_7 0x2 - -#define GALMPSC_PARITY_ODD 0x0 -#define GALMPSC_PARITY_EVEN 0x2 -#define GALMPSC_PARITY_MARK 0x3 -#define GALMPSC_PARITY_SPACE 0x1 -#define GALMPSC_PARITY_NONE -1 - -#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */ -#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */ -#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */ -#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */ -#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */ -#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */ -#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */ - -#define GALMPSC_REG_GAP 0x1000 - -#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */ -#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */ -#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */ -#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */ -#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */ -#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */ -#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */ -#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */ -#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */ -#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */ -#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */ -#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */ - -#define GALSDMA_COMMAND_FIRST (1 << 16) -#define GALSDMA_COMMAND_LAST (1 << 17) -#define GALSDMA_COMMAND_ENABLEINT (1 << 23) -#define GALSDMA_COMMAND_AUTO (1 << 30) -#define GALSDMA_COMMAND_OWNER (1 << 31) - -#define GALSDMA_RX 0 -#define GALSDMA_TX 1 - -/* CHANNEL2 should be CHANNEL1, according to documentation, - * but to work with the current GTREGS file... - */ -#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */ -#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */ -#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */ -#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */ -#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */ -#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */ -#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */ -#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */ -#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */ -#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */ -#define GALSDMA_REG_DIFF 0x2000 - -/* WRONG in gt64260R.h */ -#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */ -#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */ -#define GALMPSC_0_INT_CAUSE 0xb804 -#define GALMPSC_0_INT_MASK 0xb884 - -#define GALSDMA_MODE_UART 0 -#define GALSDMA_MODE_BISYNC 1 -#define GALSDMA_MODE_HDLC 2 -#define GALSDMA_MODE_TRANSPARENT 3 - -#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */ -#define GALBRG_REG_GAP 0x0008 -#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */ - -#endif /* __MPSC_H__ */ diff --git a/board/prodrive/p3mx/mv_eth.c b/board/prodrive/p3mx/mv_eth.c deleted file mode 100644 index ebd93c0..0000000 --- a/board/prodrive/p3mx/mv_eth.c +++ /dev/null @@ -1,3291 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus <ingo.assmus@keymile.com> - * - * based on - Driver for MV64460X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mv_eth.c - header file for the polled mode GT ethernet driver - */ -#include <common.h> -#include <net.h> -#include <malloc.h> -#include <miiphy.h> - -#include "mv_eth.h" - -/* enable Debug outputs */ - -#undef DEBUG_MV_ETH - -#ifdef DEBUG_MV_ETH -#define DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -/* PHY DFCDL Registers */ -#define ETH_PHY_DFCDL_CONFIG0_REG 0x2100 -#define ETH_PHY_DFCDL_CONFIG1_REG 0x2104 -#define ETH_PHY_DFCDL_ADDR_REG 0x2110 -#define ETH_PHY_DFCDL_DATA0_REG 0x2114 - -#define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */ -#define PHY_UPDATE_TIMEOUT 10000 - -#undef MV64460_CHECKSUM_OFFLOAD -/************************************************************************* -* The first part is the high level driver of the gigE ethernet ports. * -*************************************************************************/ - -/* Definition for configuring driver */ -/* #define UPDATE_STATS_BY_SOFTWARE */ -#undef MV64460_RX_QUEUE_FILL_ON_TASK - -/* Constants */ -#define MAGIC_ETH_RUNNING 8031971 -#define MV64460_INTERNAL_SRAM_SIZE _256K -#define EXTRA_BYTES 32 -#define WRAP ETH_HLEN + 2 + 4 + 16 -#define BUFFER_MTU dev->mtu + WRAP -#define INT_CAUSE_UNMASK_ALL 0x0007ffff -#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff -#ifdef MV64460_RX_FILL_ON_TASK -#define INT_CAUSE_MASK_ALL 0x00000000 -#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL -#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT -#endif - -/* Read/Write to/from MV64460 internal registers */ -#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset)) -#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data) -#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits))) -#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits))) - -#define my_cpu_to_le32(x) my_le32_to_cpu((x)) - -/* Static function declarations */ -static int mv64460_eth_real_open (struct eth_device *eth); -static int mv64460_eth_real_stop (struct eth_device *eth); -static struct net_device_stats *mv64460_eth_get_stats (struct eth_device - *dev); -static void eth_port_init_mac_tables (ETH_PORT eth_port_num); -static void mv64460_eth_update_stat (struct eth_device *dev); -bool db64460_eth_start (struct eth_device *eth); -unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, - unsigned int mib_offset); -int mv64460_eth_receive (struct eth_device *dev); - -int mv64460_eth_xmit (struct eth_device *, volatile void *packet, int length); - -int mv_miiphy_read(const char *devname, unsigned char phy_addr, - unsigned char phy_reg, unsigned short *value); -int mv_miiphy_write(const char *devname, unsigned char phy_addr, - unsigned char phy_reg, unsigned short value); - -int phy_setup_aneg (char *devname, unsigned char addr); - -#ifndef UPDATE_STATS_BY_SOFTWARE -static void mv64460_eth_print_stat (struct eth_device *dev); -#endif - -extern unsigned int INTERNAL_REG_BASE_ADDR; - -unsigned long my_le32_to_cpu (unsigned long x) -{ - return (((x & 0x000000ffU) << 24) | - ((x & 0x0000ff00U) << 8) | - ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24)); -} - -/************************************************* - *Helper functions - used inside the driver only * - *************************************************/ -#ifdef DEBUG_MV_ETH -void print_globals (struct eth_device *dev) -{ - printf ("Ethernet PRINT_Globals-Debug function\n"); - printf ("Base Address for ETH_PORT_INFO: %08x\n", - (unsigned int) dev->priv); - printf ("Base Address for mv64460_eth_priv: %08x\n", - (unsigned int) &(((ETH_PORT_INFO *) dev->priv)-> - port_private)); - - printf ("GT Internal Base Address: %08x\n", - INTERNAL_REG_BASE_ADDR); - printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", - (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64460_TX_QUEUE_SIZE); - printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", - (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64460_RX_QUEUE_SIZE); - printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n", - (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> - p_rx_buffer_base[0], - (MV64460_RX_QUEUE_SIZE * MV64460_RX_BUFFER_SIZE) + 32); - printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n", - (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> - p_tx_buffer_base[0], - (MV64460_TX_QUEUE_SIZE * MV64460_TX_BUFFER_SIZE) + 32); -} -#endif - -/********************************************************************** - * mv64460_eth_print_phy_status - * - * Prints gigabit ethenret phy status - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ -void mv64460_eth_print_phy_status (struct eth_device *dev) -{ - struct mv64460_eth_priv *port_private; - unsigned int port_num; - ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv; - unsigned int port_status, phy_reg_data; - - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Check Link status on phy */ - eth_port_read_smi_reg (port_num, 1, &phy_reg_data); - if (!(phy_reg_data & 0x20)) { - printf ("Ethernet port changed link status to DOWN\n"); - } else { - port_status = - MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num)); - printf ("Ethernet status port %d: Link up", port_num); - printf (", %s", - (port_status & BIT2) ? "Full Duplex" : "Half Duplex"); - if (port_status & BIT4) - printf (", Speed 1 Gbps"); - else - printf (", %s", - (port_status & BIT5) ? "Speed 100 Mbps" : - "Speed 10 Mbps"); - printf ("\n"); - } -} - -/********************************************************************** - * u-boot entry functions for mv64460_eth - * - **********************************************************************/ -int db64460_eth_probe (struct eth_device *dev) -{ - return ((int) db64460_eth_start (dev)); -} - -int db64460_eth_poll (struct eth_device *dev) -{ - return mv64460_eth_receive (dev); -} - -int db64460_eth_transmit(struct eth_device *dev, void *packet, int length) -{ - mv64460_eth_xmit (dev, packet, length); - return 0; -} - -void db64460_eth_disable (struct eth_device *dev) -{ - mv64460_eth_stop (dev); -} - -#define DFCDL(write,read) ((write << 6) | read) -unsigned int ethDfcdls[] = { - DFCDL(0,0), DFCDL(1,1), DFCDL(2,2), DFCDL(3,3), - DFCDL(4,4), DFCDL(5,5), DFCDL(6,6), DFCDL(7,7), - DFCDL(8,8), DFCDL(9,9), DFCDL(10,10), DFCDL(11,11), - DFCDL(12,12), DFCDL(13,13), DFCDL(14,14), DFCDL(15,15), - DFCDL(16,16), DFCDL(17,17), DFCDL(18,18), DFCDL(19,19), - DFCDL(20,20), DFCDL(21,21), DFCDL(22,22), DFCDL(23,23), - DFCDL(24,24), DFCDL(25,25), DFCDL(26,26), DFCDL(27,27), - DFCDL(28,28), DFCDL(29,29), DFCDL(30,30), DFCDL(31,31), - DFCDL(32,32), DFCDL(33,33), DFCDL(34,34), DFCDL(35,35), - DFCDL(36,36), DFCDL(37,37), DFCDL(38,38), DFCDL(39,39), - DFCDL(40,40), DFCDL(41,41), DFCDL(42,42), DFCDL(43,43), - DFCDL(44,44), DFCDL(45,45), DFCDL(46,46), DFCDL(47,47), - DFCDL(48,48), DFCDL(49,49), DFCDL(50,50), DFCDL(51,51), - DFCDL(52,52), DFCDL(53,53), DFCDL(54,54), DFCDL(55,55), - DFCDL(56,56), DFCDL(57,57), DFCDL(58,58), DFCDL(59,59), - DFCDL(60,60), DFCDL(61,61), DFCDL(62,62), DFCDL(63,63), -}; - -void mv_eth_phy_init (void) -{ - int i; - - MV_REG_WRITE (ETH_PHY_DFCDL_ADDR_REG, 0); - - for (i = 0; i < 64; i++) { - MV_REG_WRITE (ETH_PHY_DFCDL_DATA0_REG, ethDfcdls[i]); - } - - MV_REG_WRITE (ETH_PHY_DFCDL_CONFIG0_REG, 0x300000); -} - -void mv6446x_eth_initialize (bd_t * bis) -{ - struct eth_device *dev; - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - int devnum, x, temp; - char *s, *e, buf[64]; - - /* P3M750 only - * Set RGMII clock drives strength - */ - temp = MV_REG_READ(0x20A0); - temp |= 0x04000080; - MV_REG_WRITE(0x20A0, temp); - - mv_eth_phy_init(); - - for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) { - dev = calloc (sizeof (*dev), 1); - if (!dev) { - printf ("%s: mv_enet%d allocation failure, %s\n", - __FUNCTION__, devnum, "eth_device structure"); - return; - } - - /* must be less than sizeof(dev->name) */ - sprintf (dev->name, "mv_enet%d", devnum); - -#ifdef DEBUG - printf ("Initializing %s\n", dev->name); -#endif - - /* Extract the MAC address from the environment */ - switch (devnum) { - case 0: - s = "ethaddr"; - break; - case 1: - s = "eth1addr"; - break; - case 2: - s = "eth2addr"; - break; - default: /* this should never happen */ - printf ("%s: Invalid device number %d\n", - __FUNCTION__, devnum); - return; - } - - temp = getenv_f(s, buf, sizeof (buf)); - s = (temp > 0) ? buf : NULL; - -#ifdef DEBUG - printf ("Setting MAC %d to %s\n", devnum, s); -#endif - for (x = 0; x < 6; ++x) { - dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - /* ronen - set the MAC addr in the HW */ - eth_port_uc_addr_set (devnum, dev->enetaddr, 0); - - dev->init = (void *) db64460_eth_probe; - dev->halt = (void *) ethernet_phy_reset; - dev->send = (void *) db64460_eth_transmit; - dev->recv = (void *) db64460_eth_poll; - - ethernet_private = calloc (sizeof (*ethernet_private), 1); - dev->priv = (void *)ethernet_private; - if (!ethernet_private) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Private Device Structure"); - free (dev); - return; - } - /* start with an zeroed ETH_PORT_INFO */ - memset (ethernet_private, 0, sizeof (ETH_PORT_INFO)); - memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); - - /* set pointer to memory for stats data structure etc... */ - port_private = calloc (sizeof (*ethernet_private), 1); - ethernet_private->port_private = (void *)port_private; - if (!port_private) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Port Private Device Structure"); - - free (ethernet_private); - free (dev); - return; - } - - port_private->stats = - calloc (sizeof (struct net_device_stats), 1); - if (!port_private->stats) { - printf ("%s: %s allocation failure, %s\n", - __FUNCTION__, dev->name, - "Net stat Structure"); - - free (port_private); - free (ethernet_private); - free (dev); - return; - } - memset (ethernet_private->port_private, 0, - sizeof (struct mv64460_eth_priv)); - switch (devnum) { - case 0: - ethernet_private->port_num = ETH_0; - break; - case 1: - ethernet_private->port_num = ETH_1; - break; - case 2: - ethernet_private->port_num = ETH_2; - break; - default: - printf ("Invalid device number %d\n", devnum); - break; - }; - - port_private->port_num = devnum; - /* - * Read MIB counter on the GT in order to reset them, - * then zero all the stats fields in memory - */ - mv64460_eth_update_stat (dev); - memset (port_private->stats, 0, - sizeof (struct net_device_stats)); - /* Extract the MAC address from the environment */ - switch (devnum) { - case 0: - s = "ethaddr"; - break; - case 1: - s = "eth1addr"; - break; - case 2: - s = "eth2addr"; - break; - default: /* this should never happen */ - printf ("%s: Invalid device number %d\n", - __FUNCTION__, devnum); - return; - } - - temp = getenv_f(s, buf, sizeof (buf)); - s = (temp > 0) ? buf : NULL; - -#ifdef DEBUG - printf ("Setting MAC %d to %s\n", devnum, s); -#endif - for (x = 0; x < 6; ++x) { - dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - - DP (printf ("Allocating descriptor and buffer rings\n")); - - ethernet_private->p_rx_desc_area_base[0] = - (ETH_RX_DESC *) memalign (16, - RX_DESC_ALIGNED_SIZE * - MV64460_RX_QUEUE_SIZE + 1); - ethernet_private->p_tx_desc_area_base[0] = - (ETH_TX_DESC *) memalign (16, - TX_DESC_ALIGNED_SIZE * - MV64460_TX_QUEUE_SIZE + 1); - - ethernet_private->p_rx_buffer_base[0] = - (char *) memalign (16, - MV64460_RX_QUEUE_SIZE * - MV64460_TX_BUFFER_SIZE + 1); - ethernet_private->p_tx_buffer_base[0] = - (char *) memalign (16, - MV64460_RX_QUEUE_SIZE * - MV64460_TX_BUFFER_SIZE + 1); - -#ifdef DEBUG_MV_ETH - /* DEBUG OUTPUT prints adresses of globals */ - print_globals (dev); -#endif - eth_register (dev); - - miiphy_register(dev->name, mv_miiphy_read, mv_miiphy_write); - } - DP (printf ("%s: exit\n", __FUNCTION__)); - -} - -/********************************************************************** - * mv64460_eth_open - * - * This function is called when openning the network device. The function - * should initialize all the hardware, initialize cyclic Rx/Tx - * descriptors chain and buffers and allocate an IRQ to the network - * device. - * - * Input : a pointer to the network device structure - * / / ronen - changed the output to match net/eth.c needs - * Output : nonzero of success , zero if fails. - * under construction - **********************************************************************/ - -int mv64460_eth_open (struct eth_device *dev) -{ - return (mv64460_eth_real_open (dev)); -} - -/* Helper function for mv64460_eth_open */ -static int mv64460_eth_real_open (struct eth_device *dev) -{ - - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - unsigned int port_num; - ushort reg_short; - int speed; - int duplex; - int i; - int reg; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - /* ronen - when we update the MAC env params we only update dev->enetaddr - see ./net/eth.c eth_set_enetaddr() */ - memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); - - port_private = (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Stop RX Queues */ - MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), 0x0000ff00); - - /* Clear the ethernet port interrupts */ - MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0); - MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); - - /* Unmask RX buffer and TX end interrupt */ - MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num), - INT_CAUSE_UNMASK_ALL); - - /* Unmask phy and link status changes interrupts */ - MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), - INT_CAUSE_UNMASK_ALL_EXT); - - /* Set phy address of the port */ - ethernet_private->port_phy_addr = 0x1 + (port_num << 1); - reg = ethernet_private->port_phy_addr; - - /* Activate the DMA channels etc */ - eth_port_init (ethernet_private); - - /* "Allocate" setup TX rings */ - - for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) { - unsigned int size; - - port_private->tx_ring_size[queue] = MV64460_TX_QUEUE_SIZE; - size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */ - ethernet_private->tx_desc_area_size[queue] = size; - - /* first clear desc area completely */ - memset ((void *) ethernet_private->p_tx_desc_area_base[queue], - 0, ethernet_private->tx_desc_area_size[queue]); - - /* initialize tx desc ring with low level driver */ - if (ether_init_tx_desc_ring - (ethernet_private, ETH_Q0, - port_private->tx_ring_size[queue], - MV64460_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , - (unsigned int) ethernet_private-> - p_tx_desc_area_base[queue], - (unsigned int) ethernet_private-> - p_tx_buffer_base[queue]) == false) - printf ("### Error initializing TX Ring\n"); - } - - /* "Allocate" setup RX rings */ - for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) { - unsigned int size; - - /* Meantime RX Ring are fixed - but must be configurable by user */ - port_private->rx_ring_size[queue] = MV64460_RX_QUEUE_SIZE; - size = (port_private->rx_ring_size[queue] * - RX_DESC_ALIGNED_SIZE); - ethernet_private->rx_desc_area_size[queue] = size; - - /* first clear desc area completely */ - memset ((void *) ethernet_private->p_rx_desc_area_base[queue], - 0, ethernet_private->rx_desc_area_size[queue]); - if ((ether_init_rx_desc_ring - (ethernet_private, ETH_Q0, - port_private->rx_ring_size[queue], - MV64460_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , - (unsigned int) ethernet_private-> - p_rx_desc_area_base[queue], - (unsigned int) ethernet_private-> - p_rx_buffer_base[queue])) == false) - printf ("### Error initializing RX Ring\n"); - } - - eth_port_start (ethernet_private); - - /* Set maximum receive buffer to 9700 bytes */ - MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num), - (0x5 << 17) | - (MV_REG_READ - (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num)) - & 0xfff1ffff)); - - /* - * Set ethernet MTU for leaky bucket mechanism to 0 - this will - * disable the leaky bucket mechanism . - */ - - MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0); - MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num)); - -#if defined(CONFIG_PHY_RESET) - /* - * Reset the phy, only if its the first time through - * otherwise, just check the speeds & feeds - */ - if (port_private->first_init == 0) { - port_private->first_init = 1; - ethernet_phy_reset (port_num); - - /* Start/Restart autonegotiation */ - phy_setup_aneg (dev->name, reg); - udelay (1000); - } -#endif /* defined(CONFIG_PHY_RESET) */ - - miiphy_read (dev->name, reg, MII_BMSR, ®_short); - - /* - * Wait if PHY is capable of autonegotiation and autonegotiation is not complete - */ - if ((reg_short & BMSR_ANEGCAPABLE) - && !(reg_short & BMSR_ANEGCOMPLETE)) { - puts ("Waiting for PHY auto negotiation to complete"); - i = 0; - while (!(reg_short & BMSR_ANEGCOMPLETE)) { - /* - * Timeout reached ? - */ - if (i > PHY_AUTONEGOTIATE_TIMEOUT) { - puts (" TIMEOUT !\n"); - break; - } - - if ((i++ % 1000) == 0) { - putc ('.'); - } - udelay (1000); /* 1 ms */ - miiphy_read (dev->name, reg, MII_BMSR, ®_short); - - } - puts (" done\n"); - udelay (500000); /* another 500 ms (results in faster booting) */ - } - - speed = miiphy_speed (dev->name, reg); - duplex = miiphy_duplex (dev->name, reg); - - printf ("ENET Speed is %d Mbps - %s duplex connection\n", - (int) speed, (duplex == HALF) ? "HALF" : "FULL"); - - port_private->eth_running = MAGIC_ETH_RUNNING; - return 1; -} - -static int mv64460_eth_free_tx_rings (struct eth_device *dev) -{ - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - unsigned int port_num; - volatile ETH_TX_DESC *p_tx_curr_desc; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Stop Tx Queues */ - MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Free TX rings */ - DP (printf ("Clearing previously allocated TX queues... ")); - for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) { - /* Free on TX rings */ - for (p_tx_curr_desc = - ethernet_private->p_tx_desc_area_base[queue]; - ((unsigned int) p_tx_curr_desc <= (unsigned int) - ethernet_private->p_tx_desc_area_base[queue] + - ethernet_private->tx_desc_area_size[queue]); - p_tx_curr_desc = - (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc + - TX_DESC_ALIGNED_SIZE)) { - /* this is inside for loop */ - if (p_tx_curr_desc->return_info != 0) { - p_tx_curr_desc->return_info = 0; - DP (printf ("freed\n")); - } - } - DP (printf ("Done\n")); - } - return 0; -} - -static int mv64460_eth_free_rx_rings (struct eth_device *dev) -{ - unsigned int queue; - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - unsigned int port_num; - volatile ETH_RX_DESC *p_rx_curr_desc; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - /* Stop RX Queues */ - MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), - 0x0000ff00); - - /* Free RX rings */ - DP (printf ("Clearing previously allocated RX queues... ")); - for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) { - /* Free preallocated skb's on RX rings */ - for (p_rx_curr_desc = - ethernet_private->p_rx_desc_area_base[queue]; - (((unsigned int) p_rx_curr_desc < - ((unsigned int) ethernet_private-> - p_rx_desc_area_base[queue] + - ethernet_private->rx_desc_area_size[queue]))); - p_rx_curr_desc = - (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc + - RX_DESC_ALIGNED_SIZE)) { - if (p_rx_curr_desc->return_info != 0) { - p_rx_curr_desc->return_info = 0; - DP (printf ("freed\n")); - } - } - DP (printf ("Done\n")); - } - return 0; -} - -/********************************************************************** - * mv64460_eth_stop - * - * This function is used when closing the network device. - * It updates the hardware, - * release all memory that holds buffers and descriptors and release the IRQ. - * Input : a pointer to the device structure - * Output : zero if success , nonzero if fails - *********************************************************************/ - -int mv64460_eth_stop (struct eth_device *dev) -{ - /* Disable all gigE address decoder */ - MV_REG_WRITE (MV64460_ETH_BASE_ADDR_ENABLE_REG, 0x3f); - DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__)); - mv64460_eth_real_stop (dev); - - return 0; -}; - -/* Helper function for mv64460_eth_stop */ - -static int mv64460_eth_real_stop (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - unsigned int port_num; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - - mv64460_eth_free_tx_rings (dev); - mv64460_eth_free_rx_rings (dev); - - eth_port_reset (ethernet_private->port_num); - /* Disable ethernet port interrupts */ - MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0); - MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); - /* Mask RX buffer and TX end interrupt */ - MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num), 0); - /* Mask phy and link status changes interrupts */ - MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0); - MV_RESET_REG_BITS (MV64460_CPU_INTERRUPT0_MASK_HIGH, - BIT0 << port_num); - /* Print Network statistics */ -#ifndef UPDATE_STATS_BY_SOFTWARE - /* - * Print statistics (only if ethernet is running), - * then zero all the stats fields in memory - */ - if (port_private->eth_running == MAGIC_ETH_RUNNING) { - port_private->eth_running = 0; - mv64460_eth_print_stat (dev); - } - memset (port_private->stats, 0, sizeof (struct net_device_stats)); -#endif - DP (printf ("\nEthernet stopped ... \n")); - return 0; -} - -/********************************************************************** - * mv64460_eth_start_xmit - * - * This function is queues a packet in the Tx descriptor for - * required port. - * - * Input : skb - a pointer to socket buffer - * dev - a pointer to the required port - * - * Output : zero upon success - **********************************************************************/ - -int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr, - int dataSize) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - PKT_INFO pkt_info; - ETH_FUNC_RET_STATUS status; - struct net_device_stats *stats; - ETH_FUNC_RET_STATUS release_result; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - - stats = port_private->stats; - - /* Update packet info data structure */ - pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */ - pkt_info.byte_cnt = dataSize; - pkt_info.buf_ptr = (unsigned int) dataPtr; - pkt_info.return_info = 0; - - status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info); - if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) { - printf ("Error on transmitting packet .."); - if (status == ETH_QUEUE_FULL) - printf ("ETH Queue is full. \n"); - if (status == ETH_QUEUE_LAST_RESOURCE) - printf ("ETH Queue: using last available resource. \n"); - return 1; - } - - /* Update statistics and start of transmittion time */ - stats->tx_bytes += dataSize; - stats->tx_packets++; - - /* Check if packet(s) is(are) transmitted correctly (release everything) */ - do { - release_result = - eth_tx_return_desc (ethernet_private, ETH_Q0, - &pkt_info); - switch (release_result) { - case ETH_OK: - DP (printf ("descriptor released\n")); - if (pkt_info.cmd_sts & BIT0) { - printf ("Error in TX\n"); - stats->tx_errors++; - } - break; - case ETH_RETRY: - DP (printf ("transmission still in process\n")); - break; - - case ETH_ERROR: - printf ("routine can not access Tx desc ring\n"); - break; - - case ETH_END_OF_JOB: - DP (printf ("the routine has nothing to release\n")); - break; - default: /* should not happen */ - break; - } - } while (release_result == ETH_OK); - - return 0; /* success */ -} - -/********************************************************************** - * mv64460_eth_receive - * - * This function is forward packets that are received from the port's - * queues toward kernel core or FastRoute them to another interface. - * - * Input : dev - a pointer to the required interface - * max - maximum number to receive (0 means unlimted) - * - * Output : number of served packets - **********************************************************************/ - -int mv64460_eth_receive (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - PKT_INFO pkt_info; - struct net_device_stats *stats; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = (struct mv64460_eth_priv *) ethernet_private->port_private; - stats = port_private->stats; - - while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) == ETH_OK)) { -#ifdef DEBUG_MV_ETH - if (pkt_info.byte_cnt != 0) { - printf ("%s: Received %d byte Packet @ 0x%x\n", - __FUNCTION__, pkt_info.byte_cnt, - pkt_info.buf_ptr); - if(pkt_info.buf_ptr != 0){ - for(i=0; i < pkt_info.byte_cnt; i++){ - if((i % 4) == 0){ - printf("\n0x"); - } - printf("%02x", ((char*)pkt_info.buf_ptr)[i]); - } - printf("\n"); - } - } -#endif - /* Update statistics. Note byte count includes 4 byte CRC count */ - stats->rx_packets++; - stats->rx_bytes += pkt_info.byte_cnt; - - /* - * In case received a packet without first / last bits on OR the error - * summary bit is on, the packets needs to be dropeed. - */ - if (((pkt_info. - cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != - (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) - || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) { - stats->rx_dropped++; - - printf ("Received packet spread on multiple descriptors\n"); - - /* Is this caused by an error ? */ - if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) { - stats->rx_errors++; - } - - /* free these descriptors again without forwarding them to the higher layers */ - pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ - pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ - - if (eth_rx_return_buff - (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { - printf ("Error while returning the RX Desc to Ring\n"); - } else { - DP (printf ("RX Desc returned to Ring\n")); - } - /* /free these descriptors again */ - } else { - -/* !!! call higher layer processing */ -#ifdef DEBUG_MV_ETH - printf ("\nNow send it to upper layer protocols (NetReceive) ...\n"); -#endif - /* let the upper layer handle the packet */ - NetReceive ((uchar *) pkt_info.buf_ptr, - (int) pkt_info.byte_cnt); - -/* **************************************************************** */ -/* free descriptor */ - pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ - pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ - DP (printf ("RX: pkt_info.buf_ptr = %x\n", pkt_info.buf_ptr)); - if (eth_rx_return_buff - (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { - printf ("Error while returning the RX Desc to Ring\n"); - } else { - DP (printf ("RX: Desc returned to Ring\n")); - } - -/* **************************************************************** */ - - } - } - mv64460_eth_get_stats (dev); /* update statistics */ - return 1; -} - -/********************************************************************** - * mv64460_eth_get_stats - * - * Returns a pointer to the interface statistics. - * - * Input : dev - a pointer to the required interface - * - * Output : a pointer to the interface's statistics - **********************************************************************/ - -static struct net_device_stats *mv64460_eth_get_stats (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - - mv64460_eth_update_stat (dev); - - return port_private->stats; -} - -/********************************************************************** - * mv64460_eth_update_stat - * - * Update the statistics structure in the private data structure - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64460_eth_update_stat (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - struct net_device_stats *stats; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - stats = port_private->stats; - - /* These are false updates */ - stats->rx_packets += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_FRAMES_RECEIVED); - stats->tx_packets += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_FRAMES_SENT); - stats->rx_bytes += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_RECEIVED_LOW); - /* - * Ideally this should be as follows - - * - * stats->rx_bytes += stats->rx_bytes + - * ((unsigned long) ethReadMibCounter (ethernet_private->port_num , - * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32); - * - * But the unsigned long in PowerPC and MIPS are 32bit. So the next read - * is just a dummy read for proper work of the GigE port - */ - (void)eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH); - stats->tx_bytes += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_SENT_LOW); - (void)eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_GOOD_OCTETS_SENT_HIGH); - stats->rx_errors += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_MAC_RECEIVE_ERROR); - - /* Rx dropped is for received packet with CRC error */ - stats->rx_dropped += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_BAD_CRC_EVENT); - stats->multicast += (unsigned long) - eth_read_mib_counter (ethernet_private->port_num, - ETH_MIB_MULTICAST_FRAMES_RECEIVED); - stats->collisions += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_COLLISION) + - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_LATE_COLLISION); - /* detailed rx errors */ - stats->rx_length_errors += - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_UNDERSIZE_RECEIVED) - + - (unsigned long) eth_read_mib_counter (ethernet_private-> - port_num, - ETH_MIB_OVERSIZE_RECEIVED); - /* detailed tx errors */ -} - -#ifndef UPDATE_STATS_BY_SOFTWARE -/********************************************************************** - * mv64460_eth_print_stat - * - * Update the statistics structure in the private data structure - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - **********************************************************************/ - -static void mv64460_eth_print_stat (struct eth_device *dev) -{ - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - struct net_device_stats *stats; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - stats = port_private->stats; - - /* These are false updates */ - printf ("\n### Network statistics: ###\n"); - printf ("--------------------------\n"); - printf (" Packets received: %ld\n", stats->rx_packets); - printf (" Packets send: %ld\n", stats->tx_packets); - printf (" Received bytes: %ld\n", stats->rx_bytes); - printf (" Send bytes: %ld\n", stats->tx_bytes); - if (stats->rx_errors != 0) - printf (" Rx Errors: %ld\n", - stats->rx_errors); - if (stats->rx_dropped != 0) - printf (" Rx dropped (CRC Errors): %ld\n", - stats->rx_dropped); - if (stats->multicast != 0) - printf (" Rx mulicast frames: %ld\n", - stats->multicast); - if (stats->collisions != 0) - printf (" No. of collisions: %ld\n", - stats->collisions); - if (stats->rx_length_errors != 0) - printf (" Rx length errors: %ld\n", - stats->rx_length_errors); -} -#endif - -/************************************************************************** - *network_start - Network Kick Off Routine UBoot - *Inputs : - *Outputs : - **************************************************************************/ - -bool db64460_eth_start (struct eth_device *dev) -{ - return (mv64460_eth_open (dev)); /* calls real open */ -} - -/************************************************************************* -************************************************************************** -************************************************************************** -* The second part is the low level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ -/* - * based on Linux code - * arch/powerpc/galileo/EVB64460/mv64460_eth.c - Driver for MV64460X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - - * SPDX-License-Identifier: GPL-2.0+ - */ - -/******************************************************************************** - * Marvell's Gigabit Ethernet controller low level driver - * - * DESCRIPTION: - * This file introduce low level API to Marvell's Gigabit Ethernet - * controller. This Gigabit Ethernet Controller driver API controls - * 1) Operations (i.e. port init, start, reset etc'). - * 2) Data flow (i.e. port send, receive etc'). - * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO - * struct. - * This struct includes user configuration information as well as - * driver internal data needed for its operations. - * - * Supported Features: - * - This low level driver is OS independent. Allocating memory for - * the descriptor rings and buffers are not within the scope of - * this driver. - * - The user is free from Rx/Tx queue managing. - * - This low level driver introduce functionality API that enable - * the to operate Marvell's Gigabit Ethernet Controller in a - * convenient way. - * - Simple Gigabit Ethernet port operation API. - * - Simple Gigabit Ethernet port data flow API. - * - Data flow and operation API support per queue functionality. - * - Support cached descriptors for better performance. - * - Enable access to all four DRAM banks and internal SRAM memory - * spaces. - * - PHY access and control API. - * - Port control register configuration API. - * - Full control over Unicast and Multicast MAC configurations. - * - * Operation flow: - * - * Initialization phase - * This phase complete the initialization of the ETH_PORT_INFO - * struct. - * User information regarding port configuration has to be set - * prior to calling the port initialization routine. For example, - * the user has to assign the port_phy_addr field which is board - * depended parameter. - * In this phase any port Tx/Rx activity is halted, MIB counters - * are cleared, PHY address is set according to user parameter and - * access to DRAM and internal SRAM memory spaces. - * - * Driver ring initialization - * Allocating memory for the descriptor rings and buffers is not - * within the scope of this driver. Thus, the user is required to - * allocate memory for the descriptors ring and buffers. Those - * memory parameters are used by the Rx and Tx ring initialization - * routines in order to curve the descriptor linked list in a form - * of a ring. - * Note: Pay special attention to alignment issues when using - * cached descriptors/buffers. In this phase the driver store - * information in the ETH_PORT_INFO struct regarding each queue - * ring. - * - * Driver start - * This phase prepares the Ethernet port for Rx and Tx activity. - * It uses the information stored in the ETH_PORT_INFO struct to - * initialize the various port registers. - * - * Data flow: - * All packet references to/from the driver are done using PKT_INFO - * struct. - * This struct is a unified struct used with Rx and Tx operations. - * This way the user is not required to be familiar with neither - * Tx nor Rx descriptors structures. - * The driver's descriptors rings are management by indexes. - * Those indexes controls the ring resources and used to indicate - * a SW resource error: - * 'current' - * This index points to the current available resource for use. For - * example in Rx process this index will point to the descriptor - * that will be passed to the user upon calling the receive routine. - * In Tx process, this index will point to the descriptor - * that will be assigned with the user packet info and transmitted. - * 'used' - * This index points to the descriptor that need to restore its - * resources. For example in Rx process, using the Rx buffer return - * API will attach the buffer returned in packet info to the - * descriptor pointed by 'used'. In Tx process, using the Tx - * descriptor return will merely return the user packet info with - * the command status of the transmitted buffer pointed by the - * 'used' index. Nevertheless, it is essential to use this routine - * to update the 'used' index. - * 'first' - * This index supports Tx Scatter-Gather. It points to the first - * descriptor of a packet assembled of multiple buffers. For example - * when in middle of Such packet we have a Tx resource error the - * 'curr' index get the value of 'first' to indicate that the ring - * returned to its state before trying to transmit this packet. - * - * Receive operation: - * The eth_port_receive API set the packet information struct, - * passed by the caller, with received information from the - * 'current' SDMA descriptor. - * It is the user responsibility to return this resource back - * to the Rx descriptor ring to enable the reuse of this source. - * Return Rx resource is done using the eth_rx_return_buff API. - * - * Transmit operation: - * The eth_port_send API supports Scatter-Gather which enables to - * send a packet spanned over multiple buffers. This means that - * for each packet info structure given by the user and put into - * the Tx descriptors ring, will be transmitted only if the 'LAST' - * bit will be set in the packet info command status field. This - * API also consider restriction regarding buffer alignments and - * sizes. - * The user must return a Tx resource after ensuring the buffer - * has been transmitted to enable the Tx ring indexes to update. - * - * BOARD LAYOUT - * This device is on-board. No jumper diagram is necessary. - * - * EXTERNAL INTERFACE - * - * Prior to calling the initialization routine eth_port_init() the user - * must set the following fields under ETH_PORT_INFO struct: - * port_num User Ethernet port number. - * port_phy_addr User PHY address of Ethernet port. - * port_mac_addr[6] User defined port MAC address. - * port_config User port configuration value. - * port_config_extend User port config extend value. - * port_sdma_config User port SDMA config value. - * port_serial_control User port serial control value. - * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr. - * *port_private User scratch pad for user specific data structures. - * - * This driver introduce a set of default values: - * PORT_CONFIG_VALUE Default port configuration value - * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value - * PORT_SDMA_CONFIG_VALUE Default sdma control value - * PORT_SERIAL_CONTROL_VALUE Default port serial control value - * - * This driver data flow is done using the PKT_INFO struct which is - * a unified struct for Rx and Tx operations: - * byte_cnt Tx/Rx descriptor buffer byte count. - * l4i_chk CPU provided TCP Checksum. For Tx operation only. - * cmd_sts Tx/Rx descriptor command status. - * buf_ptr Tx/Rx descriptor buffer pointer. - * return_info Tx/Rx user resource return information. - * - * - * EXTERNAL SUPPORT REQUIREMENTS - * - * This driver requires the following external support: - * - * D_CACHE_FLUSH_LINE (address, address offset) - * - * This macro applies assembly code to flush and invalidate cache - * line. - * address - address base. - * address offset - address offset - * - * - * CPU_PIPE_FLUSH - * - * This macro applies assembly code to flush the CPU pipeline. - * - *******************************************************************************/ -/* includes */ - -/* defines */ -/* SDMA command macros */ -#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \ - MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue)) - -#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \ - MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\ - (1 << (8 + tx_queue))) - -#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \ -MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue)) - -#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \ -MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue))) - -#define CURR_RFD_GET(p_curr_desc, queue) \ - ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue]) - -#define CURR_RFD_SET(p_curr_desc, queue) \ - (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc)) - -#define USED_RFD_GET(p_used_desc, queue) \ - ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue]) - -#define USED_RFD_SET(p_used_desc, queue)\ -(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc)) - - -#define CURR_TFD_GET(p_curr_desc, queue) \ - ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue]) - -#define CURR_TFD_SET(p_curr_desc, queue) \ - (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc)) - -#define USED_TFD_GET(p_used_desc, queue) \ - ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue]) - -#define USED_TFD_SET(p_used_desc, queue) \ - (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc)) - -#define FIRST_TFD_GET(p_first_desc, queue) \ - ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue]) - -#define FIRST_TFD_SET(p_first_desc, queue) \ - (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc)) - - -/* Macros that save access to desc in order to find next desc pointer */ -#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) - -#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) - -#define LINK_UP_TIMEOUT 100000 -#define PHY_BUSY_TIMEOUT 10000000 - -/* locals */ - -/* PHY routines */ -static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr); -static int ethernet_phy_get (ETH_PORT eth_port_num); - -/* Ethernet Port routines */ -static void eth_set_access_control (ETH_PORT eth_port_num, - ETH_WIN_PARAM * param); -static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble, - ETH_QUEUE queue, int option); -#if 0 /* FIXME */ -static bool eth_port_smc_addr (ETH_PORT eth_port_num, - unsigned char mc_byte, - ETH_QUEUE queue, int option); -static bool eth_port_omc_addr (ETH_PORT eth_port_num, - unsigned char crc8, - ETH_QUEUE queue, int option); -#endif - -static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, - int byte_count); - -void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl); - - -typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK; -u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank) -{ - u32 result = 0; - u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE); - - if (enable & (1 << bank)) - return 0; - if (bank == BANK0) - result = MV_REG_READ (MV64460_CS_0_BASE_ADDR); - if (bank == BANK1) - result = MV_REG_READ (MV64460_CS_1_BASE_ADDR); - if (bank == BANK2) - result = MV_REG_READ (MV64460_CS_2_BASE_ADDR); - if (bank == BANK3) - result = MV_REG_READ (MV64460_CS_3_BASE_ADDR); - result &= 0x0000ffff; - result = result << 16; - return result; -} - -u32 mv_get_dram_bank_size (MEMORY_BANK bank) -{ - u32 result = 0; - u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE); - - if (enable & (1 << bank)) - return 0; - if (bank == BANK0) - result = MV_REG_READ (MV64460_CS_0_SIZE); - if (bank == BANK1) - result = MV_REG_READ (MV64460_CS_1_SIZE); - if (bank == BANK2) - result = MV_REG_READ (MV64460_CS_2_SIZE); - if (bank == BANK3) - result = MV_REG_READ (MV64460_CS_3_SIZE); - result += 1; - result &= 0x0000ffff; - result = result << 16; - return result; -} - -u32 mv_get_internal_sram_base (void) -{ - u32 result; - - result = MV_REG_READ (MV64460_INTEGRATED_SRAM_BASE_ADDR); - result &= 0x0000ffff; - result = result << 16; - return result; -} - -/******************************************************************************* -* eth_port_init - Initialize the Ethernet port driver -* -* DESCRIPTION: -* This function prepares the ethernet port to start its activity: -* 1) Completes the ethernet port driver struct initialization toward port -* start routine. -* 2) Resets the device to a quiescent state in case of warm reboot. -* 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. -* 4) Clean MAC tables. The reset status of those tables is unknown. -* 5) Set PHY address. -* Note: Call this routine prior to eth_port_start routine and after setting -* user values in the user fields of Ethernet port control struct (i.e. -* port_phy_addr). -* -* INPUT: -* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct -* -* OUTPUT: -* See description. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl) -{ - int queue; - ETH_WIN_PARAM win_param; - - p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE; - p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE; - p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE; - p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE; - - p_eth_port_ctrl->port_rx_queue_command = 0; - p_eth_port_ctrl->port_tx_queue_command = 0; - - /* Zero out SW structs */ - for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { - CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); - USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); - p_eth_port_ctrl->rx_resource_err[queue] = false; - } - - for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { - CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); - p_eth_port_ctrl->tx_resource_err[queue] = false; - } - - eth_port_reset (p_eth_port_ctrl->port_num); - - /* Set access parameters for DRAM bank 0 */ - win_param.win = ETH_WIN0; /* Use Ethernet window 0 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK0); - win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 1 */ - win_param.win = ETH_WIN1; /* Use Ethernet window 1 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK1); - win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 2 */ - win_param.win = ETH_WIN2; /* Use Ethernet window 2 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK2); - win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for DRAM bank 3 */ - win_param.win = ETH_WIN3; /* Use Ethernet window 3 */ - win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ - win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */ -#ifndef CONFIG_NOT_COHERENT_CACHE - win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; -#endif - win_param.high_addr = 0; - /* Get bank base */ - win_param.base_addr = mv_get_dram_bank_base_addr (BANK3); - win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */ - if (win_param.size == 0) - win_param.enable = 0; - else - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - /* Set access parameters for Internal SRAM */ - win_param.win = ETH_WIN4; /* Use Ethernet window 0 */ - win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */ - win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0; - win_param.high_addr = 0; - win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */ - win_param.size = MV64460_INTERNAL_SRAM_SIZE; /* Get bank size */ - win_param.enable = 1; /* Enable the access */ - win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ - - /* Set the access control for address window (EPAPR) READ & WRITE */ - eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); - - eth_port_init_mac_tables (p_eth_port_ctrl->port_num); - - ethernet_phy_set (p_eth_port_ctrl->port_num, - p_eth_port_ctrl->port_phy_addr); - - return; - -} - -/******************************************************************************* -* eth_port_start - Start the Ethernet port activity. -* -* DESCRIPTION: -* This routine prepares the Ethernet port for Rx and Tx activity: -* 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that -* has been initialized a descriptor's ring (using ether_init_tx_desc_ring -* for Tx and ether_init_rx_desc_ring for Rx) -* 2. Initialize and enable the Ethernet configuration port by writing to -* the port's configuration and command registers. -* 3. Initialize and enable the SDMA by writing to the SDMA's -* configuration and command registers. -* After completing these steps, the ethernet port SDMA can starts to -* perform Rx and Tx activities. -* -* Note: Each Rx and Tx queue descriptor's list must be initialized prior -* to calling this function (use ether_init_tx_desc_ring for Tx queues and -* ether_init_rx_desc_ring for Rx queues). -* -* INPUT: -* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct -* -* OUTPUT: -* Ethernet port is ready to receive and transmit. -* -* RETURN: -* false if the port PHY is not up. -* true otherwise. -* -*******************************************************************************/ -static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl) -{ - int queue; - volatile ETH_TX_DESC *p_tx_curr_desc; - volatile ETH_RX_DESC *p_rx_curr_desc; - unsigned int phy_reg_data; - ETH_PORT eth_port_num = p_eth_port_ctrl->port_num; - - /* Assignment of Tx CTRP of given queue */ - for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { - CURR_TFD_GET (p_tx_curr_desc, queue); - MV_REG_WRITE ((MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0 - (eth_port_num) - + (4 * queue)), - ((unsigned int) p_tx_curr_desc)); - - } - - /* Assignment of Rx CRDP of given queue */ - for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { - CURR_RFD_GET (p_rx_curr_desc, queue); - MV_REG_WRITE ((MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0 - (eth_port_num) - + (4 * queue)), - ((unsigned int) p_rx_curr_desc)); - - if (p_rx_curr_desc != NULL) - /* Add the assigned Ethernet address to the port's address table */ - eth_port_uc_addr_set (p_eth_port_ctrl->port_num, - p_eth_port_ctrl->port_mac_addr, - queue); - } - - /* Assign port configuration and command. */ - MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num), - p_eth_port_ctrl->port_config); - - MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), - p_eth_port_ctrl->port_config_extend); - - MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - p_eth_port_ctrl->port_serial_control); - - MV_SET_REG_BITS (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - ETH_SERIAL_PORT_ENABLE); - - /* Assign port SDMA configuration */ - MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num), - p_eth_port_ctrl->port_sdma_config); - - MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT - (eth_port_num), 0x3fffffff); - MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG - (eth_port_num), 0x03fffcff); - /* Turn off the port/queue bandwidth limitation */ - MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0); - - /* Enable port Rx. */ - MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num), - p_eth_port_ctrl->port_rx_queue_command); - - /* Check if link is up */ - eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); - - if (!(phy_reg_data & 0x20)) - return false; - - return true; -} - -/******************************************************************************* -* eth_port_uc_addr_set - This function Set the port Unicast address. -* -* DESCRIPTION: -* This function Set the port Ethernet MAC address. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* char * p_addr Address to be set -* ETH_QUEUE queue Rx queue number for this MAC address. -* -* OUTPUT: -* Set MAC address low and high registers. also calls eth_port_uc_addr() -* To set the unicast table with the proper information. -* -* RETURN: -* N/A. -* -*******************************************************************************/ -static void eth_port_uc_addr_set (ETH_PORT eth_port_num, - unsigned char *p_addr, ETH_QUEUE queue) -{ - unsigned int mac_h; - unsigned int mac_l; - - mac_l = (p_addr[4] << 8) | (p_addr[5]); - mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | - (p_addr[2] << 8) | (p_addr[3] << 0); - - MV_REG_WRITE (MV64460_ETH_MAC_ADDR_LOW (eth_port_num), mac_l); - MV_REG_WRITE (MV64460_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h); - - /* Accept frames of this address */ - eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR); - - return; -} - -/******************************************************************************* -* eth_port_uc_addr - This function Set the port unicast address table -* -* DESCRIPTION: -* This function locates the proper entry in the Unicast table for the -* specified MAC nibble and sets its properties according to function -* parameters. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char uc_nibble Unicast MAC Address last nibble. -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* This function add/removes MAC addresses from the port unicast address -* table. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_uc_addr (ETH_PORT eth_port_num, - unsigned char uc_nibble, - ETH_QUEUE queue, int option) -{ - unsigned int unicast_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the Unicast table entry */ - uc_nibble = (0xf & uc_nibble); - tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */ - reg_offset = uc_nibble % 4; /* Entry offset within the above register */ - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified unicast DA table entry */ - unicast_reg = - MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset)); - - unicast_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset), unicast_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at unicast DA filter table entry */ - unicast_reg = - MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset)); - - unicast_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) - + tbl_offset), unicast_reg); - - break; - - default: - return false; - } - return true; -} - -#if 0 /* FIXME */ -/******************************************************************************* -* eth_port_mc_addr - Multicast address settings. -* -* DESCRIPTION: -* This API controls the MV device MAC multicast support. -* The MV device supports multicast using two tables: -* 1) Special Multicast Table for MAC addresses of the form -* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). -* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -* Table entries in the DA-Filter table. -* In this case, the function calls eth_port_smc_addr() routine to set the -* Special Multicast Table. -* 2) Other Multicast Table for multicast of another type. A CRC-8bit -* is used as an index to the Other Multicast Table entries in the -* DA-Filter table. -* In this case, the function calculates the CRC-8bit value and calls -* eth_port_omc_addr() routine to set the Other Multicast Table. -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char *p_addr Unicast MAC Address. -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if add_address_table_entry( ) failed. -* -*******************************************************************************/ -static void eth_port_mc_addr (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue, int option) -{ - unsigned int mac_h; - unsigned int mac_l; - unsigned char crc_result = 0; - int mac_array[48]; - int crc[8]; - int i; - - if ((p_addr[0] == 0x01) && - (p_addr[1] == 0x00) && - (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) { - - eth_port_smc_addr (eth_port_num, p_addr[5], queue, option); - } else { - /* Calculate CRC-8 out of the given address */ - mac_h = (p_addr[0] << 8) | (p_addr[1]); - mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) | - (p_addr[4] << 8) | (p_addr[5] << 0); - - for (i = 0; i < 32; i++) - mac_array[i] = (mac_l >> i) & 0x1; - for (i = 32; i < 48; i++) - mac_array[i] = (mac_h >> (i - 32)) & 0x1; - - crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ - mac_array[39] ^ mac_array[35] ^ mac_array[34] ^ - mac_array[31] ^ mac_array[30] ^ mac_array[28] ^ - mac_array[23] ^ mac_array[21] ^ mac_array[19] ^ - mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ - mac_array[12] ^ mac_array[8] ^ mac_array[7] ^ - mac_array[6] ^ mac_array[0]; - - crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[41] ^ mac_array[39] ^ - mac_array[36] ^ mac_array[34] ^ mac_array[32] ^ - mac_array[30] ^ mac_array[29] ^ mac_array[28] ^ - mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ - mac_array[21] ^ mac_array[20] ^ mac_array[18] ^ - mac_array[17] ^ mac_array[16] ^ mac_array[15] ^ - mac_array[14] ^ mac_array[13] ^ mac_array[12] ^ - mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ - mac_array[0]; - - crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[42] ^ mac_array[39] ^ - mac_array[37] ^ mac_array[34] ^ mac_array[33] ^ - mac_array[29] ^ mac_array[28] ^ mac_array[25] ^ - mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ - mac_array[15] ^ mac_array[13] ^ mac_array[12] ^ - mac_array[10] ^ mac_array[8] ^ mac_array[6] ^ - mac_array[2] ^ mac_array[1] ^ mac_array[0]; - - crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[43] ^ mac_array[40] ^ mac_array[38] ^ - mac_array[35] ^ mac_array[34] ^ mac_array[30] ^ - mac_array[29] ^ mac_array[26] ^ mac_array[25] ^ - mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ - mac_array[14] ^ mac_array[13] ^ mac_array[11] ^ - mac_array[9] ^ mac_array[7] ^ mac_array[3] ^ - mac_array[2] ^ mac_array[1]; - - crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ - mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ - mac_array[35] ^ mac_array[31] ^ mac_array[30] ^ - mac_array[27] ^ mac_array[26] ^ mac_array[24] ^ - mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ - mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ - mac_array[8] ^ mac_array[4] ^ mac_array[3] ^ - mac_array[2]; - - crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ - mac_array[42] ^ mac_array[40] ^ mac_array[37] ^ - mac_array[36] ^ mac_array[32] ^ mac_array[31] ^ - mac_array[28] ^ mac_array[27] ^ mac_array[25] ^ - mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ - mac_array[15] ^ mac_array[13] ^ mac_array[11] ^ - mac_array[9] ^ mac_array[5] ^ mac_array[4] ^ - mac_array[3]; - - crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ - mac_array[41] ^ mac_array[38] ^ mac_array[37] ^ - mac_array[33] ^ mac_array[32] ^ mac_array[29] ^ - mac_array[28] ^ mac_array[26] ^ mac_array[21] ^ - mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ - mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ - mac_array[6] ^ mac_array[5] ^ mac_array[4]; - - crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ - mac_array[39] ^ mac_array[38] ^ mac_array[34] ^ - mac_array[33] ^ mac_array[30] ^ mac_array[29] ^ - mac_array[27] ^ mac_array[22] ^ mac_array[20] ^ - mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ - mac_array[13] ^ mac_array[11] ^ mac_array[7] ^ - mac_array[6] ^ mac_array[5]; - - for (i = 0; i < 8; i++) - crc_result = crc_result | (crc[i] << i); - - eth_port_omc_addr (eth_port_num, crc_result, queue, option); - } - return; -} - -/******************************************************************************* -* eth_port_smc_addr - Special Multicast address settings. -* -* DESCRIPTION: -* This routine controls the MV device special MAC multicast support. -* The Special Multicast Table for MAC addresses supports MAC of the form -* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). -* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -* Table entries in the DA-Filter table. -* This function set the Special Multicast Table appropriate entry -* according to the argument given. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits). -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_smc_addr (ETH_PORT eth_port_num, - unsigned char mc_byte, - ETH_QUEUE queue, int option) -{ - unsigned int smc_table_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the SMC table entry */ - tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */ - reg_offset = mc_byte % 4; /* Entry offset within the above register */ - queue &= 0x7; - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified Special DA table entry */ - smc_table_reg = - MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - smc_table_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at specified Special DA table entry */ - smc_table_reg = - MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - smc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); - break; - - default: - return false; - } - return true; -} - -/******************************************************************************* -* eth_port_omc_addr - Multicast address settings. -* -* DESCRIPTION: -* This routine controls the MV device Other MAC multicast support. -* The Other Multicast Table is used for multicast of another type. -* A CRC-8bit is used as an index to the Other Multicast Table entries -* in the DA-Filter table. -* The function gets the CRC-8bit value from the calling routine and -* set the Other Multicast Table appropriate entry according to the -* CRC-8 argument given. -* -* INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. -* -* OUTPUT: -* See description. -* -* RETURN: -* true is output succeeded. -* false if option parameter is invalid. -* -*******************************************************************************/ -static bool eth_port_omc_addr (ETH_PORT eth_port_num, - unsigned char crc8, - ETH_QUEUE queue, int option) -{ - unsigned int omc_table_reg; - unsigned int tbl_offset; - unsigned int reg_offset; - - /* Locate the OMC table entry */ - tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ - reg_offset = crc8 % 4; /* Entry offset within the above register */ - queue &= 0x7; - - switch (option) { - case REJECT_MAC_ADDR: - /* Clear accepts frame bit at specified Other DA table entry */ - omc_table_reg = - MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - omc_table_reg &= (0x0E << (8 * reg_offset)); - - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); - break; - - case ACCEPT_MAC_ADDR: - /* Set accepts frame bit at specified Other DA table entry */ - omc_table_reg = - MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); - omc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); - - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); - break; - - default: - return false; - } - return true; -} -#endif - -/******************************************************************************* -* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables -* -* DESCRIPTION: -* Go through all the DA filter tables (Unicast, Special Multicast & Other -* Multicast) and set each entry to 0. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* Multicast and Unicast packets are rejected. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void eth_port_init_mac_tables (ETH_PORT eth_port_num) -{ - int table_index; - - /* Clear DA filter unicast table (Ex_dFUT) */ - for (table_index = 0; table_index <= 0xC; table_index += 4) - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE - (eth_port_num) + table_index), 0); - - for (table_index = 0; table_index <= 0xFC; table_index += 4) { - /* Clear DA filter special multicast table (Ex_dFSMT) */ - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); - /* Clear DA filter other multicast table (Ex_dFOMT) */ - MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); - } -} - -/******************************************************************************* -* eth_clear_mib_counters - Clear all MIB counters -* -* DESCRIPTION: -* This function clears all MIB counters of a specific ethernet port. -* A read from the MIB counter will reset the counter. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* After reading all MIB counters, the counters resets. -* -* RETURN: -* MIB counter value. -* -*******************************************************************************/ -static void eth_clear_mib_counters (ETH_PORT eth_port_num) -{ - int i; - - /* Perform dummy reads from MIB counters */ - for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; - i += 4) { - (void)MV_REG_READ ((MV64460_ETH_MIB_COUNTERS_BASE - (eth_port_num) + i)); - } - - return; -} - -/******************************************************************************* -* eth_read_mib_counter - Read a MIB counter -* -* DESCRIPTION: -* This function reads a MIB counter of a specific ethernet port. -* NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the -* following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH -* register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and -* ETH_MIB_GOOD_OCTETS_SENT_HIGH -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros). -* -* OUTPUT: -* After reading the MIB counter, the counter resets. -* -* RETURN: -* MIB counter value. -* -*******************************************************************************/ -unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, - unsigned int mib_offset) -{ - return (MV_REG_READ (MV64460_ETH_MIB_COUNTERS_BASE (eth_port_num) - + mib_offset)); -} - -/******************************************************************************* -* ethernet_phy_set - Set the ethernet port PHY address. -* -* DESCRIPTION: -* This routine set the ethernet port PHY address according to given -* parameter. -* -* INPUT: -* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. -* -* OUTPUT: -* Set PHY Address Register with given PHY address parameter. -* -* RETURN: -* None. -* -*******************************************************************************/ -static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr) -{ - unsigned int reg_data; - - reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG); - - reg_data &= ~(0x1F << (5 * eth_port_num)); - reg_data |= (phy_addr << (5 * eth_port_num)); - - MV_REG_WRITE (MV64460_ETH_PHY_ADDR_REG, reg_data); - - return; -} - -/******************************************************************************* - * ethernet_phy_get - Get the ethernet port PHY address. - * - * DESCRIPTION: - * This routine returns the given ethernet port PHY address. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * None. - * - * RETURN: - * PHY address. - * - *******************************************************************************/ -static int ethernet_phy_get (ETH_PORT eth_port_num) -{ - unsigned int reg_data; - - reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG); - - return ((reg_data >> (5 * eth_port_num)) & 0x1f); -} - -/***********************************************************/ -/* (Re)start autonegotiation */ -/***********************************************************/ -int phy_setup_aneg (char *devname, unsigned char addr) -{ - unsigned short ctl, adv; - - /* Setup standard advertise */ - miiphy_read (devname, addr, MII_ADVERTISE, &adv); - adv |= (LPA_LPACK | LPA_RFAULT | LPA_100BASE4 | - LPA_100FULL | LPA_100HALF | LPA_10FULL | - LPA_10HALF); - miiphy_write (devname, addr, MII_ADVERTISE, adv); - - miiphy_read (devname, addr, MII_CTRL1000, &adv); - adv |= (0x0300); - miiphy_write (devname, addr, MII_CTRL1000, adv); - - /* Start/Restart aneg */ - miiphy_read (devname, addr, MII_BMCR, &ctl); - ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); - miiphy_write (devname, addr, MII_BMCR, ctl); - - return 0; -} - -/******************************************************************************* - * ethernet_phy_reset - Reset Ethernet port PHY. - * - * DESCRIPTION: - * This routine utilize the SMI interface to reset the ethernet port PHY. - * The routine waits until the link is up again or link up is timeout. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * The ethernet port PHY renew its link. - * - * RETURN: - * None. - * - *******************************************************************************/ -static bool ethernet_phy_reset (ETH_PORT eth_port_num) -{ - unsigned int time_out = 50; - unsigned int phy_reg_data; - - eth_port_read_smi_reg (eth_port_num, 20, &phy_reg_data); - phy_reg_data |= 0x0083; /* Set bit 7 to 1 for different RGMII timing */ - eth_port_write_smi_reg (eth_port_num, 20, phy_reg_data); - - /* Reset the PHY */ - eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data); - phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */ - eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data); - - /* Poll on the PHY LINK */ - do { - eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); - - if (time_out-- == 0) - return false; - } - while (!(phy_reg_data & 0x20)); - - return true; -} - -/******************************************************************************* - * eth_port_reset - Reset Ethernet port - * - * DESCRIPTION: - * This routine resets the chip by aborting any SDMA engine activity and - * clearing the MIB counters. The Receiver and the Transmit unit are in - * idle state after this command is performed and the port is disabled. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * Channel activity is halted. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_port_reset (ETH_PORT eth_port_num) -{ - unsigned int reg_data; - - /* Stop Tx port activity. Check port Tx activity. */ - reg_data = - MV_REG_READ (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num)); - - if (reg_data & 0xFF) { - /* Issue stop command for active channels only */ - MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num), (reg_data << 8)); - - /* Wait for all Tx activity to terminate. */ - do { - /* Check port cause register that all Tx queues are stopped */ - reg_data = - MV_REG_READ - (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG - (eth_port_num)); - } - while (reg_data & 0xFF); - } - - /* Stop Rx port activity. Check port Rx activity. */ - reg_data = - MV_REG_READ (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num)); - - if (reg_data & 0xFF) { - /* Issue stop command for active channels only */ - MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num), (reg_data << 8)); - - /* Wait for all Rx activity to terminate. */ - do { - /* Check port cause register that all Rx queues are stopped */ - reg_data = - MV_REG_READ - (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG - (eth_port_num)); - } - while (reg_data & 0xFF); - } - - /* Clear all MIB counters */ - eth_clear_mib_counters (eth_port_num); - - /* Reset the Enable bit in the Configuration Register */ - reg_data = - MV_REG_READ (MV64460_ETH_PORT_SERIAL_CONTROL_REG - (eth_port_num)); - reg_data &= ~ETH_SERIAL_PORT_ENABLE; - MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), - reg_data); - - return; -} - -#if 0 /* Not needed here */ -/******************************************************************************* - * ethernet_set_config_reg - Set specified bits in configuration register. - * - * DESCRIPTION: - * This function sets specified bits in the given ethernet - * configuration register. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int value 32 bit value. - * - * OUTPUT: - * The set bits in the value parameter are set in the configuration - * register. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void ethernet_set_config_reg (ETH_PORT eth_port_num, - unsigned int value) -{ - unsigned int eth_config_reg; - - eth_config_reg = - MV_REG_READ (MV64460_ETH_PORT_CONFIG_REG (eth_port_num)); - eth_config_reg |= value; - MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num), - eth_config_reg); - - return; -} -#endif - -#if 0 /* FIXME */ -/******************************************************************************* - * ethernet_reset_config_reg - Reset specified bits in configuration register. - * - * DESCRIPTION: - * This function resets specified bits in the given Ethernet - * configuration register. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int value 32 bit value. - * - * OUTPUT: - * The set bits in the value parameter are reset in the configuration - * register. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void ethernet_reset_config_reg (ETH_PORT eth_port_num, - unsigned int value) -{ - unsigned int eth_config_reg; - - eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG - (eth_port_num)); - eth_config_reg &= ~value; - MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), - eth_config_reg); - - return; -} -#endif - -#if 0 /* Not needed here */ -/******************************************************************************* - * ethernet_get_config_reg - Get the port configuration register - * - * DESCRIPTION: - * This function returns the configuration register value of the given - * ethernet port. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * - * OUTPUT: - * None. - * - * RETURN: - * Port configuration register value. - * - *******************************************************************************/ -static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num) -{ - unsigned int eth_config_reg; - - eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG - (eth_port_num)); - return eth_config_reg; -} - -#endif - -/******************************************************************************* - * eth_port_read_smi_reg - Read PHY registers - * - * DESCRIPTION: - * This routine utilize the SMI interface to interact with the PHY in - * order to perform PHY register read. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int phy_reg PHY register address offset. - * unsigned int *value Register value buffer. - * - * OUTPUT: - * Write the value of a specified PHY register into given buffer. - * - * RETURN: - * false if the PHY is busy or read data is not in valid state. - * true otherwise. - * - *******************************************************************************/ -static bool eth_port_read_smi_reg (ETH_PORT eth_port_num, - unsigned int phy_reg, unsigned int *value) -{ - unsigned int reg_value; - unsigned int time_out = PHY_BUSY_TIMEOUT; - int phy_addr; - - phy_addr = ethernet_phy_get (eth_port_num); - - /* first check that it is not busy */ - do { - reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while (reg_value & ETH_SMI_BUSY); - - /* not busy */ - - MV_REG_WRITE (MV64460_ETH_SMI_REG, - (phy_addr << 16) | (phy_reg << 21) | - ETH_SMI_OPCODE_READ); - - time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */ - - do { - reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */ - - /* Wait for the data to update in the SMI register */ -#define PHY_UPDATE_TIMEOUT 10000 - for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++); - - reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); - - *value = reg_value & 0xffff; - - return true; -} - -int mv_miiphy_read(const char *devname, unsigned char phy_addr, - unsigned char phy_reg, unsigned short *value) -{ - unsigned int reg_value; - unsigned int time_out = PHY_BUSY_TIMEOUT; - - /* first check that it is not busy */ - do { - reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while (reg_value & ETH_SMI_BUSY); - - /* not busy */ - MV_REG_WRITE (MV64460_ETH_SMI_REG, - (phy_addr << 16) | (phy_reg << 21) | - ETH_SMI_OPCODE_READ); - - time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */ - - do { - reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */ - - /* Wait for the data to update in the SMI register */ - for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++); - - reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); - - *value = reg_value & 0xffff; - - return 0; -} - -/******************************************************************************* - * eth_port_write_smi_reg - Write to PHY registers - * - * DESCRIPTION: - * This routine utilize the SMI interface to interact with the PHY in - * order to perform writes to PHY registers. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * unsigned int phy_reg PHY register address offset. - * unsigned int value Register value. - * - * OUTPUT: - * Write the given value to the specified PHY register. - * - * RETURN: - * false if the PHY is busy. - * true otherwise. - * - *******************************************************************************/ -static bool eth_port_write_smi_reg (ETH_PORT eth_port_num, - unsigned int phy_reg, unsigned int value) -{ - unsigned int reg_value; - unsigned int time_out = PHY_BUSY_TIMEOUT; - int phy_addr; - - phy_addr = ethernet_phy_get (eth_port_num); - - /* first check that it is not busy */ - do { - reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while (reg_value & ETH_SMI_BUSY); - - /* not busy */ - MV_REG_WRITE (MV64460_ETH_SMI_REG, - (phy_addr << 16) | (phy_reg << 21) | - ETH_SMI_OPCODE_WRITE | (value & 0xffff)); - return true; -} - -int mv_miiphy_write(const char *devname, unsigned char phy_addr, - unsigned char phy_reg, unsigned short value) -{ - unsigned int reg_value; - unsigned int time_out = PHY_BUSY_TIMEOUT; - - /* first check that it is not busy */ - do { - reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); - if (time_out-- == 0) { - return false; - } - } - while (reg_value & ETH_SMI_BUSY); - - /* not busy */ - MV_REG_WRITE (MV64460_ETH_SMI_REG, - (phy_addr << 16) | (phy_reg << 21) | - ETH_SMI_OPCODE_WRITE | (value & 0xffff)); - return 0; -} - -/******************************************************************************* - * eth_set_access_control - Config address decode parameters for Ethernet unit - * - * DESCRIPTION: - * This function configures the address decode parameters for the Gigabit - * Ethernet Controller according the given parameters struct. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. - * ETH_WIN_PARAM *param Address decode parameter struct. - * - * OUTPUT: - * An access window is opened using the given access parameters. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_set_access_control (ETH_PORT eth_port_num, - ETH_WIN_PARAM * param) -{ - unsigned int access_prot_reg; - - /* Set access control register */ - access_prot_reg = MV_REG_READ (MV64460_ETH_ACCESS_PROTECTION_REG - (eth_port_num)); - access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */ - access_prot_reg |= (param->access_ctrl << (param->win * 2)); - MV_REG_WRITE (MV64460_ETH_ACCESS_PROTECTION_REG (eth_port_num), - access_prot_reg); - - /* Set window Size reg (SR) */ - MV_REG_WRITE ((MV64460_ETH_SIZE_REG_0 + - (ETH_SIZE_REG_GAP * param->win)), - (((param->size / 0x10000) - 1) << 16)); - - /* Set window Base address reg (BA) */ - MV_REG_WRITE ((MV64460_ETH_BAR_0 + (ETH_BAR_GAP * param->win)), - (param->target | param->attributes | param->base_addr)); - /* High address remap reg (HARR) */ - if (param->win < 4) - MV_REG_WRITE ((MV64460_ETH_HIGH_ADDR_REMAP_REG_0 + - (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)), - param->high_addr); - - /* Base address enable reg (BARER) */ - if (param->enable == 1) - MV_RESET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG, - (1 << param->win)); - else - MV_SET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG, - (1 << param->win)); -} - -/******************************************************************************* - * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. - * - * DESCRIPTION: - * This function prepares a Rx chained list of descriptors and packet - * buffers in a form of a ring. The routine must be called after port - * initialization routine and before port start routine. - * The Ethernet SDMA engine uses CPU bus addresses to access the various - * devices in the system (i.e. DRAM). This function uses the ethernet - * struct 'virtual to physical' routine (set by the user) to set the ring - * with physical addresses. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * int rx_desc_num Number of Rx descriptors - * int rx_buff_size Size of Rx buffer - * unsigned int rx_desc_base_addr Rx descriptors memory area base addr. - * unsigned int rx_buff_base_addr Rx buffer memory area base addr. - * - * OUTPUT: - * The routine updates the Ethernet port control struct with information - * regarding the Rx descriptors and buffers. - * - * RETURN: - * false if the given descriptors memory area is not aligned according to - * Ethernet SDMA specifications. - * true otherwise. - * - *******************************************************************************/ -static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE rx_queue, - int rx_desc_num, - int rx_buff_size, - unsigned int rx_desc_base_addr, - unsigned int rx_buff_base_addr) -{ - ETH_RX_DESC *p_rx_desc; - ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */ - unsigned int buffer_addr; - int ix; /* a counter */ - - p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr; - p_rx_prev_desc = p_rx_desc; - buffer_addr = rx_buff_base_addr; - - /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ - if (rx_buff_base_addr & 0xF) - return false; - - /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */ - if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE)) - return false; - - /* Rx buffers must be 64-bit aligned. */ - if ((rx_buff_base_addr + rx_buff_size) & 0x7) - return false; - - /* initialize the Rx descriptors ring */ - for (ix = 0; ix < rx_desc_num; ix++) { - p_rx_desc->buf_size = rx_buff_size; - p_rx_desc->byte_cnt = 0x0000; - p_rx_desc->cmd_sts = - ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; - p_rx_desc->next_desc_ptr = - ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE; - p_rx_desc->buf_ptr = buffer_addr; - p_rx_desc->return_info = 0x00000000; - D_CACHE_FLUSH_LINE (p_rx_desc, 0); - buffer_addr += rx_buff_size; - p_rx_prev_desc = p_rx_desc; - p_rx_desc = (ETH_RX_DESC *) - ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE); - } - - /* Closing Rx descriptors ring */ - p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr); - D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0); - - /* Save Rx desc pointer to driver struct. */ - CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); - USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); - - p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] = - (ETH_RX_DESC *) rx_desc_base_addr; - p_eth_port_ctrl->rx_desc_area_size[rx_queue] = - rx_desc_num * RX_DESC_ALIGNED_SIZE; - - p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue); - - return true; -} - -/******************************************************************************* - * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. - * - * DESCRIPTION: - * This function prepares a Tx chained list of descriptors and packet - * buffers in a form of a ring. The routine must be called after port - * initialization routine and before port start routine. - * The Ethernet SDMA engine uses CPU bus addresses to access the various - * devices in the system (i.e. DRAM). This function uses the ethernet - * struct 'virtual to physical' routine (set by the user) to set the ring - * with physical addresses. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * int tx_desc_num Number of Tx descriptors - * int tx_buff_size Size of Tx buffer - * unsigned int tx_desc_base_addr Tx descriptors memory area base addr. - * unsigned int tx_buff_base_addr Tx buffer memory area base addr. - * - * OUTPUT: - * The routine updates the Ethernet port control struct with information - * regarding the Tx descriptors and buffers. - * - * RETURN: - * false if the given descriptors memory area is not aligned according to - * Ethernet SDMA specifications. - * true otherwise. - * - *******************************************************************************/ -static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE tx_queue, - int tx_desc_num, - int tx_buff_size, - unsigned int tx_desc_base_addr, - unsigned int tx_buff_base_addr) -{ - - ETH_TX_DESC *p_tx_desc; - ETH_TX_DESC *p_tx_prev_desc; - unsigned int buffer_addr; - int ix; /* a counter */ - - /* save the first desc pointer to link with the last descriptor */ - p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr; - p_tx_prev_desc = p_tx_desc; - buffer_addr = tx_buff_base_addr; - - /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ - if (tx_buff_base_addr & 0xF) - return false; - - /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */ - if ((tx_buff_size > TX_BUFFER_MAX_SIZE) - || (tx_buff_size < TX_BUFFER_MIN_SIZE)) - return false; - - /* Initialize the Tx descriptors ring */ - for (ix = 0; ix < tx_desc_num; ix++) { - p_tx_desc->byte_cnt = 0x0000; - p_tx_desc->l4i_chk = 0x0000; - p_tx_desc->cmd_sts = 0x00000000; - p_tx_desc->next_desc_ptr = - ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE; - - p_tx_desc->buf_ptr = buffer_addr; - p_tx_desc->return_info = 0x00000000; - D_CACHE_FLUSH_LINE (p_tx_desc, 0); - buffer_addr += tx_buff_size; - p_tx_prev_desc = p_tx_desc; - p_tx_desc = (ETH_TX_DESC *) - ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE); - - } - /* Closing Tx descriptors ring */ - p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr; - D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0); - /* Set Tx desc pointer in driver struct. */ - CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); - USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); - - /* Init Tx ring base and size parameters */ - p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] = - (ETH_TX_DESC *) tx_desc_base_addr; - p_eth_port_ctrl->tx_desc_area_size[tx_queue] = - (tx_desc_num * TX_DESC_ALIGNED_SIZE); - - /* Add the queue to the list of Tx queues of this port */ - p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue); - - return true; -} - -/******************************************************************************* - * eth_port_send - Send an Ethernet packet - * - * DESCRIPTION: - * This routine send a given packet described by p_pktinfo parameter. It - * supports transmitting of a packet spaned over multiple buffers. The - * routine updates 'curr' and 'first' indexes according to the packet - * segment passed to the routine. In case the packet segment is first, - * the 'first' index is update. In any case, the 'curr' index is updated. - * If the routine get into Tx resource error it assigns 'curr' index as - * 'first'. This way the function can abort Tx process of multiple - * descriptors per packet. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Tx ring 'curr' and 'first' indexes are updated. - * - * RETURN: - * ETH_QUEUE_FULL in case of Tx resource error. - * ETH_ERROR in case the routine can not access Tx desc ring. - * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_TX_DESC *p_tx_desc_first; - volatile ETH_TX_DESC *p_tx_desc_curr; - volatile ETH_TX_DESC *p_tx_next_desc_curr; - volatile ETH_TX_DESC *p_tx_desc_used; - unsigned int command_status; - - /* Do not process Tx ring in case of Tx ring resource error */ - if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) - return ETH_QUEUE_FULL; - - /* Get the Tx Desc ring indexes */ - CURR_TFD_GET (p_tx_desc_curr, tx_queue); - USED_TFD_GET (p_tx_desc_used, tx_queue); - - if (p_tx_desc_curr == NULL) - return ETH_ERROR; - - /* The following parameters are used to save readings from memory */ - p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue); - command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC; - - if (command_status & (ETH_TX_FIRST_DESC)) { - /* Update first desc */ - FIRST_TFD_SET (p_tx_desc_curr, tx_queue); - p_tx_desc_first = p_tx_desc_curr; - } else { - FIRST_TFD_GET (p_tx_desc_first, tx_queue); - command_status |= ETH_BUFFER_OWNED_BY_DMA; - } - - /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */ - /* boundary. We use the memory allocated for Tx descriptor. This memory */ - /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */ - if (p_pkt_info->byte_cnt <= 8) { - printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */ - return ETH_ERROR; - - p_tx_desc_curr->buf_ptr = - (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC; - eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr, - p_pkt_info->byte_cnt); - } else - p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr; - - p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt; - p_tx_desc_curr->return_info = p_pkt_info->return_info; - - if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) { - /* Set last desc with DMA ownership and interrupt enable. */ - p_tx_desc_curr->cmd_sts = command_status | - ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT; - - if (p_tx_desc_curr != p_tx_desc_first) - p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA; - - /* Flush CPU pipe */ - - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0); - CPU_PIPE_FLUSH; - - /* Apply send command */ - ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num); - - /* Finish Tx packet. Update first desc in case of Tx resource error */ - p_tx_desc_first = p_tx_next_desc_curr; - FIRST_TFD_SET (p_tx_desc_first, tx_queue); - - } else { - p_tx_desc_curr->cmd_sts = command_status; - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); - } - - /* Check for ring index overlap in the Tx desc ring */ - if (p_tx_next_desc_curr == p_tx_desc_used) { - /* Update the current descriptor */ - CURR_TFD_SET (p_tx_desc_first, tx_queue); - - p_eth_port_ctrl->tx_resource_err[tx_queue] = true; - return ETH_QUEUE_LAST_RESOURCE; - } else { - /* Update the current descriptor */ - CURR_TFD_SET (p_tx_next_desc_curr, tx_queue); - return ETH_OK; - } -} - -/******************************************************************************* - * eth_tx_return_desc - Free all used Tx descriptors - * - * DESCRIPTION: - * This routine returns the transmitted packet information to the caller. - * It uses the 'first' index to support Tx desc return in case a transmit - * of a packet spanned over multiple buffer still in process. - * In case the Tx queue was in "resource error" condition, where there are - * no available Tx resources, the function resets the resource error flag. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Tx ring 'first' and 'used' indexes are updated. - * - * RETURN: - * ETH_ERROR in case the routine can not access Tx desc ring. - * ETH_RETRY in case there is transmission in process. - * ETH_END_OF_JOB if the routine has nothing to release. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO * - p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_TX_DESC *p_tx_desc_used = NULL; - volatile ETH_TX_DESC *p_tx_desc_first = NULL; - unsigned int command_status; - - /* Get the Tx Desc ring indexes */ - USED_TFD_GET (p_tx_desc_used, tx_queue); - FIRST_TFD_GET (p_tx_desc_first, tx_queue); - - /* Sanity check */ - if (p_tx_desc_used == NULL) - return ETH_ERROR; - - command_status = p_tx_desc_used->cmd_sts; - - /* Still transmitting... */ - if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - return ETH_RETRY; - } - - /* Stop release. About to overlap the current available Tx descriptor */ - if ((p_tx_desc_used == p_tx_desc_first) && - (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) { - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - return ETH_END_OF_JOB; - } - - /* Pass the packet information to the caller */ - p_pkt_info->cmd_sts = command_status; - p_pkt_info->return_info = p_tx_desc_used->return_info; - p_tx_desc_used->return_info = 0; - - /* Update the next descriptor to release. */ - USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue); - - /* Any Tx return cancels the Tx resource error status */ - if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) - p_eth_port_ctrl->tx_resource_err[tx_queue] = false; - - D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); - - return ETH_OK; - -} - -/******************************************************************************* - * eth_port_receive - Get received information from Rx ring. - * - * DESCRIPTION: - * This routine returns the received data to the caller. There is no - * data copying during routine operation. All information is returned - * using pointer to packet information struct passed from the caller. - * If the routine exhausts Rx ring resources then the resource error flag - * is set. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * PKT_INFO *p_pkt_info User packet buffer. - * - * OUTPUT: - * Rx ring current and used indexes are updated. - * - * RETURN: - * ETH_ERROR in case the routine can not access Rx desc ring. - * ETH_QUEUE_FULL if Rx ring resources are exhausted. - * ETH_END_OF_JOB if there is no received data. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_RX_DESC *p_rx_curr_desc; - volatile ETH_RX_DESC *p_rx_next_curr_desc; - volatile ETH_RX_DESC *p_rx_used_desc; - unsigned int command_status; - - /* Do not process Rx ring in case of Rx ring resource error */ - if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) { - printf ("\nRx Queue is full ...\n"); - return ETH_QUEUE_FULL; - } - - /* Get the Rx Desc ring 'curr and 'used' indexes */ - CURR_RFD_GET (p_rx_curr_desc, rx_queue); - USED_RFD_GET (p_rx_used_desc, rx_queue); - - /* Sanity check */ - if (p_rx_curr_desc == NULL) - return ETH_ERROR; - - /* The following parameters are used to save readings from memory */ - p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue); - command_status = p_rx_curr_desc->cmd_sts; - - /* Nothing to receive... */ - if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { -/* DP(printf("Rx: command_status: %08x\n", command_status)); */ - D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); -/* DP(printf("\nETH_END_OF_JOB ...\n"));*/ - return ETH_END_OF_JOB; - } - - p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET; - p_pkt_info->cmd_sts = command_status; - p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET; - p_pkt_info->return_info = p_rx_curr_desc->return_info; - p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */ - - /* Clean the return info field to indicate that the packet has been */ - /* moved to the upper layers */ - p_rx_curr_desc->return_info = 0; - - /* Update 'curr' in data structure */ - CURR_RFD_SET (p_rx_next_curr_desc, rx_queue); - - /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */ - if (p_rx_next_curr_desc == p_rx_used_desc) - p_eth_port_ctrl->rx_resource_err[rx_queue] = true; - - D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); - CPU_PIPE_FLUSH; - - return ETH_OK; -} - -/******************************************************************************* - * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. - * - * DESCRIPTION: - * This routine returns a Rx buffer back to the Rx ring. It retrieves the - * next 'used' descriptor and attached the returned buffer to it. - * In case the Rx ring was in "resource error" condition, where there are - * no available Rx resources, the function resets the resource error flag. - * - * INPUT: - * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * PKT_INFO *p_pkt_info Information on the returned buffer. - * - * OUTPUT: - * New available Rx resource in Rx descriptor ring. - * - * RETURN: - * ETH_ERROR in case the routine can not access Rx desc ring. - * ETH_OK otherwise. - * - *******************************************************************************/ -static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO * - p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO * p_pkt_info) -{ - volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */ - - /* Get 'used' Rx descriptor */ - USED_RFD_GET (p_used_rx_desc, rx_queue); - - /* Sanity check */ - if (p_used_rx_desc == NULL) - return ETH_ERROR; - - p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; - p_used_rx_desc->return_info = p_pkt_info->return_info; - p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt; - p_used_rx_desc->buf_size = MV64460_RX_BUFFER_SIZE; /* Reset Buffer size */ - - /* Flush the write pipe */ - CPU_PIPE_FLUSH; - - /* Return the descriptor to DMA ownership */ - p_used_rx_desc->cmd_sts = - ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; - - /* Flush descriptor and CPU pipe */ - D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0); - CPU_PIPE_FLUSH; - - /* Move the used descriptor pointer to the next descriptor */ - USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue); - - /* Any Rx return cancels the Rx resource error status */ - if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) - p_eth_port_ctrl->rx_resource_err[rx_queue] = false; - - return ETH_OK; -} - -/******************************************************************************* - * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path - * - * DESCRIPTION: - * This routine sets the RX coalescing interrupt mechanism parameter. - * This parameter is a timeout counter, that counts in 64 t_clk - * chunks ; that when timeout event occurs a maskable interrupt - * occurs. - * The parameter is calculated using the tClk of the MV-643xx chip - * , and the required delay of the interrupt in usec. - * - * INPUT: - * ETH_PORT eth_port_num Ethernet port number - * unsigned int t_clk t_clk of the MV-643xx chip in HZ units - * unsigned int delay Delay in usec - * - * OUTPUT: - * Interrupt coalescing mechanism value is set in MV-643xx chip. - * - * RETURN: - * The interrupt coalescing value set in the gigE port. - * - *******************************************************************************/ -#if 0 /* FIXME */ -static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num, - unsigned int t_clk, - unsigned int delay) -{ - unsigned int coal; - - coal = ((t_clk / 1000000) * delay) / 64; - /* Set RX Coalescing mechanism */ - MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num), - ((coal & 0x3fff) << 8) | - (MV_REG_READ - (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num)) - & 0xffc000ff)); - return coal; -} - -#endif -/******************************************************************************* - * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path - * - * DESCRIPTION: - * This routine sets the TX coalescing interrupt mechanism parameter. - * This parameter is a timeout counter, that counts in 64 t_clk - * chunks ; that when timeout event occurs a maskable interrupt - * occurs. - * The parameter is calculated using the t_cLK frequency of the - * MV-643xx chip and the required delay in the interrupt in uSec - * - * INPUT: - * ETH_PORT eth_port_num Ethernet port number - * unsigned int t_clk t_clk of the MV-643xx chip in HZ units - * unsigned int delay Delay in uSeconds - * - * OUTPUT: - * Interrupt coalescing mechanism value is set in MV-643xx chip. - * - * RETURN: - * The interrupt coalescing value set in the gigE port. - * - *******************************************************************************/ -#if 0 /* FIXME */ -static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num, - unsigned int t_clk, - unsigned int delay) -{ - unsigned int coal; - - coal = ((t_clk / 1000000) * delay) / 64; - /* Set TX Coalescing mechanism */ - MV_REG_WRITE (MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num), - coal << 4); - return coal; -} -#endif - -/******************************************************************************* - * eth_b_copy - Copy bytes from source to destination - * - * DESCRIPTION: - * This function supports the eight bytes limitation on Tx buffer size. - * The routine will zero eight bytes starting from the destination address - * followed by copying bytes from the source address to the destination. - * - * INPUT: - * unsigned int src_addr 32 bit source address. - * unsigned int dst_addr 32 bit destination address. - * int byte_count Number of bytes to copy. - * - * OUTPUT: - * See description. - * - * RETURN: - * None. - * - *******************************************************************************/ -static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, - int byte_count) -{ - /* Zero the dst_addr area */ - *(unsigned int *) dst_addr = 0x0; - - while (byte_count != 0) { - *(char *) dst_addr = *(char *) src_addr; - dst_addr++; - src_addr++; - byte_count--; - } -} diff --git a/board/prodrive/p3mx/mv_eth.h b/board/prodrive/p3mx/mv_eth.h deleted file mode 100644 index 7bbd7f0..0000000 --- a/board/prodrive/p3mx/mv_eth.h +++ /dev/null @@ -1,815 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus <ingo.assmus@keymile.com> - * - * based on - Driver for MV64460X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mv_eth.h - header file for the polled mode GT ethernet driver - */ - -#ifndef __DB64460_ETH_H__ -#define __DB64460_ETH_H__ - -#include <asm/types.h> -#include <asm/io.h> -#include <asm/byteorder.h> -#include <common.h> -#include <net.h> -#include "mv_regs.h" -#include <asm/errno.h> -#include "../../Marvell/include/core.h" - -/************************************************************************* -************************************************************************** -************************************************************************** -* The first part is the high level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ -/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */ -#ifndef MAX_SKB_FRAGS -#define MAX_SKB_FRAGS 0 -#endif - -/* Port attributes */ -/*#define MAX_RX_QUEUE_NUM 8*/ -/*#define MAX_TX_QUEUE_NUM 8*/ -#define MAX_RX_QUEUE_NUM 1 -#define MAX_TX_QUEUE_NUM 1 - - -/* Use one TX queue and one RX queue */ -#define MV64460_TX_QUEUE_NUM 1 -#define MV64460_RX_QUEUE_NUM 1 - -/* - * Number of RX / TX descriptors on RX / TX rings. - * Note that allocating RX descriptors is done by allocating the RX - * ring AND a preallocated RX buffers (skb's) for each descriptor. - * The TX descriptors only allocates the TX descriptors ring, - * with no pre allocated TX buffers (skb's are allocated by higher layers. - */ - -/* Default TX ring size is 10 descriptors */ -#ifdef CONFIG_MV64460_ETH_TXQUEUE_SIZE -#define MV64460_TX_QUEUE_SIZE CONFIG_MV64460_ETH_TXQUEUE_SIZE -#else -#define MV64460_TX_QUEUE_SIZE 4 -#endif - -/* Default RX ring size is 4 descriptors */ -#ifdef CONFIG_MV64460_ETH_RXQUEUE_SIZE -#define MV64460_RX_QUEUE_SIZE CONFIG_MV64460_ETH_RXQUEUE_SIZE -#else -#define MV64460_RX_QUEUE_SIZE 4 -#endif - -#ifdef CONFIG_RX_BUFFER_SIZE -#define MV64460_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE -#else -#define MV64460_RX_BUFFER_SIZE 1600 -#endif - -#ifdef CONFIG_TX_BUFFER_SIZE -#define MV64460_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE -#else -#define MV64460_TX_BUFFER_SIZE 1600 -#endif - -/* - * Network device statistics. Akin to the 2.0 ether stats but - * with byte counters. - */ - -struct net_device_stats -{ - unsigned long rx_packets; /* total packets received */ - unsigned long tx_packets; /* total packets transmitted */ - unsigned long rx_bytes; /* total bytes received */ - unsigned long tx_bytes; /* total bytes transmitted */ - unsigned long rx_errors; /* bad packets received */ - unsigned long tx_errors; /* packet transmit problems */ - unsigned long rx_dropped; /* no space in linux buffers */ - unsigned long tx_dropped; /* no space available in linux */ - unsigned long multicast; /* multicast packets received */ - unsigned long collisions; - - /* detailed rx_errors: */ - unsigned long rx_length_errors; - unsigned long rx_over_errors; /* receiver ring buff overflow */ - unsigned long rx_crc_errors; /* recved pkt with crc error */ - unsigned long rx_frame_errors; /* recv'd frame alignment error */ - unsigned long rx_fifo_errors; /* recv'r fifo overrun */ - unsigned long rx_missed_errors; /* receiver missed packet */ - - /* detailed tx_errors */ - unsigned long tx_aborted_errors; - unsigned long tx_carrier_errors; - unsigned long tx_fifo_errors; - unsigned long tx_heartbeat_errors; - unsigned long tx_window_errors; - - /* for cslip etc */ - unsigned long rx_compressed; - unsigned long tx_compressed; -}; - - -/* Private data structure used for ethernet device */ -struct mv64460_eth_priv { - unsigned int port_num; - struct net_device_stats *stats; - - /* to buffer area aligned */ - char * p_eth_tx_buffer[MV64460_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */ - char * p_eth_rx_buffer[MV64460_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */ - - /* Size of Tx Ring per queue */ - unsigned int tx_ring_size [MAX_TX_QUEUE_NUM]; - - /* Size of Rx Ring per queue */ - unsigned int rx_ring_size [MAX_RX_QUEUE_NUM]; - - /* Magic Number for Ethernet running */ - unsigned int eth_running; - - int first_init; -}; - -int mv64460_eth_init (struct eth_device *dev); -int mv64460_eth_stop (struct eth_device *dev); -int mv64460_eth_start_xmit(struct eth_device *dev, void *packet, int length); -int mv64460_eth_open (struct eth_device *dev); - - -/************************************************************************* -************************************************************************** -************************************************************************** -* The second part is the low level driver of the gigE ethernet ports. * -************************************************************************** -************************************************************************** -*************************************************************************/ - - -/******************************************************************************** - * Header File for : MV-643xx network interface header - * - * DESCRIPTION: - * This header file contains macros typedefs and function declaration for - * the Marvell Gig Bit Ethernet Controller. - * - * DEPENDENCIES: - * None. - * - *******************************************************************************/ - - -#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY -#ifdef CONFIG_MV64460_SRAM_CACHEABLE -/* In case SRAM is cacheable but not cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) \ -{ \ - __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ -} -#else -/* In case SRAM is cache coherent or non-cacheable */ -#define D_CACHE_FLUSH_LINE(addr, offset) ; -#endif -#else -#ifdef CONFIG_NOT_COHERENT_CACHE -/* In case of descriptors on DDR but not cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) \ -{ \ - __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ -} -#else -/* In case of descriptors on DDR and cache coherent */ -#define D_CACHE_FLUSH_LINE(addr, offset) ; -#endif /* CONFIG_NOT_COHERENT_CACHE */ -#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */ - - -#define CPU_PIPE_FLUSH \ -{ \ - __asm__ __volatile__ ("eieio"); \ -} - - -/* defines */ - -/* Default port configuration value */ -#define PORT_CONFIG_VALUE \ - ETH_UNICAST_NORMAL_MODE | \ - ETH_DEFAULT_RX_QUEUE_0 | \ - ETH_DEFAULT_RX_ARP_QUEUE_0 | \ - ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \ - ETH_RECEIVE_BC_IF_IP | \ - ETH_RECEIVE_BC_IF_ARP | \ - ETH_CAPTURE_TCP_FRAMES_DIS | \ - ETH_CAPTURE_UDP_FRAMES_DIS | \ - ETH_DEFAULT_RX_TCP_QUEUE_0 | \ - ETH_DEFAULT_RX_UDP_QUEUE_0 | \ - ETH_DEFAULT_RX_BPDU_QUEUE_0 - -/* Default port extend configuration value */ -#define PORT_CONFIG_EXTEND_VALUE \ - ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \ - ETH_PARTITION_DISABLE - - -/* Default sdma control value */ -#ifdef CONFIG_NOT_COHERENT_CACHE -#define PORT_SDMA_CONFIG_VALUE \ - ETH_RX_BURST_SIZE_16_64BIT | \ - GT_ETH_IPG_INT_RX(0) | \ - ETH_TX_BURST_SIZE_16_64BIT; -#else -#define PORT_SDMA_CONFIG_VALUE \ - ETH_RX_BURST_SIZE_4_64BIT | \ - GT_ETH_IPG_INT_RX(0) | \ - ETH_TX_BURST_SIZE_4_64BIT; -#endif - -#define GT_ETH_IPG_INT_RX(value) \ - ((value & 0x3fff) << 8) - -/* Default port serial control value */ -#define PORT_SERIAL_CONTROL_VALUE \ - ETH_FORCE_LINK_PASS | \ - ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \ - ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ - ETH_ADV_SYMMETRIC_FLOW_CTRL | \ - ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ - ETH_FORCE_BP_MODE_NO_JAM | \ - BIT9 | \ - ETH_DO_NOT_FORCE_LINK_FAIL | \ - ETH_RETRANSMIT_16_ETTEMPTS | \ - ETH_ENABLE_AUTO_NEG_SPEED_GMII | \ - ETH_DTE_ADV_0 | \ - ETH_DISABLE_AUTO_NEG_BYPASS | \ - ETH_AUTO_NEG_NO_CHANGE | \ - ETH_MAX_RX_PACKET_1552BYTE | \ - ETH_CLR_EXT_LOOPBACK | \ - ETH_SET_FULL_DUPLEX_MODE | \ - ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX; - -#define RX_BUFFER_MAX_SIZE 0xFFFF -#define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */ - -#define RX_BUFFER_MIN_SIZE 0x8 -#define TX_BUFFER_MIN_SIZE 0x8 - -/* Tx WRR confoguration macros */ -#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */ -#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */ -#define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */ - -/* MAC accepet/reject macros */ -#define ACCEPT_MAC_ADDR 0 -#define REJECT_MAC_ADDR 1 - -/* Size of a Tx/Rx descriptor used in chain list data structure */ -#define RX_DESC_ALIGNED_SIZE 0x20 -#define TX_DESC_ALIGNED_SIZE 0x20 - -/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */ -#define TX_BUF_OFFSET_IN_DESC 0x18 -/* Buffer offset from buffer pointer */ -#define RX_BUF_OFFSET 0x2 - -/* Gap define */ -#define ETH_BAR_GAP 0x8 -#define ETH_SIZE_REG_GAP 0x8 -#define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4 -#define ETH_PORT_ACCESS_CTRL_GAP 0x4 - -/* Gigabit Ethernet Unit Global Registers */ - -/* MIB Counters register definitions */ -#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0 -#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4 -#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8 -#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc -#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10 -#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14 -#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18 -#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c -#define ETH_MIB_FRAMES_64_OCTETS 0x20 -#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24 -#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28 -#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c -#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30 -#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 -#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38 -#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c -#define ETH_MIB_GOOD_FRAMES_SENT 0x40 -#define ETH_MIB_EXCESSIVE_COLLISION 0x44 -#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48 -#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c -#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50 -#define ETH_MIB_FC_SENT 0x54 -#define ETH_MIB_GOOD_FC_RECEIVED 0x58 -#define ETH_MIB_BAD_FC_RECEIVED 0x5c -#define ETH_MIB_UNDERSIZE_RECEIVED 0x60 -#define ETH_MIB_FRAGMENTS_RECEIVED 0x64 -#define ETH_MIB_OVERSIZE_RECEIVED 0x68 -#define ETH_MIB_JABBER_RECEIVED 0x6c -#define ETH_MIB_MAC_RECEIVE_ERROR 0x70 -#define ETH_MIB_BAD_CRC_EVENT 0x74 -#define ETH_MIB_COLLISION 0x78 -#define ETH_MIB_LATE_COLLISION 0x7c - -/* Port serial status reg (PSR) */ -#define ETH_INTERFACE_GMII_MII 0 -#define ETH_INTERFACE_PCM BIT0 -#define ETH_LINK_IS_DOWN 0 -#define ETH_LINK_IS_UP BIT1 -#define ETH_PORT_AT_HALF_DUPLEX 0 -#define ETH_PORT_AT_FULL_DUPLEX BIT2 -#define ETH_RX_FLOW_CTRL_DISABLED 0 -#define ETH_RX_FLOW_CTRL_ENBALED BIT3 -#define ETH_GMII_SPEED_100_10 0 -#define ETH_GMII_SPEED_1000 BIT4 -#define ETH_MII_SPEED_10 0 -#define ETH_MII_SPEED_100 BIT5 -#define ETH_NO_TX 0 -#define ETH_TX_IN_PROGRESS BIT7 -#define ETH_BYPASS_NO_ACTIVE 0 -#define ETH_BYPASS_ACTIVE BIT8 -#define ETH_PORT_NOT_AT_PARTITION_STATE 0 -#define ETH_PORT_AT_PARTITION_STATE BIT9 -#define ETH_PORT_TX_FIFO_NOT_EMPTY 0 -#define ETH_PORT_TX_FIFO_EMPTY BIT10 - - -/* These macros describes the Port configuration reg (Px_cR) bits */ -#define ETH_UNICAST_NORMAL_MODE 0 -#define ETH_UNICAST_PROMISCUOUS_MODE BIT0 -#define ETH_DEFAULT_RX_QUEUE_0 0 -#define ETH_DEFAULT_RX_QUEUE_1 BIT1 -#define ETH_DEFAULT_RX_QUEUE_2 BIT2 -#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1) -#define ETH_DEFAULT_RX_QUEUE_4 BIT3 -#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1) -#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2) -#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1) -#define ETH_DEFAULT_RX_ARP_QUEUE_0 0 -#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4 -#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5 -#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4) -#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6 -#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4) -#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5) -#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4) -#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0 -#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7 -#define ETH_RECEIVE_BC_IF_IP 0 -#define ETH_REJECT_BC_IF_IP BIT8 -#define ETH_RECEIVE_BC_IF_ARP 0 -#define ETH_REJECT_BC_IF_ARP BIT9 -#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12 -#define ETH_CAPTURE_TCP_FRAMES_DIS 0 -#define ETH_CAPTURE_TCP_FRAMES_EN BIT14 -#define ETH_CAPTURE_UDP_FRAMES_DIS 0 -#define ETH_CAPTURE_UDP_FRAMES_EN BIT15 -#define ETH_DEFAULT_RX_TCP_QUEUE_0 0 -#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16 -#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17 -#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16) -#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18 -#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16) -#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17) -#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16) -#define ETH_DEFAULT_RX_UDP_QUEUE_0 0 -#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19 -#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20 -#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19) -#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21 -#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19) -#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20) -#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19) -#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0 -#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22 -#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23 -#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22) -#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24 -#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22) -#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23) -#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22) - - -/* These macros describes the Port configuration extend reg (Px_cXR) bits*/ -#define ETH_CLASSIFY_EN BIT0 -#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0 -#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1 -#define ETH_PARTITION_DISABLE 0 -#define ETH_PARTITION_ENABLE BIT2 - - -/* Tx/Rx queue command reg (RQCR/TQCR)*/ -#define ETH_QUEUE_0_ENABLE BIT0 -#define ETH_QUEUE_1_ENABLE BIT1 -#define ETH_QUEUE_2_ENABLE BIT2 -#define ETH_QUEUE_3_ENABLE BIT3 -#define ETH_QUEUE_4_ENABLE BIT4 -#define ETH_QUEUE_5_ENABLE BIT5 -#define ETH_QUEUE_6_ENABLE BIT6 -#define ETH_QUEUE_7_ENABLE BIT7 -#define ETH_QUEUE_0_DISABLE BIT8 -#define ETH_QUEUE_1_DISABLE BIT9 -#define ETH_QUEUE_2_DISABLE BIT10 -#define ETH_QUEUE_3_DISABLE BIT11 -#define ETH_QUEUE_4_DISABLE BIT12 -#define ETH_QUEUE_5_DISABLE BIT13 -#define ETH_QUEUE_6_DISABLE BIT14 -#define ETH_QUEUE_7_DISABLE BIT15 - -/* These macros describes the Port Sdma configuration reg (SDCR) bits */ -#define ETH_RIFB BIT0 -#define ETH_RX_BURST_SIZE_1_64BIT 0 -#define ETH_RX_BURST_SIZE_2_64BIT BIT1 -#define ETH_RX_BURST_SIZE_4_64BIT BIT2 -#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1) -#define ETH_RX_BURST_SIZE_16_64BIT BIT3 -#define ETH_BLM_RX_NO_SWAP BIT4 -#define ETH_BLM_RX_BYTE_SWAP 0 -#define ETH_BLM_TX_NO_SWAP BIT5 -#define ETH_BLM_TX_BYTE_SWAP 0 -#define ETH_DESCRIPTORS_BYTE_SWAP BIT6 -#define ETH_DESCRIPTORS_NO_SWAP 0 -#define ETH_TX_BURST_SIZE_1_64BIT 0 -#define ETH_TX_BURST_SIZE_2_64BIT BIT22 -#define ETH_TX_BURST_SIZE_4_64BIT BIT23 -#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22) -#define ETH_TX_BURST_SIZE_16_64BIT BIT24 - -/* These macros describes the Port serial control reg (PSCR) bits */ -#define ETH_SERIAL_PORT_DISABLE 0 -#define ETH_SERIAL_PORT_ENABLE BIT0 -#define ETH_FORCE_LINK_PASS BIT1 -#define ETH_DO_NOT_FORCE_LINK_PASS 0 -#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0 -#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2 -#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0 -#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3 -#define ETH_ADV_NO_FLOW_CTRL 0 -#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4 -#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0 -#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5 -#define ETH_FORCE_BP_MODE_NO_JAM 0 -#define ETH_FORCE_BP_MODE_JAM_TX BIT7 -#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8 -#define ETH_FORCE_LINK_FAIL 0 -#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10 -#define ETH_RETRANSMIT_16_ETTEMPTS 0 -#define ETH_RETRANSMIT_FOREVER BIT11 -#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13 -#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0 -#define ETH_DTE_ADV_0 0 -#define ETH_DTE_ADV_1 BIT14 -#define ETH_DISABLE_AUTO_NEG_BYPASS 0 -#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15 -#define ETH_AUTO_NEG_NO_CHANGE 0 -#define ETH_RESTART_AUTO_NEG BIT16 -#define ETH_MAX_RX_PACKET_1518BYTE 0 -#define ETH_MAX_RX_PACKET_1522BYTE BIT17 -#define ETH_MAX_RX_PACKET_1552BYTE BIT18 -#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17) -#define ETH_MAX_RX_PACKET_9192BYTE BIT19 -#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17) -#define ETH_SET_EXT_LOOPBACK BIT20 -#define ETH_CLR_EXT_LOOPBACK 0 -#define ETH_SET_FULL_DUPLEX_MODE BIT21 -#define ETH_SET_HALF_DUPLEX_MODE 0 -#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22 -#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0 -#define ETH_SET_GMII_SPEED_TO_10_100 0 -#define ETH_SET_GMII_SPEED_TO_1000 BIT23 -#define ETH_SET_MII_SPEED_TO_10 0 -#define ETH_SET_MII_SPEED_TO_100 BIT24 - - -/* SMI reg */ -#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */ -#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */ -#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */ -#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */ - -/* SDMA command status fields macros */ - -/* Tx & Rx descriptors status */ -#define ETH_ERROR_SUMMARY (BIT0) - -/* Tx & Rx descriptors command */ -#define ETH_BUFFER_OWNED_BY_DMA (BIT31) - -/* Tx descriptors status */ -#define ETH_LC_ERROR (0 ) -#define ETH_UR_ERROR (BIT1 ) -#define ETH_RL_ERROR (BIT2 ) -#define ETH_LLC_SNAP_FORMAT (BIT9 ) - -/* Rx descriptors status */ -#define ETH_CRC_ERROR (0 ) -#define ETH_OVERRUN_ERROR (BIT1 ) -#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 ) -#define ETH_RESOURCE_ERROR ((BIT2 | BIT1)) -#define ETH_VLAN_TAGGED (BIT19) -#define ETH_BPDU_FRAME (BIT20) -#define ETH_TCP_FRAME_OVER_IP_V_4 (0 ) -#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21) -#define ETH_OTHER_FRAME_TYPE (BIT22) -#define ETH_LAYER_2_IS_ETH_V_2 (BIT23) -#define ETH_FRAME_TYPE_IP_V_4 (BIT24) -#define ETH_FRAME_HEADER_OK (BIT25) -#define ETH_RX_LAST_DESC (BIT26) -#define ETH_RX_FIRST_DESC (BIT27) -#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28) -#define ETH_RX_ENABLE_INTERRUPT (BIT29) -#define ETH_LAYER_4_CHECKSUM_OK (BIT30) - -/* Rx descriptors byte count */ -#define ETH_FRAME_FRAGMENTED (BIT2) - -/* Tx descriptors command */ -#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10) -#define ETH_FRAME_SET_TO_VLAN (BIT15) -#define ETH_TCP_FRAME (0 ) -#define ETH_UDP_FRAME (BIT16) -#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17) -#define ETH_GEN_IP_V_4_CHECKSUM (BIT18) -#define ETH_ZERO_PADDING (BIT19) -#define ETH_TX_LAST_DESC (BIT20) -#define ETH_TX_FIRST_DESC (BIT21) -#define ETH_GEN_CRC (BIT22) -#define ETH_TX_ENABLE_INTERRUPT (BIT23) -#define ETH_AUTO_MODE (BIT30) - -/* Address decode parameters */ -/* Ethernet Base Address Register bits */ -#define EBAR_TARGET_DRAM 0x00000000 -#define EBAR_TARGET_DEVICE 0x00000001 -#define EBAR_TARGET_CBS 0x00000002 -#define EBAR_TARGET_PCI0 0x00000003 -#define EBAR_TARGET_PCI1 0x00000004 -#define EBAR_TARGET_CUNIT 0x00000005 -#define EBAR_TARGET_AUNIT 0x00000006 -#define EBAR_TARGET_GUNIT 0x00000007 - -/* Window attributes */ -#define EBAR_ATTR_DRAM_CS0 0x00000E00 -#define EBAR_ATTR_DRAM_CS1 0x00000D00 -#define EBAR_ATTR_DRAM_CS2 0x00000B00 -#define EBAR_ATTR_DRAM_CS3 0x00000700 - -/* DRAM Target interface */ -#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000 -#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000 -#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000 - -/* Device Bus Target interface */ -#define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00 -#define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00 -#define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00 -#define EBAR_ATTR_DEVICE_DEVCS3 0x00001700 -#define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00 - -/* PCI Target interface */ -#define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000 -#define EBAR_ATTR_PCI_NO_SWAP 0x00000100 -#define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200 -#define EBAR_ATTR_PCI_WORD_SWAP 0x00000300 -#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000 -#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400 -#define EBAR_ATTR_PCI_IO_SPACE 0x00000000 -#define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800 -#define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000 -#define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000 - -/* CPU 60x bus or internal SRAM interface */ -#define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000 -#define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100 -#define EBAR_ATTR_CBS_SRAM 0x00000000 -#define EBAR_ATTR_CBS_CPU_BUS 0x00000800 - -/* Window access control */ -#define EWIN_ACCESS_NOT_ALLOWED 0 -#define EWIN_ACCESS_READ_ONLY BIT0 -#define EWIN_ACCESS_FULL (BIT1 | BIT0) -#define EWIN0_ACCESS_MASK 0x0003 -#define EWIN1_ACCESS_MASK 0x000C -#define EWIN2_ACCESS_MASK 0x0030 -#define EWIN3_ACCESS_MASK 0x00C0 - -/* typedefs */ - -typedef enum _eth_port -{ - ETH_0 = 0, - ETH_1 = 1, - ETH_2 = 2 -}ETH_PORT; - -typedef enum _eth_func_ret_status -{ - ETH_OK, /* Returned as expected. */ - ETH_ERROR, /* Fundamental error. */ - ETH_RETRY, /* Could not process request. Try later. */ - ETH_END_OF_JOB, /* Ring has nothing to process. */ - ETH_QUEUE_FULL, /* Ring resource error. */ - ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */ -}ETH_FUNC_RET_STATUS; - -typedef enum _eth_queue -{ - ETH_Q0 = 0, - ETH_Q1 = 1, - ETH_Q2 = 2, - ETH_Q3 = 3, - ETH_Q4 = 4, - ETH_Q5 = 5, - ETH_Q6 = 6, - ETH_Q7 = 7 -} ETH_QUEUE; - -typedef enum _addr_win -{ - ETH_WIN0, - ETH_WIN1, - ETH_WIN2, - ETH_WIN3, - ETH_WIN4, - ETH_WIN5 -} ETH_ADDR_WIN; - -typedef enum _eth_target -{ - ETH_TARGET_DRAM , - ETH_TARGET_DEVICE, - ETH_TARGET_CBS , - ETH_TARGET_PCI0 , - ETH_TARGET_PCI1 -}ETH_TARGET; - -typedef struct _eth_rx_desc -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short buf_size ; /* Buffer size */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int next_desc_ptr; /* Next descriptor pointer */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} ETH_RX_DESC; - - -typedef struct _eth_tx_desc -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short l4i_chk ; /* CPU provided TCP Checksum */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int next_desc_ptr; /* Next descriptor pointer */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} ETH_TX_DESC; - -/* Unified struct for Rx and Tx operations. The user is not required to */ -/* be familier with neither Tx nor Rx descriptors. */ -typedef struct _pkt_info -{ - unsigned short byte_cnt ; /* Descriptor buffer byte count */ - unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */ - unsigned int cmd_sts ; /* Descriptor command status */ - unsigned int buf_ptr ; /* Descriptor buffer pointer */ - unsigned int return_info ; /* User resource return information */ -} PKT_INFO; - - -typedef struct _eth_win_param -{ - ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */ - ETH_TARGET target; /* System targets. See ETH_TARGET enum */ - unsigned short attributes; /* BAR attributes. See above macros. */ - unsigned int base_addr; /* Window base address in unsigned int form */ - unsigned int high_addr; /* Window high address in unsigned int form */ - unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */ - bool enable; /* Enable/disable access to the window. */ - unsigned short access_ctrl; /* Access ctrl register. see above macros */ -} ETH_WIN_PARAM; - - -/* Ethernet port specific infomation */ - -typedef struct _eth_port_ctrl -{ - ETH_PORT port_num; /* User Ethernet port number */ - int port_phy_addr; /* User phy address of Ethrnet port */ - unsigned char port_mac_addr[6]; /* User defined port MAC address. */ - unsigned int port_config; /* User port configuration value */ - unsigned int port_config_extend; /* User port config extend value */ - unsigned int port_sdma_config; /* User port SDMA config value */ - unsigned int port_serial_control; /* User port serial control value */ - unsigned int port_tx_queue_command; /* Port active Tx queues summary */ - unsigned int port_rx_queue_command; /* Port active Rx queues summary */ - - /* User function to cast virtual address to CPU bus address */ - unsigned int (*port_virt_to_phys)(unsigned int addr); - /* User scratch pad for user specific data structures */ - void *port_private; - - bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */ - bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */ - - /* Tx/Rx rings managment indexes fields. For driver use */ - - /* Next available Rx resource */ - volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM]; - /* Returning Rx resource */ - volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM]; - - /* Next available Tx resource */ - volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM]; - /* Returning Tx resource */ - volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM]; - /* An extra Tx index to support transmit of multiple buffers per packet */ - volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM]; - - /* Tx/Rx rings size and base variables fields. For driver use */ - - volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM]; - unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM]; - char *p_rx_buffer_base[MAX_RX_QUEUE_NUM]; - - volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM]; - unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM]; - char *p_tx_buffer_base[MAX_TX_QUEUE_NUM]; - -} ETH_PORT_INFO; - - -/* ethernet.h API list */ - -/* Port operation control routines */ -static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl); -static void eth_port_reset(ETH_PORT eth_port_num); -static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl); - - -/* Port MAC address routines */ -static void eth_port_uc_addr_set (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue); -#if 0 /* FIXME */ -static void eth_port_mc_addr (ETH_PORT eth_port_num, - unsigned char *p_addr, - ETH_QUEUE queue, - int option); -#endif - -/* PHY and MIB routines */ -static bool ethernet_phy_reset(ETH_PORT eth_port_num); - -static bool eth_port_write_smi_reg(ETH_PORT eth_port_num, - unsigned int phy_reg, - unsigned int value); - -static bool eth_port_read_smi_reg(ETH_PORT eth_port_num, - unsigned int phy_reg, - unsigned int* value); - -static void eth_clear_mib_counters(ETH_PORT eth_port_num); - -/* Port data flow control routines */ -static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO *p_pkt_info); -static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - PKT_INFO *p_pkt_info); - - -static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE tx_queue, - int tx_desc_num, - int tx_buff_size, - unsigned int tx_desc_base_addr, - unsigned int tx_buff_base_addr); - -static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl, - ETH_QUEUE rx_queue, - int rx_desc_num, - int rx_buff_size, - unsigned int rx_desc_base_addr, - unsigned int rx_buff_base_addr); - -#endif /* MV64460_ETH_ */ diff --git a/board/prodrive/p3mx/mv_regs.h b/board/prodrive/p3mx/mv_regs.h deleted file mode 100644 index 279a7e9..0000000 --- a/board/prodrive/p3mx/mv_regs.h +++ /dev/null @@ -1,1109 +0,0 @@ -/* - * (C) Copyright 2003 - * Ingo Assmus <ingo.assmus@keymile.com> - * - * based on - Driver for MV64460X ethernet ports - * Copyright (C) 2002 rabeeh@galileo.co.il - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/******************************************************************************** -* gt64460r.h - GT-64460 Internal registers definition file. -* -* DESCRIPTION: -* None. -* -* DEPENDENCIES: -* None. -* -*******************************************************************************/ - -#ifndef __INCmv_regsh -#define __INCmv_regsh - -#define MV64460 - -/* Supported by the Atlantis */ -#define MV64460_INCLUDE_PCI_1 -#define MV64460_INCLUDE_PCI_0_ARBITER -#define MV64460_INCLUDE_PCI_1_ARBITER -#define MV64460_INCLUDE_SNOOP_SUPPORT -#define MV64460_INCLUDE_P2P -#define MV64460_INCLUDE_ETH_PORT_2 -#define MV64460_INCLUDE_CPU_MAPPING -#define MV64460_INCLUDE_MPSC - -/* Not supported features */ -#undef INCLUDE_CNTMR_4_7 -#undef INCLUDE_DMA_4_7 - -/****************************************/ -/* Processor Address Space */ -/****************************************/ - -/* DDR SDRAM BAR and size registers */ - -#define MV64460_CS_0_BASE_ADDR 0x008 -#define MV64460_CS_0_SIZE 0x010 -#define MV64460_CS_1_BASE_ADDR 0x208 -#define MV64460_CS_1_SIZE 0x210 -#define MV64460_CS_2_BASE_ADDR 0x018 -#define MV64460_CS_2_SIZE 0x020 -#define MV64460_CS_3_BASE_ADDR 0x218 -#define MV64460_CS_3_SIZE 0x220 - -/* Devices BAR and size registers */ - -#define MV64460_DEV_CS0_BASE_ADDR 0x028 -#define MV64460_DEV_CS0_SIZE 0x030 -#define MV64460_DEV_CS1_BASE_ADDR 0x228 -#define MV64460_DEV_CS1_SIZE 0x230 -#define MV64460_DEV_CS2_BASE_ADDR 0x248 -#define MV64460_DEV_CS2_SIZE 0x250 -#define MV64460_DEV_CS3_BASE_ADDR 0x038 -#define MV64460_DEV_CS3_SIZE 0x040 -#define MV64460_BOOTCS_BASE_ADDR 0x238 -#define MV64460_BOOTCS_SIZE 0x240 - -/* PCI 0 BAR and size registers */ - -#define MV64460_PCI_0_IO_BASE_ADDR 0x048 -#define MV64460_PCI_0_IO_SIZE 0x050 -#define MV64460_PCI_0_MEMORY0_BASE_ADDR 0x058 -#define MV64460_PCI_0_MEMORY0_SIZE 0x060 -#define MV64460_PCI_0_MEMORY1_BASE_ADDR 0x080 -#define MV64460_PCI_0_MEMORY1_SIZE 0x088 -#define MV64460_PCI_0_MEMORY2_BASE_ADDR 0x258 -#define MV64460_PCI_0_MEMORY2_SIZE 0x260 -#define MV64460_PCI_0_MEMORY3_BASE_ADDR 0x280 -#define MV64460_PCI_0_MEMORY3_SIZE 0x288 - -/* PCI 1 BAR and size registers */ -#define MV64460_PCI_1_IO_BASE_ADDR 0x090 -#define MV64460_PCI_1_IO_SIZE 0x098 -#define MV64460_PCI_1_MEMORY0_BASE_ADDR 0x0a0 -#define MV64460_PCI_1_MEMORY0_SIZE 0x0a8 -#define MV64460_PCI_1_MEMORY1_BASE_ADDR 0x0b0 -#define MV64460_PCI_1_MEMORY1_SIZE 0x0b8 -#define MV64460_PCI_1_MEMORY2_BASE_ADDR 0x2a0 -#define MV64460_PCI_1_MEMORY2_SIZE 0x2a8 -#define MV64460_PCI_1_MEMORY3_BASE_ADDR 0x2b0 -#define MV64460_PCI_1_MEMORY3_SIZE 0x2b8 - -/* SRAM base address */ -#define MV64460_INTEGRATED_SRAM_BASE_ADDR 0x268 - -/* internal registers space base address */ -#define MV64460_INTERNAL_SPACE_BASE_ADDR 0x068 - -/* Enables the CS , DEV_CS , PCI 0 and PCI 1 - windows above */ -#define MV64460_BASE_ADDR_ENABLE 0x278 - -/****************************************/ -/* PCI remap registers */ -/****************************************/ - /* PCI 0 */ -#define MV64460_PCI_0_IO_ADDR_REMAP 0x0f0 -#define MV64460_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8 -#define MV64460_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320 -#define MV64460_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100 -#define MV64460_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328 -#define MV64460_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8 -#define MV64460_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330 -#define MV64460_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300 -#define MV64460_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338 - /* PCI 1 */ -#define MV64460_PCI_1_IO_ADDR_REMAP 0x108 -#define MV64460_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110 -#define MV64460_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340 -#define MV64460_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118 -#define MV64460_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348 -#define MV64460_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310 -#define MV64460_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350 -#define MV64460_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318 -#define MV64460_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358 - -#define MV64460_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0 -#define MV64460_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8 -#define MV64460_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0 -#define MV64460_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8 -#define MV64460_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0 -#define MV64460_CPU_GE_HEADERS_RETARGET_BASE 0x3d8 -#define MV64460_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0 -#define MV64460_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8 - -/****************************************/ -/* CPU Control Registers */ -/****************************************/ - -#define MV64460_CPU_CONFIG 0x000 -#define MV64460_CPU_MODE 0x120 -#define MV64460_CPU_MASTER_CONTROL 0x160 -#define MV64460_CPU_CROSS_BAR_CONTROL_LOW 0x150 -#define MV64460_CPU_CROSS_BAR_CONTROL_HIGH 0x158 -#define MV64460_CPU_CROSS_BAR_TIMEOUT 0x168 - -/****************************************/ -/* SMP RegisterS */ -/****************************************/ - -#define MV64460_SMP_WHO_AM_I 0x200 -#define MV64460_SMP_CPU0_DOORBELL 0x214 -#define MV64460_SMP_CPU0_DOORBELL_CLEAR 0x21C -#define MV64460_SMP_CPU1_DOORBELL 0x224 -#define MV64460_SMP_CPU1_DOORBELL_CLEAR 0x22C -#define MV64460_SMP_CPU0_DOORBELL_MASK 0x234 -#define MV64460_SMP_CPU1_DOORBELL_MASK 0x23C -#define MV64460_SMP_SEMAPHOR0 0x244 -#define MV64460_SMP_SEMAPHOR1 0x24c -#define MV64460_SMP_SEMAPHOR2 0x254 -#define MV64460_SMP_SEMAPHOR3 0x25c -#define MV64460_SMP_SEMAPHOR4 0x264 -#define MV64460_SMP_SEMAPHOR5 0x26c -#define MV64460_SMP_SEMAPHOR6 0x274 -#define MV64460_SMP_SEMAPHOR7 0x27c - -/****************************************/ -/* CPU Sync Barrier Register */ -/****************************************/ - -#define MV64460_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0 -#define MV64460_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8 -#define MV64460_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0 -#define MV64460_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8 - -/****************************************/ -/* CPU Access Protect */ -/****************************************/ - -#define MV64460_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180 -#define MV64460_CPU_PROTECT_WINDOW_0_SIZE 0x188 -#define MV64460_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190 -#define MV64460_CPU_PROTECT_WINDOW_1_SIZE 0x198 -#define MV64460_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0 -#define MV64460_CPU_PROTECT_WINDOW_2_SIZE 0x1a8 -#define MV64460_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0 -#define MV64460_CPU_PROTECT_WINDOW_3_SIZE 0x1b8 - - -/****************************************/ -/* CPU Error Report */ -/****************************************/ - -#define MV64460_CPU_ERROR_ADDR_LOW 0x070 -#define MV64460_CPU_ERROR_ADDR_HIGH 0x078 -#define MV64460_CPU_ERROR_DATA_LOW 0x128 -#define MV64460_CPU_ERROR_DATA_HIGH 0x130 -#define MV64460_CPU_ERROR_PARITY 0x138 -#define MV64460_CPU_ERROR_CAUSE 0x140 -#define MV64460_CPU_ERROR_MASK 0x148 - -/****************************************/ -/* CPU Interface Debug Registers */ -/****************************************/ - -#define MV64460_PUNIT_SLAVE_DEBUG_LOW 0x360 -#define MV64460_PUNIT_SLAVE_DEBUG_HIGH 0x368 -#define MV64460_PUNIT_MASTER_DEBUG_LOW 0x370 -#define MV64460_PUNIT_MASTER_DEBUG_HIGH 0x378 -#define MV64460_PUNIT_MMASK 0x3e4 - -/****************************************/ -/* Integrated SRAM Registers */ -/****************************************/ - -#define MV64460_SRAM_CONFIG 0x380 -#define MV64460_SRAM_TEST_MODE 0X3F4 -#define MV64460_SRAM_ERROR_CAUSE 0x388 -#define MV64460_SRAM_ERROR_ADDR 0x390 -#define MV64460_SRAM_ERROR_ADDR_HIGH 0X3F8 -#define MV64460_SRAM_ERROR_DATA_LOW 0x398 -#define MV64460_SRAM_ERROR_DATA_HIGH 0x3a0 -#define MV64460_SRAM_ERROR_DATA_PARITY 0x3a8 - -/****************************************/ -/* SDRAM Configuration */ -/****************************************/ - -#define MV64460_SDRAM_CONFIG 0x1400 -#define MV64460_D_UNIT_CONTROL_LOW 0x1404 -#define MV64460_D_UNIT_CONTROL_HIGH 0x1424 -#define MV64460_D_UNIT_MMASK 0x14B0 -#define MV64460_SDRAM_TIMING_CONTROL_LOW 0x1408 -#define MV64460_SDRAM_TIMING_CONTROL_HIGH 0x140c -#define MV64460_SDRAM_ADDR_CONTROL 0x1410 -#define MV64460_SDRAM_OPEN_PAGES_CONTROL 0x1414 -#define MV64460_SDRAM_OPERATION 0x1418 -#define MV64460_SDRAM_MODE 0x141c -#define MV64460_EXTENDED_DRAM_MODE 0x1420 -#define MV64460_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430 -#define MV64460_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434 -#define MV64460_SDRAM_CROSS_BAR_TIMEOUT 0x1438 -#define MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0 -#define MV64460_SDRAM_DATA_PADS_CALIBRATION 0x14c4 - -/****************************************/ -/* SDRAM Error Report */ -/****************************************/ - -#define MV64460_SDRAM_ERROR_DATA_LOW 0x1444 -#define MV64460_SDRAM_ERROR_DATA_HIGH 0x1440 -#define MV64460_SDRAM_ERROR_ADDR 0x1450 -#define MV64460_SDRAM_RECEIVED_ECC 0x1448 -#define MV64460_SDRAM_CALCULATED_ECC 0x144c -#define MV64460_SDRAM_ECC_CONTROL 0x1454 -#define MV64460_SDRAM_ECC_ERROR_COUNTER 0x1458 - -/******************************************/ -/* Controlled Delay Line (CDL) Registers */ -/******************************************/ - -#define MV64460_DFCDL_CONFIG0 0x1480 -#define MV64460_DFCDL_CONFIG1 0x1484 -#define MV64460_DLL_WRITE 0x1488 -#define MV64460_DLL_READ 0x148c -#define MV64460_SRAM_ADDR 0x1490 -#define MV64460_SRAM_DATA0 0x1494 -#define MV64460_SRAM_DATA1 0x1498 -#define MV64460_SRAM_DATA2 0x149c -#define MV64460_DFCL_PROBE 0x14a0 - -/******************************************/ -/* Debug Registers */ -/******************************************/ - -#define MV64460_DUNIT_DEBUG_LOW 0x1460 -#define MV64460_DUNIT_DEBUG_HIGH 0x1464 -#define MV64460_DUNIT_MMASK 0X1b40 - -/****************************************/ -/* Device Parameters */ -/****************************************/ - -#define MV64460_DEVICE_BANK0_PARAMETERS 0x45c -#define MV64460_DEVICE_BANK1_PARAMETERS 0x460 -#define MV64460_DEVICE_BANK2_PARAMETERS 0x464 -#define MV64460_DEVICE_BANK3_PARAMETERS 0x468 -#define MV64460_DEVICE_BOOT_BANK_PARAMETERS 0x46c -#define MV64460_DEVICE_INTERFACE_CONTROL 0x4c0 -#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8 -#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc -#define MV64460_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4 - -/****************************************/ -/* Device interrupt registers */ -/****************************************/ - -#define MV64460_DEVICE_INTERRUPT_CAUSE 0x4d0 -#define MV64460_DEVICE_INTERRUPT_MASK 0x4d4 -#define MV64460_DEVICE_ERROR_ADDR 0x4d8 -#define MV64460_DEVICE_ERROR_DATA 0x4dc -#define MV64460_DEVICE_ERROR_PARITY 0x4e0 - -/****************************************/ -/* Device debug registers */ -/****************************************/ - -#define MV64460_DEVICE_DEBUG_LOW 0x4e4 -#define MV64460_DEVICE_DEBUG_HIGH 0x4e8 -#define MV64460_RUNIT_MMASK 0x4f0 - -/****************************************/ -/* PCI Slave Address Decoding registers */ -/****************************************/ - -#define MV64460_PCI_0_CS_0_BANK_SIZE 0xc08 -#define MV64460_PCI_1_CS_0_BANK_SIZE 0xc88 -#define MV64460_PCI_0_CS_1_BANK_SIZE 0xd08 -#define MV64460_PCI_1_CS_1_BANK_SIZE 0xd88 -#define MV64460_PCI_0_CS_2_BANK_SIZE 0xc0c -#define MV64460_PCI_1_CS_2_BANK_SIZE 0xc8c -#define MV64460_PCI_0_CS_3_BANK_SIZE 0xd0c -#define MV64460_PCI_1_CS_3_BANK_SIZE 0xd8c -#define MV64460_PCI_0_DEVCS_0_BANK_SIZE 0xc10 -#define MV64460_PCI_1_DEVCS_0_BANK_SIZE 0xc90 -#define MV64460_PCI_0_DEVCS_1_BANK_SIZE 0xd10 -#define MV64460_PCI_1_DEVCS_1_BANK_SIZE 0xd90 -#define MV64460_PCI_0_DEVCS_2_BANK_SIZE 0xd18 -#define MV64460_PCI_1_DEVCS_2_BANK_SIZE 0xd98 -#define MV64460_PCI_0_DEVCS_3_BANK_SIZE 0xc14 -#define MV64460_PCI_1_DEVCS_3_BANK_SIZE 0xc94 -#define MV64460_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14 -#define MV64460_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94 -#define MV64460_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c -#define MV64460_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c -#define MV64460_PCI_0_P2P_MEM1_BAR_SIZE 0xd20 -#define MV64460_PCI_1_P2P_MEM1_BAR_SIZE 0xda0 -#define MV64460_PCI_0_P2P_I_O_BAR_SIZE 0xd24 -#define MV64460_PCI_1_P2P_I_O_BAR_SIZE 0xda4 -#define MV64460_PCI_0_CPU_BAR_SIZE 0xd28 -#define MV64460_PCI_1_CPU_BAR_SIZE 0xda8 -#define MV64460_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00 -#define MV64460_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80 -#define MV64460_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c -#define MV64460_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c -#define MV64460_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c -#define MV64460_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc -#define MV64460_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48 -#define MV64460_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8 -#define MV64460_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48 -#define MV64460_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8 -#define MV64460_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c -#define MV64460_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc -#define MV64460_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c -#define MV64460_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc -#define MV64460_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04 -#define MV64460_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84 -#define MV64460_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08 -#define MV64460_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88 -#define MV64460_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C -#define MV64460_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C -#define MV64460_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10 -#define MV64460_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90 -#define MV64460_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50 -#define MV64460_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0 -#define MV64460_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50 -#define MV64460_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0 -#define MV64460_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58 -#define MV64460_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8 -#define MV64460_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54 -#define MV64460_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4 -#define MV64460_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54 -#define MV64460_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4 -#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c -#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc -#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60 -#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0 -#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64 -#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4 -#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68 -#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8 -#define MV64460_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c -#define MV64460_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec -#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70 -#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0 -#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74 -#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4 -#define MV64460_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00 -#define MV64460_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80 -#define MV64460_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38 -#define MV64460_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8 -#define MV64460_PCI_0_ADDR_DECODE_CONTROL 0xd3c -#define MV64460_PCI_1_ADDR_DECODE_CONTROL 0xdbc -#define MV64460_PCI_0_HEADERS_RETARGET_CONTROL 0xF40 -#define MV64460_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0 -#define MV64460_PCI_0_HEADERS_RETARGET_BASE 0xF44 -#define MV64460_PCI_1_HEADERS_RETARGET_BASE 0xFc4 -#define MV64460_PCI_0_HEADERS_RETARGET_HIGH 0xF48 -#define MV64460_PCI_1_HEADERS_RETARGET_HIGH 0xFc8 - -/***********************************/ -/* PCI Control Register Map */ -/***********************************/ - -#define MV64460_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20 -#define MV64460_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0 -#define MV64460_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C -#define MV64460_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C -#define MV64460_PCI_0_COMMAND 0xc00 -#define MV64460_PCI_1_COMMAND 0xc80 -#define MV64460_PCI_0_MODE 0xd00 -#define MV64460_PCI_1_MODE 0xd80 -#define MV64460_PCI_0_RETRY 0xc04 -#define MV64460_PCI_1_RETRY 0xc84 -#define MV64460_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04 -#define MV64460_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84 -#define MV64460_PCI_0_MSI_TRIGGER_TIMER 0xc38 -#define MV64460_PCI_1_MSI_TRIGGER_TIMER 0xcb8 -#define MV64460_PCI_0_ARBITER_CONTROL 0x1d00 -#define MV64460_PCI_1_ARBITER_CONTROL 0x1d80 -#define MV64460_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08 -#define MV64460_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88 -#define MV64460_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c -#define MV64460_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c -#define MV64460_PCI_0_CROSS_BAR_TIMEOUT 0x1d04 -#define MV64460_PCI_1_CROSS_BAR_TIMEOUT 0x1d84 -#define MV64460_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18 -#define MV64460_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98 -#define MV64460_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10 -#define MV64460_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90 -#define MV64460_PCI_0_P2P_CONFIG 0x1d14 -#define MV64460_PCI_1_P2P_CONFIG 0x1d94 - -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04 -#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14 -#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24 -#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34 -#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44 -#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50 -#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54 -#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58 - -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84 -#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94 -#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 -#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 -#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 -#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0 -#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 -#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8 - -/****************************************/ -/* PCI Configuration Access Registers */ -/****************************************/ - -#define MV64460_PCI_0_CONFIG_ADDR 0xcf8 -#define MV64460_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc -#define MV64460_PCI_1_CONFIG_ADDR 0xc78 -#define MV64460_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c -#define MV64460_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34 -#define MV64460_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4 - -/****************************************/ -/* PCI Error Report Registers */ -/****************************************/ - -#define MV64460_PCI_0_SERR_MASK 0xc28 -#define MV64460_PCI_1_SERR_MASK 0xca8 -#define MV64460_PCI_0_ERROR_ADDR_LOW 0x1d40 -#define MV64460_PCI_1_ERROR_ADDR_LOW 0x1dc0 -#define MV64460_PCI_0_ERROR_ADDR_HIGH 0x1d44 -#define MV64460_PCI_1_ERROR_ADDR_HIGH 0x1dc4 -#define MV64460_PCI_0_ERROR_ATTRIBUTE 0x1d48 -#define MV64460_PCI_1_ERROR_ATTRIBUTE 0x1dc8 -#define MV64460_PCI_0_ERROR_COMMAND 0x1d50 -#define MV64460_PCI_1_ERROR_COMMAND 0x1dd0 -#define MV64460_PCI_0_ERROR_CAUSE 0x1d58 -#define MV64460_PCI_1_ERROR_CAUSE 0x1dd8 -#define MV64460_PCI_0_ERROR_MASK 0x1d5c -#define MV64460_PCI_1_ERROR_MASK 0x1ddc - -/****************************************/ -/* PCI Debug Registers */ -/****************************************/ - -#define MV64460_PCI_0_MMASK 0X1D24 -#define MV64460_PCI_1_MMASK 0X1DA4 - -/*********************************************/ -/* PCI Configuration, Function 0, Registers */ -/*********************************************/ - -#define MV64460_PCI_DEVICE_AND_VENDOR_ID 0x000 -#define MV64460_PCI_STATUS_AND_COMMAND 0x004 -#define MV64460_PCI_CLASS_CODE_AND_REVISION_ID 0x008 -#define MV64460_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C - -#define MV64460_PCI_SCS_0_BASE_ADDR_LOW 0x010 -#define MV64460_PCI_SCS_0_BASE_ADDR_HIGH 0x014 -#define MV64460_PCI_SCS_1_BASE_ADDR_LOW 0x018 -#define MV64460_PCI_SCS_1_BASE_ADDR_HIGH 0x01C -#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020 -#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024 -#define MV64460_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c -#define MV64460_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 -#define MV64460_PCI_CAPABILTY_LIST_POINTER 0x034 -#define MV64460_PCI_INTERRUPT_PIN_AND_LINE 0x03C - /* capability list */ -#define MV64460_PCI_POWER_MANAGEMENT_CAPABILITY 0x040 -#define MV64460_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 -#define MV64460_PCI_VPD_ADDR 0x048 -#define MV64460_PCI_VPD_DATA 0x04c -#define MV64460_PCI_MSI_MESSAGE_CONTROL 0x050 -#define MV64460_PCI_MSI_MESSAGE_ADDR 0x054 -#define MV64460_PCI_MSI_MESSAGE_UPPER_ADDR 0x058 -#define MV64460_PCI_MSI_MESSAGE_DATA 0x05c -#define MV64460_PCI_X_COMMAND 0x060 -#define MV64460_PCI_X_STATUS 0x064 -#define MV64460_PCI_COMPACT_PCI_HOT_SWAP 0x068 - -/***********************************************/ -/* PCI Configuration, Function 1, Registers */ -/***********************************************/ - -#define MV64460_PCI_SCS_2_BASE_ADDR_LOW 0x110 -#define MV64460_PCI_SCS_2_BASE_ADDR_HIGH 0x114 -#define MV64460_PCI_SCS_3_BASE_ADDR_LOW 0x118 -#define MV64460_PCI_SCS_3_BASE_ADDR_HIGH 0x11c -#define MV64460_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120 -#define MV64460_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124 - -/***********************************************/ -/* PCI Configuration, Function 2, Registers */ -/***********************************************/ - -#define MV64460_PCI_DEVCS_0_BASE_ADDR_LOW 0x210 -#define MV64460_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214 -#define MV64460_PCI_DEVCS_1_BASE_ADDR_LOW 0x218 -#define MV64460_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c -#define MV64460_PCI_DEVCS_2_BASE_ADDR_LOW 0x220 -#define MV64460_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224 - -/***********************************************/ -/* PCI Configuration, Function 3, Registers */ -/***********************************************/ - -#define MV64460_PCI_DEVCS_3_BASE_ADDR_LOW 0x310 -#define MV64460_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314 -#define MV64460_PCI_BOOT_CS_BASE_ADDR_LOW 0x318 -#define MV64460_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c -#define MV64460_PCI_CPU_BASE_ADDR_LOW 0x220 -#define MV64460_PCI_CPU_BASE_ADDR_HIGH 0x224 - -/***********************************************/ -/* PCI Configuration, Function 4, Registers */ -/***********************************************/ - -#define MV64460_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410 -#define MV64460_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414 -#define MV64460_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418 -#define MV64460_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c -#define MV64460_PCI_P2P_I_O_BASE_ADDR 0x420 -#define MV64460_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424 - -/****************************************/ -/* Messaging Unit Registers (I20) */ -/****************************************/ - -#define MV64460_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010 -#define MV64460_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C -#define MV64460_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020 -#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024 -#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028 -#define MV64460_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C -#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030 -#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034 -#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040 -#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044 -#define MV64460_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050 -#define MV64460_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054 -#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060 -#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064 -#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068 -#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C -#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070 -#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074 -#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8 -#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC - -#define MV64460_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090 -#define MV64460_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C -#define MV64460_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0 -#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4 -#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8 -#define MV64460_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC -#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0 -#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4 -#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0 -#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4 -#define MV64460_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0 -#define MV64460_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4 -#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0 -#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4 -#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8 -#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC -#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0 -#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4 -#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078 -#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C - -#define MV64460_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10 -#define MV64460_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C -#define MV64460_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20 -#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24 -#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28 -#define MV64460_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C -#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30 -#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34 -#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40 -#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44 -#define MV64460_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50 -#define MV64460_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54 -#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60 -#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64 -#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68 -#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C -#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70 -#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74 -#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8 -#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC -#define MV64460_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90 -#define MV64460_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98 -#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C -#define MV64460_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0 -#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4 -#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8 -#define MV64460_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC -#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0 -#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4 -#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0 -#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4 -#define MV64460_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0 -#define MV64460_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4 -#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0 -#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4 -#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8 -#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC -#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0 -#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4 -#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78 -#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C - -/****************************************/ -/* Ethernet Unit Registers */ -/****************************************/ - -#define MV64460_ETH_PHY_ADDR_REG 0x2000 -#define MV64460_ETH_SMI_REG 0x2004 -#define MV64460_ETH_UNIT_DEFAULT_ADDR_REG 0x2008 -#define MV64460_ETH_UNIT_DEFAULTID_REG 0x200c -#define MV64460_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080 -#define MV64460_ETH_UNIT_INTERRUPT_MASK_REG 0x2084 -#define MV64460_ETH_UNIT_INTERNAL_USE_REG 0x24fc -#define MV64460_ETH_UNIT_ERROR_ADDR_REG 0x2094 -#define MV64460_ETH_BAR_0 0x2200 -#define MV64460_ETH_BAR_1 0x2208 -#define MV64460_ETH_BAR_2 0x2210 -#define MV64460_ETH_BAR_3 0x2218 -#define MV64460_ETH_BAR_4 0x2220 -#define MV64460_ETH_BAR_5 0x2228 -#define MV64460_ETH_SIZE_REG_0 0x2204 -#define MV64460_ETH_SIZE_REG_1 0x220c -#define MV64460_ETH_SIZE_REG_2 0x2214 -#define MV64460_ETH_SIZE_REG_3 0x221c -#define MV64460_ETH_SIZE_REG_4 0x2224 -#define MV64460_ETH_SIZE_REG_5 0x222c -#define MV64460_ETH_HEADERS_RETARGET_BASE_REG 0x2230 -#define MV64460_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234 -#define MV64460_ETH_HIGH_ADDR_REMAP_REG_0 0x2280 -#define MV64460_ETH_HIGH_ADDR_REMAP_REG_1 0x2284 -#define MV64460_ETH_HIGH_ADDR_REMAP_REG_2 0x2288 -#define MV64460_ETH_HIGH_ADDR_REMAP_REG_3 0x228c -#define MV64460_ETH_BASE_ADDR_ENABLE_REG 0x2290 -#define MV64460_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2)) -#define MV64460_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7)) -#define MV64460_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10)) -#define MV64460_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10)) -#define MV64460_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10)) -#define MV64460_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10)) -#define MV64460_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10)) -#define MV64460_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10)) -#define MV64460_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10)) -#define MV64460_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10)) -#define MV64460_ETH_DSCP_0(port) (0x2420 + (port<<10)) -#define MV64460_ETH_DSCP_1(port) (0x2424 + (port<<10)) -#define MV64460_ETH_DSCP_2(port) (0x2428 + (port<<10)) -#define MV64460_ETH_DSCP_3(port) (0x242c + (port<<10)) -#define MV64460_ETH_DSCP_4(port) (0x2430 + (port<<10)) -#define MV64460_ETH_DSCP_5(port) (0x2434 + (port<<10)) -#define MV64460_ETH_DSCP_6(port) (0x2438 + (port<<10)) -#define MV64460_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10)) -#define MV64460_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10)) -#define MV64460_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10)) -#define MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10)) -#define MV64460_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10)) -#define MV64460_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10)) -#define MV64460_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10)) -#define MV64460_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10)) -#define MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10)) -#define MV64460_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10)) -#define MV64460_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10)) -#define MV64460_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10)) -#define MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10)) -#define MV64460_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10)) -#define MV64460_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10) -#define MV64460_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10)) -#define MV64460_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10)) -#define MV64460_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10)) -#define MV64460_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10)) -#define MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10)) -#define MV64460_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10)) -#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10)) -#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10)) -#define MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10)) -#define MV64460_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10)) -#define MV64460_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10)) -#define MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10)) -#define MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10)) -#define MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10)) - -/*******************************************/ -/* CUNIT Registers */ -/*******************************************/ - - /* Address Decoding Register Map */ - -#define MV64460_CUNIT_BASE_ADDR_REG0 0xf200 -#define MV64460_CUNIT_BASE_ADDR_REG1 0xf208 -#define MV64460_CUNIT_BASE_ADDR_REG2 0xf210 -#define MV64460_CUNIT_BASE_ADDR_REG3 0xf218 -#define MV64460_CUNIT_SIZE0 0xf204 -#define MV64460_CUNIT_SIZE1 0xf20c -#define MV64460_CUNIT_SIZE2 0xf214 -#define MV64460_CUNIT_SIZE3 0xf21c -#define MV64460_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240 -#define MV64460_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244 -#define MV64460_CUNIT_BASE_ADDR_ENABLE_REG 0xf250 -#define MV64460_MPSC0_ACCESS_PROTECTION_REG 0xf254 -#define MV64460_MPSC1_ACCESS_PROTECTION_REG 0xf258 -#define MV64460_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C - - /* Error Report Registers */ - -#define MV64460_CUNIT_INTERRUPT_CAUSE_REG 0xf310 -#define MV64460_CUNIT_INTERRUPT_MASK_REG 0xf314 -#define MV64460_CUNIT_ERROR_ADDR 0xf318 - - /* Cunit Control Registers */ - -#define MV64460_CUNIT_ARBITER_CONTROL_REG 0xf300 -#define MV64460_CUNIT_CONFIG_REG 0xb40c -#define MV64460_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304 - - /* Cunit Debug Registers */ - -#define MV64460_CUNIT_DEBUG_LOW 0xf340 -#define MV64460_CUNIT_DEBUG_HIGH 0xf344 -#define MV64460_CUNIT_MMASK 0xf380 - - /* Cunit Base Address Enable Window Bits*/ -#define MV64460_CUNIT_BASE_ADDR_WIN_0_BIT 0x0 -#define MV64460_CUNIT_BASE_ADDR_WIN_1_BIT 0x1 -#define MV64460_CUNIT_BASE_ADDR_WIN_2_BIT 0x2 -#define MV64460_CUNIT_BASE_ADDR_WIN_3_BIT 0x3 - - /* MPSCs Clocks Routing Registers */ - -#define MV64460_MPSC_ROUTING_REG 0xb400 -#define MV64460_MPSC_RX_CLOCK_ROUTING_REG 0xb404 -#define MV64460_MPSC_TX_CLOCK_ROUTING_REG 0xb408 - - /* MPSCs Interrupts Registers */ - -#define MV64460_MPSC_CAUSE_REG(port) (0xb804 + (port<<3)) -#define MV64460_MPSC_MASK_REG(port) (0xb884 + (port<<3)) - -#define MV64460_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12)) -#define MV64460_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12)) -#define MV64460_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG1(port) (0x800c + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG5(port) (0x801c + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG9(port) (0x802c + (port<<12)) -#define MV64460_MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12)) - - /* MPSC0 Registers */ - - -/***************************************/ -/* SDMA Registers */ -/***************************************/ - -#define MV64460_SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13)) -#define MV64460_SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13)) -#define MV64460_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13)) -#define MV64460_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13)) -#define MV64460_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13)) - -#define MV64460_SDMA_CAUSE_REG 0xb800 -#define MV64460_SDMA_MASK_REG 0xb880 - - -/****************************************/ -/* SDMA Address Space Targets */ -/****************************************/ - -#define MV64460_SDMA_DRAM_CS_0_TARGET 0x0e00 -#define MV64460_SDMA_DRAM_CS_1_TARGET 0x0d00 -#define MV64460_SDMA_DRAM_CS_2_TARGET 0x0b00 -#define MV64460_SDMA_DRAM_CS_3_TARGET 0x0700 - -#define MV64460_SDMA_DEV_CS_0_TARGET 0x1e01 -#define MV64460_SDMA_DEV_CS_1_TARGET 0x1d01 -#define MV64460_SDMA_DEV_CS_2_TARGET 0x1b01 -#define MV64460_SDMA_DEV_CS_3_TARGET 0x1701 - -#define MV64460_SDMA_BOOT_CS_TARGET 0x0f00 - -#define MV64460_SDMA_SRAM_TARGET 0x0003 -#define MV64460_SDMA_60X_BUS_TARGET 0x4003 - -#define MV64460_PCI_0_TARGET 0x0003 -#define MV64460_PCI_1_TARGET 0x0004 - - -/* Devices BAR and size registers */ - -#define MV64460_DEV_CS0_BASE_ADDR 0x028 -#define MV64460_DEV_CS0_SIZE 0x030 -#define MV64460_DEV_CS1_BASE_ADDR 0x228 -#define MV64460_DEV_CS1_SIZE 0x230 -#define MV64460_DEV_CS2_BASE_ADDR 0x248 -#define MV64460_DEV_CS2_SIZE 0x250 -#define MV64460_DEV_CS3_BASE_ADDR 0x038 -#define MV64460_DEV_CS3_SIZE 0x040 -#define MV64460_BOOTCS_BASE_ADDR 0x238 -#define MV64460_BOOTCS_SIZE 0x240 - -/* SDMA Window access protection */ -#define MV64460_SDMA_WIN_ACCESS_NOT_ALLOWED 0 -#define MV64460_SDMA_WIN_ACCESS_READ_ONLY 1 -#define MV64460_SDMA_WIN_ACCESS_FULL 2 - -/* BRG Interrupts */ - -#define MV64460_BRG_CONFIG_REG(brg) (0xb200 + (brg<<3)) -#define MV64460_BRG_BAUDE_TUNING_REG(brg) (0xb204 + (brg<<3)) -#define MV64460_BRG_CAUSE_REG 0xb834 -#define MV64460_BRG_MASK_REG 0xb8b4 - -/****************************************/ -/* DMA Channel Control */ -/****************************************/ - -#define MV64460_DMA_CHANNEL0_CONTROL 0x840 -#define MV64460_DMA_CHANNEL0_CONTROL_HIGH 0x880 -#define MV64460_DMA_CHANNEL1_CONTROL 0x844 -#define MV64460_DMA_CHANNEL1_CONTROL_HIGH 0x884 -#define MV64460_DMA_CHANNEL2_CONTROL 0x848 -#define MV64460_DMA_CHANNEL2_CONTROL_HIGH 0x888 -#define MV64460_DMA_CHANNEL3_CONTROL 0x84C -#define MV64460_DMA_CHANNEL3_CONTROL_HIGH 0x88C - - -/****************************************/ -/* IDMA Registers */ -/****************************************/ - -#define MV64460_DMA_CHANNEL0_BYTE_COUNT 0x800 -#define MV64460_DMA_CHANNEL1_BYTE_COUNT 0x804 -#define MV64460_DMA_CHANNEL2_BYTE_COUNT 0x808 -#define MV64460_DMA_CHANNEL3_BYTE_COUNT 0x80C -#define MV64460_DMA_CHANNEL0_SOURCE_ADDR 0x810 -#define MV64460_DMA_CHANNEL1_SOURCE_ADDR 0x814 -#define MV64460_DMA_CHANNEL2_SOURCE_ADDR 0x818 -#define MV64460_DMA_CHANNEL3_SOURCE_ADDR 0x81c -#define MV64460_DMA_CHANNEL0_DESTINATION_ADDR 0x820 -#define MV64460_DMA_CHANNEL1_DESTINATION_ADDR 0x824 -#define MV64460_DMA_CHANNEL2_DESTINATION_ADDR 0x828 -#define MV64460_DMA_CHANNEL3_DESTINATION_ADDR 0x82C -#define MV64460_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830 -#define MV64460_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834 -#define MV64460_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838 -#define MV64460_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C -#define MV64460_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870 -#define MV64460_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874 -#define MV64460_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878 -#define MV64460_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C - - /* IDMA Address Decoding Base Address Registers */ - -#define MV64460_DMA_BASE_ADDR_REG0 0xa00 -#define MV64460_DMA_BASE_ADDR_REG1 0xa08 -#define MV64460_DMA_BASE_ADDR_REG2 0xa10 -#define MV64460_DMA_BASE_ADDR_REG3 0xa18 -#define MV64460_DMA_BASE_ADDR_REG4 0xa20 -#define MV64460_DMA_BASE_ADDR_REG5 0xa28 -#define MV64460_DMA_BASE_ADDR_REG6 0xa30 -#define MV64460_DMA_BASE_ADDR_REG7 0xa38 - - /* IDMA Address Decoding Size Address Register */ - -#define MV64460_DMA_SIZE_REG0 0xa04 -#define MV64460_DMA_SIZE_REG1 0xa0c -#define MV64460_DMA_SIZE_REG2 0xa14 -#define MV64460_DMA_SIZE_REG3 0xa1c -#define MV64460_DMA_SIZE_REG4 0xa24 -#define MV64460_DMA_SIZE_REG5 0xa2c -#define MV64460_DMA_SIZE_REG6 0xa34 -#define MV64460_DMA_SIZE_REG7 0xa3C - - /* IDMA Address Decoding High Address Remap and Access - Protection Registers */ - -#define MV64460_DMA_HIGH_ADDR_REMAP_REG0 0xa60 -#define MV64460_DMA_HIGH_ADDR_REMAP_REG1 0xa64 -#define MV64460_DMA_HIGH_ADDR_REMAP_REG2 0xa68 -#define MV64460_DMA_HIGH_ADDR_REMAP_REG3 0xa6C -#define MV64460_DMA_BASE_ADDR_ENABLE_REG 0xa80 -#define MV64460_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70 -#define MV64460_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74 -#define MV64460_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78 -#define MV64460_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c -#define MV64460_DMA_ARBITER_CONTROL 0x860 -#define MV64460_DMA_CROSS_BAR_TIMEOUT 0x8d0 - - /* IDMA Headers Retarget Registers */ - -#define MV64460_DMA_HEADERS_RETARGET_CONTROL 0xa84 -#define MV64460_DMA_HEADERS_RETARGET_BASE 0xa88 - - /* IDMA Interrupt Register */ - -#define MV64460_DMA_INTERRUPT_CAUSE_REG 0x8c0 -#define MV64460_DMA_INTERRUPT_CAUSE_MASK 0x8c4 -#define MV64460_DMA_ERROR_ADDR 0x8c8 -#define MV64460_DMA_ERROR_SELECT 0x8cc - - /* IDMA Debug Register ( for internal use ) */ - -#define MV64460_DMA_DEBUG_LOW 0x8e0 -#define MV64460_DMA_DEBUG_HIGH 0x8e4 -#define MV64460_DMA_SPARE 0xA8C - -/****************************************/ -/* Timer_Counter */ -/****************************************/ - -#define MV64460_TIMER_COUNTER0 0x850 -#define MV64460_TIMER_COUNTER1 0x854 -#define MV64460_TIMER_COUNTER2 0x858 -#define MV64460_TIMER_COUNTER3 0x85C -#define MV64460_TIMER_COUNTER_0_3_CONTROL 0x864 -#define MV64460_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 -#define MV64460_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c - -/****************************************/ -/* Watchdog registers */ -/****************************************/ - -#define MV64460_WATCHDOG_CONFIG_REG 0xb410 -#define MV64460_WATCHDOG_VALUE_REG 0xb414 - -/****************************************/ -/* I2C Registers */ -/****************************************/ - -#define MV64460_I2C_SLAVE_ADDR 0xc000 -#define MV64460_I2C_EXTENDED_SLAVE_ADDR 0xc010 -#define MV64460_I2C_DATA 0xc004 -#define MV64460_I2C_CONTROL 0xc008 -#define MV64460_I2C_STATUS_BAUDE_RATE 0xc00C -#define MV64460_I2C_SOFT_RESET 0xc01c - -/****************************************/ -/* GPP Interface Registers */ -/****************************************/ - -#define MV64460_GPP_IO_CONTROL 0xf100 -#define MV64460_GPP_LEVEL_CONTROL 0xf110 -#define MV64460_GPP_VALUE 0xf104 -#define MV64460_GPP_INTERRUPT_CAUSE 0xf108 -#define MV64460_GPP_INTERRUPT_MASK0 0xf10c -#define MV64460_GPP_INTERRUPT_MASK1 0xf114 -#define MV64460_GPP_VALUE_SET 0xf118 -#define MV64460_GPP_VALUE_CLEAR 0xf11c - -/****************************************/ -/* Interrupt Controller Registers */ -/****************************************/ - -/****************************************/ -/* Interrupts */ -/****************************************/ - -#define MV64460_MAIN_INTERRUPT_CAUSE_LOW 0x004 -#define MV64460_MAIN_INTERRUPT_CAUSE_HIGH 0x00c -#define MV64460_CPU_INTERRUPT0_MASK_LOW 0x014 -#define MV64460_CPU_INTERRUPT0_MASK_HIGH 0x01c -#define MV64460_CPU_INTERRUPT0_SELECT_CAUSE 0x024 -#define MV64460_CPU_INTERRUPT1_MASK_LOW 0x034 -#define MV64460_CPU_INTERRUPT1_MASK_HIGH 0x03c -#define MV64460_CPU_INTERRUPT1_SELECT_CAUSE 0x044 -#define MV64460_INTERRUPT0_MASK_0_LOW 0x054 -#define MV64460_INTERRUPT0_MASK_0_HIGH 0x05c -#define MV64460_INTERRUPT0_SELECT_CAUSE 0x064 -#define MV64460_INTERRUPT1_MASK_0_LOW 0x074 -#define MV64460_INTERRUPT1_MASK_0_HIGH 0x07c -#define MV64460_INTERRUPT1_SELECT_CAUSE 0x084 - -/****************************************/ -/* MPP Interface Registers */ -/****************************************/ - -#define MV64460_MPP_CONTROL0 0xf000 -#define MV64460_MPP_CONTROL1 0xf004 -#define MV64460_MPP_CONTROL2 0xf008 -#define MV64460_MPP_CONTROL3 0xf00c - -/****************************************/ -/* Serial Initialization registers */ -/****************************************/ - -#define MV64460_SERIAL_INIT_LAST_DATA 0xf324 -#define MV64460_SERIAL_INIT_CONTROL 0xf328 -#define MV64460_SERIAL_INIT_STATUS 0xf32c - - -#endif /* __INCgt64460rh */ diff --git a/board/prodrive/p3mx/p3mx.c b/board/prodrive/p3mx/p3mx.c deleted file mode 100644 index 28c4eba..0000000 --- a/board/prodrive/p3mx/p3mx.c +++ /dev/null @@ -1,838 +0,0 @@ -/* - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Based on original work by - * Roel Loeffen, (C) Copyright 2006 Prodrive B.V. - * Josh Huber, (C) Copyright 2001 Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com - * modifications for the cpci750 by reinhard.arlt@esd-electronics.com - * modifications for the P3M750 by roel.loeffen@prodrive.nl - */ - -/* - * p3m750.c - main board support/init for the Prodrive p3m750/p3m7448. - */ - -#include <common.h> -#include <74xx_7xx.h> -#include "../../Marvell/include/memory.h" -#include "../../Marvell/include/pci.h" -#include "../../Marvell/include/mv_gen_reg.h" -#include <net.h> -#include <i2c.h> - -#include "eth.h" -#include "mpsc.h" -#include "64460.h" -#include "mv_regs.h" -#include "p3mx.h" - -DECLARE_GLOBAL_DATA_PTR; - -#undef DEBUG -/*#define DEBUG */ - -#ifdef CONFIG_PCI -#define MAP_PCI -#endif /* of CONFIG_PCI */ - -#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -extern flash_info_t flash_info[]; - -/* ------------------------------------------------------------------------- */ - -/* this is the current GT register space location */ -/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */ - -/* Unfortunately, we cant change it while we are in flash, so we initialize it - * to the "final" value. This means that any debug_led calls before - * board_early_init_f wont work right (like in cpu_init_f). - * See also my_remap_gt_regs below. (NTL) - */ - -void board_prebootm_init (void); -unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS; -int display_mem_map (void); -void set_led(int); - -/* ------------------------------------------------------------------------- */ - -/* - * This is a version of the GT register space remapping function that - * doesn't touch globals (meaning, it's ok to run from flash.) - * - * Unfortunately, this has the side effect that a writable - * INTERNAL_REG_BASE_ADDR is impossible. Oh well. - */ - -void my_remap_gt_regs (u32 cur_loc, u32 new_loc) -{ - u32 temp; - - /* check and see if it's already moved */ - temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 16) - return; - - temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 16); - - out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp); - - while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp); -} - -#ifdef CONFIG_PCI - -static void gt_pci_config (void) -{ - unsigned int stat; - unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, */ - /* FuncNum 10:8, RegNum 7:2 */ - - /* - * In PCIX mode devices provide their own bus and device numbers. - * We query the Discovery II's - * config registers by writing ones to the bus and device. - * We then update the Virtual register with the correct value for the - * bus and device. - */ - if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /* if PCI-X */ - GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); - - GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat); - - GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); - GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); - - } - if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /* if PCI-X */ - GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); - GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat); - - GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); - GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); - } - - /* Enable master */ - PCI_MASTER_ENABLE (0, SELF); - PCI_MASTER_ENABLE (1, SELF); - - /* Enable PCI0/1 Mem0 and IO 0 disable all others */ - GT_REG_READ (BASE_ADDR_ENABLE, &stat); - stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | - (1 << 18); - stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15)); - GT_REG_WRITE (BASE_ADDR_ENABLE, stat); - - /* ronen: - * add write to pci remap registers for 64460. - * in 64360 when writing to pci base go and overide remap automaticaly, - * in 64460 it doesn't - */ - GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_SPACE >> 16); - GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_SPACE_PCI >> 16); - GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_SPACE >> 16); - GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_SPACE_PCI >> 16); - GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16); - - GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16); - - /* PCI interface settings */ - /* Timeout set to retry forever */ - GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0); - GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0); - - /* ronen - enable only CS0 and Internal reg!! */ - GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); - GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); - - /* ronen: - * update the pci internal registers base address. - */ -#ifdef MAP_PCI - for (stat = 0; stat <= PCI_HOST1; stat++) - pciWriteConfigReg (stat, - PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, - SELF, CONFIG_SYS_GT_REGS); -#endif - -} -#endif - -/* Setup CPU interface paramaters */ -static void gt_cpu_config (void) -{ - cpu_t cpu = get_cpu_type (); - ulong tmp; - - /* cpu configuration register */ - tmp = GTREGREAD (CPU_CONFIGURATION); - /* set the SINGLE_CPU bit see MV64460 */ -#ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ - tmp |= CPU_CONF_SINGLE_CPU; -#endif - tmp &= ~CPU_CONF_AACK_DELAY_2; - tmp |= CPU_CONF_DP_VALID; - tmp |= CPU_CONF_AP_VALID; - tmp |= CPU_CONF_PIPELINE; - GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */ - - /* CPU master control register */ - tmp = GTREGREAD (CPU_MASTER_CONTROL); - tmp |= CPU_MAST_CTL_ARB_EN; - - if ((cpu == CPU_7400) || - (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) { - - tmp |= CPU_MAST_CTL_CLEAN_BLK; - tmp |= CPU_MAST_CTL_FLUSH_BLK; - - } else { - /* cleanblock must be cleared for CPUs - * that do not support this command (603e, 750) - * see Res#1 */ - tmp &= ~CPU_MAST_CTL_CLEAN_BLK; - tmp &= ~CPU_MAST_CTL_FLUSH_BLK; - } - GT_REG_WRITE (CPU_MASTER_CONTROL, tmp); -} - -/* - * board_early_init_f. - * - * set up gal. device mappings, etc. - */ -int board_early_init_f (void) -{ - /* set up the GT the way the kernel wants it - * the call to move the GT register space will obviously - * fail if it has already been done, but we're going to assume - * that if it's not at the power-on location, it's where we put - * it last time. (huber) - */ - my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS); - -#ifdef CONFIG_PCI - gt_pci_config (); -#endif - /* mask all external interrupt sources */ - GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0); - /* new in >MV6436x */ - GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0); - /* --------------------- */ - GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); - GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); - GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); - - /* Device and Boot bus settings - */ - memoryMapDeviceSpace(DEVICE0, 0, 0); - GT_REG_WRITE(DEVICE_BANK0PARAMETERS, 0); - memoryMapDeviceSpace(DEVICE1, 0, 0); - GT_REG_WRITE(DEVICE_BANK1PARAMETERS, 0); - memoryMapDeviceSpace(DEVICE2, 0, 0); - GT_REG_WRITE(DEVICE_BANK2PARAMETERS, 0); - memoryMapDeviceSpace(DEVICE3, 0, 0); - GT_REG_WRITE(DEVICE_BANK3PARAMETERS, 0); - - GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_BOOT_PAR); - - gt_cpu_config(); - - /* MPP setup */ - GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0); - GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1); - GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2); - GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3); - - GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL); - - set_led(LED_RED); - - return 0; -} - -/* various things to do after relocation */ - -int misc_init_r () -{ - u8 val; - - icache_enable (); -#ifdef CONFIG_SYS_L2 - l2cache_enable (); -#endif -#ifdef CONFIG_MPSC - mpsc_sdma_init (); - mpsc_init2 (); -#endif - - /* - * Enable trickle changing in RTC upon powerup - * No diode, 250 ohm series resistor - */ - val = 0xa5; - i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 8, 1, &val, 1); - - return 0; -} - -void after_reloc (ulong dest_addr, gd_t * gd) -{ - memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE, CONFIG_SYS_BOOT_SIZE); - -/* display_mem_map(); */ - - /* now, jump to the main U-Boot board init code */ - set_led(LED_GREEN); - board_init_r (gd, dest_addr); - /* NOTREACHED */ -} - -/* - * Check Board Identity: - * right now, assume borad type. (there is just one...after all) - */ - -int checkboard (void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf("Board: %s", CONFIG_SYS_BOARD_NAME); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return (0); -} - -void set_led(int col) -{ - int tmp; - int on_pin; - int off_pin; - - /* Program Mpp[22] as Gpp[22] - * Program Mpp[23] as Gpp[23] - */ - tmp = GTREGREAD(MPP_CONTROL2); - tmp &= 0x00ffffff; - GT_REG_WRITE(MPP_CONTROL2,tmp); - - /* Program Gpp[22] and Gpp[23] as output - */ - tmp = GTREGREAD(GPP_IO_CONTROL); - tmp |= 0x00C00000; - GT_REG_WRITE(GPP_IO_CONTROL, tmp); - - /* Program Gpp[22] and Gpp[23] as active high - */ - tmp = GTREGREAD(GPP_LEVEL_CONTROL); - tmp &= 0xff3fffff; - GT_REG_WRITE(GPP_LEVEL_CONTROL, tmp); - - switch(col) { - default: - case LED_OFF : - on_pin = 0; - off_pin = ((1 << 23) | (1 << 22)); - break; - case LED_RED : - on_pin = (1 << 23); - off_pin = (1 << 22); - break; - case LED_GREEN : - on_pin = (1 << 22); - off_pin = (1 << 23); - break; - case LED_ORANGE : - on_pin = ((1 << 23) | (1 << 22)); - off_pin = 0; - break; - } - - /* Set output Gpp[22] and Gpp[23] - */ - tmp = GTREGREAD(GPP_VALUE); - tmp |= on_pin; - tmp &= ~off_pin; - GT_REG_WRITE(GPP_VALUE, tmp); -} - -int display_mem_map (void) -{ - int i; - unsigned int base, size, width; -#ifdef CONFIG_PCI - int j; -#endif - - /* SDRAM */ - printf ("SD (DDR) RAM\n"); - for (i = 0; i <= BANK3; i++) { - base = memoryGetBankBaseAddress (i); - size = memoryGetBankSize (i); - if (size != 0) - printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n", - i, base, size >> 20); - } -#ifdef CONFIG_PCI - /* CPU's PCI windows */ - for (i = 0; i <= PCI_HOST1; i++) { - printf ("\nCPU's PCI %d windows\n", i); - base = pciGetSpaceBase (i, PCI_IO); - size = pciGetSpaceSize (i, PCI_IO); - printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base, - size >> 20); - /* ronen currently only first PCI MEM is used 3 */ - for (j = 0; j <= PCI_REGION0; j++) { - base = pciGetSpaceBase (i, j); - size = pciGetSpaceSize (i, j); - printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", - j, base, size >> 20); - } - } -#endif /* of CONFIG_PCI */ - - /* Bootrom */ - base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */ - size = memoryGetDeviceSize (BOOT_DEVICE); - width = memoryGetDeviceWidth (BOOT_DEVICE) * 8; - printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\t- FLASH\n", - base, size >> 20, width); - - return (0); -} - -/* DRAM check routines copied from gw8260 */ - -#if defined (CONFIG_SYS_DRAM_TEST) - -/*********************************************************************/ -/* NAME: move64() - moves a double word (64-bit) */ -/* */ -/* DESCRIPTION: */ -/* this function performs a double word move from the data at */ -/* the source pointer to the location at the destination pointer. */ -/* */ -/* INPUTS: */ -/* unsigned long long *src - pointer to data to move */ -/* */ -/* OUTPUTS: */ -/* unsigned long long *dest - pointer to locate to move data */ -/* */ -/* RETURNS: */ -/* None */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* May cloober fr0. */ -/* */ -/*********************************************************************/ -static void move64 (unsigned long long *src, unsigned long long *dest) -{ - asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ - "stfd 0, 0(4)" /* *dest = fpr0 */ - : : : "fr0"); /* Clobbers fr0 */ - return; -} - - -#if defined (CONFIG_SYS_DRAM_TEST_DATA) - -unsigned long long pattern[] = { - 0xaaaaaaaaaaaaaaaaULL, - 0xccccccccccccccccULL, - 0xf0f0f0f0f0f0f0f0ULL, - 0xff00ff00ff00ff00ULL, - 0xffff0000ffff0000ULL, - 0xffffffff00000000ULL, - 0x00000000ffffffffULL, - 0x0000ffff0000ffffULL, - 0x00ff00ff00ff00ffULL, - 0x0f0f0f0f0f0f0f0fULL, - 0x3333333333333333ULL, - 0x5555555555555555ULL -}; - -/*********************************************************************/ -/* NAME: mem_test_data() - test data lines for shorts and opens */ -/* */ -/* DESCRIPTION: */ -/* Tests data lines for shorts and opens by forcing adjacent data */ -/* to opposite states. Because the data lines could be routed in */ -/* an arbitrary manner the must ensure test patterns ensure that */ -/* every case is tested. By using the following series of binary */ -/* patterns every combination of adjacent bits is test regardless */ -/* of routing. */ -/* */ -/* ...101010101010101010101010 */ -/* ...110011001100110011001100 */ -/* ...111100001111000011110000 */ -/* ...111111110000000011111111 */ -/* */ -/* Carrying this out, gives us six hex patterns as follows: */ -/* */ -/* 0xaaaaaaaaaaaaaaaa */ -/* 0xcccccccccccccccc */ -/* 0xf0f0f0f0f0f0f0f0 */ -/* 0xff00ff00ff00ff00 */ -/* 0xffff0000ffff0000 */ -/* 0xffffffff00000000 */ -/* */ -/* The number test patterns will always be given by: */ -/* */ -/* log(base 2)(number data bits) = log2 (64) = 6 */ -/* */ -/* To test for short and opens to other signals on our boards. we */ -/* simply */ -/* test with the 1's complemnt of the paterns as well. */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* Assumes only one one SDRAM bank */ -/* */ -/*********************************************************************/ -int mem_test_data (void) -{ - unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START; - unsigned long long temp64 = 0; - int num_patterns = sizeof (pattern) / sizeof (pattern[0]); - int i; - unsigned int hi, lo; - - for (i = 0; i < num_patterns; i++) { - move64 (&(pattern[i]), pmem); - move64 (pmem, &temp64); - - /* hi = (temp64>>32) & 0xffffffff; */ - /* lo = temp64 & 0xffffffff; */ - /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */ - - hi = (pattern[i] >> 32) & 0xffffffff; - lo = pattern[i] & 0xffffffff; - /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */ - - if (temp64 != pattern[i]) { - printf ("\n Data Test Failed, pattern 0x%08x%08x", - hi, lo); - return 1; - } - } - - return 0; -} -#endif /* CONFIG_SYS_DRAM_TEST_DATA */ - -#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS) -/*********************************************************************/ -/* NAME: mem_test_address() - test address lines */ -/* */ -/* DESCRIPTION: */ -/* This function performs a test to verify that each word im */ -/* memory is uniquly addressable. The test sequence is as follows: */ -/* */ -/* 1) write the address of each word to each word. */ -/* 2) verify that each location equals its address */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern and address */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_test_address (void) -{ - volatile unsigned int *pmem = - (volatile unsigned int *) CONFIG_SYS_MEMTEST_START; - const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4; - unsigned int i; - - /* write address to each location */ - for (i = 0; i < size; i++) - pmem[i] = i; - - /* verify each loaction */ - for (i = 0; i < size; i++) { - if (pmem[i] != i) { - printf ("\n Address Test Failed at 0x%x", i); - return 1; - } - } - return 0; -} -#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */ - -#if defined (CONFIG_SYS_DRAM_TEST_WALK) -/*********************************************************************/ -/* NAME: mem_march() - memory march */ -/* */ -/* DESCRIPTION: */ -/* Marches up through memory. At each location verifies rmask if */ -/* read = 1. At each location write wmask if write = 1. Displays */ -/* failing address and pattern. */ -/* */ -/* INPUTS: */ -/* volatile unsigned long long * base - start address of test */ -/* unsigned int size - number of dwords(64-bit) to test */ -/* unsigned long long rmask - read verify mask */ -/* unsigned long long wmask - wrtie verify mask */ -/* short read - verifies rmask if read = 1 */ -/* short write - writes wmask if write = 1 */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern and address */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_march (volatile unsigned long long *base, - unsigned int size, - unsigned long long rmask, - unsigned long long wmask, short read, short write) -{ - unsigned int i; - unsigned long long temp = 0; - unsigned int hitemp, lotemp, himask, lomask; - - for (i = 0; i < size; i++) { - if (read != 0) { - /* temp = base[i]; */ - move64 ((unsigned long long *) &(base[i]), &temp); - if (rmask != temp) { - hitemp = (temp >> 32) & 0xffffffff; - lotemp = temp & 0xffffffff; - himask = (rmask >> 32) & 0xffffffff; - lomask = rmask & 0xffffffff; - - printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp); - return 1; - } - } - if (write != 0) { - /* base[i] = wmask; */ - move64 (&wmask, (unsigned long long *) &(base[i])); - } - } - return 0; -} -#endif /* CONFIG_SYS_DRAM_TEST_WALK */ - -/*********************************************************************/ -/* NAME: mem_test_walk() - a simple walking ones test */ -/* */ -/* DESCRIPTION: */ -/* Performs a walking ones through entire physical memory. The */ -/* test uses as series of memory marches, mem_march(), to verify */ -/* and write the test patterns to memory. The test sequence is as */ -/* follows: */ -/* 1) march writing 0000...0001 */ -/* 2) march verifying 0000...0001 , writing 0000...0010 */ -/* 3) repeat step 2 shifting masks left 1 bit each time unitl */ -/* the write mask equals 1000...0000 */ -/* 4) march verifying 1000...0000 */ -/* The test fails if any of the memory marches return a failure. */ -/* */ -/* OUTPUTS: */ -/* Displays which pass on the memory test is executing */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_test_walk (void) -{ - unsigned long long mask; - volatile unsigned long long *pmem = - (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START; - const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8; - - unsigned int i; - - mask = 0x01; - - printf ("Initial Pass"); - mem_march (pmem, size, 0x0, 0x1, 0, 1); - - printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); - printf (" "); - printf (" "); - printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); - - for (i = 0; i < 63; i++) { - printf ("Pass %2d", i + 2); - if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) { - /*printf("mask: 0x%x, pass: %d, ", mask, i); */ - return 1; - } - mask = mask << 1; - printf ("\b\b\b\b\b\b\b"); - } - - printf ("Last Pass"); - if (mem_march (pmem, size, 0, mask, 0, 1) != 0) { - /* printf("mask: 0x%x", mask); */ - return 1; - } - printf ("\b\b\b\b\b\b\b\b\b"); - printf (" "); - printf ("\b\b\b\b\b\b\b\b\b"); - - return 0; -} - -/*********************************************************************/ -/* NAME: testdram() - calls any enabled memory tests */ -/* */ -/* DESCRIPTION: */ -/* Runs memory tests if the environment test variables are set to */ -/* 'y'. */ -/* */ -/* INPUTS: */ -/* testdramdata - If set to 'y', data test is run. */ -/* testdramaddress - If set to 'y', address test is run. */ -/* testdramwalk - If set to 'y', walking ones test is run */ -/* */ -/* OUTPUTS: */ -/* None */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int testdram (void) -{ - int rundata = 0; - int runaddress = 0; - int runwalk = 0; - -#ifdef CONFIG_SYS_DRAM_TEST_DATA - rundata = getenv_yesno("testdramdata") == 1; -#endif -#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS - runaddress = getenv_yesno("testdramaddress") == 1; -#endif -#ifdef CONFIG_SYS_DRAM_TEST_WALK - runwalk = getenv_yesno("testdramwalk") == 1; -#endif - - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) - printf ("Testing RAM from 0x%08x to 0x%08x ... " - "(don't panic... that will take a moment !!!!)\n", - CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END); -#ifdef CONFIG_SYS_DRAM_TEST_DATA - if (rundata == 1) { - printf ("Test DATA ... "); - if (mem_test_data () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif -#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS - if (runaddress == 1) { - printf ("Test ADDRESS ... "); - if (mem_test_address () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif -#ifdef CONFIG_SYS_DRAM_TEST_WALK - if (runwalk == 1) { - printf ("Test WALKING ONEs ... "); - if (mem_test_walk () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) - printf ("passed\n"); - return 0; - -} -#endif /* CONFIG_SYS_DRAM_TEST */ - -/* ronen - the below functions are used by the bootm function */ -/* - we map the base register to fbe00000 (same mapping as in the LSP) */ -/* - we turn off the RX gig dmas - to prevent the dma from overunning */ -/* the kernel data areas. */ -/* - we diable and invalidate the icache and dcache. */ -void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc) -{ - u32 temp; - - temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE)); - if ((temp & 0xffff) == new_loc >> 16) - return; - - temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) & - 0xffff0000) | (new_loc >> 16); - - out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp); - - while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE | - new_loc | - (INTERNAL_SPACE_DECODE))))) - != temp); - -} - -int board_eth_init(bd_t *bis) -{ - return mv6446x_eth_initialize(bis); -} diff --git a/board/prodrive/p3mx/p3mx.h b/board/prodrive/p3mx/p3mx.h deleted file mode 100644 index e6518cb..0000000 --- a/board/prodrive/p3mx/p3mx.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * (C) Copyright 2005 - * - * Roel Loeffen, (C) Copyright 2006 Prodrive B.V. roel.loeffen@prodrive.nl - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __P3MX_H__ -#define __P3MX_H__ - -#define LED_OFF 1 -#define LED_GREEN 2 -#define LED_RED 3 -#define LED_ORANGE 4 - -#endif /* __P3MX_H__ */ diff --git a/board/prodrive/p3mx/pci.c b/board/prodrive/p3mx/pci.c deleted file mode 100644 index 56cdfc2..0000000 --- a/board/prodrive/p3mx/pci.c +++ /dev/null @@ -1,1003 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* PCI.c - PCI functions */ - - -#include <common.h> -#ifdef CONFIG_PCI -#include <pci.h> - -#include "../../Marvell/include/pci.h" - -#undef DEBUG -#undef IDE_SET_NATIVE_MODE -static unsigned int local_buses[] = { 0, 0 }; - -static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = { - {0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 }, - {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 }, -}; - -#ifdef CONFIG_USE_CPCIDVI -typedef struct { - unsigned int base; - unsigned int init; -} GT_CPCIDVI_ROM_T; - -static GT_CPCIDVI_ROM_T gt_cpcidvi_rom = {0, 0}; -#endif - -#ifdef DEBUG -static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE }; -static void gt_pci_bus_mode_display (PCI_HOST host) -{ - unsigned int mode; - - - mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4; - switch (mode) { - case 0: - printf ("PCI %d bus mode: Conventional PCI\n", host); - break; - case 1: - printf ("PCI %d bus mode: 66 MHz PCIX\n", host); - break; - case 2: - printf ("PCI %d bus mode: 100 MHz PCIX\n", host); - break; - case 3: - printf ("PCI %d bus mode: 133 MHz PCIX\n", host); - break; - default: - printf ("Unknown BUS %d\n", mode); - } -} -#endif - -static const unsigned int pci_p2p_configuration_reg[] = { - PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION -}; - -static const unsigned int pci_configuration_address[] = { - PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS -}; - -static const unsigned int pci_configuration_data[] = { - PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, - PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER -}; - -static const unsigned int pci_error_cause_reg[] = { - PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE -}; - -static const unsigned int pci_arbiter_control[] = { - PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL -}; - -static const unsigned int pci_address_space_en[] = { - PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE -}; - -static const unsigned int pci_snoop_control_base_0_low[] = { - PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW -}; -static const unsigned int pci_snoop_control_top_0[] = { - PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0 -}; - -static const unsigned int pci_access_control_base_0_low[] = { - PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW -}; -static const unsigned int pci_access_control_top_0[] = { - PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0 -}; - -static const unsigned int pci_scs_bank_size[2][4] = { - {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE, - PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE}, - {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE, - PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE} -}; - -static const unsigned int pci_p2p_configuration[] = { - PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION -}; - - -/******************************************************************** -* pciWriteConfigReg - Write to a PCI configuration register -* - Make sure the GT is configured as a master before writing -* to another device on the PCI. -* - The function takes care of Big/Little endian conversion. -* -* -* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec -* (or any other PCI device spec) -* pciDevNum: The device number needs to be addressed. -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum, unsigned int data) -{ - volatile unsigned int DataForAddrReg; - unsigned int functionNum; - unsigned int busNum = 0; - unsigned int addr; - - if (pciDevNum > 32) /* illegal device Number */ - return; - if (pciDevNum == SELF) { /* configure our configuration space. */ - pciDevNum = - (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & - 0x1f; - busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & - 0xff0000; - } - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xfc; - DataForAddrReg = - (regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); - GT_REG_READ (pci_configuration_address[host], &addr); - if (addr != DataForAddrReg) - return; - GT_REG_WRITE (pci_configuration_data[host], data); -} - -/******************************************************************** -* pciReadConfigReg - Read from a PCI0 configuration register -* - Make sure the GT is configured as a master before reading -* from another device on the PCI. -* - The function takes care of Big/Little endian conversion. -* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec) -* pciDevNum: The device number needs to be addressed. -* RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum) -{ - volatile unsigned int DataForAddrReg; - unsigned int data; - unsigned int functionNum; - unsigned int busNum = 0; - - if (pciDevNum > 32) /* illegal device Number */ - return 0xffffffff; - if (pciDevNum == SELF) { /* configure our configuration space. */ - pciDevNum = - (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & - 0x1f; - busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & - 0xff0000; - } - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xfc; - DataForAddrReg = - (regOffset | pciDevNum | functionNum | busNum) | BIT31; - GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); - GT_REG_READ (pci_configuration_address[host], &data); - if (data != DataForAddrReg) - return 0xffffffff; - GT_REG_READ (pci_configuration_data[host], &data); - return data; -} - -/******************************************************************** -* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where -* the agent is placed on another Bus. For more -* information read P2P in the PCI spec. -* -* Inputs: unsigned int regOffset - The register offset as it apears in the -* GT spec (or any other PCI device spec). -* unsigned int pciDevNum - The device number needs to be addressed. -* unsigned int busNum - On which bus does the Target agent connect -* to. -* unsigned int data - data to be written. -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -* The configuration Address is configure as type-I (bits[1:0] = '01') due to -* PCI spec referring to P2P. -* -*********************************************************************/ -void pciOverBridgeWriteConfigReg (PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum, unsigned int data) -{ - unsigned int DataForReg; - unsigned int functionNum; - - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - busNum = busNum << 16; - if (pciDevNum == SELF) { /* This board */ - DataForReg = (regOffset | pciDevNum | functionNum) | BIT0; - } else { - DataForReg = (regOffset | pciDevNum | functionNum | busNum) | - BIT31 | BIT0; - } - GT_REG_WRITE (pci_configuration_address[host], DataForReg); - GT_REG_WRITE (pci_configuration_data[host], data); -} - - -/******************************************************************** -* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where -* the agent target locate on another PCI bus. -* - Make sure the GT is configured as a master -* before reading from another device on the PCI. -* - The function takes care of Big/Little endian -* conversion. -* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec). (configuration register offset.) -* pciDevNum: The device number needs to be addressed. -* busNum: the Bus number where the agent is place. -* RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid -* -* Configuration Address 0xCF8: -* -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number -* |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name -* -*********************************************************************/ -unsigned int pciOverBridgeReadConfigReg (PCI_HOST host, - unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum) -{ - unsigned int DataForReg; - unsigned int data; - unsigned int functionNum; - - functionNum = regOffset & 0x00000700; - pciDevNum = pciDevNum << 11; - regOffset = regOffset & 0xff; - busNum = busNum << 16; - if (pciDevNum == SELF) { /* This board */ - DataForReg = (regOffset | pciDevNum | functionNum) | BIT31; - } else { /* agent on another bus */ - - DataForReg = (regOffset | pciDevNum | functionNum | busNum) | - BIT0 | BIT31; - } - GT_REG_WRITE (pci_configuration_address[host], DataForReg); - GT_REG_READ (pci_configuration_data[host], &data); - return data; -} - - -/******************************************************************** -* pciGetRegOffset - Gets the register offset for this region config. -* -* INPUT: Bus, Region - The bus and region we ask for its base address. -* OUTPUT: N/A -* RETURNS: PCI register base address -*********************************************************************/ -static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region) -{ - switch (host) { - case PCI_HOST0: - switch (region) { - case PCI_IO: - return PCI_0I_O_LOW_DECODE_ADDRESS; - case PCI_REGION0: - return PCI_0MEMORY0_LOW_DECODE_ADDRESS; - case PCI_REGION1: - return PCI_0MEMORY1_LOW_DECODE_ADDRESS; - case PCI_REGION2: - return PCI_0MEMORY2_LOW_DECODE_ADDRESS; - case PCI_REGION3: - return PCI_0MEMORY3_LOW_DECODE_ADDRESS; - } - case PCI_HOST1: - switch (region) { - case PCI_IO: - return PCI_1I_O_LOW_DECODE_ADDRESS; - case PCI_REGION0: - return PCI_1MEMORY0_LOW_DECODE_ADDRESS; - case PCI_REGION1: - return PCI_1MEMORY1_LOW_DECODE_ADDRESS; - case PCI_REGION2: - return PCI_1MEMORY2_LOW_DECODE_ADDRESS; - case PCI_REGION3: - return PCI_1MEMORY3_LOW_DECODE_ADDRESS; - } - } - return PCI_0MEMORY0_LOW_DECODE_ADDRESS; -} - -static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region) -{ - switch (host) { - case PCI_HOST0: - switch (region) { - case PCI_IO: - return PCI_0I_O_ADDRESS_REMAP; - case PCI_REGION0: - return PCI_0MEMORY0_ADDRESS_REMAP; - case PCI_REGION1: - return PCI_0MEMORY1_ADDRESS_REMAP; - case PCI_REGION2: - return PCI_0MEMORY2_ADDRESS_REMAP; - case PCI_REGION3: - return PCI_0MEMORY3_ADDRESS_REMAP; - } - case PCI_HOST1: - switch (region) { - case PCI_IO: - return PCI_1I_O_ADDRESS_REMAP; - case PCI_REGION0: - return PCI_1MEMORY0_ADDRESS_REMAP; - case PCI_REGION1: - return PCI_1MEMORY1_ADDRESS_REMAP; - case PCI_REGION2: - return PCI_1MEMORY2_ADDRESS_REMAP; - case PCI_REGION3: - return PCI_1MEMORY3_ADDRESS_REMAP; - } - } - return PCI_0MEMORY0_ADDRESS_REMAP; -} - -/******************************************************************** -* pciGetBaseAddress - Gets the base address of a PCI. -* - If the PCI size is 0 then this base address has no meaning!!! -* -* -* INPUT: Bus, Region - The bus and region we ask for its base address. -* OUTPUT: N/A -* RETURNS: PCI base address. -*********************************************************************/ -unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region) -{ - unsigned int regBase; - unsigned int regEnd; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, ®Base); - GT_REG_READ (regOffset + 8, ®End); - - if (regEnd <= regBase) - return 0xffffffff; /* ERROR !!! */ - - regBase = regBase << 16; - return regBase; -} - -bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase, - unsigned int bankBase, unsigned int bankLength) -{ - unsigned int low = 0xfff; - unsigned int high = 0x0; - unsigned int regOffset = pciGetRegOffset (host, region); - unsigned int remapOffset = pciGetRemapOffset (host, region); - - if (bankLength != 0) { - low = (bankBase >> 16) & 0xffff; - high = ((bankBase + bankLength) >> 16) - 1; - } - - GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */ - GT_REG_WRITE (regOffset + 8, high); - - if (bankLength != 0) { /* must do AFTER writing maps */ - GT_REG_WRITE (remapOffset, remapBase >> 16); /* sorry, 32 bits only. - dont support upper 32 - in this driver */ - } - return true; -} - -unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region) -{ - unsigned int low; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, &low); - return (low & 0xffff) << 16; -} - -unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region) -{ - unsigned int low, high; - unsigned int regOffset = pciGetRegOffset (host, region); - - GT_REG_READ (regOffset, &low); - GT_REG_READ (regOffset + 8, &high); - return ((high & 0xffff) + 1) << 16; -} - - -/* ronen - 7/Dec/03*/ -/******************************************************************** -* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS. -* Inputs: one of the PCI BAR -*********************************************************************/ -void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR) -{ - RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR); -} - -void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR) -{ - SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR); -} - -/******************************************************************** -* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave. -* -* Inputs: base and size of PCI SCS -*********************************************************************/ -void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank, - unsigned int pciDramBase, unsigned int pciDramSize) -{ - /*ronen different function for 3rd bank. */ - unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8; - - pciDramBase = pciDramBase & 0xfffff000; - pciDramBase = pciDramBase | (pciReadConfigReg (host, - PCI_SCS_0_BASE_ADDRESS - + offset, - SELF) & 0x00000fff); - pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF, - pciDramBase); - if (pciDramSize == 0) - pciDramSize++; - GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1); - gtPciEnableInternalBAR (host, bank); -} - -/******************************************************************** -* pciSetRegionFeatures - This function modifys one of the 8 regions with -* feature bits given as an input. -* - Be advised to check the spec before modifying them. -* Inputs: PCI_PROTECT_REGION region - one of the eight regions. -* unsigned int features - See file: pci.h there are defintion for those -* region features. -* unsigned int baseAddress - The region base Address. -* unsigned int topAddress - The region top Address. -* Returns: false if one of the parameters is erroneous true otherwise. -*********************************************************************/ -bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region, - unsigned int features, unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int accessLow; - unsigned int accessHigh; - unsigned int accessTop = baseAddress + regionLength; - - if (regionLength == 0) { /* close the region. */ - pciDisableAccessRegion (host, region); - return true; - } - /* base Address is store is bits [11:0] */ - accessLow = (baseAddress & 0xfff00000) >> 20; - /* All the features are update according to the defines in pci.h (to be on - the safe side we disable bits: [11:0] */ - accessLow = accessLow | (features & 0xfffff000); - /* write to the Low Access Region register */ - GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, - accessLow); - - accessHigh = (accessTop & 0xfff00000) >> 20; - - /* write to the High Access Region register */ - GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, - accessHigh - 1); - return true; -} - -/******************************************************************** -* pciDisableAccessRegion - Disable The given Region by writing MAX size -* to its low Address and MIN size to its high Address. -* -* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled. -* Returns: N/A. -*********************************************************************/ -void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region) -{ - /* writing back the registers default values. */ - GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, - 0x01001fff); - GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0); -} - -/******************************************************************** -* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism. -* -* Inputs: N/A -* Returns: true. -*********************************************************************/ -bool pciArbiterEnable (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31); - return true; -} - -/******************************************************************** -* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism. -* -* Inputs: N/A -* Returns: true -*********************************************************************/ -bool pciArbiterDisable (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff); - return true; -} - -/******************************************************************** -* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low) -* -* Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent. -* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent. -* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent. -* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent. -* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent. -* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent. -* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent. -* Returns: true -*********************************************************************/ -bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent, - PCI_AGENT_PRIO externalAgent0, - PCI_AGENT_PRIO externalAgent1, - PCI_AGENT_PRIO externalAgent2, - PCI_AGENT_PRIO externalAgent3, - PCI_AGENT_PRIO externalAgent4, - PCI_AGENT_PRIO externalAgent5) -{ - unsigned int regData; - unsigned int writeData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - writeData = (internalAgent << 7) + (externalAgent0 << 8) + - (externalAgent1 << 9) + (externalAgent2 << 10) + - (externalAgent3 << 11) + (externalAgent4 << 12) + - (externalAgent5 << 13); - regData = (regData & 0xffffc07f) | writeData; - GT_REG_WRITE (pci_arbiter_control[host], regData & regData); - return true; -} - -/******************************************************************** -* pciParkingDisable - Park on last option disable, with this function you can -* disable the park on last mechanism for each agent. -* disabling this option for all agents results parking -* on the internal master. -* -* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent. -* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. -* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. -* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. -* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. -* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. -* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. -* Returns: true -*********************************************************************/ -bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent, - PCI_AGENT_PARK externalAgent0, - PCI_AGENT_PARK externalAgent1, - PCI_AGENT_PARK externalAgent2, - PCI_AGENT_PARK externalAgent3, - PCI_AGENT_PARK externalAgent4, - PCI_AGENT_PARK externalAgent5) -{ - unsigned int regData; - unsigned int writeData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - writeData = (internalAgent << 14) + (externalAgent0 << 15) + - (externalAgent1 << 16) + (externalAgent2 << 17) + - (externalAgent3 << 18) + (externalAgent4 << 19) + - (externalAgent5 << 20); - regData = (regData & ~(0x7f << 14)) | writeData; - GT_REG_WRITE (pci_arbiter_control[host], regData); - return true; -} - -/******************************************************************** -* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to -* respond to grant assertion within a window specified in -* the input value: 'brokenValue'. -* -* Inputs: unsigned char brokenValue - A value which limits the Master to hold the -* grant without asserting frame. -* Returns: Error for illegal broken value otherwise true. -*********************************************************************/ -bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue) -{ - unsigned int data; - unsigned int regData; - - if (brokenValue > 0xf) - return false; /* brokenValue must be 4 bit */ - data = brokenValue << 3; - GT_REG_READ (pci_arbiter_control[host], ®Data); - regData = (regData & 0xffffff87) | data; - GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1); - return true; -} - -/******************************************************************** -* pciDisableBrokenAgentDetection - This function disable the Broken agent -* Detection mechanism. -* NOTE: This operation may cause a dead lock on the -* pci0 arbitration. -* -* Inputs: N/A -* Returns: true. -*********************************************************************/ -bool pciDisableBrokenAgentDetection (PCI_HOST host) -{ - unsigned int regData; - - GT_REG_READ (pci_arbiter_control[host], ®Data); - regData = regData & 0xfffffffd; - GT_REG_WRITE (pci_arbiter_control[host], regData); - return true; -} - -/******************************************************************** -* pciP2PConfig - This function set the PCI_n P2P configurate. -* For more information on the P2P read PCI spec. -* -* Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower -* Boundry. -* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper -* Boundry. -* unsigned int busNum - The CPI bus number to which the PCI interface -* is connected. -* unsigned int devNum - The PCI interface's device number. -* -* Returns: true. -*********************************************************************/ -bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow, - unsigned int SecondBusHigh, - unsigned int busNum, unsigned int devNum) -{ - unsigned int regData; - - regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) | - ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24); - GT_REG_WRITE (pci_p2p_configuration[host], regData); - return true; -} - -/******************************************************************** -* pciSetRegionSnoopMode - This function modifys one of the 4 regions which -* supports Cache Coherency in the PCI_n interface. -* Inputs: region - One of the four regions. -* snoopType - There is four optional Types: -* 1. No Snoop. -* 2. Snoop to WT region. -* 3. Snoop to WB region. -* 4. Snoop & Invalidate to WB region. -* baseAddress - Base Address of this region. -* regionLength - Region length. -* Returns: false if one of the parameters is wrong otherwise return true. -*********************************************************************/ -bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region, - PCI_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength) -{ - unsigned int snoopXbaseAddress; - unsigned int snoopXtopAddress; - unsigned int data; - unsigned int snoopHigh = baseAddress + regionLength; - - if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB)) - return false; - snoopXbaseAddress = - pci_snoop_control_base_0_low[host] + 0x10 * region; - snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region; - if (regionLength == 0) { /* closing the region */ - GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff); - GT_REG_WRITE (snoopXtopAddress, 0); - return true; - } - baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ - data = (baseAddress >> 20) | snoopType << 12; - GT_REG_WRITE (snoopXbaseAddress, data); - snoopHigh = (snoopHigh & 0xfff00000) >> 20; - GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1); - return true; -} - -static int gt_read_config_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, u32 * value) -{ - int bus = PCI_BUS (dev); - - if ((bus == local_buses[0]) || (bus == local_buses[1])) { - *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset, - PCI_DEV (dev)); - } else { - *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose-> - cfg_addr, offset, - PCI_DEV (dev), bus); - } - - return 0; -} - -static int gt_write_config_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, u32 value) -{ - int bus = PCI_BUS (dev); - - if ((bus == local_buses[0]) || (bus == local_buses[1])) { - pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset, - PCI_DEV (dev), value); - } else { - pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr, - offset, PCI_DEV (dev), bus, - value); - } - return 0; -} - - -static void gt_setup_ide (struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *entry) -{ - static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 }; - u32 bar_response, bar_value; - int bar; - - for (bar = 0; bar < 6; bar++) { - /*ronen different function for 3rd bank. */ - unsigned int offset = - (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8; - - pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset, - 0x0); - pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset, - &bar_response); - - pciauto_region_allocate (bar_response & - PCI_BASE_ADDRESS_SPACE_IO ? hose-> - pci_io : hose->pci_mem, ide_bar[bar], - &bar_value); - - pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + bar * 4, - bar_value); - } -} - -#ifdef CONFIG_USE_CPCIDVI -static void gt_setup_cpcidvi (struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *entry) -{ - u32 bar_value, pci_response; - - pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response); - pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff); - pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pci_response); - pciauto_region_allocate (hose->pci_mem, 0x01000000, &bar_value); - pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, (bar_value & 0xffffff00)); - pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, 0x0); - pciauto_region_allocate (hose->pci_mem, 0x40000, &bar_value); - pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, (bar_value & 0xffffff00) | 0x01); - gt_cpcidvi_rom.base = bar_value & 0xffffff00; - gt_cpcidvi_rom.init = 1; -} - -unsigned char gt_cpcidvi_in8(unsigned int offset) -{ - unsigned char data; - - if (gt_cpcidvi_rom.init == 0) { - return(0); - } - data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base); - return(data); -} - -void gt_cpcidvi_out8(unsigned int offset, unsigned char data) -{ - unsigned int off; - - if (gt_cpcidvi_rom.init == 0) { - return; - } - off = data; - off = ((off << 3) & 0x7f8) + (offset & 0x4) + 0x3e000 + gt_cpcidvi_rom.base; - in8(off); - return; -} -#endif - -/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */ -/* and is curently not called *. */ -#if 0 -static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char pin, irq; - - pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin); - - if (pin == 1) { /* only allow INT A */ - irq = pci_irq_swizzle[(PCI_HOST) hose-> - cfg_addr][PCI_DEV (dev)]; - if (irq) - pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq); - } -} -#endif - -struct pci_config_table gt_config_table[] = { -#ifdef CONFIG_USE_CPCIDVI - {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030, PCI_CLASS_DISPLAY_VGA, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_cpcidvi}, -#endif - {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide}, - {} -}; - -struct pci_controller pci0_hose = { -/* fixup_irq: gt_fixup_irq, */ - config_table:gt_config_table, -}; - -struct pci_controller pci1_hose = { -/* fixup_irq: gt_fixup_irq, */ - config_table:gt_config_table, -}; - -void pci_init_board (void) -{ - unsigned int command; -#ifdef CONFIG_PCI_PNP - unsigned int bar; -#endif -#ifdef DEBUG - gt_pci_bus_mode_display (PCI_HOST0); -#endif -#ifdef CONFIG_USE_CPCIDVI - gt_cpcidvi_rom.init = 0; - gt_cpcidvi_rom.base = 0; -#endif - - pci0_hose.config_table = gt_config_table; - pci1_hose.config_table = gt_config_table; - -#ifdef CONFIG_USE_CPCIDVI - gt_config_table[0].config_device = gt_setup_cpcidvi; -#endif - gt_config_table[1].config_device = gt_setup_ide; - - pci0_hose.first_busno = 0; - pci0_hose.last_busno = 0xff; - local_buses[0] = pci0_hose.first_busno; - - /* PCI memory space */ - pci_set_region (pci0_hose.regions + 0, - CONFIG_SYS_PCI0_0_MEM_SPACE, - CONFIG_SYS_PCI0_0_MEM_SPACE, - CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (pci0_hose.regions + 1, - CONFIG_SYS_PCI0_IO_SPACE_PCI, - CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO); - - pci_set_ops (&pci0_hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - gt_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - gt_write_config_dword); - pci0_hose.region_count = 2; - - pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0; - - pci_register_hose (&pci0_hose); - pciArbiterDisable(PCI_HOST0); /* on PMC modules no arbiter is used */ - pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1); - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - -#ifdef CONFIG_PCI_PNP - pciauto_config_init(&pci0_hose); - pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar); -#endif -#ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Bus Dev VenId DevId Class Int\n"); -#endif - pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose, pci0_hose.first_busno); - -#ifdef DEBUG - gt_pci_bus_mode_display (PCI_HOST1); -#endif - pci1_hose.first_busno = pci0_hose.last_busno + 1; - pci1_hose.last_busno = 0xff; - pci1_hose.current_busno = pci1_hose.first_busno; - local_buses[1] = pci1_hose.first_busno; - - /* PCI memory space */ - pci_set_region (pci1_hose.regions + 0, - CONFIG_SYS_PCI1_0_MEM_SPACE, - CONFIG_SYS_PCI1_0_MEM_SPACE, - CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (pci1_hose.regions + 1, - CONFIG_SYS_PCI1_IO_SPACE_PCI, - CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); - - pci_set_ops (&pci1_hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - gt_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - gt_write_config_dword); - - pci1_hose.region_count = 2; - - pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1; - - pci_register_hose (&pci1_hose); - - pciArbiterEnable (PCI_HOST1); - pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1); - - command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); - -#ifdef CONFIG_PCI_PNP - pciauto_config_init(&pci1_hose); - pciauto_region_allocate(pci1_hose.pci_io, 0x400, &bar); -#endif - pci1_hose.last_busno = pci_hose_scan_bus (&pci1_hose, pci1_hose.first_busno); - - command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); - -} -#endif /* of CONFIG_PCI */ diff --git a/board/prodrive/p3mx/sdram_init.c b/board/prodrive/p3mx/sdram_init.c deleted file mode 100644 index 4220930..0000000 --- a/board/prodrive/p3mx/sdram_init.c +++ /dev/null @@ -1,418 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************* - * adaption for the Marvell DB64460 Board - * Ingo Assmus (ingo.assmus@keymile.com) - *************************************************************************/ - -/* sdram_init.c - automatic memory sizing */ - -#include <common.h> -#include <74xx_7xx.h> -#include "../../Marvell/include/memory.h" -#include "../../Marvell/include/pci.h" -#include "../../Marvell/include/mv_gen_reg.h" -#include <net.h> - -#include "eth.h" -#include "mpsc.h" -#include "../../Marvell/common/i2c.h" -#include "64460.h" -#include "mv_regs.h" - -DECLARE_GLOBAL_DATA_PTR; - -#undef DEBUG -#define MAP_PCI - -#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - -int set_dfcdlInit (void); /* setup delay line of Mv64460 */ -int mvDmaIsChannelActive (int); -int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong); -int mvDmaTransfer (int, ulong, ulong, ulong, ulong); - -#define D_CACHE_FLUSH_LINE(addr, offset) \ - { \ - __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ - } - -int memory_map_bank (unsigned int bankNo, - unsigned int bankBase, unsigned int bankLength) -{ -#if defined (MAP_PCI) && defined (CONFIG_PCI) - PCI_HOST host; -#endif - -#ifdef DEBUG - if (bankLength > 0) { - printf ("mapping bank %d at %08x - %08x\n", - bankNo, bankBase, bankBase + bankLength - 1); - } else { - printf ("unmapping bank %d\n", bankNo); - } -#endif - - memoryMapBank (bankNo, bankBase, bankLength); - -#if defined (MAP_PCI) && defined (CONFIG_PCI) - for (host = PCI_HOST0; host <= PCI_HOST1; host++) { - const int features = - PREFETCH_ENABLE | - DELAYED_READ_ENABLE | - AGGRESSIVE_PREFETCH | - READ_LINE_AGGRESSIVE_PREFETCH | - READ_MULTI_AGGRESSIVE_PREFETCH | - MAX_BURST_4 | PCI_NO_SWAP; - - pciMapMemoryBank (host, bankNo, bankBase, bankLength); - - pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase, - bankLength); - - pciSetRegionFeatures (host, bankNo, features, bankBase, - bankLength); - } -#endif - - return 0; -} - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ -long int dram_size (long int *base, long int maxsize) -{ - volatile long int *addr, *b = base; - long int cnt, val, save1, save2; - -#define STARTVAL (1<<20) /* start test at 1M */ - for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long); - cnt <<= 1) { - addr = base + cnt; /* pointer arith! */ - - save1 = *addr; /* save contents of addr */ - save2 = *b; /* save contents of base */ - - *addr = cnt; /* write cnt to addr */ - *b = 0; /* put null at base */ - - /* check at base address */ - if ((*b) != 0) { - *addr = save1; /* restore *addr */ - *b = save2; /* restore *b */ - return (0); - } - val = *addr; /* read *addr */ - val = *addr; /* read *addr */ - - *addr = save1; - *b = save2; - - if (val != cnt) { - DP (printf - ("Found %08x at Address %08x (failure)\n", - (unsigned int) val, (unsigned int) addr)); - /* fix boundary condition.. STARTVAL means zero */ - if (cnt == STARTVAL / sizeof (long)) - cnt = 0; - return (cnt * sizeof (long)); - } - } - - return maxsize; -} - -#define SDRAM_NORMAL 0x0 -#define SDRAM_PRECHARGE_ALL 0x1 -#define SDRAM_REFRESH_ALL 0x2 -#define SDRAM_MODE_REG_SETUP 0x3 -#define SDRAM_XTEN_MODE_REG_SETUP 0x4 -#define SDRAM_NOP 0x5 -#define SDRAM_SELF_REFRESH 0x7 - -phys_size_t initdram (int board_type) -{ - int tmp; - int start; - ulong size; - ulong memSpaceAttr; - ulong dest; - - /* first disable all banks */ - memory_map_bank(0, 0, 0); - memory_map_bank(1, 0, 0); - memory_map_bank(2, 0, 0); - memory_map_bank(3, 0, 0); - - /* calibrate delay lines */ - set_dfcdlInit(); - - GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_NOP); /* 0x1418 */ - do { - tmp = GTREGREAD(MV64460_SDRAM_OPERATION); - } while(tmp != 0x0); - - /* SDRAM controller configuration */ -#ifdef CONFIG_MV64460_ECC - GT_REG_WRITE(MV64460_SDRAM_CONFIG, 0x58201400); /* 0x1400 */ -#else - GT_REG_WRITE(MV64460_SDRAM_CONFIG, 0x58200400); /* 0x1400 */ -#endif - GT_REG_WRITE(MV64460_D_UNIT_CONTROL_LOW, 0xC3000540); /* 0x1404 */ - GT_REG_WRITE(MV64460_D_UNIT_CONTROL_HIGH, 0x0300F777); /* 0x1424 */ - GT_REG_WRITE(MV64460_SDRAM_TIMING_CONTROL_LOW, 0x01712220); /* 0x1408 */ - GT_REG_WRITE(MV64460_SDRAM_TIMING_CONTROL_HIGH, 0x0000005D); /* 0x140C */ - GT_REG_WRITE(MV64460_SDRAM_ADDR_CONTROL, 0x00000012); /* 0x1410 */ - GT_REG_WRITE(MV64460_SDRAM_OPEN_PAGES_CONTROL, 0x00000001); /* 0x1414 */ - - /* SDRAM drive strength */ - GT_REG_WRITE(MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x80000000); /* 0x14C0 */ - GT_REG_WRITE(MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x80000008); /* 0x14C0 */ - GT_REG_WRITE(MV64460_SDRAM_DATA_PADS_CALIBRATION, 0x80000000); /* 0x14C4 */ - GT_REG_WRITE(MV64460_SDRAM_DATA_PADS_CALIBRATION, 0x80000008); /* 0x14C4 */ - - /* setup SDRAM device registers */ - - /* precharge all */ - GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_PRECHARGE_ALL); /* 0x1418 */ - do { - tmp = GTREGREAD(MV64460_SDRAM_OPERATION); - } while(tmp != 0x0); - - /* enable DLL */ - GT_REG_WRITE(MV64460_EXTENDED_DRAM_MODE, 0x00000000); /* 0x1420 */ - GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_XTEN_MODE_REG_SETUP); /* 0x1418 */ - do { - tmp = GTREGREAD(MV64460_SDRAM_OPERATION); - } while(tmp != 0x0); - - /* reset DLL */ - GT_REG_WRITE(MV64460_SDRAM_MODE, 0x00000132); /* 0x141C */ - GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_MODE_REG_SETUP); /* 0x1418 */ - do { - tmp = GTREGREAD(MV64460_SDRAM_OPERATION); - } while(tmp != 0x0); - - /* precharge all */ - GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_PRECHARGE_ALL); /* 0x1418 */ - do { - tmp = GTREGREAD(MV64460_SDRAM_OPERATION); - } while(tmp != 0x0); - - /* wait for 2 auto refresh commands */ - udelay(20); - - /* un-reset DLL */ - GT_REG_WRITE(MV64460_SDRAM_MODE, 0x00000032); /* 0x141C */ - GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_MODE_REG_SETUP); /* 0x1418 */ - do { - tmp = GTREGREAD(MV64460_SDRAM_OPERATION); - } while(tmp != 0x0); - - /* wait 200 cycles */ - udelay(2); /* FIXME make this dynamic for the system clock */ - - /* SDRAM init done */ - memory_map_bank(0, CONFIG_SYS_SDRAM_BASE, (256 << 20)); -#ifdef CONFIG_SYS_SDRAM1_BASE - memory_map_bank(1, CONFIG_SYS_SDRAM1_BASE, (256 << 20)); -#endif - - /* DUNIT_MMASK: enable SnoopHitEn bit to avoid errata CPU-#4 - */ - tmp = GTREGREAD(MV64460_D_UNIT_MMASK); /* 0x14B0 */ - GT_REG_WRITE(MV64460_D_UNIT_MMASK, tmp | 0x2); - - start = (0 << 20); -#ifdef CONFIG_P3M750 - size = (512 << 20); -#elif defined (CONFIG_P3M7448) - size = (128 << 20); -#endif - -#ifdef CONFIG_MV64460_ECC - memSpaceAttr = ((~(BIT0 << 0)) & 0xf) << 8; - mvDmaSetMemorySpace (0, 0, memSpaceAttr, start, size); - for (dest = start; dest < start + size; dest += _8M) { - mvDmaTransfer (0, start, dest, _8M, - BIT8 /*DMA_DTL_128BYTES */ | - BIT3 /*DMA_HOLD_SOURCE_ADDR */ | - BIT11 /*DMA_BLOCK_TRANSFER_MODE */ ); - while (mvDmaIsChannelActive (0)); - } -#endif - - return (size); -} - -void board_add_ram_info(int use_default) -{ - u32 val; - - puts(" (CL="); - switch ((GTREGREAD(MV64460_SDRAM_MODE) >> 4) & 0x7) { - case 0x2: - puts("2"); - break; - case 0x3: - puts("3"); - break; - case 0x5: - puts("1.5"); - break; - case 0x6: - puts("2.5"); - break; - } - - val = GTREGREAD(MV64460_SDRAM_CONFIG); - - puts(", ECC "); - if (val & 0x00001000) - puts("enabled)"); - else - puts("not enabled)"); -} - -/* - * mvDmaIsChannelActive - Check if IDMA channel is active - * - * channel = IDMA channel number from 0 to 7 - */ -int mvDmaIsChannelActive (int channel) -{ - ulong data; - - data = GTREGREAD (MV64460_DMA_CHANNEL0_CONTROL + 4 * channel); - if (data & BIT14) /* activity status */ - return 1; - - return 0; -} - -/* - * mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding - * map. - * - * memSpace = IDMA memory window number from 0 to 7 - * trg_if = Target interface: - * 0x0 DRAM - * 0x1 Device Bus - * 0x2 Integrated SDRAM (or CPU bus 60x only) - * 0x3 PCI0 - * 0x4 PCI1 - * attr = IDMA attributes (see MV datasheet) - * base_addr = Sets up memory window for transfers - * - */ -int mvDmaSetMemorySpace (ulong memSpace, - ulong trg_if, - ulong attr, ulong base_addr, ulong size) -{ - ulong temp; - - /* The base address must be aligned to the size. */ - if (base_addr % size != 0) - return 0; - - if (size >= 0x10000) { /* 64K */ - size &= 0xffff0000; - base_addr = (base_addr & 0xffff0000); - /* Set the new attributes */ - GT_REG_WRITE (MV64460_DMA_BASE_ADDR_REG0 + memSpace * 8, - (base_addr | trg_if | attr)); - GT_REG_WRITE ((MV64460_DMA_SIZE_REG0 + memSpace * 8), - (size - 1) & 0xffff0000); - temp = GTREGREAD (MV64460_DMA_BASE_ADDR_ENABLE_REG); - GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG, - (temp & ~(BIT0 << memSpace))); - return 1; - } - - return 0; -} - -/* - * mvDmaTransfer - Transfer data from src_addr to dst_addr on one of the 4 - * DMA channels. - * - * channel = IDMA channel number from 0 to 3 - * destAddr = Destination address - * sourceAddr = Source address - * size = Size in bytes - * command = See MV datasheet - * - */ -int mvDmaTransfer (int channel, ulong sourceAddr, - ulong destAddr, ulong size, ulong command) -{ - ulong engOffReg = 0; /* Engine Offset Register */ - - if (size > 0xffff) - command = command | BIT31; /* DMA_16M_DESCRIPTOR_MODE */ - command = command | ((command >> 6) & 0x7); - engOffReg = channel * 4; - GT_REG_WRITE (MV64460_DMA_CHANNEL0_BYTE_COUNT + engOffReg, size); - GT_REG_WRITE (MV64460_DMA_CHANNEL0_SOURCE_ADDR + engOffReg, sourceAddr); - GT_REG_WRITE (MV64460_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg, destAddr); - command = command | - BIT12 | /* DMA_CHANNEL_ENABLE */ - BIT9; /* DMA_NON_CHAIN_MODE */ - /* Activate DMA channel By writting to mvDmaControlRegister */ - GT_REG_WRITE (MV64460_DMA_CHANNEL0_CONTROL + engOffReg, command); - return 1; -} - -/**************************************************************************************** - * SDRAM INIT * - * This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb * - * This procedure fits only the Atlantis * - * * - ***************************************************************************************/ - -/**************************************************************************************** - * DFCDL initialize MV643xx Design Considerations * - * * - ***************************************************************************************/ -int set_dfcdlInit (void) -{ - int i; - - /* Values from MV64460 User Manual */ - unsigned int dfcdl_tbl[] = { 0x00000000, 0x00000001, 0x00000042, 0x00000083, - 0x000000c4, 0x00000105, 0x00000146, 0x00000187, - 0x000001c8, 0x00000209, 0x0000024a, 0x0000028b, - 0x000002cc, 0x0000030d, 0x0000034e, 0x0000038f, - 0x000003d0, 0x00000411, 0x00000452, 0x00000493, - 0x000004d4, 0x00000515, 0x00000556, 0x00000597, - 0x000005d8, 0x00000619, 0x0000065a, 0x0000069b, - 0x000006dc, 0x0000071d, 0x0000075e, 0x0000079f, - 0x000007e0, 0x00000821, 0x00000862, 0x000008a3, - 0x000008e4, 0x00000925, 0x00000966, 0x000009a7, - 0x000009e8, 0x00000a29, 0x00000a6a, 0x00000aab, - 0x00000aec, 0x00000b2d, 0x00000b6e, 0x00000baf, - 0x00000bf0, 0x00000c31, 0x00000c72, 0x00000cb3, - 0x00000cf4, 0x00000d35, 0x00000d76, 0x00000db7, - 0x00000df8, 0x00000e39, 0x00000e7a, 0x00000ebb, - 0x00000efc, 0x00000f3d, 0x00000f7e, 0x00000fbf }; - - for (i = 0; i < 64; i++) - GT_REG_WRITE (SRAM_DATA0, dfcdl_tbl[i]); - GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000); /* enable dynamic delay line updating */ - - return (0); -} diff --git a/board/prodrive/p3mx/serial.c b/board/prodrive/p3mx/serial.c deleted file mode 100644 index 5b7b989..0000000 --- a/board/prodrive/p3mx/serial.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * modified for marvell db64360 eval board by - * Ingo Assmus <ingo.assmus@keymile.com> - * - * modified for cpci750 board by - * Reinhard Arlt <reinhard.arlt@esd-electronics.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * serial.c - serial support for esd cpci750 board - */ - -/* supports the MPSC */ - -#include <common.h> -#include <command.h> -#include <serial.h> -#include <linux/compiler.h> - -#include "../../Marvell/include/memory.h" - -#include "mpsc.h" - -DECLARE_GLOBAL_DATA_PTR; - -static int p3mx_serial_init(void) -{ - mpsc_init (gd->baudrate); - - return (0); -} - -static void p3mx_serial_putc(const char c) -{ - if (c == '\n') - mpsc_putchar ('\r'); - - mpsc_putchar (c); -} - -static int p3mx_serial_getc(void) -{ - return mpsc_getchar (); -} - -static int p3mx_serial_tstc(void) -{ - return mpsc_test_char (); -} - -static void p3mx_serial_setbrg(void) -{ - galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate); -} - -static struct serial_device p3mx_serial_drv = { - .name = "p3mx_serial", - .start = p3mx_serial_init, - .stop = NULL, - .setbrg = p3mx_serial_setbrg, - .putc = p3mx_serial_putc, - .puts = default_serial_puts, - .getc = p3mx_serial_getc, - .tstc = p3mx_serial_tstc, -}; - -void p3mx_serial_initialize(void) -{ - serial_register(&p3mx_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &p3mx_serial_drv; -} - -#if defined(CONFIG_CMD_KGDB) -void kgdb_serial_init (void) -{ -} - -void putDebugChar (int c) -{ - serial_putc (c); -} - -void putDebugStr (const char *str) -{ - serial_puts (str); -} - -int getDebugChar (void) -{ - return serial_getc (); -} - -void kgdb_interruptible (int yes) -{ - return; -} -#endif diff --git a/board/tqc/tqm8260/Kconfig b/board/tqc/tqm8260/Kconfig deleted file mode 100644 index 90a96eb..0000000 --- a/board/tqc/tqm8260/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_TQM8260 - -config SYS_BOARD - default "tqm8260" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM8260" - -endif diff --git a/board/tqc/tqm8260/MAINTAINERS b/board/tqc/tqm8260/MAINTAINERS deleted file mode 100644 index 266910f..0000000 --- a/board/tqc/tqm8260/MAINTAINERS +++ /dev/null @@ -1,16 +0,0 @@ -TQM8260 BOARD -M: Wolfgang Denk <wd@denx.de> -S: Maintained -F: board/tqc/tqm8260/ -F: include/configs/TQM8260.h -F: configs/TQM8255_AA_defconfig -F: configs/TQM8260_AA_defconfig -F: configs/TQM8260_AB_defconfig -F: configs/TQM8260_AC_defconfig -F: configs/TQM8260_AD_defconfig -F: configs/TQM8260_AE_defconfig -F: configs/TQM8260_AF_defconfig -F: configs/TQM8260_AG_defconfig -F: configs/TQM8260_AH_defconfig -F: configs/TQM8260_AI_defconfig -F: configs/TQM8265_AA_defconfig diff --git a/board/tqc/tqm8260/Makefile b/board/tqc/tqm8260/Makefile deleted file mode 100644 index 6b8573d..0000000 --- a/board/tqc/tqm8260/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = tqm8260.o ../tqm8xx/load_sernum_ethaddr.o diff --git a/board/tqc/tqm8260/README b/board/tqc/tqm8260/README deleted file mode 100644 index 93b5506..0000000 --- a/board/tqc/tqm8260/README +++ /dev/null @@ -1,415 +0,0 @@ - -This file contains basic information on the port of U-Boot to TQM8260. -All the changes fit in the common U-Boot infrastructure, providing a -new TQM8260-specific entry in makefiles. To build U-Boot for TQM8260, -type "make TQM8260_config", edit the "include/config_TQM8260.h" file -if necessary, then type "make". - - -Common file modifications: --------------------------- - -The following common files have been modified by this project: -(starting from the ppcboot-0.9.3/ directory) - -MAKEALL - TQM8260 entry added -Makefile - TQM8260_config entry added -arch/powerpc/cpu/mpc8260/Makefile - soft_i2c.o module added -arch/powerpc/cpu/mpc8260/ether_scc.c - TQM8260-specific definitions added, an obvious - bug fixed (fcr -> scr) -arch/powerpc/cpu/mpc8260/ether_fcc.c - TQM8260-specific definitions added -include/flash.h - added definitions for the AM29LV640D Flash chip - - -New files: ----------- - -The following new files have been added by this project: -(starting from the ppcboot-0.9.3/ directory) - -board/tqm8260/ - board-specific directory -board/tqm8260/Makefile - board-specific makefile -board/tqm8260/config.mk - config file -board/tqm8260/flash.c - flash driver (for AM29LV640D) -board/tqm8260/ppcboot.lds - linker script -board/tqm8260/tqm8260.c - ioport and memory initialization -arch/powerpc/cpu/mpc8260/soft_i2c.c - software i2c EEPROM driver -include/config_TQM8260.h - main configuration file - - -New configuration options: --------------------------- - -CONFIG_TQM8260 - - Main board-specific option (should be defined for TQM8260). - -CONFIG_82xx_CONS_SMC1 - - If defined, SMC1 will be used as the console - -CONFIG_82xx_CONS_SMC2 - - If defined, SMC2 will be used as the console - -CONFIG_SYS_INIT_LOCAL_SDRAM - - If defined, the SDRAM on the local bus will be initialized and - mapped at BR2. - - -Acceptance criteria tests: --------------------------- - -The following tests have been conducted to validate the port of U-Boot -to TQM8260: - -1. Operation on serial console: - -With the CONFIG_82xx_CONS_SMC1 option defined in the main configuration file, -the U-Boot output appeared on the serial terminal connected to COM1 as -follows: - ------------------------------------------------------------------------------- -=> help -go - start application at address 'addr' -run - run commands in an environment variable -bootm - boot application image from memory -bootp - boot image via network using BootP/TFTP protocol -tftpboot- boot image via network using TFTP protocol - and env variables ipaddr and serverip -rarpboot- boot image via network using RARP/TFTP protocol -bootd - boot default, i.e., run 'bootcmd' -loads - load S-Record file over serial line -loadb - load binary file over serial line (kermit mode) -md - memory display -mm - memory modify (auto-incrementing) -nm - memory modify (constant address) -mw - memory write (fill) -cp - memory copy -cmp - memory compare -crc32 - checksum calculation -base - print or set address offset -printenv- print environment variables -setenv - set environment variables -saveenv - save environment variables to persistent storage -protect - enable or disable FLASH write protection -erase - erase FLASH memory -flinfo - print FLASH memory information -bdinfo - print Board Info structure -iminfo - print header information for application image -coninfo - print console devices and informations -eeprom - EEPROM sub-system -loop - infinite loop on address range -mtest - simple RAM test -icache - enable or disable instruction cache -dcache - enable or disable data cache -reset - Perform RESET of the CPU -echo - echo args to console -version - print monitor version -help - print online help -? - alias for 'help' -=> ------------------------------------------------------------------------------- - - -2. Flash driver operation - -The following sequence was performed to test the "flinfo" command: - ------------------------------------------------------------------------------- -=> flinfo - -Bank # 1: AMD 29LV640D (64 M, uniform sector) - Size: 32 MB in 128 Sectors - Sector Start Addresses: - 40000000 40040000 (RO) 40080000 400C0000 40100000 - 40140000 40180000 401C0000 40200000 40240000 - 40280000 402C0000 40300000 40340000 40380000 - 403C0000 40400000 40440000 40480000 404C0000 - 40500000 40540000 40580000 405C0000 40600000 - 40640000 40680000 406C0000 40700000 40740000 - 40780000 407C0000 40800000 40840000 40880000 - 408C0000 40900000 40940000 40980000 409C0000 - 40A00000 40A40000 40A80000 40AC0000 40B00000 - 40B40000 40B80000 40BC0000 40C00000 40C40000 - 40C80000 40CC0000 40D00000 40D40000 40D80000 - 40DC0000 40E00000 40E40000 40E80000 40EC0000 - 40F00000 40F40000 40F80000 40FC0000 41000000 - 41040000 41080000 410C0000 41100000 41140000 - 41180000 411C0000 41200000 41240000 41280000 - 412C0000 41300000 41340000 41380000 413C0000 - 41400000 41440000 41480000 414C0000 41500000 - 41540000 41580000 415C0000 41600000 41640000 - 41680000 416C0000 41700000 41740000 41780000 - 417C0000 41800000 41840000 41880000 418C0000 - 41900000 41940000 41980000 419C0000 41A00000 - 41A40000 41A80000 41AC0000 41B00000 41B40000 - 41B80000 41BC0000 41C00000 41C40000 41C80000 - 41CC0000 41D00000 41D40000 41D80000 41DC0000 - 41E00000 41E40000 41E80000 41EC0000 41F00000 - 41F40000 41F80000 41FC0000 -=> ------------------------------------------------------------------------------- - - -The following sequence was performed to test the erase command: - ------------------------------------------------------------------------------- -=> cp 0 40080000 10 -Copy to Flash... done -=> erase 40080000 400bffff -Erase Flash from 0x40080000 to 0x400bffff -.. done -Erased 1 sectors -=> md 40080000 -40080000: ffffffff ffffffff ffffffff ffffffff ................ -40080010: ffffffff ffffffff ffffffff ffffffff ................ -40080020: ffffffff ffffffff ffffffff ffffffff ................ -40080030: ffffffff ffffffff ffffffff ffffffff ................ -40080040: ffffffff ffffffff ffffffff ffffffff ................ -40080050: ffffffff ffffffff ffffffff ffffffff ................ -40080060: ffffffff ffffffff ffffffff ffffffff ................ -40080070: ffffffff ffffffff ffffffff ffffffff ................ -40080080: ffffffff ffffffff ffffffff ffffffff ................ -40080090: ffffffff ffffffff ffffffff ffffffff ................ -400800a0: ffffffff ffffffff ffffffff ffffffff ................ -400800b0: ffffffff ffffffff ffffffff ffffffff ................ -400800c0: ffffffff ffffffff ffffffff ffffffff ................ -400800d0: ffffffff ffffffff ffffffff ffffffff ................ -400800e0: ffffffff ffffffff ffffffff ffffffff ................ -400800f0: ffffffff ffffffff ffffffff ffffffff ................ -=> cp 0 40080000 10 -Copy to Flash... done -=> erase 1:2 -Erase Flash Sectors 2-2 in Bank # 1 -.. done -=> md 40080000 -40080000: ffffffff ffffffff ffffffff ffffffff ................ -40080010: ffffffff ffffffff ffffffff ffffffff ................ -40080020: ffffffff ffffffff ffffffff ffffffff ................ -40080030: ffffffff ffffffff ffffffff ffffffff ................ -40080040: ffffffff ffffffff ffffffff ffffffff ................ -40080050: ffffffff ffffffff ffffffff ffffffff ................ -40080060: ffffffff ffffffff ffffffff ffffffff ................ -40080070: ffffffff ffffffff ffffffff ffffffff ................ -40080080: ffffffff ffffffff ffffffff ffffffff ................ -40080090: ffffffff ffffffff ffffffff ffffffff ................ -400800a0: ffffffff ffffffff ffffffff ffffffff ................ -400800b0: ffffffff ffffffff ffffffff ffffffff ................ -400800c0: ffffffff ffffffff ffffffff ffffffff ................ -400800d0: ffffffff ffffffff ffffffff ffffffff ................ -400800e0: ffffffff ffffffff ffffffff ffffffff ................ -400800f0: ffffffff ffffffff ffffffff ffffffff ................ -=> cp 0 40080000 10 -Copy to Flash... done -=> cp 0 400c0000 10 -Copy to Flash... done -=> erase 1:2-3 -Erase Flash Sectors 2-3 in Bank # 1 -... done -=> md 40080000 -40080000: ffffffff ffffffff ffffffff ffffffff ................ -40080010: ffffffff ffffffff ffffffff ffffffff ................ -40080020: ffffffff ffffffff ffffffff ffffffff ................ -40080030: ffffffff ffffffff ffffffff ffffffff ................ -40080040: ffffffff ffffffff ffffffff ffffffff ................ -40080050: ffffffff ffffffff ffffffff ffffffff ................ -40080060: ffffffff ffffffff ffffffff ffffffff ................ -40080070: ffffffff ffffffff ffffffff ffffffff ................ -40080080: ffffffff ffffffff ffffffff ffffffff ................ -40080090: ffffffff ffffffff ffffffff ffffffff ................ -400800a0: ffffffff ffffffff ffffffff ffffffff ................ -400800b0: ffffffff ffffffff ffffffff ffffffff ................ -400800c0: ffffffff ffffffff ffffffff ffffffff ................ -400800d0: ffffffff ffffffff ffffffff ffffffff ................ -400800e0: ffffffff ffffffff ffffffff ffffffff ................ -400800f0: ffffffff ffffffff ffffffff ffffffff ................ -=> md 400c0000 -400c0000: ffffffff ffffffff ffffffff ffffffff ................ -400c0010: ffffffff ffffffff ffffffff ffffffff ................ -400c0020: ffffffff ffffffff ffffffff ffffffff ................ -400c0030: ffffffff ffffffff ffffffff ffffffff ................ -400c0040: ffffffff ffffffff ffffffff ffffffff ................ -400c0050: ffffffff ffffffff ffffffff ffffffff ................ -400c0060: ffffffff ffffffff ffffffff ffffffff ................ -400c0070: ffffffff ffffffff ffffffff ffffffff ................ -400c0080: ffffffff ffffffff ffffffff ffffffff ................ -400c0090: ffffffff ffffffff ffffffff ffffffff ................ -400c00a0: ffffffff ffffffff ffffffff ffffffff ................ -400c00b0: ffffffff ffffffff ffffffff ffffffff ................ -400c00c0: ffffffff ffffffff ffffffff ffffffff ................ -400c00d0: ffffffff ffffffff ffffffff ffffffff ................ -400c00e0: ffffffff ffffffff ffffffff ffffffff ................ -400c00f0: ffffffff ffffffff ffffffff ffffffff ................ -=> ------------------------------------------------------------------------------- - - -The following sequence was performed to test the Flash programming commands: - ------------------------------------------------------------------------------- -=> erase 40080000 400bffff -Erase Flash from 0x40080000 to 0x400bffff -.. done -Erased 1 sectors -=> cp 0 40080000 10 -Copy to Flash... done -=> md 0 -00000000: 00000000 00000104 61100200 01000000 ........a....... -00000010: 00000000 00000000 81140000 82000100 ................ -00000020: 01080000 00004000 22800000 00000600 ......@."....... -00000030: 00200800 00000000 10000100 00008000 . .............. -00000040: 00812000 00000200 00020000 80000000 .. ............. -00000050: 00028001 00001000 00040400 00000200 ................ -00000060: 20480000 00000000 20090000 00142000 H...... ..... . -00000070: 00000000 00004000 24210000 10000000 ......@.$!...... -00000080: 02440002 10000000 00200008 00000000 .D....... ...... -00000090: 02440900 00000000 30a40000 00004400 .D......0.....D. -000000a0: 04420800 00000000 00000040 00020000 .B.........@.... -000000b0: 05020000 00100000 00060000 00000000 ................ -000000c0: 00400000 00000000 00080000 00040000 .@.............. -000000d0: 10400000 00800004 00000000 00000200 .@.............. -000000e0: 80890000 00010004 00080000 00000020 ............... -000000f0: 08000000 10000000 00010000 00000000 ................ -=> md 40080000 -40080000: 00000000 00000104 61100200 01000000 ........a....... -40080010: 00000000 00000000 81140000 82000100 ................ -40080020: 01080000 00004000 22800000 00000600 ......@."....... -40080030: 00200800 00000000 10000100 00008000 . .............. -40080040: ffffffff ffffffff ffffffff ffffffff ................ -40080050: ffffffff ffffffff ffffffff ffffffff ................ -40080060: ffffffff ffffffff ffffffff ffffffff ................ -40080070: ffffffff ffffffff ffffffff ffffffff ................ -40080080: ffffffff ffffffff ffffffff ffffffff ................ -40080090: ffffffff ffffffff ffffffff ffffffff ................ -400800a0: ffffffff ffffffff ffffffff ffffffff ................ -400800b0: ffffffff ffffffff ffffffff ffffffff ................ -400800c0: ffffffff ffffffff ffffffff ffffffff ................ -400800d0: ffffffff ffffffff ffffffff ffffffff ................ -400800e0: ffffffff ffffffff ffffffff ffffffff ................ -400800f0: ffffffff ffffffff ffffffff ffffffff ................ -=> ------------------------------------------------------------------------------- - - -The following sequence was performed to test storage of the environment -variables in Flash: - ------------------------------------------------------------------------------- -=> setenv foo bar -=> saveenv -Un-Protected 1 sectors -Erasing Flash... -.. done -Erased 1 sectors -Saving Environment to Flash... -Protected 1 sectors -=> reset -... -=> printenv -bootdelay=CONFIG_BOOTDELAY -baudrate=9600 -ipaddr=192.168.4.7 -serverip=192.168.4.1 -ethaddr=66:55:44:33:22:11 -foo=bar -stdin=serial -stdout=serial -stderr=serial - -Environment size: 170/262140 bytes -=> ------------------------------------------------------------------------------- - - -The following sequence was performed to test image download and run over -Ethernet interface (both interfaces were tested): - ------------------------------------------------------------------------------- -=> tftpboot 40000 hello_world.bin -ARP broadcast 1 -TFTP from server 192.168.2.2; our IP address is 192.168.2.7 -Filename 'hello_world.bin'. -Load address: 0x40000 -Loading: ############# -done -Bytes transferred = 65912 (10178 hex) -=> go 40004 -## Starting application at 0x00040004 ... -Hello World -argc = 1 -argv[0] = "40004" -argv[1] = "<NULL>" -Hit any key to exit ... - -## Application terminated, rc = 0x0 -=> ------------------------------------------------------------------------------- - - -The following sequence was performed to test eeprom read/write commands: - ------------------------------------------------------------------------------- -=> md 40000 -00040000: 00018148 9421ffe0 7c0802a6 bf61000c ...H.!..|....a.. -00040010: 90010024 48000005 7fc802a6 801effe8 ...$H........... -00040020: 7fc0f214 7c7f1b78 813f004c 7c9c2378 ....|..x.?.L|.#x -00040030: 807e8000 7cbd2b78 80090010 3b600000 .~..|.+x....;`.. -00040040: 7c0803a6 4e800021 813f004c 7f84e378 |...N..!.?.L...x -00040050: 807e8004 80090010 7c0803a6 4e800021 .~......|...N..! -00040060: 7c1be000 4181003c 80bd0000 813f004c |...A..<.....?.L -00040070: 3bbd0004 2c050000 40820008 80be8008 ;...,...@....... -00040080: 80090010 7f64db78 807e800c 3b7b0001 .....d.x.~..;{.. -00040090: 7c0803a6 4e800021 7c1be000 4081ffcc |...N..!|...@... -000400a0: 813f004c 807e8010 80090010 7c0803a6 .?.L.~......|... -000400b0: 4e800021 813f004c 80090004 7c0803a6 N..!.?.L....|... -000400c0: 4e800021 2c030000 4182ffec 813f004c N..!,...A....?.L -000400d0: 80090000 7c0803a6 4e800021 813f004c ....|...N..!.?.L -000400e0: 807e8014 80090010 7c0803a6 4e800021 .~......|...N..! -000400f0: 38600000 80010024 7c0803a6 bb61000c 8`.....$|....a.. -=> eeprom write 40000 0 40 - -EEPROM write: addr 00040000 off 0000 count 64 ... done -=> mw 50000 0 1000 -=> eeprom read 50000 0 40 - -EEPROM read: addr 00050000 off 0000 count 64 ... done -=> md 50000 -00050000: 00018148 9421ffe0 7c0802a6 bf61000c ...H.!..|....a.. -00050010: 90010024 48000005 7fc802a6 801effe8 ...$H........... -00050020: 7fc0f214 7c7f1b78 813f004c 7c9c2378 ....|..x.?.L|.#x -00050030: 807e8000 7cbd2b78 80090010 3b600000 .~..|.+x....;`.. -00050040: 00000000 00000000 00000000 00000000 ................ -00050050: 00000000 00000000 00000000 00000000 ................ -00050060: 00000000 00000000 00000000 00000000 ................ -00050070: 00000000 00000000 00000000 00000000 ................ -00050080: 00000000 00000000 00000000 00000000 ................ -00050090: 00000000 00000000 00000000 00000000 ................ -000500a0: 00000000 00000000 00000000 00000000 ................ -000500b0: 00000000 00000000 00000000 00000000 ................ -000500c0: 00000000 00000000 00000000 00000000 ................ -000500d0: 00000000 00000000 00000000 00000000 ................ -000500e0: 00000000 00000000 00000000 00000000 ................ -000500f0: 00000000 00000000 00000000 00000000 ................ -=> ------------------------------------------------------------------------------- - - -Patch per Mon, 06 Aug 2001 17:57:27: - -- upgraded Flash support (added support for the following chips: - AM29LV800T/B, AM29LV160T/B, AM29DL322T/B, AM29DL323T/B) -- BCR tweakage for the 8260 bus mode -- SIUMCR tweakage enabling the MI interrupt (IRQ7) - -To simplify switching between the bus modes, a new configuration -option (CONFIG_BUSMODE_60x) has been added to the "config_TQM8260.h" -file. If it is defined, BCR will be configured for the 60x mode, -otherwise - for the 8260 mode. - -Concerning the SIUMCR modification: it's hard to predict whether it -will induce any problems on the other (60x mode) board. However, the -problems (if they appear) should be easy to notice - if the board -does not boot, it's most likely caused by the DPPC configuration in -SIUMCR. diff --git a/board/tqc/tqm8260/tqm8260.c b/board/tqc/tqm8260/tqm8260.c deleted file mode 100644 index c361f18..0000000 --- a/board/tqc/tqm8260/tqm8260.c +++ /dev/null @@ -1,352 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ioports.h> -#include <mpc8260.h> - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */ - /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */ - /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */ - /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */ - /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */ - /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */ - /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */ - /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ - /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDC */ - /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ -#if defined(CONFIG_SYS_I2C_SOFT) - /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ - /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ -#else -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#else /* normal I/O port pins */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#endif -#endif - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* Check Board Identity: - */ -int checkboard (void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts ("Board: "); - - if (i < 0 || strncmp(buf, "TQM82", 5)) { - puts ("### No HW ID - assuming TQM8260\n"); - return (0); - } - - puts (buf); - putc ('\n'); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, - ulong orx, volatile uchar * base) -{ - volatile uchar c = 0xff; - volatile uint *sdmr_ptr; - volatile uint *orx_ptr; - ulong maxsize, size; - int i; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff)) / 2; - - /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that - * we are configuring CS1 if base != 0 - */ - sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr; - orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1; - - *orx_ptr = orx; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - *sdmr_ptr = sdmr | PSDMR_OP_PREA; - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ - - *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *base = c; - - size = get_ram_size((long *)base, maxsize); - *orx_ptr = orx | ~(size - 1); - - return (size); -} - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - -#ifndef CONFIG_SYS_RAMBOOT - long size8, size9; -#endif - long psize, lsize; - - psize = 16 * 1024 * 1024; - lsize = 0; - - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - -#if 0 /* Just for debugging */ -#define prt_br_or(brX,orX) do { \ - ulong start = memctl->memc_ ## brX & 0xFFFF8000; \ - ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF; \ - printf ("\n" \ - #brX " 0x%08x " #orX " 0x%08x " \ - "==> 0x%08lx ... 0x%08lx = %ld MB\n", \ - memctl->memc_ ## brX, memctl->memc_ ## orX, \ - start, start+sizem, (sizem+1)>>20); \ - } while (0) - prt_br_or (br0, or0); - prt_br_or (br1, or1); - prt_br_or (br2, or2); - prt_br_or (br3, or3); -#endif - -#ifndef CONFIG_SYS_RAMBOOT - /* 60x SDRAM setup: - */ - size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - - if (size8 < size9) { - psize = size9; - printf ("(60x:9COL - %ld MB, ", psize >> 20); - } else { - psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, - (uchar *) CONFIG_SYS_SDRAM_BASE); - printf ("(60x:8COL - %ld MB, ", psize >> 20); - } - - /* Local SDRAM setup: - */ -#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM - memctl->memc_lsrt = CONFIG_SYS_LSRT; - size8 = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL, - (uchar *) SDRAM_BASE2_PRELIM); - size9 = try_init (memctl, CONFIG_SYS_LSDMR_9COL, CONFIG_SYS_OR2_9COL, - (uchar *) SDRAM_BASE2_PRELIM); - - if (size8 < size9) { - lsize = size9; - printf ("Local:9COL - %ld MB) using ", lsize >> 20); - } else { - lsize = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL, - (uchar *) SDRAM_BASE2_PRELIM); - printf ("Local:8COL - %ld MB) using ", lsize >> 20); - } - -#if 0 - /* Set up BR2 so that the local SDRAM goes - * right after the 60x SDRAM - */ - memctl->memc_br2 = (CONFIG_SYS_BR2_PRELIM & ~BRx_BA_MSK) | - (CONFIG_SYS_SDRAM_BASE + psize); -#endif -#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */ -#endif /* CONFIG_SYS_RAMBOOT */ - - icache_enable (); - - return (psize); -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/tqc/tqm8272/Kconfig b/board/tqc/tqm8272/Kconfig deleted file mode 100644 index 7b5cd8b..0000000 --- a/board/tqc/tqm8272/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_TQM8272 - -config SYS_BOARD - default "tqm8272" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM8272" - -endif diff --git a/board/tqc/tqm8272/MAINTAINERS b/board/tqc/tqm8272/MAINTAINERS deleted file mode 100644 index 988d2b1..0000000 --- a/board/tqc/tqm8272/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -TQM8272 BOARD -#M: - -S: Maintained -F: board/tqc/tqm8272/ -F: include/configs/TQM8272.h -F: configs/TQM8272_defconfig diff --git a/board/tqc/tqm8272/Makefile b/board/tqc/tqm8272/Makefile deleted file mode 100644 index 8bf0241..0000000 --- a/board/tqc/tqm8272/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = tqm8272.o ../tqm8xx/load_sernum_ethaddr.o nand.o diff --git a/board/tqc/tqm8272/nand.c b/board/tqc/tqm8272/nand.c deleted file mode 100644 index 7fb2dfa..0000000 --- a/board/tqc/tqm8272/nand.c +++ /dev/null @@ -1,264 +0,0 @@ -/* - * (C) Copyright 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ioports.h> -#include <mpc8260.h> - -#include "tqm8272.h" - -/* UPM pattern for bus clock = 66.7 MHz */ -static const uint upmTable67[] = -{ - /* Offset UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000, - /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ - /* 0x18 */ 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, - /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for bus clock = 100 MHz */ -static const uint upmTable100[] = -{ - /* Offset UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000, - /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ - /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fc00, 0x0fa3fc00, - /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for bus clock = 133.3 MHz */ -static const uint upmTable133[] = -{ - /* Offset UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000, - /* 0x04 */ 0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ - /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fd00, 0x0fa3fc00, - /* 0x1C */ 0x0fa3fd00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -static int chipsel = 0; - -#if defined(CONFIG_CMD_NAND) - -#include <nand.h> -#include <linux/mtd/mtd.h> - -static u8 hwctl = 0; - -static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte) -{ - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); - - if (hwctl & 0x1) { - WRITE_NAND_UPM(byte, base, CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS); - } else if (hwctl & 0x2) { - WRITE_NAND_UPM(byte, base, CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS); - } else { - WRITE_NAND(byte, base); - } -} - -static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - if (ctrl & NAND_CTRL_CHANGE) { - if ( ctrl & NAND_CLE ) - hwctl |= 0x1; - else - hwctl &= ~0x1; - if ( ctrl & NAND_ALE ) - hwctl |= 0x2; - else - hwctl &= ~0x2; - } - if (cmd != NAND_CMD_NONE) - upmnand_write_byte (mtd, cmd); -} - -static u_char upmnand_read_byte(struct mtd_info *mtdinfo) -{ - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); - - return READ_NAND(base); -} - -static int tqm8272_dev_ready(struct mtd_info *mtdinfo) -{ - /* constant delay (see also tR in the datasheet) */ - udelay(12); \ - return 1; -} - -#ifndef CONFIG_NAND_SPL -static void tqm8272_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) -{ - struct nand_chip *this = mtdinfo->priv; - unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); - int i; - - for (i = 0; i< len; i++) - buf[i] = *base; -} - -static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) -{ - struct nand_chip *this = mtdinfo->priv; - unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); - int i; - - for (i = 0; i< len; i++) - *base = buf[i]; -} - -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) -static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) -{ - struct nand_chip *this = mtdinfo->priv; - unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); - int i; - - for (i = 0; i < len; i++) - if (buf[i] != *base) - return -1; - return 0; -} -#endif -#endif /* #ifndef CONFIG_NAND_SPL */ - -void board_nand_select_device(struct nand_chip *nand, int chip) -{ - chipsel = chip; -} - -int board_nand_init(struct nand_chip *nand) -{ - static int UpmInit = 0; - volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immr->im_memctl; - - if (hwinf.nand == 0) return -1; - - /* Setup the UPM */ - if (UpmInit == 0) { - switch (hwinf.busclk_real) { - case 100000000: - upmconfig (UPMB, (uint *) upmTable100, - sizeof (upmTable100) / sizeof (uint)); - break; - case 133333333: - upmconfig (UPMB, (uint *) upmTable133, - sizeof (upmTable133) / sizeof (uint)); - break; - default: - upmconfig (UPMB, (uint *) upmTable67, - sizeof (upmTable67) / sizeof (uint)); - break; - } - UpmInit = 1; - } - - /* Setup the memctrl */ - memctl->memc_or3 = CONFIG_SYS_NAND_OR; - memctl->memc_br3 = CONFIG_SYS_NAND_BR; - memctl->memc_mbmr = (MxMR_OP_NORM); - - nand->ecc.mode = NAND_ECC_SOFT; - - nand->cmd_ctrl = upmnand_hwcontrol; - nand->read_byte = upmnand_read_byte; - nand->dev_ready = tqm8272_dev_ready; - -#ifndef CONFIG_NAND_SPL - nand->write_buf = tqm8272_write_buf; - nand->read_buf = tqm8272_read_buf; -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) - nand->verify_buf = tqm8272_verify_buf; -#endif -#endif - - /* - * Select required NAND chip - */ - board_nand_select_device(nand, 0); - return 0; -} - -#endif diff --git a/board/tqc/tqm8272/tqm8272.c b/board/tqc/tqm8272/tqm8272.c deleted file mode 100644 index d650868..0000000 --- a/board/tqc/tqm8272/tqm8272.c +++ /dev/null @@ -1,944 +0,0 @@ -/* - * (C) Copyright 2006 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ioports.h> -#include <mpc8260.h> - -#include <command.h> -#include <netdev.h> -#ifdef CONFIG_PCI -#include <pci.h> -#include <asm/m8260_pci.h> -#endif -#include "tqm8272.h" - -#if 0 -#define deb_printf(fmt,arg...) \ - printf ("TQM8272 %s %s: " fmt,__FILE__, __FUNCTION__, ##arg) -#else -#define deb_printf(fmt,arg...) \ - do { } while (0) -#endif - -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) -unsigned long board_get_cpu_clk_f (void); -#endif - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */ - /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */ - /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */ - /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */ - /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */ - /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */ - /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ - /* PC17 */ { 1, 0, 0, 1, 0, 0 }, /* PC17 MDC */ - /* PC16 */ { 1, 0, 0, 0, 0, 0 }, /* PC16 MDIO*/ - /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ - /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* PC10 */ - /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* PC9 */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* PC5 SMC1 TXD */ - /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* PC4 SMC1 RXD */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ -#if defined(CONFIG_SYS_I2C_SOFT) - /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ - /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ -#else -#if defined(CONFIG_HARD_I2C) - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#else /* normal I/O port pins */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ -#endif -#endif - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 0 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* UPM pattern for slow init */ -static const uint upmTableSlow[] = -{ - /* Offset UPM Read Single RAM array entry */ - /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcf00, 0x00ffdc00, - /* 0x04 */ 0x00ffce80, 0x00ffcc00, 0x00ffee00, 0x3fffcc07, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry */ - /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffef00, 0x00fffc80, - /* 0x1C */ 0x00fffe00, 0x00ffec00, 0x0fffef00, 0x3fffec05, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for fast init */ -static const uint upmTableFast[] = -{ - /* Offset UPM Read Single RAM array entry */ - /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcd80, 0x00ffdc00, - /* 0x04 */ 0x00ffdc00, 0x00ffcf00, 0x00ffec00, 0x3fffcc07, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry */ - /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffee80, 0x00fffc00, - /* 0x1C */ 0x00fffc00, 0x00ffec00, 0x0fffef00, 0x3fffec05, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - - -/* ------------------------------------------------------------------------- */ - -/* Check Board Identity: - */ -int checkboard (void) -{ - char *p = (char *) HWIB_INFO_START_ADDR; - - puts ("Board: "); - if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { - puts (p); - } else { - puts ("No HWIB assuming TQM8272"); - } - putc ('\n'); - - return 0; -} - -/* ------------------------------------------------------------------------- */ -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) -static int get_cas_latency (void) -{ - /* get it from the option -ts in CIB */ - /* default is 3 */ - int ret = 3; - int pos = 0; - char *p = (char *) CIB_INFO_START_ADDR; - - while ((*p != '\0') && (pos < CIB_INFO_LEN)) { - if (*p < ' ' || *p > '~') { /* ASCII strings! */ - return ret; - } - if (*p == '-') { - if ((p[1] == 't') && (p[2] == 's')) { - return (p[4] - '0'); - } - } - p++; - pos++; - } - return ret; -} -#endif - -static ulong set_sdram_timing (volatile uint *sdmr_ptr, ulong sdmr, int col) -{ -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) - int clk = board_get_cpu_clk_f (); - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - int busmode = (immr->im_siu_conf.sc_bcr & BCR_EBM ? 1 : 0); - int cas; - - sdmr = sdmr & ~(PSDMR_RFRC_MSK | PSDMR_PRETOACT_MSK | PSDMR_WRC_MSK | \ - PSDMR_BUFCMD); - if (busmode) { - switch (clk) { - case 66666666: - sdmr |= (PSDMR_RFRC_66MHZ_60X | \ - PSDMR_PRETOACT_66MHZ_60X | \ - PSDMR_WRC_66MHZ_60X | \ - PSDMR_BUFCMD_66MHZ_60X); - break; - case 100000000: - sdmr |= (PSDMR_RFRC_100MHZ_60X | \ - PSDMR_PRETOACT_100MHZ_60X | \ - PSDMR_WRC_100MHZ_60X | \ - PSDMR_BUFCMD_100MHZ_60X); - break; - - } - } else { - switch (clk) { - case 66666666: - sdmr |= (PSDMR_RFRC_66MHZ_SINGLE | \ - PSDMR_PRETOACT_66MHZ_SINGLE | \ - PSDMR_WRC_66MHZ_SINGLE | \ - PSDMR_BUFCMD_66MHZ_SINGLE); - break; - case 100000000: - sdmr |= (PSDMR_RFRC_100MHZ_SINGLE | \ - PSDMR_PRETOACT_100MHZ_SINGLE | \ - PSDMR_WRC_100MHZ_SINGLE | \ - PSDMR_BUFCMD_100MHZ_SINGLE); - break; - case 133333333: - sdmr |= (PSDMR_RFRC_133MHZ_SINGLE | \ - PSDMR_PRETOACT_133MHZ_SINGLE | \ - PSDMR_WRC_133MHZ_SINGLE | \ - PSDMR_BUFCMD_133MHZ_SINGLE); - break; - } - } - cas = get_cas_latency(); - sdmr &=~ (PSDMR_CL_MSK | PSDMR_LDOTOPRE_MSK); - sdmr |= cas; - sdmr |= ((cas - 1) << 6); - return sdmr; -#else - return sdmr; -#endif -} - -/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, - ulong orx, volatile uchar * base, int col) -{ - volatile uchar c = 0xff; - volatile uint *sdmr_ptr; - volatile uint *orx_ptr; - ulong maxsize, size; - int i; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff)) / 2; - - /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that - * we are configuring CS1 if base != 0 - */ - sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr; - orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1; - - *orx_ptr = orx; - sdmr = set_sdram_timing (sdmr_ptr, sdmr, col); - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - *sdmr_ptr = sdmr | PSDMR_OP_PREA; - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ - - *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *base = c; - - size = get_ram_size((long *)base, maxsize); - *orx_ptr = orx | ~(size - 1); - - return (size); -} - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - -#ifndef CONFIG_SYS_RAMBOOT - long size8, size9; -#endif - long psize; - - psize = 16 * 1024 * 1024; - - memctl->memc_psrt = CONFIG_SYS_PSRT; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - -#ifndef CONFIG_SYS_RAMBOOT - /* 60x SDRAM setup: - */ - size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, - (uchar *) CONFIG_SYS_SDRAM_BASE, 8); - size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL, - (uchar *) CONFIG_SYS_SDRAM_BASE, 9); - - if (size8 < size9) { - psize = size9; - printf ("(60x:9COL - %ld MB, ", psize >> 20); - } else { - psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, - (uchar *) CONFIG_SYS_SDRAM_BASE, 8); - printf ("(60x:8COL - %ld MB, ", psize >> 20); - } - -#endif /* CONFIG_SYS_RAMBOOT */ - - icache_enable (); - - return (psize); -} - - -static inline int scanChar (char *p, int len, unsigned long *number) -{ - int akt = 0; - - *number = 0; - while (akt < len) { - if ((*p >= '0') && (*p <= '9')) { - *number *= 10; - *number += *p - '0'; - p += 1; - } else { - if (*p == '-') return akt; - return -1; - } - akt ++; - } - return akt; -} - -static int dump_hwib(void) -{ - HWIB_INFO *hw = &hwinf; - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - - if (i < 0) - buf[0] = '\0'; - - if (hw->OK) { - printf ("HWIB on %x\n", HWIB_INFO_START_ADDR); - printf ("serial : %s\n", buf); - printf ("ethaddr: %s\n", hw->ethaddr); - printf ("FLASH : %x nr:%d\n", hw->flash, hw->flash_nr); - printf ("RAM : %x cs:%d\n", hw->ram, hw->ram_cs); - printf ("CPU : %lu\n", hw->cpunr); - printf ("CAN : %d\n", hw->can); - if (hw->eeprom) printf ("EEprom : %x\n", hw->eeprom); - else printf ("No EEprom\n"); - if (hw->nand) { - printf ("NAND : %x\n", hw->nand); - printf ("NAND CS: %d\n", hw->nand_cs); - } else { printf ("No NAND\n");} - printf ("Bus %s mode.\n", (hw->Bus ? "60x" : "Single PQII")); - printf (" real : %s\n", (immr->im_siu_conf.sc_bcr & BCR_EBM ? \ - "60x" : "Single PQII")); - printf ("Option : %lx\n", hw->option); - printf ("%s Security Engine\n", (hw->SecEng ? "with" : "no")); - printf ("CPM Clk: %d\n", hw->cpmcl); - printf ("CPU Clk: %d\n", hw->cpucl); - printf ("Bus Clk: %d\n", hw->buscl); - if (hw->busclk_real_ok) { - printf (" real Clk: %d\n", hw->busclk_real); - } - printf ("CAS : %d\n", get_cas_latency()); - } else { - printf("HWIB @%x not OK\n", HWIB_INFO_START_ADDR); - } - return 0; -} - -static inline int search_real_busclk (int *clk) -{ - int part = 0, pos = 0; - char *p = (char *) CIB_INFO_START_ADDR; - int ok = 0; - - while ((*p != '\0') && (pos < CIB_INFO_LEN)) { - if (*p < ' ' || *p > '~') { /* ASCII strings! */ - return 0; - } - switch (part) { - default: - if (*p == '-') { - ++part; - } - break; - case 3: - if (*p == '-') { - ++part; - break; - } - if (*p == 'b') { - ok = 1; - p++; - break; - } - if (ok) { - switch (*p) { - case '6': - *clk = 66666666; - return 1; - break; - case '1': - if (p[1] == '3') { - *clk = 133333333; - } else { - *clk = 100000000; - } - return 1; - break; - } - } - break; - } - p++; - } - return 0; -} - -int analyse_hwib (void) -{ - char *p = (char *) HWIB_INFO_START_ADDR; - int anz; - int part = 1, i = 0, pos = 0; - HWIB_INFO *hw = &hwinf; - - deb_printf(" %s pointer: %p\n", __FUNCTION__, p); - /* Head = TQM */ - if (*((unsigned long *)p) != (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { - deb_printf("No HWIB\n"); - return -1; - } - p += 3; - if (scanChar (p, 4, &hw->cpunr) < 0) { - deb_printf("No CPU\n"); - return -2; - } - p +=4; - - hw->flash = 0x200000 << (*p - 'A'); - p++; - hw->flash_nr = *p - '0'; - p++; - - hw->ram = 0x2000000 << (*p - 'A'); - p++; - if (*p == '2') { - hw->ram_cs = 2; - p++; - } - - if (*p == 'A') hw->can = 1; - if (*p == 'B') hw->can = 2; - p +=1; - p +=1; /* connector */ - if (*p != '0') { - hw->eeprom = 0x1000 << (*p - 'A'); - } - p++; - - if ((*p < '0') || (*p > '9')) { - /* NAND before z-option */ - hw->nand = 0x8000000 << (*p - 'A'); - p++; - hw->nand_cs = *p - '0'; - p += 2; - } - /* z-option */ - anz = scanChar (p, 4, &hw->option); - if (anz < 0) { - deb_printf("No option\n"); - return -3; - } - if (hw->option & 0x8) hw->Bus = 1; - p += anz; - if (*p != '-') { - deb_printf("No -\n"); - return -4; - } - p++; - /* C option */ - if (*p == 'E') { - hw->SecEng = 1; - p++; - } - switch (*p) { - case 'M': hw->cpucl = 266666666; - break; - case 'P': hw->cpucl = 300000000; - break; - case 'T': hw->cpucl = 400000000; - break; - default: - deb_printf("No CPU Clk: %c\n", *p); - return -5; - break; - } - p++; - switch (*p) { - case 'I': hw->cpmcl = 200000000; - break; - case 'M': hw->cpmcl = 300000000; - break; - default: - deb_printf("No CPM Clk\n"); - return -6; - break; - } - p++; - switch (*p) { - case 'B': hw->buscl = 66666666; - break; - case 'E': hw->buscl = 100000000; - break; - case 'F': hw->buscl = 133333333; - break; - default: - deb_printf("No BUS Clk\n"); - return -7; - break; - } - p++; - - hw->OK = 1; - /* search MAC Address */ - while ((*p != '\0') && (pos < CONFIG_SYS_HWINFO_SIZE)) { - if (*p < ' ' || *p > '~') { /* ASCII strings! */ - return 0; - } - switch (part) { - default: - if (*p == ' ') { - ++part; - i = 0; - } - break; - case 3: /* Copy MAC address */ - if (*p == ' ') { - ++part; - i = 0; - break; - } - hw->ethaddr[i++] = *p; - if ((i % 3) == 2) - hw->ethaddr[i++] = ':'; - break; - - } - p++; - } - - hw->busclk_real_ok = search_real_busclk (&hw->busclk_real); - return 0; -} - -#if defined(CONFIG_GET_CPU_STR_F) -/* !! This routine runs from Flash */ -char get_cpu_str_f (char *buf) -{ - char *p = (char *) HWIB_INFO_START_ADDR; - int i = 0; - - buf[i++] = 'M'; - buf[i++] = 'P'; - buf[i++] = 'C'; - if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { - buf[i++] = *&p[3]; - buf[i++] = *&p[4]; - buf[i++] = *&p[5]; - buf[i++] = *&p[6]; - } else { - buf[i++] = '8'; - buf[i++] = '2'; - buf[i++] = '7'; - buf[i++] = 'x'; - } - buf[i++] = 0; - return 0; -} -#endif - -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) -/* !! This routine runs from Flash */ -unsigned long board_get_cpu_clk_f (void) -{ - char *p = (char *) HWIB_INFO_START_ADDR; - int i = 0; - - if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { - if (search_real_busclk (&i)) - return i; - } - return CONFIG_8260_CLKIN; -} -#endif - -#if CONFIG_BOARD_EARLY_INIT_R - -static int can_test (unsigned long off) -{ - volatile unsigned char *base = (unsigned char *) (CONFIG_SYS_CAN_BASE + off); - - *(base + 0x17) = 'T'; - *(base + 0x18) = 'Q'; - *(base + 0x19) = 'M'; - if ((*(base + 0x17) != 'T') || - (*(base + 0x18) != 'Q') || - (*(base + 0x19) != 'M')) { - return 0; - } - return 1; -} - -static int can_config_one (unsigned long off) -{ - volatile unsigned char *ctrl = (unsigned char *) (CONFIG_SYS_CAN_BASE + off); - volatile unsigned char *cpu_if = (unsigned char *) (CONFIG_SYS_CAN_BASE + off + 0x02); - volatile unsigned char *clkout = (unsigned char *) (CONFIG_SYS_CAN_BASE + off + 0x1f); - unsigned char temp; - - *cpu_if = 0x45; - temp = *ctrl; - temp |= 0x40; - *ctrl = temp; - *clkout = 0x20; - temp = *ctrl; - temp &= ~0x40; - *ctrl = temp; - return 0; -} - -static int can_config (void) -{ - int ret = 0; - can_config_one (0); - if (hwinf.can == 2) { - can_config_one (0x100); - } - /* make Test if they really there */ - ret += can_test (0); - ret += can_test (0x100); - return ret; -} - -static int init_can (void) -{ - volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immr->im_memctl; - int count = 0; - - if ((hwinf.OK) && (hwinf.can)) { - memctl->memc_or4 = CONFIG_SYS_CAN_OR; - memctl->memc_br4 = CONFIG_SYS_CAN_BR; - /* upm Init */ - upmconfig (UPMC, (uint *) upmTableFast, - sizeof (upmTableFast) / sizeof (uint)); - memctl->memc_mcmr = (MxMR_DSx_3_CYCL | - MxMR_GPL_x4DIS | - MxMR_RLFx_2X | - MxMR_WLFx_2X | - MxMR_OP_NORM); - /* can configure */ - count = can_config (); - printf ("CAN: %d @ %x\n", count, CONFIG_SYS_CAN_BASE); - if (hwinf.can != count) printf("!!! difference to HWIB\n"); - } else { - printf ("CAN: No\n"); - } - return 0; -} - -int board_early_init_r(void) -{ - analyse_hwib (); - init_can (); - return 0; -} -#endif - -int do_hwib_dump (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - dump_hwib (); - return 0; -} - -U_BOOT_CMD( - hwib, 1, 1, do_hwib_dump, - "dump HWIB'", - "" -); - -#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE -static int get_flash_timing (void) -{ - /* get it from the option -tf in CIB */ - /* default is 0x00000c84 */ - int ret = 0x00000c84; - int pos = 0; - int nr = 0; - char *p = (char *) CIB_INFO_START_ADDR; - - while ((*p != '\0') && (pos < CIB_INFO_LEN)) { - if (*p < ' ' || *p > '~') { /* ASCII strings! */ - return ret; - } - if (*p == '-') { - if ((p[1] == 't') && (p[2] == 'f')) { - p += 6; - ret = 0; - while (nr < 8) { - if ((*p >= '0') && (*p <= '9')) { - ret *= 0x10; - ret += *p - '0'; - p += 1; - nr ++; - } else if ((*p >= 'A') && (*p <= 'F')) { - ret *= 10; - ret += *p - '7'; - p += 1; - nr ++; - } else { - if (nr < 8) return 0x00000c84; - return ret; - } - } - } - } - p++; - pos++; - } - return ret; -} - -/* Update the Flash_Size and the Flash Timing */ -int update_flash_size (int flash_size) -{ - volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immr->im_memctl; - unsigned long reg; - unsigned long tim; - - /* I must use reg, otherwise the board hang */ - reg = memctl->memc_or0; - reg &= ~ORxU_AM_MSK; - reg |= MEG_TO_AM(flash_size >> 20); - tim = get_flash_timing (); - reg &= ~0xfff; - reg |= (tim & 0xfff); - memctl->memc_or0 = reg; - return 0; -} -#endif - -#ifdef CONFIG_PCI -struct pci_controller hose; - -int board_early_init_f (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN; - return 0; -} - -extern void pci_mpc8250_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc8250_init(&hose); -} -#endif - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/tqc/tqm8272/tqm8272.h b/board/tqc/tqm8272/tqm8272.h deleted file mode 100644 index 1eeaf0e..0000000 --- a/board/tqc/tqm8272/tqm8272.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * (C) Copyright 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TQM8272_HEADER_H -#define _TQM8272_HEADER_H - -#define _NOT_USED_ 0xFFFFFFFF - -typedef struct{ - int Bus; - int flash; - int flash_nr; - int ram; - int ram_cs; - int nand; - int nand_cs; - int eeprom; - int can; - unsigned long cpunr; - unsigned long option; - int SecEng; - int cpucl; - int cpmcl; - int buscl; - int busclk_real_ok; - int busclk_real; - unsigned char OK; - unsigned char ethaddr[20]; -} HWIB_INFO; - -static HWIB_INFO hwinf = {0, 0, 1, 0, 1, 0, 0, 0, 0, 8272, 0 ,0, - 0, 0, 0, 0, 0, 0}; -#endif /* __CONFIG_H */ diff --git a/configs/CPCI750_defconfig b/configs/CPCI750_defconfig deleted file mode 100644 index abdd4d2..0000000 --- a/configs/CPCI750_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_74xx_7xx=y -CONFIG_TARGET_CPCI750=y diff --git a/configs/DB64360_defconfig b/configs/DB64360_defconfig deleted file mode 100644 index 358b096..0000000 --- a/configs/DB64360_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_74xx_7xx=y -CONFIG_TARGET_DB64360=y diff --git a/configs/DB64460_defconfig b/configs/DB64460_defconfig deleted file mode 100644 index 4ff2fad..0000000 --- a/configs/DB64460_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_74xx_7xx=y -CONFIG_TARGET_DB64460=y diff --git a/configs/HWW1U1A_defconfig b/configs/HWW1U1A_defconfig deleted file mode 100644 index 8947be2..0000000 --- a/configs/HWW1U1A_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_HWW1U1A=y diff --git a/configs/ICU862_100MHz_defconfig b/configs/ICU862_100MHz_defconfig deleted file mode 100644 index 72f0dfa..0000000 --- a/configs/ICU862_100MHz_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="100MHz" -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_ICU862=y diff --git a/configs/ICU862_defconfig b/configs/ICU862_defconfig deleted file mode 100644 index b58ea05..0000000 --- a/configs/ICU862_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_ICU862=y diff --git a/configs/IDS8247_defconfig b/configs/IDS8247_defconfig deleted file mode 100644 index b4dd23f..0000000 --- a/configs/IDS8247_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_IDS8247=y diff --git a/configs/MHPC_defconfig b/configs/MHPC_defconfig deleted file mode 100644 index b05d3c4..0000000 --- a/configs/MHPC_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_8xx=y -CONFIG_TARGET_MHPC=y diff --git a/configs/TQM8255_AA_defconfig b/configs/TQM8255_AA_defconfig deleted file mode 100644 index a9f9f01..0000000 --- a/configs/TQM8255_AA_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="MPC8255,300MHz" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_TQM8260=y diff --git a/configs/TQM8260_AA_defconfig b/configs/TQM8260_AA_defconfig deleted file mode 100644 index b762fe4..0000000 --- a/configs/TQM8260_AA_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="MPC8260,200MHz" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_TQM8260=y diff --git a/configs/TQM8260_AB_defconfig b/configs/TQM8260_AB_defconfig deleted file mode 100644 index 6ff8d17..0000000 --- a/configs/TQM8260_AB_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="MPC8260,200MHz,L2_CACHE,BUSMODE_60x" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_TQM8260=y diff --git a/configs/TQM8260_AC_defconfig b/configs/TQM8260_AC_defconfig deleted file mode 100644 index 6ff8d17..0000000 --- a/configs/TQM8260_AC_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="MPC8260,200MHz,L2_CACHE,BUSMODE_60x" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_TQM8260=y diff --git a/configs/TQM8260_AD_defconfig b/configs/TQM8260_AD_defconfig deleted file mode 100644 index 3f406a4..0000000 --- a/configs/TQM8260_AD_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="MPC8260,300MHz,BUSMODE_60x" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_TQM8260=y diff --git a/configs/TQM8260_AE_defconfig b/configs/TQM8260_AE_defconfig deleted file mode 100644 index 1077b19..0000000 --- a/configs/TQM8260_AE_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="MPC8260,266MHz" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_TQM8260=y diff --git a/configs/TQM8260_AF_defconfig b/configs/TQM8260_AF_defconfig deleted file mode 100644 index 3f406a4..0000000 --- a/configs/TQM8260_AF_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="MPC8260,300MHz,BUSMODE_60x" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_TQM8260=y diff --git a/configs/TQM8260_AG_defconfig b/configs/TQM8260_AG_defconfig deleted file mode 100644 index b0d67fa..0000000 --- a/configs/TQM8260_AG_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="MPC8260,300MHz" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_TQM8260=y diff --git a/configs/TQM8260_AH_defconfig b/configs/TQM8260_AH_defconfig deleted file mode 100644 index 65c73e8..0000000 --- a/configs/TQM8260_AH_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="MPC8260,300MHz,L2_CACHE,BUSMODE_60x" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_TQM8260=y diff --git a/configs/TQM8260_AI_defconfig b/configs/TQM8260_AI_defconfig deleted file mode 100644 index 3f406a4..0000000 --- a/configs/TQM8260_AI_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="MPC8260,300MHz,BUSMODE_60x" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_TQM8260=y diff --git a/configs/TQM8265_AA_defconfig b/configs/TQM8265_AA_defconfig deleted file mode 100644 index d8806c4..0000000 --- a/configs/TQM8265_AA_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="MPC8265,300MHz,BUSMODE_60x" -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_TQM8260=y diff --git a/configs/TQM8272_defconfig b/configs/TQM8272_defconfig deleted file mode 100644 index 0070baf..0000000 --- a/configs/TQM8272_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_TQM8272=y diff --git a/configs/hymod_defconfig b/configs/hymod_defconfig deleted file mode 100644 index a6dc1d8..0000000 --- a/configs/hymod_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC8260=y -CONFIG_TARGET_HYMOD=y diff --git a/configs/p3m7448_defconfig b/configs/p3m7448_defconfig deleted file mode 100644 index 9b03689..0000000 --- a/configs/p3m7448_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="P3M7448" -CONFIG_PPC=y -CONFIG_74xx_7xx=y -CONFIG_TARGET_P3MX=y diff --git a/configs/p3m750_defconfig b/configs/p3m750_defconfig deleted file mode 100644 index e5377eb..0000000 --- a/configs/p3m750_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="P3M750" -CONFIG_PPC=y -CONFIG_74xx_7xx=y -CONFIG_TARGET_P3MX=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 1dcdcc7..775c3a7 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,14 +12,26 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= -MVBC_P powerpc mpc5xxx - - Andre Schwarz <andre.schwarz@matrix-vision.de> -MVSMR powerpc mpc5xxx - - Andre Schwarz <andre.schwarz@matrix-vision.de> -MERGERBOX powerpc mpc83xx - - Andre Schwarz <andre.schwarz@matrix-vision.de> -MVBLM7 powerpc mpc83xx - - Andre Schwarz <andre.schwarz@matrix-vision.de> -bluestone powerpc ppc4xx - - Tirumala Marri <tmarri@apm.com> -CRAYL1 powerpc ppc4xx - - David Updegraff <dave@cray.com> -KAREF powerpc ppc4xx - - Travis Sawyer <travis.sawyer@sandburst.com> -METROBOX powerpc ppc4xx - - Travis Sawyer <travis.sawyer@sandburst.com> +TQM8272 powerpc mpc8260 - - - +TQM8260 powerpc mpc8260 - - Wolfgang Denk <wd@denx.de> +IDS8247 powerpc mpc8260 - - Heiko Schocher <hs@denx.de> +HWW1U1A powerpc mpc85xx - - Kyle Moffett <Kyle.D.Moffett@boeing.com> +hymod powerpc mpc8260 - - Murray Jensen <Murray.Jensen@csiro.au> +MHPC powerpc mpc8xx - - Frank Gottschling <fgottschling@eltec.de> +ICU862 powerpc mpc8xx - - Wolfgang Denk <wd@denx.de> +CPCI750 powerpc 74xx_7xx - - Reinhard Arlt <reinhard.arlt@esd-electronics.com> +DB64360 powerpc 74xx_7xx - - +DB64460 powerpc 74xx_7xx - - +p3m750 powerpc 74xx_7xx - - Stefan Roese <sr@denx.de> +p3m7448 powerpc 74xx_7xx - - Stefan Roese <sr@denx.de> +MVBC_P powerpc mpc5xxx af55e35 2014-10-10 Andre Schwarz <andre.schwarz@matrix-vision.de> +MVSMR powerpc mpc5xxx af55e35 2014-10-10 Andre Schwarz <andre.schwarz@matrix-vision.de> +MERGERBOX powerpc mpc83xx e7a5656 2014-10-10 Andre Schwarz <andre.schwarz@matrix-vision.de> +MVBLM7 powerpc mpc83xx e7a5656 2014-10-10 Andre Schwarz <andre.schwarz@matrix-vision.de> +bluestone powerpc ppc4xx 9ed3246 2014-10-10 Tirumala Marri <tmarri@apm.com> +CRAYL1 powerpc ppc4xx 1521cdc 2014-10-10 David Updegraff <dave@cray.com> +KAREF powerpc ppc4xx dc9617e 2014-10-10 Travis Sawyer <travis.sawyer@sandburst.com> +METROBOX powerpc ppc4xx dc9617e 2014-10-10 Travis Sawyer <travis.sawyer@sandburst.com> PK1C20 nios2 - 70fbc461 2014-08-24 Scott McNutt <smcnutt@psyent.com> PCI5441 nios2 - 70fbc461 2014-08-24 Scott McNutt <smcnutt@psyent.com> flagadm powerpc mpc8xx aec6f8c5 2014-08-22 Kári DavÃðsson <kd@flaga.is> diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c index 1e4ea0c..a23a585 100644 --- a/drivers/net/eepro100.c +++ b/drivers/net/eepro100.c @@ -230,7 +230,7 @@ static int eepro100_send(struct eth_device *dev, void *packet, int length); static int eepro100_recv (struct eth_device *dev); static void eepro100_halt (struct eth_device *dev); -#if defined(CONFIG_E500) || defined(CONFIG_DB64360) || defined(CONFIG_DB64460) +#if defined(CONFIG_E500) #define bus_to_phys(a) (a) #define phys_to_bus(a) (a) #else diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index 62cb1ea..aef39d7 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -79,9 +79,6 @@ typedef struct bd_info { unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ #endif -#if defined(CONFIG_HYMOD) - hymod_conf_t bi_hymod_conf; /* hymod configuration information */ -#endif #ifdef CONFIG_HAS_ETH1 unsigned char bi_enet1addr[6]; /* OLD: see README.enetaddr */ diff --git a/include/common.h b/include/common.h index bcf6c7e..a5764d8 100644 --- a/include/common.h +++ b/include/common.h @@ -69,9 +69,6 @@ typedef volatile unsigned char vu_char; #ifdef CONFIG_4xx #include <asm/ppc4xx.h> #endif -#ifdef CONFIG_HYMOD -#include <board/hymod/hymod.h> -#endif #ifdef CONFIG_ARM #define asmlinkage /* nothing */ #endif diff --git a/include/commproc.h b/include/commproc.h index 82a1a98..d78ab00 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -563,16 +563,6 @@ typedef struct scc_enet { #endif /* CONFIG_HERMES */ -/*** ICU862 **********************************************************/ - -#if defined(CONFIG_ICU862) - -#ifdef CONFIG_FEC_ENET -#define FEC_ENET /* use FEC for EThernet */ -#endif /* CONFIG_FEC_ETHERNET */ - -#endif /* CONFIG_ICU862 */ - /*** IP860 **********************************************************/ #if defined(CONFIG_IP860) @@ -713,28 +703,6 @@ typedef struct scc_enet { #define SICR_ENET_CLKRT ((uint)0x00250000) #endif /* CONFIG_KM8XX */ - -/*** MHPC ********************************************************/ - -#if defined(CONFIG_MHPC) -/* This ENET stuff is for the MHPC with ethernet on SCC2. - * Note TENA is on Port B. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002e00) /* RCLK-CLK2, TCLK-CLK3 */ -#endif /* CONFIG_MHPC */ - /*** NETVIA *******************************************************/ #if defined(CONFIG_NETVIA) diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h deleted file mode 100644 index 304a12b..0000000 --- a/include/configs/CPCI750.h +++ /dev/null @@ -1,609 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -/************************************************************************* - * (c) 2004 esd gmbh Hannover - * - * - * from db64360.h file - * by Reinhard Arlt reinhard.arlt@esd-electronics.com - * - ************************************************************************/ - - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* This define must be before the core.h include */ -#define CONFIG_CPCI750 1 /* this is an CPCI750 board */ - -#ifndef __ASSEMBLY__ -#include <../board/Marvell/include/core.h> -#endif -/*-----------------------------------------------------*/ - -#include "../board/esd/cpci750/local.h" - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_750FX /* we have a 750FX (override local.h) */ - -#define CONFIG_CPCI750 1 /* this is an CPCI750 board */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 */ - -#define CONFIG_MV64360_ECC /* enable ECC support */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* which initialization functions to call for this board */ -#define CONFIG_MISC_INIT_R -#define CONFIG_BOARD_PRE_INIT -#define CONFIG_BOARD_EARLY_INIT_F 1 - -#define CONFIG_SYS_BOARD_NAME "CPCI750" -#define CONFIG_IDENT_STRING "Marvell 64360 + IBM750FX" - -/*#define CONFIG_SYS_HUSH_PARSER*/ -#define CONFIG_SYS_HUSH_PARSER - - -#define CONFIG_CMDLINE_EDITING /* add command line history */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ - -/* Define which ETH port will be used for connecting the network */ -#define CONFIG_SYS_ETH_PORT ETH_0 - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * what to do: - * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial - * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1 - * to 0 below. - * - * to use the MPSC, #define CONFIG_MPSC. If you have wired up another - * mpsc channel, change CONFIG_MPSC_PORT to the desired value. - */ -#define CONFIG_MPSC -#define CONFIG_MPSC_PORT 0 - -/* to change the default ethernet port, use this define (options: 0, 1, 2) */ -#define MV_ETH_DEVS 1 -#define CONFIG_ETHER_PORT 0 - -#undef CONFIG_ETHER_PORT_MII /* use RMII */ - -#define CONFIG_BOOTDELAY 5 /* autoboot disabled */ - -#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ - -#define CONFIG_ZERO_BOOTDELAY_CHECK - - -#undef CONFIG_BOOTARGS - -/* ----------------------------------------------------------------------------- - * New bootcommands for Marvell CPCI750 c 2002 Ingo Assmus - */ - -#define CONFIG_IPADDR "192.168.0.185" - -#define CONFIG_SERIAL "AA000001" -#define CONFIG_SERVERIP "10.0.0.79" -#define CONFIG_ROOTPATH "/export/nfs_cpci750/%s" - -#define CONFIG_TESTDRAMDATA y -#define CONFIG_TESTDRAMADDRESS n -#define CONFIG_TESETDRAMWALK n - -/* ----------------------------------------------------------------------------- */ - - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_I2C -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_PCI -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 - - -#define CONFIG_DOS_PARTITION - -#define CONFIG_USE_CPCIDVI - -#ifdef CONFIG_USE_CPCIDVI -#define CONFIG_VIDEO -#define CONFIG_VIDEO_CT69000 -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_VIDEO_LOGO -#define CONFIG_I8042_KBD -#define CONFIG_SYS_ISA_IO 0 -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_MULTI_EEPROMS -#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed default */ - -#define CONFIG_PRAM 0 - -#define CONFIG_SYS_GT_DUAL_CPU /* also for JTAG even with one cpu */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/*#define CONFIG_SYS_MEMTEST_START 0x00400000*/ /* memtest works on */ -/*#define CONFIG_SYS_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */ -/*#define CONFIG_SYS_MEMTEST_END 0x07c00000*/ /* 4 ... 124 MB in DRAM */ - -/* -#define CONFIG_SYS_DRAM_TEST - * DRAM tests - * CONFIG_SYS_DRAM_TEST - enables the following tests. - * - * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines - * Environment variable 'test_dram_data' must be - * set to 'y'. - * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely - * addressable. Environment variable - * 'test_dram_address' must be set to 'y'. - * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. - * This test takes about 6 minutes to test 64 MB. - * Environment variable 'test_dram_walk' must be - * set to 'y'. - */ -#define CONFIG_SYS_DRAM_TEST -#if defined(CONFIG_SYS_DRAM_TEST) -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -/*#define CONFIG_SYS_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */ -#define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ -#define CONFIG_SYS_DRAM_TEST_DATA -#define CONFIG_SYS_DRAM_TEST_ADDRESS -#define CONFIG_SYS_DRAM_TEST_WALK -#endif /* CONFIG_SYS_DRAM_TEST */ - -#define CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */ -#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ - -#define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */ - -#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_SYS_TCLK 133000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - - /* - * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS - * To an unused memory region. The stack will remain in cache until RAM - * is initialized -*/ -#undef CONFIG_SYS_INIT_RAM_LOCK -/* #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000*/ /* unused memory region */ -/* #define CONFIG_SYS_INIT_RAM_ADDR 0xfba00000*/ /* unused memory region */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xf1080000 /* unused memory region */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -#define RELOCATE_INTERNAL_RAM_ADDR -#ifdef RELOCATE_INTERNAL_RAM_ADDR -/*#define CONFIG_SYS_INTERNAL_RAM_ADDR 0xfba00000*/ -#define CONFIG_SYS_INTERNAL_RAM_ADDR 0xf1080000 -#endif - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -/* Dummies for BAT 4-7 */ -#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */ -#define CONFIG_SYS_SDRAM2_BASE 0x20000000 -#define CONFIG_SYS_SDRAM3_BASE 0x30000000 -#define CONFIG_SYS_SDRAM4_BASE 0x40000000 -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE 0xfff00000 -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 256 kB for malloc */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of flash banks */ -#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */ -#define CONFIG_SYS_FLASH_INCREMENT 0x01000000 /* size of flash bank */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ - CONFIG_SYS_FLASH_BASE + 1*CONFIG_SYS_FLASH_INCREMENT, \ - CONFIG_SYS_FLASH_BASE + 2*CONFIG_SYS_FLASH_INCREMENT, \ - CONFIG_SYS_FLASH_BASE + 3*CONFIG_SYS_FLASH_INCREMENT } -#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* show if bank is empty */ - -/* areas to map different things with the GT in physical space */ -#define CONFIG_SYS_DRAM_BANKS 4 - -/* What to put in the bats. */ -#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 - -/* Peripheral Device section */ - -/*******************************************************/ -/* We have on the cpci750 Board : */ -/* GT-Chipset Register Area */ -/* GT-Chipset internal SRAM 256k */ -/* SRAM on external device module */ -/* Real time clock on external device module */ -/* dobble UART on external device module */ -/* Data flash on external device module */ -/* Boot flash on external device module */ -/*******************************************************/ -#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ -#define CONFIG_SYS_CPCI750_RESET_ADDR 0x14000000 /* After power on Reset the CPCI750 is here */ - -#undef MARVEL_STANDARD_CFG -#ifndef MARVEL_STANDARD_CFG -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ -#define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ -/*#define CONFIG_SYS_DEV_BASE 0xfc000000*/ /* GT Devices CS start here */ -#define CONFIG_SYS_INT_SRAM_BASE 0xf1080000 /* GT offers 256k internal fast SRAM */ - -#define CONFIG_SYS_BOOT_SPACE 0xff000000 /* BOOT_CS0 flash 0 */ -#define CONFIG_SYS_DEV0_SPACE 0xfc000000 /* DEV_CS0 flash 1 */ -#define CONFIG_SYS_DEV1_SPACE 0xfd000000 /* DEV_CS1 flash 2 */ -#define CONFIG_SYS_DEV2_SPACE 0xfe000000 /* DEV_CS2 flash 3 */ -#define CONFIG_SYS_DEV3_SPACE 0xf0000000 /* DEV_CS3 nvram/can */ - -#define CONFIG_SYS_BOOT_SIZE _16M /* cpci750 flash 0 */ -#define CONFIG_SYS_DEV0_SIZE _16M /* cpci750 flash 1 */ -#define CONFIG_SYS_DEV1_SIZE _16M /* cpci750 flash 2 */ -#define CONFIG_SYS_DEV2_SIZE _16M /* cpci750 flash 3 */ -#define CONFIG_SYS_DEV3_SIZE _16M /* cpci750 nvram/can */ - -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ -#endif - -/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */ -#define CONFIG_SYS_DEV0_PAR 0x8FDFFFFF /* 16 bit flash */ -#define CONFIG_SYS_DEV1_PAR 0x8FDFFFFF /* 16 bit flash */ -#define CONFIG_SYS_DEV2_PAR 0x8FDFFFFF /* 16 bit flash */ -#define CONFIG_SYS_DEV3_PAR 0x8FCFFFFF /* nvram/can */ -#define CONFIG_SYS_BOOT_PAR 0x8FDFFFFF /* 16 bit flash */ - - /* c 4 a 8 2 4 1 c */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ - /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ - /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ - /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ - - -/* MPP Control MV64360 Appendix P P. 632*/ -#define CONFIG_SYS_MPP_CONTROL_0 0x00002222 /* */ -#define CONFIG_SYS_MPP_CONTROL_1 0x11110000 /* */ -#define CONFIG_SYS_MPP_CONTROL_2 0x11111111 /* */ -#define CONFIG_SYS_MPP_CONTROL_3 0x00001111 /* */ -/* #define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102*/ /* */ - - -#define CONFIG_SYS_GPP_LEVEL_CONTROL 0xffffffff /* 1111 1111 1111 1111 1111 1111 1111 1111*/ - -/* setup new config_value for MV64360 DDR-RAM To_do !! */ -/*# define CONFIG_SYS_SDRAM_CONFIG 0xd8e18200*/ /* 0x448 */ -/*# define CONFIG_SYS_SDRAM_CONFIG 0xd8e14400*/ /* 0x1400 */ - /* GB has high prio. - idma has low prio - MPSC has low prio - pci has low prio 1 and 2 - cpu has high prio - Data DQS pins == eight (DQS[7:0] foe x8 and x16 devices - ECC disable - non registered DRAM */ - /* 31:26 25:22 21:20 19 18 17 16 */ - /* 100001 0000 010 0 0 0 0 */ - /* refresh_count=0x400 - phisical interleaving disable - virtual interleaving enable */ - /* 15 14 13:0 */ - /* 0 1 0x400 */ -# define CONFIG_SYS_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ - -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */ - -/* PCI MEMORY MAP section */ -#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI0_MEM_SIZE _128M -#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 -#define CONFIG_SYS_PCI1_MEM_SIZE _128M - -#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) -#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) - -/* PCI I/O MAP section */ -#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 -#define CONFIG_SYS_PCI0_IO_SIZE _16M -#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 -#define CONFIG_SYS_PCI1_IO_SIZE _16M - -#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) -#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000 -#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) -#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000 - -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE) - -#if defined (CONFIG_750CX) -#define CONFIG_SYS_PCI_IDSEL 0x0 -#else -#define CONFIG_SYS_PCI_IDSEL 0x30 -#endif - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET /* no reset for ide supported */ -#define CONFIG_IDE_PREINIT /* check for units */ - -#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 1 IDE busses */ -#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */ - -#define CONFIG_SYS_ATA_BASE_ADDR 0 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0 -#define CONFIG_SYS_ATA_IDE1_OFFSET 0 - -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ -#ifndef __ASSEMBLY__ -int ata_device(int dev); -#endif -#define ATA_DEVICE(dev) ata_device(dev) -#define CONFIG_ATAPI 1 - -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ - -/* SDRAM */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* init ram */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PCI0, PCI1 in one BAT */ -#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * 750FX IBAT and DBAT pairs (To_do: define regins for I(D)BAT4 - I(D)BAT7) - * IBAT4 and DBAT4 - * FIXME: ingo disable BATs for Linux Kernel - */ -/* #undef SETUP_HIGH_BATS_FX750 */ /* don't initialize BATS 4-7 */ -#define SETUP_HIGH_BATS_FX750 /* initialize BATS 4-7 */ - -#ifdef SETUP_HIGH_BATS_FX750 -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -/* IBAT5 and DBAT5 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_SDRAM2_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -/* IBAT6 and DBAT6 */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_SDRAM3_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT6L (CONFIG_SYS_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - -/* IBAT7 and DBAT7 */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - -#else /* set em out of range for Linux !!!!!!!!!!! */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -/* IBAT5 and DBAT5 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT4U - -/* IBAT6 and DBAT6 */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT6L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT4U - -/* IBAT7 and DBAT7 */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT4U - -#endif -/* FIXME: ingo end: disable BATs for Linux Kernel */ - -/* I2C addresses for the two DIMM SPD chips */ -#define DIMM0_I2C_ADDR 0x51 -#define DIMM1_I2C_ADDR 0x52 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_BOOT_FLASH_WIDTH 2 /* 16 bit */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ - -#if 0 -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */ -/* #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */ -#endif - -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x050 -#define CONFIG_ENV_OFFSET 0x200 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x600 /* 2048 bytes may be used for env vars*/ - -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ -#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-0x40) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/mpc74xx.h for the defines used here - */ - -/*#define CONFIG_SYS_L2*/ -#undef CONFIG_SYS_L2 - -/* #ifdef CONFIG_750CX*/ -#if defined (CONFIG_750CX) || defined (CONFIG_750FX) -#define L2_INIT 0 -#else -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#endif - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -#define CONFIG_SYS_BOARD_ASM_INIT 1 - -#define CPCI750_SLAVE_TEST (((in8(0xf0300000) & 0x80) == 0) ? 0 : 1) -#define CPCI750_ECC_TEST (((in8(0xf0300000) & 0x02) == 0) ? 1 : 0) -#define CONFIG_SYS_PLD_VER 0xf0e00000 - -#define CONFIG_OF_LIBFDT 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/DB64360.h b/include/configs/DB64360.h deleted file mode 100644 index b77c8b2..0000000 --- a/include/configs/DB64360.h +++ /dev/null @@ -1,579 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -/************************************************************************* - * (c) 2002 Datentechnik AG - Project: Dino - * - * - * $Id: DB64360.h,v 1.3 2003/04/26 04:58:13 brad Exp $ - * - ************************************************************************/ - -/************************************************************************* - * - * History: - * - * $Log: DB64360.h,v $ - * Revision 1.3 2003/04/26 04:58:13 brad - * Cosmetic changes and compiler warning cleanups - * - * Revision 1.2 2003/04/23 15:48:15 ingo - * mem. map output added - * - * Revision 1.1 2003/04/17 09:31:42 ias - * keymile changes 17_04_2003 - * - * Revision 1.10 2003/03/06 12:25:04 ias - * 750 FX CPU HID settings updated - * - * Revision 1.9 2003/03/03 16:14:36 ias - * cleanup compiler warnings of printf fuctions - * - * Revision 1.8 2003/03/03 15:11:44 ias - * Marvell MPSC-UART is working - * - * Revision 1.7 2003/02/26 12:15:45 ssu - * adapted default parameters to new board flash address - * - * Revision 1.6 2003/02/25 14:55:42 ssu - * changed default environment parameters - * - * Revision 1.5 2003/02/21 17:14:23 ias - * added extended SPD handling - * - * Revision 1.4 2003/01/14 09:16:08 ias - * PPCBoot for Marvel Beta 0.9 - * - * Revision 1.3 2002/12/03 13:56:26 ias - * Environment in flash support added - * - * Revision 1.2 2002/11/29 16:53:29 ias - * Flash support for STM added - * - * Revision 1.1 2002/11/29 13:36:31 ias - * Revision 0.1 of PPCBOOT (1.1.5) for Marvell DB64360 IBM750FX Board - * - working DDRRAM (only 32MByte of 128MB Modul) - * - working I2C Driver for SPD EEPROM read - * - working DUART 16650 for Serial Console - * - working "console" - * - * - * - ************************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* This define must be before the core.h include */ -#define CONFIG_DB64360 1 /* this is an DB64360 board */ - -#ifndef __ASSEMBLY__ -#include "../board/Marvell/include/core.h" -#endif - -/*-----------------------------------------------------*/ -/* #include "../board/db64360/local.h" */ -#ifndef __LOCAL_H -#define __LOCAL_H - -/* first ethernet */ -#define CONFIG_ETHADDR 64:36:00:00:00:01 - /* next two ethernet hwaddrs */ -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 64:36:00:00:00:02 -/* in the atlantis 64360 we have only 2 ETH port on the board, -if we use PCI it has its own MAC addr */ - -#define CONFIG_ENV_OVERWRITE -#endif /* __CONFIG_H */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_74xx /* we have a 750FX (override local.h) */ - -#define CONFIG_DB64360 1 /* this is an DB64360 board */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ -/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the - DRAM for ECC in the phase we are relocating to it, which isn't so sufficient. - so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase, - see sdram_init.c */ -#undef CONFIG_ECC /* enable ECC support */ -#define CONFIG_MV64360_ECC - -/* which initialization functions to call for this board */ -#define CONFIG_MISC_INIT_R /* initialize the icache L1 */ -#define CONFIG_BOARD_EARLY_INIT_F - -#define CONFIG_SYS_BOARD_NAME "DB64360" -#define CONFIG_IDENT_STRING "Marvell DB64360 (1.1)" - -/*#define CONFIG_SYS_HUSH_PARSER */ -#undef CONFIG_SYS_HUSH_PARSER - - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * what to do: - * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial - * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1 - * to 0 below. - * - * to use the MPSC, #define CONFIG_MPSC. If you have wired up another - * mpsc channel, change CONFIG_MPSC_PORT to the desired value. - */ - -#define CONFIG_MPSC_PORT 0 - -/* to change the default ethernet port, use this define (options: 0, 1, 2) */ -#define MV_ETH_DEVS 2 - -/* #undef CONFIG_ETHER_PORT_MII */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ -#endif -#define CONFIG_ZERO_BOOTDELAY_CHECK - - -#undef CONFIG_BOOTARGS -/*#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */ - -/* ronen - autoboot using tftp */ -#if (CONFIG_BOOTDELAY >= 0) -#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\ - setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \ - ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000; " - -#define CONFIG_BOOTARGS "console=ttyS0,115200" - -#endif - -/* ronen - the u-boot.bin should be ~0x30000 bytes */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \ -cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \ - "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \ -cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \ - "bootargs_root=root=/dev/nfs rw\0" \ - "bootargs_end=:::DB64360:eth0:none \0"\ - "ethprime=mv_enet0\0"\ - "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \ -ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" - -/* --------------------------------------------------------------------------------------------------------------- */ -/* New bootcommands for Marvell DB64360 c 2002 Ingo Assmus */ - -#define CONFIG_IPADDR 10.2.40.90 - -#define CONFIG_SERIAL "No. 1" -#define CONFIG_SERVERIP 10.2.1.126 -#define CONFIG_ROOTPATH "/mnt/yellow_dog_mini" - - -#define CONFIG_TESTDRAMDATA y -#define CONFIG_TESTDRAMADDRESS n -#define CONFIG_TESETDRAMWALK n - -/* --------------------------------------------------------------------------------------------------------------- */ - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor1" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ - -/* Use first bank for JFFS2, second bank contains U-Boot. - * - * Note: fake mtd_id's used, no linux mtd map file. - */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor1=db64360-1" -#define MTDPARTS_DEFAULT "mtdparts=db64360-1:-(jffs2)" -*/ - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_PCI -#define CONFIG_CMD_NET - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_MULTI_EEPROMS -#define CONFIG_SYS_I2C_SPEED 40000 /* I2C speed default */ - -/* #define CONFIG_SYS_GT_DUAL_CPU also for JTAG even with one cpu */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/*#define CONFIG_SYS_MEMTEST_START 0x00400000 memtest works on */ -/*#define CONFIG_SYS_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ -/*#define CONFIG_SYS_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */ - -/* -#define CONFIG_SYS_DRAM_TEST - * DRAM tests - * CONFIG_SYS_DRAM_TEST - enables the following tests. - * - * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines - * Environment variable 'test_dram_data' must be - * set to 'y'. - * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely - * addressable. Environment variable - * 'test_dram_address' must be set to 'y'. - * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. - * This test takes about 6 minutes to test 64 MB. - * Environment variable 'test_dram_walk' must be - * set to 'y'. - */ -#define CONFIG_SYS_DRAM_TEST -#if defined(CONFIG_SYS_DRAM_TEST) -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -/* #define CONFIG_SYS_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ -#define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ -#define CONFIG_SYS_DRAM_TEST_DATA -#define CONFIG_SYS_DRAM_TEST_ADDRESS -#define CONFIG_SYS_DRAM_TEST_WALK -#endif /* CONFIG_SYS_DRAM_TEST */ - -#undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */ -#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ - -#define CONFIG_SYS_LOAD_ADDR 0x00400000 /* default load address */ - -/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */ -#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ - -#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */ -#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 400MHZ -> 5.0 ns, for 133MHZ -> 7.50 ns */ - -/*ronen - this is the Tclk (MV64360 core) */ -#define CONFIG_SYS_TCLK 133000000 - - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_SYS_750FX_HID0 0x8000c084 -#define CONFIG_SYS_750FX_HID1 0x54800000 -#define CONFIG_SYS_750FX_HID2 0x00000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -/* - * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS - * To an unused memory region. The stack will remain in cache until RAM - * is initialized -*/ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* unused memory region */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -#define RELOCATE_INTERNAL_RAM_ADDR -#ifdef RELOCATE_INTERNAL_RAM_ADDR - #define CONFIG_SYS_INTERNAL_RAM_ADDR 0xf8000000 -#endif - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -/* Dummies for BAT 4-7 */ -#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */ -#define CONFIG_SYS_SDRAM2_BASE 0x20000000 -#define CONFIG_SYS_SDRAM3_BASE 0x30000000 -#define CONFIG_SYS_SDRAM4_BASE 0x40000000 -#define CONFIG_SYS_FLASH_BASE 0xfff00000 - -#define CONFIG_SYS_DFL_BOOTCS_BASE 0xff800000 -#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS*/ - -#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */ -#define UART_BASE_BOOTM 0xfbb00000 /* in order to be sync with the kernel parameters. */ -#define PCI0_IO_BASE_BOOTM 0xfd000000 - -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ - -/* areas to map different things with the GT in physical space */ -#define CONFIG_SYS_DRAM_BANKS 4 - -/* What to put in the bats. */ -#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 - -/* Peripheral Device section */ - -/*******************************************************/ -/* We have on the db64360 Board : */ -/* GT-Chipset Register Area */ -/* GT-Chipset internal SRAM 256k */ -/* SRAM on external device module */ -/* Real time clock on external device module */ -/* dobble UART on external device module */ -/* Data flash on external device module */ -/* Boot flash on external device module */ -/*******************************************************/ -#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ -#define CONFIG_SYS_DB64360_RESET_ADDR 0x14000000 /* After power on Reset the DB64360 is here */ - -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ -#define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ -#define CONFIG_SYS_DEV_BASE 0xfc000000 /* GT Devices CS start here */ - -#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE /* DEV_CS0 device modul sram */ -#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */ -#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */ -#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE) /* DEV_CS3 device modul large flash */ - -#define CONFIG_SYS_DEV0_SIZE _8M /* db64360 sram @ 0xfc00.0000 */ -#define CONFIG_SYS_DEV1_SIZE _8M /* db64360 rtc @ 0xfc80.0000 */ -#define CONFIG_SYS_DEV2_SIZE _16M /* db64360 duart @ 0xfd00.0000 */ -#define CONFIG_SYS_DEV3_SIZE _16M /* db64360 flash @ 0xfe00.0000 */ -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ - -/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */ -#define CONFIG_SYS_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */ -#define CONFIG_SYS_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */ -#define CONFIG_SYS_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */ -#define CONFIG_SYS_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */ -#define CONFIG_SYS_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */ - - /* c 4 a 8 2 4 1 c */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ - /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ - /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ - /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ - - -/* ronen - update MPP Control MV64360*/ -#define CONFIG_SYS_MPP_CONTROL_0 0x02222222 -#define CONFIG_SYS_MPP_CONTROL_1 0x11333011 -#define CONFIG_SYS_MPP_CONTROL_2 0x40431111 -#define CONFIG_SYS_MPP_CONTROL_3 0x00000044 - -/*# define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */ - - -# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/ - /* gpp[31] gpp[30] gpp[29] gpp[28] */ - /* gpp[27] gpp[24]*/ - /* gpp[19:14] */ - -/* setup new config_value for MV64360 DDR-RAM !! */ -# define CONFIG_SYS_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ - -#define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE -#define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */ -#define CONFIG_SYS_INIT_CHAN1 -#define CONFIG_SYS_INIT_CHAN2 - -#define SRAM_BASE CONFIG_SYS_DEV0_SPACE -#define SRAM_SIZE 0x00100000 /* 1 MB of sram */ - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ - -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_EEPRO100 /* ronen - Support for Intel 82557/82559/82559ER chips */ - -/* PCI MEMORY MAP section */ -#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI0_MEM_SIZE _128M -#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 -#define CONFIG_SYS_PCI1_MEM_SIZE _128M - -#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) -#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) - -/* PCI I/O MAP section */ -#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 -#define CONFIG_SYS_PCI0_IO_SIZE _16M -#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 -#define CONFIG_SYS_PCI1_IO_SIZE _16M - -#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) -#define CONFIG_SYS_PCI0_IO_SPACE_PCI (CONFIG_SYS_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */ -#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) -#define CONFIG_SYS_PCI1_IO_SPACE_PCI (CONFIG_SYS_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */ - -#if defined (CONFIG_750CX) -#define CONFIG_SYS_PCI_IDSEL 0x0 -#else -#define CONFIG_SYS_PCI_IDSEL 0x30 -#endif -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ - -/* SDRAM */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* init ram */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PCI0, PCI1 in one BAT */ -#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* I2C addresses for the two DIMM SPD chips */ -#define DIMM0_I2C_ADDR 0x56 -#define DIMM1_I2C_ADDR 0x54 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CONFIG_SYS_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */ -#define CONFIG_SYS_EXTRA_FLASH_WIDTH 4 /* 32 bit */ -#define CONFIG_SYS_BOOT_FLASH_WIDTH 1 /* 8 bit */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ -#define CONFIG_SYS_FLASH_CFI 1 - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */ -/* #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/mpc74xx.h for the defines used here - */ - -#define CONFIG_SYS_L2 - - -#if defined (CONFIG_750CX) || defined (CONFIG_750FX) -#define L2_INIT 0 -#else - -#define L2_INIT 0 -/* -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -*/ -#endif - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -#define CONFIG_SYS_BOARD_ASM_INIT 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/DB64460.h b/include/configs/DB64460.h deleted file mode 100644 index abc4434..0000000 --- a/include/configs/DB64460.h +++ /dev/null @@ -1,517 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* This define must be before the core.h include */ -#define CONFIG_DB64460 1 /* this is an DB64460 board */ - -#ifndef __ASSEMBLY__ -#include "../board/Marvell/include/core.h" -#endif - -/*-----------------------------------------------------*/ -/* #include "../board/db64460/local.h" */ -#ifndef __LOCAL_H -#define __LOCAL_H - -#define CONFIG_ETHADDR 64:46:00:00:00:01 -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 64:46:00:00:00:02 -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 64:46:00:00:00:03 - -#define CONFIG_ENV_OVERWRITE -#endif /* __CONFIG_H */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_74xx /* we have a 750FX (override local.h) */ - -#define CONFIG_DB64460 1 /* this is an DB64460 board */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */ -/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the - DRAM for ECC in the phase we are relocating to it, which isn't so sufficient. - so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase, - see sdram_init.c */ -#undef CONFIG_ECC /* enable ECC support */ -#define CONFIG_MV64460_ECC - -/* which initialization functions to call for this board */ -#define CONFIG_MISC_INIT_R /* initialize the icache L1 */ -#define CONFIG_BOARD_EARLY_INIT_F - -#define CONFIG_SYS_BOARD_NAME "DB64460" -#define CONFIG_IDENT_STRING "Marvell DB64460 (1.0)" - -/*#define CONFIG_SYS_HUSH_PARSER */ -#undef CONFIG_SYS_HUSH_PARSER - - -/* - * The following defines let you select what serial you want to use - * for your console driver. - * - * what to do: - * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial - * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1 - * to 0 below. - * - * to use the MPSC, #define CONFIG_MPSC. If you have wired up another - * mpsc channel, change CONFIG_MPSC_PORT to the desired value. - */ - -#define CONFIG_MPSC_PORT 0 - -/* to change the default ethernet port, use this define (options: 0, 1, 2) */ -#define MV_ETH_DEVS 3 - -/* #undef CONFIG_ETHER_PORT_MII */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ -#endif -#define CONFIG_ZERO_BOOTDELAY_CHECK - - -#undef CONFIG_BOOTARGS -/*#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */ - -/* ronen - autoboot using tftp */ -#if (CONFIG_BOOTDELAY >= 0) -#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\ - setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \ - ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000; " - -#define CONFIG_BOOTARGS "console=ttyS0,115200" - -#endif - -/* ronen - the u-boot.bin should be ~0x30000 bytes */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \ -cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \ - "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \ -cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \ - "bootargs_root=root=/dev/nfs rw\0" \ - "bootargs_end=:::DB64460:eth0:none \0"\ - "ethprime=mv_enet0\0"\ - "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \ -ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" - -/* --------------------------------------------------------------------------------------------------------------- */ -/* New bootcommands for Marvell DB64460 c 2002 Ingo Assmus */ - -#define CONFIG_IPADDR 10.2.40.90 - -#define CONFIG_SERIAL "No. 1" -#define CONFIG_SERVERIP 10.2.1.126 -#define CONFIG_ROOTPATH "/mnt/yellow_dog_mini" - - -#define CONFIG_TESTDRAMDATA y -#define CONFIG_TESTDRAMADDRESS n -#define CONFIG_TESETDRAMWALK n - -/* --------------------------------------------------------------------------------------------------------------- */ - -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#undef CONFIG_ALTIVEC /* undef to disable */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor1" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ - -/* Use first bank for JFFS2, second bank contains U-Boot. - * - * Note: fake mtd_id's used, no linux mtd map file. - */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor1=db64460-1" -#define MTDPARTS_DEFAULT "mtdparts=db64460-1:-(jffs2)" -*/ - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_PCI -#define CONFIG_CMD_NET - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_MULTI_EEPROMS -#define CONFIG_SYS_I2C_SPEED 40000 /* I2C speed default */ - -/* #define CONFIG_SYS_GT_DUAL_CPU also for JTAG even with one cpu */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/*#define CONFIG_SYS_MEMTEST_START 0x00400000 memtest works on */ -/*#define CONFIG_SYS_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ -/*#define CONFIG_SYS_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */ - -/* -#define CONFIG_SYS_DRAM_TEST - * DRAM tests - * CONFIG_SYS_DRAM_TEST - enables the following tests. - * - * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines - * Environment variable 'test_dram_data' must be - * set to 'y'. - * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely - * addressable. Environment variable - * 'test_dram_address' must be set to 'y'. - * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. - * This test takes about 6 minutes to test 64 MB. - * Environment variable 'test_dram_walk' must be - * set to 'y'. - */ -#define CONFIG_SYS_DRAM_TEST -#if defined(CONFIG_SYS_DRAM_TEST) -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -/* #define CONFIG_SYS_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */ -#define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ -#define CONFIG_SYS_DRAM_TEST_DATA -#define CONFIG_SYS_DRAM_TEST_ADDRESS -#define CONFIG_SYS_DRAM_TEST_WALK -#endif /* CONFIG_SYS_DRAM_TEST */ - -#undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */ -#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ - -#define CONFIG_SYS_LOAD_ADDR 0x00400000 /* default load address */ - -/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */ -#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ - -#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */ -#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 200MHZ -> 5.0 ns, 166MHZ -> 6.0, 133MHZ -> 7.50 ns */ - -/*ronen - this is the Tclk (MV64460 core) */ -#define CONFIG_SYS_TCLK 133000000 - - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_SYS_750FX_HID0 0x8000c084 -#define CONFIG_SYS_750FX_HID1 0x54800000 -#define CONFIG_SYS_750FX_HID2 0x00000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -/* - * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS - * To an unused memory region. The stack will remain in cache until RAM - * is initialized -*/ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* unused memory region */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -#define RELOCATE_INTERNAL_RAM_ADDR -#ifdef RELOCATE_INTERNAL_RAM_ADDR - #define CONFIG_SYS_INTERNAL_RAM_ADDR 0xf8000000 -#endif - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -/* Dummies for BAT 4-7 */ -#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */ -#define CONFIG_SYS_SDRAM2_BASE 0x20000000 -#define CONFIG_SYS_SDRAM3_BASE 0x30000000 -#define CONFIG_SYS_SDRAM4_BASE 0x40000000 -#define CONFIG_SYS_FLASH_BASE 0xfff00000 - -#define CONFIG_SYS_DFL_BOOTCS_BASE 0xff800000 -#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS*/ - -#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */ -#define UART_BASE_BOOTM 0xfbb00000 /* in order to be sync with the kernel parameters. */ -#define PCI0_IO_BASE_BOOTM 0xfd000000 - -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ - -/* areas to map different things with the GT in physical space */ -#define CONFIG_SYS_DRAM_BANKS 4 - -/* What to put in the bats. */ -#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 - -/* Peripheral Device section */ - -/*******************************************************/ -/* We have on the db64460 Board : */ -/* GT-Chipset Register Area */ -/* GT-Chipset internal SRAM 256k */ -/* SRAM on external device module */ -/* Real time clock on external device module */ -/* dobble UART on external device module */ -/* Data flash on external device module */ -/* Boot flash on external device module */ -/*******************************************************/ -#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ -#define CONFIG_SYS_DB64460_RESET_ADDR 0x14000000 /* After power on Reset the DB64460 is here */ - -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ -#define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ -#define CONFIG_SYS_DEV_BASE 0xfc000000 /* GT Devices CS start here */ - -#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE /* DEV_CS0 device modul sram */ -#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */ -#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */ -#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE) /* DEV_CS3 device modul large flash */ - -#define CONFIG_SYS_DEV0_SIZE _8M /* db64460 sram @ 0xfc00.0000 */ -#define CONFIG_SYS_DEV1_SIZE _8M /* db64460 rtc @ 0xfc80.0000 */ -#define CONFIG_SYS_DEV2_SIZE _16M /* db64460 duart @ 0xfd00.0000 */ -#define CONFIG_SYS_DEV3_SIZE _16M /* db64460 flash @ 0xfe00.0000 */ -/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ - -/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */ -#define CONFIG_SYS_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */ -#define CONFIG_SYS_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */ -#define CONFIG_SYS_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */ -#define CONFIG_SYS_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */ -#define CONFIG_SYS_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */ - - /* c 4 a 8 2 4 1 c */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ - /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ - /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ - /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ - - -/* ronen - update MPP Control MV64460*/ -#define CONFIG_SYS_MPP_CONTROL_0 0x02222222 -#define CONFIG_SYS_MPP_CONTROL_1 0x11333011 -#define CONFIG_SYS_MPP_CONTROL_2 0x40431111 -#define CONFIG_SYS_MPP_CONTROL_3 0x00000044 - -/*# define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */ - - -# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/ - /* gpp[31] gpp[30] gpp[29] gpp[28] */ - /* gpp[27] gpp[24]*/ - /* gpp[19:14] */ - -/* setup new config_value for MV64460 DDR-RAM !! */ -# define CONFIG_SYS_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ - -#define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE -#define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */ -#define CONFIG_SYS_INIT_CHAN1 -#define CONFIG_SYS_INIT_CHAN2 - -#define SRAM_BASE CONFIG_SYS_DEV0_SPACE -#define SRAM_SIZE 0x00100000 /* 1 MB of sram */ - - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ - -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_EEPRO100 /* ronen - Support for Intel 82557/82559/82559ER chips */ - -/* PCI MEMORY MAP section */ -#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI0_MEM_SIZE _128M -#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 -#define CONFIG_SYS_PCI1_MEM_SIZE _128M - -#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) -#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) - -/* PCI I/O MAP section */ -#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 -#define CONFIG_SYS_PCI0_IO_SIZE _16M -#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 -#define CONFIG_SYS_PCI1_IO_SIZE _16M - -#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) -#define CONFIG_SYS_PCI0_IO_SPACE_PCI (CONFIG_SYS_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */ -#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) -#define CONFIG_SYS_PCI1_IO_SPACE_PCI (CONFIG_SYS_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */ - -#if defined (CONFIG_750CX) -#define CONFIG_SYS_PCI_IDSEL 0x0 -#else -#define CONFIG_SYS_PCI_IDSEL 0x30 -#endif -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ - -/* SDRAM */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* init ram */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PCI0, PCI1 in one BAT */ -#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* I2C addresses for the two DIMM SPD chips */ -#define DIMM0_I2C_ADDR 0x56 -#define DIMM1_I2C_ADDR 0x54 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CONFIG_SYS_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */ -#define CONFIG_SYS_EXTRA_FLASH_WIDTH 4 /* 32 bit */ -#define CONFIG_SYS_BOOT_FLASH_WIDTH 1 /* 8 bit */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ -#define CONFIG_SYS_FLASH_CFI 1 - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */ -/* #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/mpc74xx.h for the defines used here - */ - -#define CONFIG_SYS_L2 - - -#if defined (CONFIG_750CX) || defined (CONFIG_750FX) -#define L2_INIT 0 -#else - -#define L2_INIT 0 -/* -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -*/ -#endif - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -#define CONFIG_SYS_BOARD_ASM_INIT 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/HWW1U1A.h b/include/configs/HWW1U1A.h deleted file mode 100644 index 6a3a11c..0000000 --- a/include/configs/HWW1U1A.h +++ /dev/null @@ -1,460 +0,0 @@ -/* - * Copyright 2009-2010 eXMeritus, A Boeing Company - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * HardwareWall HWW-1U-1A airborne unit configuration file - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High-level system configuration options */ -#define CONFIG_BOOKE /* Power/PowerPC Book-E */ -#define CONFIG_E500 /* e500 (Power ISA v2.03 with SPE) */ -#define CONFIG_FSL_ELBC /* FreeScale Enhanced LocalBus Cntlr */ -#define CONFIG_FSL_LAW /* FreeScale Local Access Window */ -#define CONFIG_P2020 /* FreeScale P2020 */ -#define CONFIG_HWW1U1A /* eXMeritus HardwareWall HWW-1U-1A */ -#define CONFIG_MP /* Multiprocessing support */ -#define CONFIG_HWCONFIG /* Use hwconfig from environment */ - -#define CONFIG_L2_CACHE /* L2 cache enabled */ -#define CONFIG_BTB /* Branch predition enabled */ - -#define CONFIG_PANIC_HANG /* No board reset on panic */ -#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r() */ -#define CONFIG_CMD_REGINFO /* Dump various CPU regs */ - -/* - * Allow the use of 36-bit physical addresses. Device-trees with 64-bit - * addresses have known compatibility issues with some existing kernels. - */ -#define CONFIG_ENABLE_36BIT_PHYS -#define CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* Number of entries in TLB1 */ - -/* Reserve plenty of RAM for malloc (we have 2GB+) */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) - -/* How much L2 cache do we map so we can use it as RAM */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -/* This is our temporary global data area just above the stack */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* The stack grows down from the global data area */ -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* Enable IRQs and watchdog with a 1000Hz system decrementer */ -#define CONFIG_CMD_IRQ - -/* -------------------------------------------------------------------- */ - -/* - * Clock crystal configuration: - * (1) SYS: 66.666MHz +/- 50ppm (drives CPU/PCI/DDR) - * (2) CCB: Multiplier from SYS_CLK - * (3) RTC: 25.000MHz +/- 50ppm (sampled against CCB clock) - */ -#define CONFIG_SYS_CLK_FREQ 66666000/*Hz*/ -#define CONFIG_DDR_CLK_FREQ 66666000/*Hz*/ - - -/* -------------------------------------------------------------------- */ - -/* - * Memory map - * - * 0x0000_0000 0x7fff_ffff 2G DDR2 ECC SDRAM - * 0x8000_0000 0x9fff_ffff 512M PCI-E Bus 1 - * 0xa000_0000 0xbfff_ffff 512M PCI-E Bus 2 (unused) - * 0xc000_0000 0xdfff_ffff 512M PCI-E Bus 3 - * 0xe000_0000 0xe7ff_ffff 128M Spansion FLASH - * 0xe800_0000 0xefff_ffff 128M Spansion FLASH - * 0xffd0_0000 0xffd0_3fff 16K L1 boot stack (TLB0) - * 0xffe0_0000 0xffef_ffff 1M CCSR - * 0xffe0_5000 0xffe0_5fff 4K Enhanced LocalBus Controller - */ - -/* Virtual Memory Map */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_FLASH_BASE 0xe0000000 -#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 -#define CONFIG_SYS_CCSRBAR 0xffe00000 /* CCSRBAR @ runtime */ - -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ - -/* Physical Memory Map */ -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull -#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull -#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull -#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfffd00000ull -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf /* for ASM code */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xffd00000 /* for ASM code */ -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf /* for ASM code */ -#define CONFIG_SYS_CCSRBAR_PHYS_LOW 0xffe00000 /* for ASM code */ - - -/* -------------------------------------------------------------------- */ - -/* U-Boot image (MONITOR_BASE == TEXT_BASE) */ -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc /* Top address in flash */ -#define CONFIG_SYS_TEXT_BASE 0xeff80000 /* Start of U-Boot image */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN 0x80000 /* 512kB (4 flash sectors) */ - -/* - * U-Boot Environment Image: The two sectors immediately below U-Boot - * form the U-Boot environment (regular and redundant). - */ -#define CONFIG_ENV_IS_IN_FLASH /* The environment image is stored in FLASH */ -#define CONFIG_ENV_OVERWRITE /* Allow "protected" variables to be erased */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128kB (1 flash sector) */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) - -/* Only use 8kB of each environment sector for data */ -#define CONFIG_ENV_SIZE 0x2000 /* 8kB */ -#define CONFIG_ENV_SIZE_REDUND 0x2000 /* 8kB */ - - -/* -------------------------------------------------------------------- */ - -/* Serial Console Configuration */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* Echo back characters received during a serial download */ -#define CONFIG_LOADS_ECHO - -/* Allow a serial-download to temporarily change baud */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE - - -/* -------------------------------------------------------------------- */ - -/* PCI and PCI-Express Support */ -#define CONFIG_PCI /* Enable PCI/PCIE */ -#define CONFIG_PCI_PNP /* Scan PCI busses */ -#define CONFIG_CMD_PCI /* Enable the "pci" command */ -#define CONFIG_FSL_PCI_INIT /* Common FreeScale PCI initialization */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET /* We have PCI-E reset errata */ -#define CONFIG_SYS_PCI_64BIT /* PCI resources are 64-bit */ -#define CONFIG_PCI_SCAN_SHOW /* Display PCI scan during boot */ - -/* Enable 2 of the 3 PCI-E controllers */ -#define CONFIG_PCIE3 -#undef CONFIG_PCIE2 -#define CONFIG_PCIE1 - -/* Display human-readable names when initializing */ -#define CONFIG_SYS_PCIE3_NAME "Intel 82571EB" -#define CONFIG_SYS_PCIE2_NAME "Unused" -#define CONFIG_SYS_PCIE1_NAME "Silicon Image SIL3531" - -/* - * PCI bus addresses - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 - - -/* -------------------------------------------------------------------- */ - -/* Generic FreeScale hardware I2C support */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } -#define CONFIG_CMD_I2C - -/* DDR2 SO-RDIMM SPD EEPROM is at I2C0-0x51 */ -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS 0x51 - -/* DS1339 RTC is at I2C0-0x68 (I know it says "DS1337", it's a DS1339) */ -#define CONFIG_CMD_DATE -#define CONFIG_RTC_DS1337 -#define CONFIG_SYS_RTC_BUS_NUM 0 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -/* Turn off RTC square-wave output to save battery */ -#define CONFIG_SYS_RTC_DS1337_NOOSC - -/* - * AT24C128N EEPROM at I2C0-0x53. - * - * That Atmel EEPROM has 128kbit of memory (16kByte) divided into 256 pages - * of 64 bytes per page. The chip uses 2-byte addresses and has a max write - * cycle time of 20ms according to the datasheet. - * - * NOTE: Our environment is stored on regular direct-attached FLASH, this - * chip is only used as a write-protected backup for certain key settings - * such as the serial# and macaddr values. (EG: "env import") - */ -#define CONFIG_CMD_EEPROM -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 1 << 6 == 64 byte pages */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 21 - -/* - * PCA9554 is at I2C1-0x3f (I know it says "PCA953X", it's a PCA9554). You - * must first select the I2C1 bus with "i2c dev 1" or the "pca953x" command - * will not be able to access the chip. - */ -#define CONFIG_PCA953X -#define CONFIG_CMD_PCA953X -#define CONFIG_CMD_PCA953X_INFO -#define CONFIG_SYS_I2C_PCA953X_ADDR 0x3f - - -/* -------------------------------------------------------------------- */ - -/* FreeScale DDR2/3 SDRAM Controller */ -#define CONFIG_SYS_FSL_DDR2 /* Our SDRAM slot is DDR2 */ -#define CONFIG_DDR_ECC /* Enable ECC by default */ -#define CONFIG_DDR_SPD /* Detect DDR config from SPD EEPROM */ -#define CONFIG_SPD_EEPROM /* ...why 2 config variables for this? */ -#define CONFIG_VERY_BIG_RAM /* Allow 2GB+ of RAM */ -#define CONFIG_CMD_SDRAM - -/* Standard P2020 DDR controller parameters */ -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 - -/* Make sure to tell the DDR controller to preinitialze all of RAM */ -#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER - - -/* -------------------------------------------------------------------- */ - -/* FLASH Memory Configuration (2x 128MB SPANSION FLASH) */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 - -/* Flash banks (2x 128MB) */ -#define FLASH0_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000ull) -#define FLASH1_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x0000000ull) -#define CONFIG_SYS_MAX_FLASH_BANKS 2 -#define CONFIG_SYS_MAX_FLASH_SECT 1024 -#define CONFIG_SYS_FLASH_BANKS_LIST { FLASH0_PHYS, FLASH1_PHYS } - -/* - * Flash access modes and timings (values are the defaults after a RESET). - * - * NOTE: These could probably be optimized but are more than sufficient for - * this particular system for the moment. - */ -#define FLASH_BRx (BR_PS_16 | BR_MS_GPCM | BR_V) -#define FLASH_ORx (OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) - -/* Configure both flash banks */ -#define CONFIG_SYS_BR0_PRELIM (FLASH_BRx | BR_PHYS_ADDR(FLASH0_PHYS)) -#define CONFIG_SYS_BR1_PRELIM (FLASH_BRx | BR_PHYS_ADDR(FLASH1_PHYS)) -#define CONFIG_SYS_OR0_PRELIM (FLASH_ORx | OR_AM_128MB) -#define CONFIG_SYS_OR1_PRELIM (FLASH_ORx | OR_AM_128MB) - -/* Flash timeouts (in ms) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000UL /* Erase (60s) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500UL /* Write (0.5s) */ - -/* Quiet flash testing */ -#define CONFIG_SYS_FLASH_QUIET_TEST - -/* Make program/erase count down from 45/5 (9....8....7....) */ -#define CONFIG_FLASH_SHOW_PROGRESS 45 - - -/* -------------------------------------------------------------------- */ - -/* Ethernet Device Support */ -#define CONFIG_MII /* Enable MII PHY code */ -#define CONFIG_MII_DEFAULT_TSEC /* ??? Copied from P2020DS */ -#define CONFIG_PHY_GIGE /* Support Gigabit PHYs */ -#define CONFIG_ETHPRIME "e1000#0" /* Default to external ports */ - -/* Turn on various helpful networking commands */ -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING - -/* On-chip FreeScale P2020 "tsec" Ethernet (oneway fibers and peer) */ -#define CONFIG_TSEC_ENET -#define CONFIG_TSEC1 -#define CONFIG_TSEC2 -#define CONFIG_TSEC3 -#define CONFIG_TSEC1_NAME "owt0" -#define CONFIG_TSEC2_NAME "owt1" -#define CONFIG_TSEC3_NAME "peer" -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 3 -#define TSEC3_PHY_ADDR 4 -#define TSEC3_PHY_ADDR_CPUA 4 -#define TSEC3_PHY_ADDR_CPUB 5 - -/* PCI-E dual-port E1000 (external ethernet ports) */ -#define CONFIG_E1000 -#define CONFIG_E1000_SPI -#define CONFIG_E1000_SPI_GENERIC -#define CONFIG_CMD_E1000 - -/* We need the SPI infrastructure to poke the E1000's EEPROM */ -#define CONFIG_SPI -#define CONFIG_SPI_X -#define CONFIG_CMD_SPI -#define MAX_SPI_BYTES 32 - - -/* -------------------------------------------------------------------- */ - -/* USB Thumbdrive Device Support */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_FSL -#define CONFIG_USB_STORAGE -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_CMD_USB - -/* Partition and Filesystem support */ -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_ISO_PARTITION -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT - - -/* -------------------------------------------------------------------- */ - -/* Command line configuration. */ -#define CONFIG_CMDLINE_EDITING /* Enable command editing */ -#define CONFIG_COMMAND_HISTORY /* Enable command history */ -#define CONFIG_AUTO_COMPLETE /* Enable command completion */ -#define CONFIG_SYS_LONGHELP /* Enable detailed command help */ -#define CONFIG_SYS_MAXARGS 128 /* Up to 128 command-line args */ -#define CONFIG_SYS_PBSIZE 8192 /* Allow up to 8k printed lines */ -#define CONFIG_SYS_CBSIZE 4096 /* Allow up to 4k command lines */ -#define CONFIG_SYS_BARGSIZE 4096 /* Allow up to 4k boot args */ -#define CONFIG_SYS_HUSH_PARSER /* Enable a fancier shell */ - -/* A little extra magic here for the prompt */ -#define CONFIG_SYS_PROMPT hww1u1a_get_ps1() -#ifndef __ASSEMBLY__ -const char *hww1u1a_get_ps1(void); -#endif - -/* Include a bunch of default commands we probably want */ -#include <config_cmd_default.h> - -/* Other helpful shell-like commands */ -#define CONFIG_MD5 -#define CONFIG_SHA1 -#define CONFIG_CMD_MD5SUM -#define CONFIG_CMD_SHA1SUM -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_SETEXPR - - -/* -------------------------------------------------------------------- */ - -/* Image manipulation and booting */ - -/* We use the OpenFirmware-esque "Flattened Device Tree" */ -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP -#define CONFIG_OF_STDOUT_VIA_ALIAS - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMD_ELF -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Maximum kernel memory map */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Maximum kernel size of 64MB */ - -/* This is the default address for commands with an optional address arg */ -#define CONFIG_LOADADDR 100000 -#define CONFIG_SYS_LOAD_ADDR 0x100000 - -/* Test memory starting from the default load address to just below 2GB */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_LOAD_ADDR -#define CONFIG_SYS_MEMTEST_END 0x7f000000 - -#define CONFIG_BOOTDELAY 20 -#define CONFIG_BOOTCOMMAND "echo Not yet flashed" -#define CONFIG_BOOTARGS "" -#define CONFIG_BOOTARGS_DYNAMIC "console=ttyS0,${baudrate}n1" - -/* Extra environment parameters */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "ethprime=e1000#0\0" \ - "ethrotate=no\0" \ - "setbootargs=setenv bootargs " \ - "\"${bootargs} "CONFIG_BOOTARGS_DYNAMIC"\"\0" \ - "perf_mode=performance\0" \ - "hwconfig=" "fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;" \ - "usb1:dr_mode=host,phy_type=ulpi\0" \ - "flkernel=0xe8000000\0" \ - "flinitramfs=0xe8800000\0" \ - "fldevicetree=0xeff20000\0" \ - "flbootm=bootm ${flkernel} ${flinitramfs} ${fldevicetree}\0" \ - "flboot=run preboot; run flbootm\0" \ - "restore_eeprom=i2c dev 0 && " \ - "eeprom read $loadaddr 0x0000 0x2000 && " \ - "env import -c $loadaddr 0x2000\0" - -#endif /* __CONFIG_H */ diff --git a/include/configs/ICU862.h b/include/configs/ICU862.h deleted file mode 100644 index 16af4bb..0000000 --- a/include/configs/ICU862.h +++ /dev/null @@ -1,443 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <mpc8xx_irq.h> - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_ICU862 1 -#define CONFIG_MPC862 1 - -#define CONFIG_SYS_TEXT_BASE 0x40F00000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ - -#ifdef CONFIG_100MHz -#define MPC8XX_FACT 24 /* Multiply by 24 */ -#define MPC8XX_XIN 4165000 /* 4.165 MHz in */ -#define CONFIG_8xx_GCLK_FREQ (MPC8XX_FACT * MPC8XX_XIN) - /* define if cant' use get_gclk_freq */ -#else -#if 1 /* for 50MHz version of processor */ -#define MPC8XX_FACT 12 /* Multiply by 12 */ -#define MPC8XX_XIN 4000000 /* 4 MHz in */ -#define CONFIG_8xx_GCLK_FREQ 48000000 /* define if cant use get_gclk_freq */ -#else /* for 80MHz version of processor */ -#define MPC8XX_FACT 20 /* Multiply by 20 */ -#define MPC8XX_XIN 4000000 /* 4 MHz in */ -#define CONFIG_8xx_GCLK_FREQ 80000000 /* define if cant use get_gclk_freq */ -#endif -#endif - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ -#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ -#define CONFIG_MII 1 -#if 1 -#define CONFIG_SYS_DISCOVER_PHY 1 -#else -#undef CONFIG_SYS_DISCOVER_PHY -#endif - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CONFIG_SYS_EEPROM_X40430 /* Use a Xicor X40430 EEPROM */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16 bytes page write mode */ - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 -#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_FLASH_SIZE ((uint)(16 * 1024 * 1024)) /* max 16Mbyte */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#if 0 -#if defined(DEBUG) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#else -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x00F40000 - -#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */ -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control (15-29) - */ -#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#ifdef CONFIG_100MHz /* for 100 MHz, external bus is half CPU clock */ -#define SCCR_MASK 0 -#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \ - SCCR_DFLCD000 |SCCR_DFALCD00 | SCCR_EBDF01) -#else /* up to 50 MHz we use a 1:1 clock */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \ - SCCR_DFLCD000 |SCCR_DFALCD00 ) -#endif /* CONFIG_100MHz */ - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration Register 19-4 - *----------------------------------------------------------------------- - */ -/* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */ -#define CONFIG_SYS_RCCR 0x0020 - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * PCMCIA Power Switch - * - * The ICU862 uses a TPS2205 PC-Card Power-Interface Switch to - * control the voltages on the PCMCIA slot which is connected to Port B - *----------------------------------------------------------------------- - */ - /* Output pins */ -#define TPS2205_VCC5 0x00008000 /* PB.16: 5V Voltage Control */ -#define TPS2205_VCC3 0x00004000 /* PB.17: 3V Voltage Control */ -#define TPS2205_VPP_PGM 0x00002000 /* PB.18: PGM Voltage Control */ -#define TPS2205_VPP_VCC 0x00001000 /* PB.19: VPP Voltage Control */ -#define TPS2205_SHDN 0x00000200 /* PB.22: Shutdown */ -#define TPS2205_OUTPUTS ( TPS2205_VCC5 | TPS2205_VCC3 | \ - TPS2205_VPP_PGM | TPS2205_VPP_VCC | \ - TPS2205_SHDN) - - /* Input pins */ -#define TPS2205_OC 0x00000100 /* PB.23: Over-Current */ -#define TPS2205_INPUTS ( TPS2205_OC ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x0 /* FLASH bank #1 */ - -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) - -#define CONFIG_SYS_OR0_PRELIM 0xFF000954 /* Real values for the board */ -#define CONFIG_SYS_BR0_PRELIM 0x40000001 /* Real values for the board */ - -/* - * BR1 and OR1 (SDRAM) - */ -#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000800 /* BIH is not set */ - -#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM) -#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SYS_MAMR 0x13a01114 - -#ifdef CONFIG_MPC860T - -/* Interrupt level assignments. -*/ -#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ - -#endif /* CONFIG_MPC860T */ - - -#endif /* __CONFIG_H */ diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h deleted file mode 100644 index 8ccb0ff..0000000 --- a/include/configs/IDS8247.h +++ /dev/null @@ -1,462 +0,0 @@ -/* - * (C) Copyright 2005 - * Heiko Schocher, DENX Software Engineering, <hs@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8272_FAMILY 1 -#define CONFIG_IDS8247 1 -#define CPU_ID_STR "MPC8247" -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw " \ - "console=ttyS0,115200\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "bootfile=/tftpboot/IDS8247/uImage\0" \ - "kernel_addr=ff800000\0" \ - "ramdisk_addr=ffa00000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_MISC_INIT_R 1 - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 400000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F -/* - * Software (bit-bang) I2C driver configuration - */ - -#define I2C_PORT 0 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00000080) -#define I2C_TRISTATE (iop->pdir &= ~0x00000080) -#define I2C_READ ((iop->pdat & 0x00000080) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000080; \ - else iop->pdat &= ~0x00000080 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000100; \ - else iop->pdat &= ~0x00000100 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#if 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CONFIG_I2C_X -#endif - -/* - * select serial console configuration - * use the extern UART for the console - */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#define CONFIG_SYS_NS16550_CLK 14745600 - -#define CONFIG_SYS_UART_BASE 0xE0000000 -#define CONFIG_SYS_UART_SIZE 0x10000 - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_UART_BASE + 0x8000) - - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc@f0000000/serial8250@e0008000" - - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ -#define CONFIG_ETHER_ON_FCC1 -#define FCC_ENET - -/* - * - Rx-CLK is CLK10 - * - Tx-CLK is CLK9 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#define CONFIG_8260_CLKIN 66666666 /* in Hz */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_PCF8563 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NFS -#define CONFIG_CMD_NAND -#define CONFIG_CMD_I2C -#define CONFIG_CMD_SNTP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { 0xFF800000 } -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ids8247/config.mk - * The main FLASH is whichever is connected to *CS0. - */ -#define CONFIG_SYS_FLASH0_BASE 0xFFF00000 -#define CONFIG_SYS_FLASH0_SIZE 8 - -/* Flash bank size (for preliminary settings) - */ -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -/* Environment in flash */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x60000) -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#if defined(CONFIG_CMD_NAND) - -#define CONFIG_SYS_NAND0_BASE 0xE1000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ - -#endif /* CONFIG_CMD_NAND */ - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CONFIG_SYS_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. - */ -#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000) - -/* no slaves so just fill with zeros */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * - * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ - -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI) -#define CONFIG_SYS_HID0_FINAL 0 -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR 0 - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BCR 0 - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CONFIG_SYS_SCCR (0x00000028 | SCCR_DFBRG01) - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 16 bit FLASH - * 1 60x GPCM 8 bit NAND - * 2 60x SDRAM 32 bit SDRAM - * 3 60x GPCM 8 bit UART - * - */ - -#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ - -/* Minimum mask to separate preliminary - * address ranges for CS[0:2] - */ -#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (32<<20) /* less than 32 MB */ - -#define CONFIG_SYS_MPTPR 0x6600 - -/*----------------------------------------------------------------------------- - * Address for Mode Register Set (MRS) command - *----------------------------------------------------------------------------- - */ -#define CONFIG_SYS_MRS_OFFS 0x00000110 - - -/* Bank 0 - FLASH - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_SCY_6_CLK ) - -#if defined(CONFIG_CMD_NAND) -/* Bank 1 - NAND Flash -*/ -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_NAND0_BASE -#define CONFIG_SYS_NAND_SIZE 0x8000 - -#define CONFIG_SYS_OR_TIMING_NAND 0x000036 - -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V ) -#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | CONFIG_SYS_OR_TIMING_NAND ) -#endif - -/* Bank 2 - 60x bus SDRAM - */ -#define CONFIG_SYS_PSRT 0x20 -#define CONFIG_SYS_LSRT 0x20 - -#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2 - - -/* SDRAM initialization values -*/ -#define CONFIG_SYS_OR2 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A9 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A15_A17 |\ - PSDMR_SDA10_PBI0_A10 |\ - PSDMR_RFRC_5_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_BL |\ - PSDMR_LDOTOPRE_2C |\ - PSDMR_WRC_3C |\ - PSDMR_CL_3) - -/* Bank 3 - UART -*/ - -#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V ) -#define CONFIG_SYS_OR3_PRELIM (((-CONFIG_SYS_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX ) - -#endif /* __CONFIG_H */ diff --git a/include/configs/MHPC.h b/include/configs/MHPC.h deleted file mode 100644 index d45be0f..0000000 --- a/include/configs/MHPC.h +++ /dev/null @@ -1,369 +0,0 @@ -/* - * (C) Copyright 2001 - * Frank Gottschling, ELTEC Elektronik AG, fgottschling@eltec.de - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Configuation settings for the miniHiPerCam. - * - * ----------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_MHPC 1 /* on a miniHiPerCam */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* do special hardware init. */ -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_SYS_TEXT_BASE 0xfe000000 - -#define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED -#undef CONFIG_8xx_CONS_SMC1 -#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_ETHADDR 00:00:5b:ee:de:ad - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#undef CONFIG_UCODE_PATCH - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C04 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -#define LCD_VIDEO_ADDR (SDRAM_MAX_SIZE-SDRAM_RES_SIZE) -#define LCD_VIDEO_SIZE SDRAM_RES_SIZE /* 2MB */ -#define LCD_VIDEO_COLS 640 -#define LCD_VIDEO_ROWS 480 -#define LCD_VIDEO_FG 255 -#define LCD_VIDEO_BG 0 - -#undef CONFIG_VIDEO /* test only ! s.a devices.c and 8xx */ -#define CONFIG_CFB_CONSOLE /* framebuffer console with std input */ -#define CONFIG_VIDEO_LOGO - -#define VIDEO_KBD_INIT_FCT 0 /* no KBD dev on MHPC - use serial */ -#define VIDEO_TSTC_FCT serial_stub_tstc -#define VIDEO_GETC_FCT serial_stub_getc - -#define CONFIG_BR0_WORKAROUND 1 - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_REGINFO - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x300000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Physical memory map - */ -#define CONFIG_SYS_IMMR 0xFFF00000 /* Internal Memory Mapped Register*/ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xfe000000 - -#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */ -#undef CONFIG_SYS_MONITOR_BASE /* to run U-Boot from RAM */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor0=mhpc-0" -#define MTDPARTS_DEFAULT "mtdparts=mhpc-0:-(jffs2)" -*/ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map- for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN /* Offset of Environment */ -#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_SEME) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 12-18 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - leave PLL multiplication factor unchanged ! - */ -#define MPC8XX_SPEED 50000000L -#define MPC8XX_XIN 5000000L /* ref clk */ -#define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN) -#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ - -#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) /* SCCR_EBDF11 */ -#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_DFLCD001) - - -/*----------------------------------------------------------------------- - * MAMR settings for SDRAM - 16-14 - * => 0xC080200F - *----------------------------------------------------------------------- - * periodic timer for refresh - */ -#define CONFIG_SYS_MAMR_PTA 0xC0 -#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_G0CLA_A11 | MAMR_TLFA_MSK) - -/* - * BR0 and OR0 (FLASH) used to re-map FLASH - */ - -/* allow for max 8 MB of Flash */ -#define FLASH_BASE 0xFE000000 /* FLASH bank #0*/ -#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0*/ -#define CONFIG_SYS_REMAP_OR_AM 0xFF800000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ - -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK) /* (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)*/ - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V ) - -/* - * BR1 and OR1 (SDRAM) - */ -#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */ -#define SDRAM_RES_SIZE 0x00200000 /* 2 MB for framebuffer */ - -/* SDRAM timing: drive GPL5 high on first cycle */ -#define CONFIG_SYS_OR_TIMING_SDRAM (OR_G5LS) - -#define CONFIG_SYS_OR1_PRELIM ((~(SDRAM_MAX_SIZE)+1)| CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* - * BR2/OR2 - DIMM - */ -#define CONFIG_SYS_OR2 (OR_ACS_DIV4) -#define CONFIG_SYS_BR2 (BR_MS_UPMA) - -/* - * BR3/OR3 - DIMM - */ -#define CONFIG_SYS_OR3 (OR_ACS_DIV4) -#define CONFIG_SYS_BR3 (BR_MS_UPMA) - -/* - * BR4/OR4 - */ -#define CONFIG_SYS_OR4 0 -#define CONFIG_SYS_BR4 0 - -/* - * BR5/OR5 - */ -#define CONFIG_SYS_OR5 0 -#define CONFIG_SYS_BR5 0 - -/* - * BR6/OR6 - */ -#define CONFIG_SYS_OR6 0 -#define CONFIG_SYS_BR6 0 - -/* - * BR7/OR7 - */ -#define CONFIG_SYS_OR7 0 -#define CONFIG_SYS_BR7 0 - - -/*----------------------------------------------------------------------- - * Debug Entry Mode - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h deleted file mode 100644 index 7fd12d3..0000000 --- a/include/configs/TQM8260.h +++ /dev/null @@ -1,620 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Imported from global configuration: - * CONFIG_MPC8255 - * CONFIG_MPC8265 - * CONFIG_200MHz - * CONFIG_266MHz - * CONFIG_300MHz - * CONFIG_L2_CACHE - * CONFIG_BUSMODE_60x - */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - - -#if 0 -#define CONFIG_TQM8260 100 /* ...on a TQM8260 module Rev.100 */ -#else -#define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */ -#endif - -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=tqm8260/uImage\0" \ - "kernel_addr=400C0000\0" \ - "ramdisk_addr=40240000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 400000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F - -/* - * Software (bit-bang) I2C driver configuration - */ - -/* TQM8260 Rev.100 has the clock and data pins swapped (!!!) on EEPROM */ -#if (CONFIG_TQM8260 <= 100) - -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00020000) -#define I2C_TRISTATE (iop->pdir &= ~0x00020000) -#define I2C_READ ((iop->pdat & 0x00020000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#else - -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CONFIG_I2C_X - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#ifdef CONFIG_82xx_CONS_SMC1 -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ -#endif -#ifdef CONFIG_82xx_CONS_SMC2 -#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ -#endif - -#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ -#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ -#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - * - * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the - * X.29 connector, and FCC2 is hardwired to the X.1 connector) - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ - -#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) - -/* - * - RX clk is CLK11 - * - TX clk is CLK12 - */ -# define CONFIG_SYS_CMXSCR_VALUE1 (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) - -#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ - - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265) -# define CONFIG_8260_CLKIN 66666666 /* in Hz */ -#else /* !CONFIG_MPC8255 && !CONFIG_MPC8265 */ -# ifndef CONFIG_300MHz -# define CONFIG_8260_CLKIN 66666666 /* in Hz */ -# else -# define CONFIG_8260_CLKIN 83333000 /* in Hz */ -# endif -#endif /* CONFIG_MPC8255 */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8260/config.mk - * The main FLASH is whichever is connected to *CS0. - */ -#define CONFIG_SYS_FLASH0_BASE 0x40000000 -#define CONFIG_SYS_FLASH1_BASE 0x60000000 -#define CONFIG_SYS_FLASH0_SIZE 32 -#define CONFIG_SYS_FLASH1_SIZE 32 - -/* Flash bank size (for preliminary settings) - */ -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO 1 -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) -#define CONFIG_ENV_SIZE 0x08000 -#define CONFIG_ENV_SECT_SIZE 0x40000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CONFIG_SYS_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. - */ -#define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) - -#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265) -# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) -#else /* ! MPC8255 && !MPC8265 */ -# if defined(CONFIG_266MHz) -# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) -# elif defined(CONFIG_300MHz) -# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0110) -# else -# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__) -# endif -#endif /* CONFIG_MPC8255 */ - -/* no slaves so just fill with zeros */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - * - * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM - * is mapped at SDRAM_BASE2_PRELIM. - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc()*/ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#ifdef CONFIG_BUSMODE_60x -#define CONFIG_SYS_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\ - BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode */ -#else -#define BCR_APD01 0x10000000 -#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#if 0 -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) -#else -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10) -#endif - - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CONFIG_SYS_SCCR 0 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 64 bit FLASH - * 1 60x SDRAM 64 bit SDRAM - * 2 Local SDRAM 32 bit SDRAM - * - */ - - /* Initialize SDRAM on local bus - */ -#define CONFIG_SYS_INIT_LOCAL_SDRAM - -#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ - -/* Minimum mask to separate preliminary - * address ranges for CS[0:2] - */ -#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ -#define CONFIG_SYS_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */ - -#define CONFIG_SYS_MPTPR 0x4000 - -/*----------------------------------------------------------------------------- - * Address for Mode Register Set (MRS) command - *----------------------------------------------------------------------------- - * In fact, the address is rather configuration data presented to the SDRAM on - * its address lines. Because the address lines may be mux'ed externally either - * for 8 column or 9 column devices, some bits appear twice in the 8260's - * address: - * - * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length | - * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 | - * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 | - * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 | - * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | - *----------------------------------------------------------------------------- - */ -#define CONFIG_SYS_MRS_OFFS 0x00000110 - - -/* Bank 0 - FLASH - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) - - /* SDRAM on TQM8260 can have either 8 or 9 columns. - * The number affects configuration values. - */ - -/* Bank 1 - 60x bus SDRAM - */ -#define CONFIG_SYS_PSRT 0x20 -#define CONFIG_SYS_LSRT 0x20 -#ifndef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_8COL - - - /* SDRAM initialization values for 8-column chips - */ -#define CONFIG_SYS_OR1_8COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A7 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\ - PSDMR_SDAM_A15_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A8 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_CL_2) - - /* SDRAM initialization values for 9-column chips - */ -#define CONFIG_SYS_OR1_9COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A5 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\ - PSDMR_SDAM_A16_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A7 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_CL_2) - -/* Bank 2 - Local bus SDRAM - */ -#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_SDRAM_L |\ - BRx_V) - -#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL - -#define SDRAM_BASE2_PRELIM 0x80000000 - - /* SDRAM initialization values for 8-column chips - */ -#define CONFIG_SYS_OR2_8COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A8 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_LSDMR_8COL (PSDMR_PBI |\ - PSDMR_SDAM_A15_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI1_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_BL |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_CL_2) - - /* SDRAM initialization values for 9-column chips - */ -#define CONFIG_SYS_OR2_9COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A6 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_LSDMR_9COL (PSDMR_PBI |\ - PSDMR_SDAM_A16_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI1_A8 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_BL |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_CL_2) - -#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */ - -#endif /* CONFIG_SYS_RAMBOOT */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h deleted file mode 100644 index 9c7e163..0000000 --- a/include/configs/TQM8272.h +++ /dev/null @@ -1,735 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8272_FAMILY 1 -#define CONFIG_TQM8272 1 - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_GET_CPU_STR_F 1 /* Get the CPU ID STR */ -#define CONFIG_BOARD_GET_CPU_CLK_F 1 /* Get the CLKIN from board fct */ - -#define STK82xx_150 1 /* on a STK82xx.150 */ - -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */ - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_EARLY_INIT_R 1 - -#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) -#define CONFIG_BAUDRATE 230400 -#else -#define CONFIG_BAUDRATE 115200 -#endif - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consdev=ttyCPM0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "hostname=tqm8272\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addcons=setenv bootargs ${bootargs} " \ - "console=$(consdev),$(baudrate)\0" \ - "flash_nfs=run nfsargs addip addcons;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addcons;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 300000 ${bootfile};" \ - "run nfsargs addip addcons;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "bootfile=/tftpboot/tqm8272/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40100000\0" \ - "load=tftp 300000 /tftpboot/tqm8272/u-boot.bin\0" \ - "update=protect off 40000000 4003ffff;era 40000000 4003ffff;" \ - "cp.b 300000 40000000 40000;" \ - "setenv filesize;saveenv\0" \ - "cphwib=cp.b 4003fc00 33fc00 400\0" \ - "upd=run load cphwib update\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_I2C 1 - -#if CONFIG_I2C -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 400000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F -/* - * Software (bit-bang) I2C driver configuration - */ -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CONFIG_I2C_X - -/* EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ - -/* I2C RTC */ -#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* I2C SYSMON (LM75) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 -#define CONFIG_SYS_DTT_HYSTERESIS 3 - -#else -#undef CONFIG_SYS_I2C -#undef CONFIG_HARD_I2C -#undef CONFIG_SYS_I2C_SOFT -#endif - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#define CONFIG_CONS_ON_SMC /* define if console on SMC */ -#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#ifdef CONFIG_82xx_CONS_SMC1 -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ -#endif -#ifdef CONFIG_82xx_CONS_SMC2 -#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ -#endif - -#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ -#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ -#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - * - * (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the - * X.29 connector, and FCC2 is hardwired to the X.1 connector) - */ -#define CONFIG_SYS_FCC_ETHERNET - -#if defined(CONFIG_SYS_FCC_ETHERNET) -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ -#else -#define CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ -#endif - -#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) - -/* - * - RX clk is CLK11 - * - TX clk is CLK12 - */ -# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) - -#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ -/* - * GPIO pins used for bit-banged MII communications - */ -#define MDIO_PORT 2 /* Port C */ -#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -#define MDC_DECLARE MDIO_DECLARE - -#if STK82xx_150 -#define CONFIG_SYS_MDIO_PIN 0x00008000 /* PC16 */ -#define CONFIG_SYS_MDC_PIN 0x00004000 /* PC17 */ -#endif - -#if STK82xx_100 -#define CONFIG_SYS_MDIO_PIN 0x00000002 /* PC30 */ -#define CONFIG_SYS_MDC_PIN 0x00000001 /* PC31 */ -#endif - -#if 1 -#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN) -#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN) -#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \ - else iop->pdat &= ~CONFIG_SYS_MDIO_PIN - -#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \ - else iop->pdat &= ~CONFIG_SYS_MDC_PIN -#else -#define MDIO_ACTIVE ({unsigned long tmp; tmp = iop->pdir; tmp |= CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;}) -#define MDIO_TRISTATE ({unsigned long tmp; tmp = iop->pdir; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;}) -#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0) - -#define MDIO(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}\ - else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;} - -#define MDC(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}\ - else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDC_PIN; iop->pdat = tmp;} -#endif - -#define MIIDELAY udelay(1) - - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#define CONFIG_8260_CLKIN 66666666 /* in Hz */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII -#define CONFIG_CMD_NAND -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_SNTP - -#if CONFIG_I2C - #define CONFIG_CMD_I2C - #define CONFIG_CMD_DATE - #define CONFIG_CMD_DTT - #define CONFIG_CMD_EEPROM -#endif - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#if 0 -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x300000 /* default load address */ - -#define CONFIG_SYS_RESET_ADDRESS 0x40000104 /* "bad" address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * CAN stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_CAN_BASE 0x51000000 -#define CONFIG_SYS_CAN_SIZE 1 -#define CONFIG_SYS_CAN_BR ((CONFIG_SYS_CAN_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_UPMC |\ - BRx_V) - -#define CONFIG_SYS_CAN_OR (MEG_TO_AM(CONFIG_SYS_CAN_SIZE) |\ - ORxU_BI) - - -/* What should the base address of the main FLASH be and how big is - * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8272/config.mk - * The main FLASH is whichever is connected to *CS0. - */ -#define CONFIG_SYS_FLASH0_BASE 0x40000000 -#define CONFIG_SYS_FLASH0_SIZE 32 /* 32 MB */ - -/* Flash bank size (for preliminary settings) - */ -#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/ -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */ -#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#define CONFIG_SYS_UPDATE_FLASH_SIZE - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND 0x20000 - -/* Where is the Hardwareinformation Block (from Monitor Sources) */ -#define MON_RES_LENGTH (0x0003FC00) -#define HWIB_INFO_START_ADDR (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH) -#define HWIB_INFO_LEN 512 -#define CIB_INFO_START_ADDR (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN) -#define CIB_INFO_LEN 512 - -#define CONFIG_SYS_HWINFO_OFFSET 0x3fc00 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000060 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *----------------------------------------------------------------------- - */ -#if defined(CONFIG_CMD_NAND) - -#define CONFIG_SYS_NAND_CS_DIST 0x80 -#define CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS 0x20 -#define CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS 0x40 - -#define CONFIG_SYS_NAND_BR ((CONFIG_SYS_NAND0_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_UPMB |\ - BRx_V) - -#define CONFIG_SYS_NAND_OR (MEG_TO_AM(CONFIG_SYS_NAND_SIZE) |\ - ORxU_BI |\ - ORxU_EHTR_8IDLE) - -#define CONFIG_SYS_NAND_SIZE 1 -#define CONFIG_SYS_NAND0_BASE 0x50000000 -#define CONFIG_SYS_NAND1_BASE (CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST) -#define CONFIG_SYS_NAND2_BASE (CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST) -#define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST) - -#define CONFIG_SYS_MAX_NAND_DEVICE 4 /* Max number of NAND devices */ - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \ - CONFIG_SYS_NAND1_BASE, \ - CONFIG_SYS_NAND2_BASE, \ - CONFIG_SYS_NAND3_BASE, \ - } - -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr))) -#define WRITE_NAND_UPM(d, adr, off) do \ -{ \ - volatile unsigned char *addr = (unsigned char *) (adr + off); \ - WRITE_NAND(d, addr); \ -} while(0) - -#endif /* CONFIG_CMD_NAND */ - -#define CONFIG_PCI -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_PCI_PNP -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_PCI_SCAN_SHOW -#endif - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CONFIG_SYS_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. - */ -#if 0 -#define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) - -# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) -#else -#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111) -#endif - -/* no slaves so just fill with zeros */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE) -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR RMR_CSRE - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BCR_60x (BCR_EBM|BCR_NPQM0|BCR_NPQM2) /* 60x mode */ -#define BCR_APD01 0x10000000 -#define CONFIG_SYS_BCR_SINGLE (BCR_APD01|BCR_ETM) /* 8260 mode */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) -#define CONFIG_SYS_SIUMCR_LOW (SIUMCR_DPPC00) -#define CONFIG_SYS_SIUMCR_HIGH (SIUMCR_DPPC00 | SIUMCR_ABE) -#else -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00) -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CONFIG_SYS_SCCR SCCR_DFBRG01 - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 32 bit FLASH - * 1 60x SDRAM 64 bit SDRAM - * 2 60x UPMB 8 bit NAND - * 3 60x UPMC 8 bit CAN - * - */ - -/* Initialize SDRAM - */ -#undef CONFIG_SYS_INIT_LOCAL_SDRAM /* No SDRAM on Local Bus */ - -#define SDRAM_MAX_SIZE 0x20000000 /* max. 512 MB */ - -/* Minimum mask to separate preliminary - * address ranges for CS[0:2] - */ -#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ - -#define CONFIG_SYS_MPTPR 0x4000 - -/*----------------------------------------------------------------------------- - * Address for Mode Register Set (MRS) command - *----------------------------------------------------------------------------- - * In fact, the address is rather configuration data presented to the SDRAM on - * its address lines. Because the address lines may be mux'ed externally either - * for 8 column or 9 column devices, some bits appear twice in the 8260's - * address: - * - * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length | - * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 | - * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 | - * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 | - * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | - *----------------------------------------------------------------------------- - */ -#define CONFIG_SYS_MRS_OFFS 0x00000110 - -/* Bank 0 - FLASH - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV4 |\ - ORxG_SCY_8_CLK |\ - ORxG_TRLX) - -/* SDRAM on TQM8272 can have either 8 or 9 columns. - * The number affects configuration values. - */ - -/* Bank 1 - 60x bus SDRAM - */ -#define CONFIG_SYS_PSRT 0x20 /* Low Value */ -/* #define CONFIG_SYS_PSRT 0x10 Fast Value */ -#define CONFIG_SYS_LSRT 0x20 /* Local Bus */ -#ifndef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_8COL - -/* SDRAM initialization values for 8-column chips - */ -#define CONFIG_SYS_OR1_8COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A7 |\ - ORxS_NUMR_12) - -#define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\ - PSDMR_SDAM_A15_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A8 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_BUFCMD |\ - PSDMR_CL_2) - - -/* SDRAM initialization values for 9-column chips - */ -#define CONFIG_SYS_OR1_9COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A5 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\ - PSDMR_SDAM_A16_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A7 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_BUFCMD |\ - PSDMR_CL_2) - -#define CONFIG_SYS_OR1_10COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A4 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR_10COL (PSDMR_PBI |\ - PSDMR_SDAM_A17_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A4 |\ - PSDMR_RFRC_6_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_BUFCMD |\ - PSDMR_CL_2) - -#define PSDMR_RFRC_66MHZ_SINGLE 0x00028000 /* PSDMR[RFRC] at 66 MHz single mode */ -#define PSDMR_RFRC_100MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 100 MHz single mode */ -#define PSDMR_RFRC_133MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 133 MHz single mode */ -#define PSDMR_RFRC_66MHZ_60X 0x00030000 /* PSDMR[RFRC] at 66 MHz 60x mode */ -#define PSDMR_RFRC_100MHZ_60X 0x00028000 /* PSDMR[RFRC] at 100 MHz 60x mode */ -#define PSDMR_RFRC_DEFAULT PSDMR_RFRC_133MHZ_SINGLE /* PSDMR[RFRC] default value */ - -#define PSDMR_PRETOACT_66MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 66 MHz single mode */ -#define PSDMR_PRETOACT_100MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 100 MHz single mode */ -#define PSDMR_PRETOACT_133MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 133 MHz single mode */ -#define PSDMR_PRETOACT_66MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 66 MHz 60x mode */ -#define PSDMR_PRETOACT_100MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 100 MHz 60x mode */ -#define PSDMR_PRETOACT_DEFAULT PSDMR_PRETOACT_133MHZ_SINGLE /* PSDMR[PRETOACT] default value */ - -#define PSDMR_WRC_66MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 66 MHz single mode */ -#define PSDMR_WRC_100MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 100 MHz single mode */ -#define PSDMR_WRC_133MHZ_SINGLE 0x00000010 /* PSDMR[WRC] at 133 MHz single mode */ -#define PSDMR_WRC_66MHZ_60X 0x00000010 /* PSDMR[WRC] at 66 MHz 60x mode */ -#define PSDMR_WRC_100MHZ_60X 0x00000010 /* PSDMR[WRC] at 100 MHz 60x mode */ -#define PSDMR_WRC_DEFAULT PSDMR_WRC_133MHZ_SINGLE /* PSDMR[WRC] default value */ - -#define PSDMR_BUFCMD_66MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 66 MHz single mode */ -#define PSDMR_BUFCMD_100MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 100 MHz single mode */ -#define PSDMR_BUFCMD_133MHZ_SINGLE 0x00000004 /* PSDMR[BUFCMD] at 133 MHz single mode */ -#define PSDMR_BUFCMD_66MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 66 MHz 60x mode */ -#define PSDMR_BUFCMD_100MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 100 MHz 60x mode */ -#define PSDMR_BUFCMD_DEFAULT PSDMR_BUFCMD_133MHZ_SINGLE /* PSDMR[BUFCMD] default value */ - -#endif /* CONFIG_SYS_RAMBOOT */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h index f57820d..54b7028 100644 --- a/include/configs/ac14xx.h +++ b/include/configs/ac14xx.h @@ -13,6 +13,9 @@ #define __CONFIG_H #define CONFIG_AC14XX 1 +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD + /* * Memory map for the ifm AC14xx board: * diff --git a/include/configs/aria.h b/include/configs/aria.h index c36cf33..2f9677c 100644 --- a/include/configs/aria.h +++ b/include/configs/aria.h @@ -13,6 +13,9 @@ #define __CONFIG_H #define CONFIG_ARIA 1 +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD + /* * Memory map for the ARIA board: * diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h index 2a8cb39..76ec168 100644 --- a/include/configs/digsy_mtc.h +++ b/include/configs/digsy_mtc.h @@ -22,6 +22,8 @@ #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */ +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD /* * Valid values for CONFIG_SYS_TEXT_BASE are: diff --git a/include/configs/hymod.h b/include/configs/hymod.h deleted file mode 100644 index c973365..0000000 --- a/include/configs/hymod.h +++ /dev/null @@ -1,728 +0,0 @@ -/* - * (C) Copyright 2000 - * Murray Jensen <Murray.Jensen@cmst.csiro.au> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Config header file for Hymod board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_HYMOD 1 /* ...on a Hymod board */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ - -#define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */ - -/* - * select serial console configuration - * - * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - * - * if CONFIG_CONS_NONE is defined, then the serial console routines must - * defined elsewhere (for example, on the cogent platform, there are serial - * ports on the motherboard which are used for the serial console - see - * cogent/cma101/serial.[ch]). - */ -#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else*/ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ -#define CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ -#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ -#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/ - -/* - * select ethernet configuration - * - * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then - * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 - * for FCC) - * - * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. - */ -#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 1 /* which channel for ether */ -#define CONFIG_ETHER_LOOPBACK_TEST /* add ether external loopback test */ - -#ifdef CONFIG_ETHER_ON_FCC - -#if (CONFIG_ETHER_INDEX == 1) - -/* - * - Rx-CLK is CLK10 - * - Tx-CLK is CLK11 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -# define MDIO_PORT 0 /* Port A */ -# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -# define MDC_DECLARE MDIO_DECLARE - -# define MDIO_DATA_PINMASK 0x00040000 /* Pin 13 */ -# define MDIO_CLCK_PINMASK 0x00080000 /* Pin 12 */ - -#elif (CONFIG_ETHER_INDEX == 2) - -/* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -# define MDIO_PORT 0 /* Port A */ -# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -# define MDC_DECLARE MDIO_DECLARE - -# define MDIO_DATA_PINMASK 0x00000040 /* Pin 25 */ -# define MDIO_CLCK_PINMASK 0x00000080 /* Pin 24 */ - -#elif (CONFIG_ETHER_INDEX == 3) - -/* - * - Rx-CLK is CLK15 - * - Tx-CLK is CLK16 - * - RAM for BD/Buffers is on the 60x Bus (see 28-13) - * - Enable Full Duplex in FSMR - */ -# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) -# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) -# define CONFIG_SYS_CPMFCR_RAMTYPE 0 -# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) - -# define MDIO_PORT 0 /* Port A */ -# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -# define MDC_DECLARE MDIO_DECLARE - -# define MDIO_DATA_PINMASK 0x00000100 /* Pin 23 */ -# define MDIO_CLCK_PINMASK 0x00000200 /* Pin 22 */ - -#endif /* CONFIG_ETHER_INDEX */ - -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ - -#define MDIO_ACTIVE (iop->pdir |= MDIO_DATA_PINMASK) -#define MDIO_TRISTATE (iop->pdir &= ~MDIO_DATA_PINMASK) -#define MDIO_READ ((iop->pdat & MDIO_DATA_PINMASK) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= MDIO_DATA_PINMASK; \ - else iop->pdat &= ~MDIO_DATA_PINMASK - -#define MDC(bit) if(bit) iop->pdat |= MDIO_CLCK_PINMASK; \ - else iop->pdat &= ~MDIO_CLCK_PINMASK - -#define MIIDELAY udelay(1) - -#endif /* CONFIG_ETHER_ON_FCC */ - - -/* other options */ -#define CONFIG_HARD_I2C 1 /* To enable I2C hardware support */ -#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */ - -/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ -#ifdef DEBUG -#define CONFIG_8260_CLKIN 33333333 /* in Hz */ -#else -#define CONFIG_8260_CLKIN 66666666 /* in Hz */ -#endif - -#if defined(CONFIG_CONS_USE_EXTC) -#define CONFIG_BAUDRATE 115200 -#else -#define CONFIG_BAUDRATE 9600 -#endif - -/* default ip addresses - these will be overridden */ -#define CONFIG_IPADDR 192.168.1.1 /* hymod "boot" address */ -#define CONFIG_SERVERIP 192.168.1.254 /* hymod "server" address */ - -#define CONFIG_LAST_STAGE_INIT - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BSP -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_CDP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_DTT -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_KGDB -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_PORTIO -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP - -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_XIMG - -#ifdef DEBUG -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_BOOT_RETRY_TIME 30 /* retry autoboot after 30 secs */ -#define CONFIG_BOOT_RETRY_MIN 1 /* can go down to 1 second timeout */ -/* Be selective on what keys can delay or stop the autoboot process - * To stop use: " " - */ -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \ - "press <SPACE> to stop\n", bootdelay -#define CONFIG_AUTOBOOT_STOP_STR " " -#undef CONFIG_AUTOBOOT_DELAY_STR -#define DEBUG_BOOTKEYS 0 -#endif - -#if defined(CONFIG_CMD_KGDB) -#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ -#define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ -#define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */ -#define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/ -# if defined(CONFIG_KGDB_USE_EXTC) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ -# else -#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */ -# endif -#endif - -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ - -#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ - -/* - * Hymod specific configurable options - */ -#undef CONFIG_SYS_HYMOD_DBLEDS /* walk mezz board LEDs */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x03c00000 /* 4 ... 60 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0x7e - -/* these are for the ST M24C02 2kbit serial i2c eeprom */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 - -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16 byte write page size */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* hymod has two eeproms */ - -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* philips PCF8563 RTC address */ - -/* - * standard dtt sensor configuration - bottom bit will determine local or - * remote sensor of the ADM1021, the rest determines index into - * CONFIG_SYS_DTT_ADM1021 array below. - * - * On HYMOD board, the remote sensor should be connected to the MPC8260 - * temperature diode thingy, but an errata said this didn't work and - * should be disabled - so it isn't connected. - */ -#if 0 -#define CONFIG_DTT_SENSORS { 0, 1 } -#else -#define CONFIG_DTT_SENSORS { 0 } -#endif - -/* - * ADM1021 temp sensor configuration (see dtt/adm1021.c for details). - * there will be one entry in this array for each two (dummy) sensors in - * CONFIG_DTT_SENSORS. - * - * For HYMOD board: - * - only one ADM1021 - * - i2c addr 0x2a (both ADD0 and ADD1 are N/C) - * - conversion rate 0x02 = 0.25 conversions/second - * - ALERT ouput disabled - * - local temp sensor enabled, min set to 0 deg, max set to 85 deg - * - remote temp sensor disabled (see comment for CONFIG_DTT_SENSORS above) - */ -#define CONFIG_SYS_DTT_ADM1021 { { 0x2a, 0x02, 0, 1, 0, 85, 0, } } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Words - * - * if you change bits in the HRCW, you must also change the CONFIG_SYS_* - * defines for the various registers affected by the HRCW e.g. changing - * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. - */ -#ifdef DEBUG -#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\ - HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\ - HRCW_MODCK_H0010) -#else -#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\ - HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\ - HRCW_MODCK_H0101) -#endif -/* no slaves so just duplicate the master hrcw */ -#define CONFIG_SYS_HRCW_SLAVE1 CONFIG_SYS_HRCW_MASTER -#define CONFIG_SYS_HRCW_SLAVE2 CONFIG_SYS_HRCW_MASTER -#define CONFIG_SYS_HRCW_SLAVE3 CONFIG_SYS_HRCW_MASTER -#define CONFIG_SYS_HRCW_SLAVE4 CONFIG_SYS_HRCW_MASTER -#define CONFIG_SYS_HRCW_SLAVE5 CONFIG_SYS_HRCW_MASTER -#define CONFIG_SYS_HRCW_SLAVE6 CONFIG_SYS_HRCW_MASTER -#define CONFIG_SYS_HRCW_SLAVE7 CONFIG_SYS_HRCW_MASTER - -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_FPGA_BASE 0x80000000 -/* - * unfortunately, CONFIG_SYS_MONITOR_LEN must include the - * (very large i.e. 256kB) environment flash sector - */ -#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor*/ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ -#endif - -/*----------------------------------------------------------------------- - * HIDx - Hardware Implementation-dependent Registers 2-11 - *----------------------------------------------------------------------- - * HID0 also contains cache control - initially enable both caches and - * invalidate contents, then the final state leaves only the instruction - * cache enabled. Note that Power-On and Hard reset invalidate the caches, - * but Soft reset does not. - * - * HID1 has only read-only information - nothing to set. - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) -#ifdef DEBUG -#define CONFIG_SYS_HID0_FINAL 0 -#else -#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) -#endif -#define CONFIG_SYS_HID2 0 - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#ifdef DEBUG -#define CONFIG_SYS_RMR 0 -#else -#define CONFIG_SYS_RMR RMR_CSRE -#endif - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration 4-25 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BCR (BCR_ETM) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 4-31 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_L2CPC01|\ - SIUMCR_APPC10|SIUMCR_MMR11) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 4-35 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Watchdog & Bus Monitor Timer max, 60x & Local Bus Monitor enable - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control 9-8 - *----------------------------------------------------------------------- - * Ensure DFBRG is Divide by 16 - */ -#define CONFIG_SYS_SCCR (SCCR_DFBRG01) - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 32 bit FLASH - * 1 60x GPCM 32 bit FLASH (same as 0 - unused for now) - * 2 60x SDRAM 64 bit SDRAM - * 3 Local UPMC 8 bit Main Xilinx configuration - * 4 Local GPCM 32 bit Main Xilinx register mode - * 5 Local UPMB 32 bit Main Xilinx port mode - * 6 Local UPMC 8 bit Mezz Xilinx configuration - */ - -/* - * Bank 0 - FLASH - * - * Quotes from the HYMOD IO Board Reference manual: - * - * "The flash memory is two Intel StrataFlash chips, each configured for - * 16 bit operation and connected to give a 32 bit wide port." - * - * "The chip select logic is configured to respond to both *CS0 and *CS1. - * Therefore the FLASH memory will be mapped to both bank 0 and bank 1. - * It is suggested that bank 0 be read-only and bank 1 be read/write. The - * FLASH will then appear as ROM during boot." - * - * Initially, we are only going to use bank 0 in read/write mode. - */ - -/* 32 bit, read-write, GPCM on 60x bus */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE&BRx_BA_MSK)|\ - BRx_PS_32|BRx_MS_GPCM_P|BRx_V) -/* up to 32 Mb */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK) - -/* - * Bank 2 - SDRAM - * - * Quotes from the HYMOD IO Board Reference manual: - * - * "The main memory is implemented using TC59SM716FTL-10 SDRAM and has a - * fixed size of 64 Mbytes. The Toshiba TC59SM716FTL-10 is a CMOS synchronous - * dynamic random access memory organised as 4 banks by 4096 rows by 512 - * columns by 16 bits. Four chips provide a 64-bit port on the 60x bus." - * - * "The locations in SDRAM are accessed using multiplexed address pins to - * specify row and column. The pins also act to specify commands. The state - * of the inputs *RAS, *CAS and *WE defines the required action. The a10/AP - * pin may function as a row address or as the AUTO PRECHARGE control line, - * depending on the cycle type. The 60x bus SDRAM machine allows the MPC8260 - * address lines to be configured to the required multiplexing scheme." - */ - -#define CONFIG_SYS_SDRAM_SIZE 64 - -/* 64 bit, read-write, SDRAM on 60x bus */ -#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE&BRx_BA_MSK)|\ - BRx_PS_64|BRx_MS_SDRAM_P|BRx_V) -/* 64 Mb, 4 int banks per dev, row start addr bit = A6, 12 row addr lines */ -#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM_SIZE)|\ - ORxS_BPD_4|ORxS_ROWST_PBI1_A6|ORxS_NUMR_12) - -/* - * The 60x Bus SDRAM Mode Register (PDSMR) is set as follows: - * - * Page Based Interleaving, Refresh Enable, Address Multiplexing where A5 - * is output on A16 pin (A6 on A17, and so on), use address pins A14-A16 - * as bank select, A7 is output on SDA10 during an ACTIVATE command, - * earliest timing for ACTIVATE command after REFRESH command is 6 clocks, - * earliest timing for ACTIVATE or REFRESH command after PRECHARGE command - * is 2 clocks, earliest timing for READ/WRITE command after ACTIVATE - * command is 2 clocks, earliest timing for PRECHARGE after last data - * was read is 1 clock, earliest timing for PRECHARGE after last data - * was written is 1 clock, CAS Latency is 2. - */ - -#define CONFIG_SYS_PSDMR (PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\ - PSDMR_BSMA_A14_A16|PSDMR_SDA10_PBI1_A7|\ - PSDMR_RFRC_6_CLK|PSDMR_PRETOACT_2W|\ - PSDMR_ACTTORW_2W|PSDMR_LDOTOPRE_1C|\ - PSDMR_WRC_1C|PSDMR_CL_2) - -/* - * The 60x bus-assigned SDRAM Refresh Timer (PSRT) (10-31) and the Refresh - * Timers Prescale (PTP) value in the Memory Refresh Timer Prescaler Register - * (MPTPR) (10-32) must also be set up (it used to be called the Periodic Timer - * Prescaler, hence the P instead of the R). The refresh timer period is given - * by (note that there was a change in the 8260 UM Errata): - * - * TimerPeriod = (PSRT + 1) / Fmptc - * - * where Fmptc is the BusClock divided by PTP. i.e. - * - * TimerPeriod = (PSRT + 1) / (BusClock / PTP) - * - * or - * - * TImerPeriod = (PTP * (PSRT + 1)) / BusClock - * - * The requirement for the Toshiba TC59SM716FTL-10 is that there must be - * 4K refresh cycles every 64 ms. i.e. one refresh cycle every 64000/4096 - * = 15.625 usecs. - * - * So PTP * (PSRT + 1) <= 15.625 * BusClock. At 66.666MHz, PSRT=31 and PTP=32 - * appear to be reasonable. - */ - -#ifdef DEBUG -#define CONFIG_SYS_PSRT 39 -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV8 -#else -#define CONFIG_SYS_PSRT 31 -#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 -#endif - -/* - * Banks 3,4,5 and 6 - FPGA access - * - * Quotes from the HYMOD IO Board Reference manual: - * - * "The IO Board is fitted with a Xilinx XCV300E main FPGA. Provision is made - * for configuring an optional FPGA on the mezzanine interface. - * - * Access to the FPGAs may be divided into several catagories: - * - * 1. Configuration - * 2. Register mode access - * 3. Port mode access - * - * The main FPGA is supported for modes 1, 2 and 3. The mezzanine FPGA can be - * configured only (mode 1). Consequently there are four access types. - * - * To improve interface performance and simplify software design, the four - * possible access types are separately mapped to different memory banks. - * - * All are accessed using the local bus." - * - * Device Mode Memory Bank Machine Port Size Access - * - * Main Configuration 3 UPMC 8bit R/W - * Main Register 4 GPCM 32bit R/W - * Main Port 5 UPMB 32bit R/W - * Mezzanine Configuration 6 UPMC 8bit W/O - * - * "Note that mezzanine mode 1 access is write-only." - */ - -/* all the bank sizes must be a power of two, greater or equal to 32768 */ -#define FPGA_MAIN_CFG_BASE (CONFIG_SYS_FPGA_BASE) -#define FPGA_MAIN_CFG_SIZE 32768 -#define FPGA_MAIN_REG_BASE (FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE) -#define FPGA_MAIN_REG_SIZE 32768 -#define FPGA_MAIN_PORT_BASE (FPGA_MAIN_REG_BASE + FPGA_MAIN_REG_SIZE) -#define FPGA_MAIN_PORT_SIZE 32768 -#define FPGA_MEZZ_CFG_BASE (FPGA_MAIN_PORT_BASE + FPGA_MAIN_PORT_SIZE) -#define FPGA_MEZZ_CFG_SIZE 32768 - -/* 8 bit, read-write, UPMC */ -#define CONFIG_SYS_BR3_PRELIM (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V) -/* up to 32Kbyte, burst inhibit */ -#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI) - -/* 32 bit, read-write, GPCM */ -#define CONFIG_SYS_BR4_PRELIM (FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V) -/* up to 32Kbyte */ -#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(FPGA_MAIN_REG_SIZE)) - -/* 32 bit, read-write, UPMB */ -#define CONFIG_SYS_BR5_PRELIM (FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V) -/* up to 32Kbyte */ -#define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI) - -/* 8 bit, write-only, UPMC */ -#define CONFIG_SYS_BR6_PRELIM (FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V) -/* up to 32Kbyte, burst inhibit */ -#define CONFIG_SYS_OR6_PRELIM (P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI) - -/*----------------------------------------------------------------------- - * MBMR - Machine B Mode 10-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_MBMR (MxMR_BSEL|MxMR_OP_NORM) /* XXX - needs more */ - -/*----------------------------------------------------------------------- - * MCMR - Machine C Mode 10-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_MCMR (MxMR_BSEL|MxMR_DSx_2_CYCL) /* XXX - needs more */ - -/* - * FPGA I/O Port/Bit information - */ - -#define FPGA_MAIN_PROG_PORT IOPIN_PORTA -#define FPGA_MAIN_PROG_PIN 4 /* PA4 */ -#define FPGA_MAIN_INIT_PORT IOPIN_PORTA -#define FPGA_MAIN_INIT_PIN 5 /* PA5 */ -#define FPGA_MAIN_DONE_PORT IOPIN_PORTA -#define FPGA_MAIN_DONE_PIN 6 /* PA6 */ - -#define FPGA_MEZZ_PROG_PORT IOPIN_PORTA -#define FPGA_MEZZ_PROG_PIN 0 /* PA0 */ -#define FPGA_MEZZ_INIT_PORT IOPIN_PORTA -#define FPGA_MEZZ_INIT_PIN 1 /* PA1 */ -#define FPGA_MEZZ_DONE_PORT IOPIN_PORTA -#define FPGA_MEZZ_DONE_PIN 2 /* PA2 */ -#define FPGA_MEZZ_ENABLE_PORT IOPIN_PORTA -#define FPGA_MEZZ_ENABLE_PIN 3 /* PA3 */ - -/* - * FPGA Interrupt configuration - */ -#define FPGA_MAIN_IRQ SIU_INT_IRQ2 - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "" -#define MTDPARTS_DEFAULT "" -*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h index 6c19817..0b9cbae 100644 --- a/include/configs/mecp5123.h +++ b/include/configs/mecp5123.h @@ -15,6 +15,9 @@ #define __CONFIG_H #define CONFIG_MECP5123 1 +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD + /* * Memory map for the MECP5123 board: * diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index 7de245b..41ae0a5 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -12,6 +12,9 @@ #define __CONFIG_H #define CONFIG_MPC5121ADS 1 +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD + /* * Memory map for the MPC5121ADS board: * diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h deleted file mode 100644 index a210e29..0000000 --- a/include/configs/p3mx.h +++ /dev/null @@ -1,434 +0,0 @@ -/* - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Based on original work by - * Roel Loeffen, (C) Copyright 2006 Prodrive B.V. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************ - * p3mx.h - configuration for Prodrive P3M750 & P3M7448 boards - * - * The defines: - * CONFIG_P3M750 or - * CONFIG_P3M7448 - * are written into include/config.h by the "make xxx_config" command - ***********************************************************************/ -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_P3Mx /* used for both board versions */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#if defined (CONFIG_P3M750) -#define CONFIG_750FX /* 750GL/GX/FX */ -#define CONFIG_HIGH_BATS /* High BATs supported */ -#define CONFIG_SYS_BOARD_NAME "P3M750" -#define CONFIG_SYS_BUS_CLK 100000000 -#define CONFIG_SYS_TCLK 100000000 -#elif defined (CONFIG_P3M7448) -#define CONFIG_74xx -#define CONFIG_SYS_BOARD_NAME "P3M7448" -#define CONFIG_SYS_BUS_CLK 133333333 -#define CONFIG_SYS_TCLK 133333333 -#endif -#define CONFIG_SYS_GT_DUAL_CPU /* also for JTAG even with one cpu */ - -/* which initialization functions to call for this board */ -#define CONFIG_SYS_BOARD_ASM_INIT 1 -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#ifdef CONFIG_P3M750 -#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */ -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#if defined (CONFIG_P3M750) -#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of flash banks */ -#define CONFIG_SYS_BOOT_SIZE _8M /* boot flash */ -#elif defined (CONFIG_P3M7448) -#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of flash banks */ -#define CONFIG_SYS_BOOT_SIZE _16M /* boot flash */ -#endif -#define CONFIG_SYS_BOOT_SPACE CONFIG_SYS_FLASH_BASE /* BOOT_CS0 flash 0 */ -#define CONFIG_SYS_MONITOR_BASE 0xfff00000 -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ -#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 - -#define CONFIG_SYS_DFL_GT_REGS 0xf1000000 /* boot time GT_REGS */ -#define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers are mapped here */ -#define CONFIG_SYS_INT_SRAM_BASE 0x42000000 /* GT offers 256k internal SRAM */ - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in internal SRAM) - *----------------------------------------------------------------------*/ - /* - * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS - * To an unused memory region. The stack will remain in cache until RAM - * is initialized -*/ -#undef CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0x42000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#define CONFIG_MPSC /* MV64460 Serial */ -#define CONFIG_MPSC_PORT 0 -#define CONFIG_BAUDRATE 115200 /* console baudrate */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/*----------------------------------------------------------------------- - * Ethernet - *----------------------------------------------------------------------*/ -/* Change the default ethernet port, use this define (options: 0, 1, 2) */ -#define CONFIG_SYS_ETH_PORT ETH_0 -#define MV_ETH_DEVS 2 -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */ -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#if defined (CONFIG_P3M750) -#define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (1 device) */ -#elif defined (CONFIG_P3M7448) -#define CONFIG_ENV_SECT_SIZE 0x40000 /* two sectors (2 devices parallel */ -#endif -#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#define CONFIG_MV64460_ECC - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed default */ - -/* I2C RTC */ -#define CONFIG_RTC_M41T11 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------*/ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#undef CONFIG_PCI /* include pci support */ -#ifdef CONFIG_PCI -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */ -#endif /* CONFIG_PCI */ - -/* PCI MEMORY MAP section */ -#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI0_MEM_SIZE _128M -#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 -#define CONFIG_SYS_PCI1_MEM_SIZE _128M - -#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) -#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) - -/* PCI I/O MAP section */ -#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 -#define CONFIG_SYS_PCI0_IO_SIZE _16M -#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 -#define CONFIG_SYS_PCI1_IO_SIZE _16M - -#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) -#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000 -#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) -#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000 - -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE) -#define CONFIG_SYS_PCI_IDSEL 0x30 - -#undef CONFIG_BOOTARGS -#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "u-boot=p3mx/u-boot/u-boot.bin\0" \ - "load=tftp 100000 ${u-boot}\0" \ - "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \ - "cp.b 100000 fff00000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ - "serverip=11.0.0.152\0" - -#if defined (CONFIG_P3M750) -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - "hostname=p3m750\0" \ - "bootfile=/tftpboot/p3mx/vxWorks.st\0" \ - "kernel_addr=fc000000\0" \ - "ramdisk_addr=fc180000\0" \ - "vxfile=p3m750/vxWorks\0" \ - "vxuser=ddg\0" \ - "vxpass=ddg\0" \ - "vxtarget=target\0" \ - "vxflags=0x8\0" \ - "vxargs=setenv bootargs mgi(0,0)host:${vxfile} h=${serverip} " \ - "e=${ipaddr} u=${vxuser} pw=${vxpass} tn=${vxtarget} " \ - "f=${vxflags}\0" -#elif defined (CONFIG_P3M7448) -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - "hostname=p3m7448\0" -#endif - -#if defined (CONFIG_P3M750) -#define CONFIG_BOOTCOMMAND "tftp;run vxargs;bootvx" -#elif defined (CONFIG_P3M7448) -#define CONFIG_BOOTCOMMAND " " -#endif - -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_PCI -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_SDRAM - - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_HUSH_PARSER - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x08000000 /* default load address */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -/*----------------------------------------------------------------------- - * Marvell MV64460 config settings - *----------------------------------------------------------------------*/ -/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected device width */ -#if defined (CONFIG_P3M750) -#define CONFIG_SYS_BOOT_PAR 0x8FDFF87F /* 16 bit flash, disable burst*/ -#elif defined (CONFIG_P3M7448) -#define CONFIG_SYS_BOOT_PAR 0x8FEFFFFF /* 32 bit flash, burst enabled */ -#endif - -/* - * MPP[0] Serial Port 0 TxD TxD OUT Connected to P14 (buffered) - * MPP[1] Serial Port 0 RxD RxD IN Connected to P14 (buffered) - * MPP[2] NC - * MPP[3] Serial Port 1 TxD TxD OUT Connected to P14 (buffered) - * MPP[4] PCI Monarch# GPIO IN Connected to P12 - * MPP[5] Serial Port 1 RxD RxD IN Connected to P14 (buffered) - * MPP[6] PMC Carrier Interrupt 0 Int IN Connected to P14 - * MPP[7] PMC Carrier Interrupt 1 Int IN Connected to P14 - * MPP[8] Reserved Do not use - * MPP[9] Reserved Do not use - * MPP[10] Reserved Do not use - * MPP[11] Reserved Do not use - * MPP[12] Phy 0 Interrupt Int IN - * MPP[13] Phy 1 Interrupt Int IN - * MPP[14] NC - * MPP[15] NC - * MPP[16] PCI Interrupt C Int IN Connected to P11 - * MPP[17] PCI Interrupt D Int IN Connected to P11 - * MPP[18] Watchdog NMI# GPIO IN Connected to MPP[24] - * MPP[19] Watchdog Expired# WDE OUT Connected to rst logic - * MPP[20] Watchdog Status WD_STS IN Read back of rst by watchdog - * MPP[21] NC - * MPP[22] GP LED Green GPIO OUT - * MPP[23] GP LED Red GPIO OUT - * MPP[24] Watchdog NMI# Int OUT - * MPP[25] NC - * MPP[26] NC - * MPP[27] PCI Interrupt A Int IN Connected to P11 - * MPP[28] NC - * MPP[29] PCI Interrupt B Int IN Connected to P11 - * MPP[30] Module reset GPIO OUT Board reset - * MPP[31] PCI EReady GPIO IN Connected to P12 - */ -#define CONFIG_SYS_MPP_CONTROL_0 0x00303022 -#define CONFIG_SYS_MPP_CONTROL_1 0x00000000 -#define CONFIG_SYS_MPP_CONTROL_2 0x00004000 -#define CONFIG_SYS_MPP_CONTROL_3 0x00000004 -#define CONFIG_SYS_GPP_LEVEL_CONTROL 0x280730D0 - -/*---------------------------------------------------------------------- - * Initial BAT mappings - */ - -/* NOTES: - * 1) GUARDED and WRITE_THRU not allowed in IBATS - * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT - */ -/* SDRAM */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT) -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -/* init ram */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* PCI0, PCI1 in one BAT */ -#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* GT regs, bootrom, all the devices, PCI I/O */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -/* set rest out of range for Linux !!!!!!!!!!! */ - -/* IBAT5 and DBAT5 */ -#define CONFIG_SYS_IBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT5U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -/* IBAT6 and DBAT6 */ -#define CONFIG_SYS_IBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT6U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - -/* IBAT7 and DBAT7 */ -#define CONFIG_SYS_IBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT7U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_VXWORKS_MAC_PTR 0x42010000 /* use some memory in SRAM that's not used!!! */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * L2CR setup -- make sure this is right for your board! - * look in include/mpc74xx.h for the defines used here - */ -#define CONFIG_SYS_L2 - -#if defined (CONFIG_750CX) || defined (CONFIG_750FX) -#define L2_INIT 0 -#else -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#endif - -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -#ifndef __ASSEMBLY__ -#include <../board/Marvell/include/core.h> -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/pdm360ng.h b/include/configs/pdm360ng.h index 553eb8f..17d7bca 100644 --- a/include/configs/pdm360ng.h +++ b/include/configs/pdm360ng.h @@ -13,6 +13,8 @@ #define __CONFIG_H #define CONFIG_PDM360NG 1 +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD /* * Memory map for the PDM360NG board: diff --git a/include/pcmcia.h b/include/pcmcia.h index 4b667f4..00065b2 100644 --- a/include/pcmcia.h +++ b/include/pcmcia.h @@ -29,8 +29,6 @@ # define CONFIG_PCMCIA_SLOT_A #elif defined(CONFIG_LWMON) /* The LWMON use SLOT_B */ # define CONFIG_PCMCIA_SLOT_B -#elif defined(CONFIG_ICU862) /* The ICU862 use SLOT_B */ -# define CONFIG_PCMCIA_SLOT_B #elif defined(CONFIG_R360MPI) /* The R360MPI use SLOT_B */ # define CONFIG_PCMCIA_SLOT_B #elif defined(CONFIG_ATC) /* The ATC use SLOT_A */ diff --git a/include/status_led.h b/include/status_led.h index c1d2242..c5de894 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -114,25 +114,6 @@ void status_led_set (int led, int state); # define STATUS_LED_GREEN 1 # define STATUS_LED_BOOT 2 /* IDE LED used for boot status */ -/***** ICU862 ********************************************************/ -#elif defined(CONFIG_ICU862) - -# define STATUS_LED_PAR im_ioport.iop_papar -# define STATUS_LED_DIR im_ioport.iop_padir -# define STATUS_LED_ODR im_ioport.iop_paodr -# define STATUS_LED_DAT im_ioport.iop_padat - -# define STATUS_LED_BIT 0x4000 /* LED 0 is on PA.1 */ -# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -# define STATUS_LED_STATE STATUS_LED_BLINKING -# define STATUS_LED_BIT1 0x1000 /* LED 1 is on PA.3 */ -# define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ) -# define STATUS_LED_STATE1 STATUS_LED_OFF - -# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - -# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - /***** Someone else defines these *************************************/ #elif defined(STATUS_LED_PAR) diff --git a/tools/bddb/README b/tools/bddb/README deleted file mode 100644 index 9bee59a..0000000 --- a/tools/bddb/README +++ /dev/null @@ -1,116 +0,0 @@ -Hymod Board Database - -(C) Copyright 2001 -Murray Jensen <Murray.Jensen@csiro.au> -CSIRO Manufacturing Science and Technology, Preston Lab - -25-Jun-01 - -This stuff is a set of PHP/MySQL scripts to implement a custom board -database. It will need *extensive* hacking to modify it to keep the -information about your custom boards that you want, however it is a good -starting point. - -How it is used: - - 1. a board has gone through all the hardware testing etc and is - ready to have the flash programmed for the first time - first you - go to a web page and fill in information about the board in a form - to register it in a database - - 2. the web stuff allocates a (unique) serial number and (optionally) - a (locally administered) ethernet address and stores the information - in a database using the serial number as the key (can do whole - batches of boards in one go and/or use a previously registered board - as defaults for the new board(s)) - - 3. it then creates a file in the tftp area of a server somewhere - containing the board information in a simple text format (one - per serial number) - - 4. all hymod boards have an i2c eeprom, and when U-Boot sees that - the eeprom is unitialised, it prompts for a serial number and - ethernet address (if not set), then transfers the file created - in step 3 from the server and initialises the eeprom from its - contents - -What this means is you can't boot the board until you have allocated a serial -number, but you don't have to type it all twice - you do it once on the web -and the board then finds the info it needs to initialise its eeprom. The -other side of the coin is the reading of the eeprom and how it gets passed -to Linux (or another O/S). - -To see how this is all done for the hymod boards look at the code in the -"board/hymod" directory and in the file "include/asm/hymod.h". Hymod boards -can have a mezzanine card which also have an eeprom that needs allocating, -the same process is used for these as well - just a different i2c address. - -Other forms provide the following functions: - - - browsing the board database - - editing board information (one at a time) - - maintaining/browsing a (simple) per board event log - -You will need: MySQL (I use version 3.23.7-alpha), PHP4 (with MySQL -support enabled) and a web server (I use Apache 1.3.x). - -I originally started by using phpMyBuilder (http://kyber.dk/phpMyBuilder) -but it soon got far more complicated than that could handle (but I left -the copyright messages in there anyway). Most of the code resides in the -common defs.php file, which shouldn't need much alteration - all the work -will be in shaping the front-end php files to your liking. - -Here's a quick summary of what needs doing to use it for your boards: - -1. get phpMyAdmin (http://phpwizard.net/projects/phpMyAdmin/) - it's an - invaluable tool for this sort of stuff (this step is optional of course) - -2. edit "bddb.css" to your taste, if you could be bothered - I have no - idea what is in there or what it does - I copied it from somewhere else - ("user.css" from the phpMyEdit (http://phpmyedit.sourcerforge.net) package, - I think) - I figure one day I'll see what sort of things I can change - in there. - -3. create a mysql database - call it whatever you like - -4. edit "create_tables.sql" and modify the "boards" table schema to - reflect the information you want to keep about your boards. It may or - may not be easier to do this and the next step in phpMyAdmin. Check out - the MySQL documentation at http://www.mysql.com/doc/ in particular the - column types at http://www.mysql.com/doc/C/o/Column_types.html - Note - there is only support for a few data types: - - int - presented as an html text input - char/text - presented as an html text input - date - presented as an html text input - enum - presented as an html radio input - - I also have what I call "enum_multi" which is a set of enums with the - same name, but suffixed with a number e.g. fred0, fred1, fred2. These - are presented as a number of html select's with a single label "fred" - this is useful for board characteristics that have multiple items of - the same type e.g. multiple banks of sdram. - -5. use the "create_tables.sql" file to create the "boards" table in the - database e.g. mysql dbname < create_tables.sql - -6. create a user and password for the web server to log into the MySQL - database with; give this user select, insert and update privileges - to the database created in 3 (and delete, if you want the "delete" - functions in the edit forms to work- I have this turned off). phpMyAdmin - helps in this step. - -7. edit "config.php" and set the variables: $mysql_user, $mysql_pw, $mysql_db, - $bddb_cfgdir and $bddb_label - keep the contents of this file secret - it - contains the web servers username and password (the three $mysql_* vars - are set from the previous step) - -8. edit "defs.php" and a. adjust the various enum value arrays and b. edit - the function "pg_foot()" to remove my email address :-) - -9. do major hacking on the following files: browse.php, doedit.php, donew.php, - edit.php and new.php to reflect your database schema - fortunately the - hacking is fairly straight-forward, but it is boring and time-consuming. - -These notes were written rather hastily - if you find any obvious problems -please let me know. diff --git a/tools/bddb/badsubmit.php b/tools/bddb/badsubmit.php deleted file mode 100644 index 5092a31..0000000 --- a/tools/bddb/badsubmit.php +++ /dev/null @@ -1,23 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - require("defs.php"); - pg_head("$bddb_label - Unknown Submit Type"); -?> -<center> - <font size="+4"> - <b> - The <?php echo "$bddb_label"; ?> form was submitted with an - unknown SUBMIT type <?php echo "(value was '$submit')" ?>. - <br></br> - Perhaps you typed the URL in directly? Click here to go to the - home page of the <a href="index.php"><?php echo "$bddb_label"; ?></a>. - </b> - </font> -</center> -<?php - pg_foot(); -?> diff --git a/tools/bddb/bddb.css b/tools/bddb/bddb.css deleted file mode 100644 index dee2b2e..0000000 --- a/tools/bddb/bddb.css +++ /dev/null @@ -1,207 +0,0 @@ -BODY { - background: #e0ffff; - color: #000000; - font-family: Arial, Verdana, Helvetica; -} -H1 { - font-family: "Copperplate Gothic Bold"; - background: transparent; - color: #993300; - text-align: center; -} -H2, H3, H4, H5 { - background: transparent; - color: #993300; - margin-top: 4%; - text-align: center; -} -Body.Plain Div.Abstract, Body.Plain P.Abstract { - background: #cccc99; - color: #333300; - border: white; - padding: 3%; - font-family: Times, Verdana; -} -TH.Nav { - background: #0000cc; - color: #ff9900; -} -TH.Menu { - background: #3366cc; - color: #ff9900; -} -A:hover { - color: #ff6600; -} -A.Menu:hover { - color: #ff6600; -} -A.HoMe:hover { - color: #ff6600; -} -A.Menu { - background: transparent; - color: #ffcc33; - font-family: Verdana, Helvetica, Arial; - font-size: smaller; - text-decoration: none; -} -A.Menu:visited { - background: transparent; - color: #ffcc99; -} -A.HoMe { - background: transparent; - color: #ffcc33; - font-family: Verdana, Helvetica, Arial; - text-decoration:none; -} -A.HoMe:visited { - background: transparent; - color: #ffcc99; -} -TH.Xmp { - background: #eeeeee; - color: #330066; - font-family: courier; - font-weight: normal; -} -TH.LuT { - background: #cccccc; - color: #000000; -} -TD.LuT { - background: #ffffcc; - color: #000000; - font-size: 85%; -} -TH.Info, TD.Info { - background: #ffffcc; - color: #660000; - font-family: "Comic Sans MS", Cursive, Verdana; - font-size: smaller; -} -Div.Info, P.Info { - background: #ffff99; - color: #990033; - text-align: left; - padding: 2%; - font-family: "Comic Sans MS", Cursive, Verdana; - font-size: 85%; - } -Div.Info A { - background: transparent; - color: #ff6600; -} -.HL { - background: #ffff99; - color: #000000; -} -TD.HL { - background: #ccffff; - color: #000000; -} -Div.Margins { - width: 512px; - text-align: center; -} -TD.Plain { - background: #ffffcc; - color: #000033; -} -.Type { - background: #cccccc; - color: #660000; -} -.Name { - background: #eeeeee; - color: #660000; - vertical-align: top; - text-align: right; -} -.Value { - background: #ffffee; - color: #000066; -} -.Drop { - background: #333366; - color: #ffcc33; - font-family: "Copperplate Gothic Light", Helvetica, Verdana, Arial; -} -A.Button:hover { - color: #ff6600; -} -A.Button { - text-decoration:none; - color: #003366; - background: #ffcc66; -} -.Button { - font-size: 9pt; - text-align: center; - text-decoration:none; - color: #003366; - background: #ffcc66; - margin-bottom: 2pt; - border-top: 2px solid #ffff99; - border-left: 2px solid #ffff99; - border-right: 2px solid #cc9933; - border-bottom: 2px solid #cc9933; - font-family: Verdana, Arial, "Comic Sans MS"; -} -.Banner { - width: 468; - font-size: 12pt; - text-align: center; - text-decoration:none; - color: #003366; - background: #ffcc66; - border-top: 4px solid #ffff99; - border-left: 4px solid #ffff99; - border-right: 4px solid #cc9933; - border-bottom: 4px solid #cc9933; - font-family: Verdana, Arial, "Comic Sans MS"; -} -TD.Nova, Body.Nova { - background: #000000; - font-family: "Times New Roman"; - font-weight: light; - color: #ffcc00; -} -Body.Nova A.Button { - background: gold; - color: #003366; -} -Body.Nova A.Banner { - background: transparent; - color: #003366; -} -Body.Nova A { - background: transparent; - text-decoration:none; - color: #ffd766; -} -Body.Nova H1, Body.Nova H2, Body.Nova H3, Body.Nova H4 { - background: transparent; - color: white; - margin-top: 4%; - text-align: center; - filter: Blur(Add=1, Direction=0, Strength=8); -} -Body.Nova Div.Abstract { - background: #000000; - color: #ffffff; - font-family: Times, Verdana; -} -Body.Nova A.Abstract { - background: transparent; - color: #ffeedd; -} -Body.Nova TH.LuT { - background: black; - color: #ffff99; -} -Body.Nova TD.LuT { - background: navy; - color: #ffff99; -} diff --git a/tools/bddb/brlog.php b/tools/bddb/brlog.php deleted file mode 100644 index fccfbd0..0000000 --- a/tools/bddb/brlog.php +++ /dev/null @@ -1,109 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - // list page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - Browse Board Log"); - - $serno=intval($serno); - if ($serno == 0) - die("serial number not specified or invalid!"); - - function print_cell($str) { - if ($str == '') - $str = ' '; - echo "\t<td>$str</td>\n"; - } -?> -<table align=center border=1 cellpadding=10> -<tr> -<th>serno / edit</th> -<th>ethaddr</th> -<th>date</th> -<th>batch</th> -<th>type</th> -<th>rev</th> -<th>location</th> -</tr> -<?php - $r=mysql_query("select * from boards where serno=$serno"); - - while($row=mysql_fetch_array($r)){ - foreach ($columns as $key) { - if (!key_in_array($key, $row)) - $row[$key] = ''; - } - - echo "<tr>\n"; - print_cell("<a href=\"edit.php?serno=$row[serno]\">$row[serno]</a>"); - print_cell($row['ethaddr']); - print_cell($row['date']); - print_cell($row['batch']); - print_cell($row['type']); - print_cell($row['rev']); - print_cell($row['location']); - echo "</tr>\n"; - } - - mysql_free_result($r); -?> -</table> -<hr></hr> -<p></p> -<?php - $limit=abs(isset($_REQUEST['limit'])?$_REQUEST['limit']:20); - $offset=abs(isset($_REQUEST['offset'])?$_REQUEST['offset']:0); - $lr=mysql_query("select count(*) as n from log where serno=$serno"); - $lrow=mysql_fetch_array($lr); - if($lrow['n']>$limit){ - $preoffset=max(0,$offset-$limit); - $postoffset=$offset+$limit; - echo "<table width=\"100%\">\n<tr align=center>\n"; - printf("<td><%sa href=\"%s?submit=Log&serno=$serno&offset=%d\"><img border=0 alt=\"<\" src=\"/icons/left.gif\"></a></td>\n", $offset>0?"":"no", $PHP_SELF, $preoffset); - printf("<td><%sa href=\"%s?submit=Log&serno=$serno&offset=%d\"><img border=0 alt=\">\" src=\"/icons/right.gif\"></a></td>\n", $postoffset<$lrow['n']?"":"no", $PHP_SELF, $postoffset); - echo "</tr>\n</table>\n"; - } - mysql_free_result($lr); -?> -<table width="100%" border=1 cellpadding=10> -<tr valign=top> -<th>logno / edit</th> -<th>date</th> -<th>who</th> -<th width="70%">details</th> -</tr> -<?php - $r=mysql_query("select * from log where serno=$serno order by logno limit $offset,$limit"); - - while($row=mysql_fetch_array($r)){ - echo "<tr>\n"; - print_cell("<a href=\"edlog.php?serno=$row[serno]&logno=$row[logno]\">$row[logno]</a>"); - print_cell($row['date']); - print_cell($row['who']); - print_cell("<pre>" . urldecode($row['details']) . "</pre>"); - echo "</tr>\n"; - } - - mysql_free_result($r); -?> -</table> -<hr></hr> -<p></p> -<table width="100%"> -<tr> - <td align=center> - <a href="newlog.php?serno=<?php echo "$serno"; ?>">Add to Log</a> - </td> - <td align=center> - <a href="index.php">Back to Start</a> - </td> -</tr> -</table> -<?php - pg_foot(); -?> diff --git a/tools/bddb/browse.php b/tools/bddb/browse.php deleted file mode 100644 index 675dfab..0000000 --- a/tools/bddb/browse.php +++ /dev/null @@ -1,147 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - // list page (hymod_bddb / boards) - - require("defs.php"); - - $serno=isset($_REQUEST['serno'])?$_REQUEST['serno']:''; - - $verbose=isset($_REQUEST['verbose'])?intval($_REQUEST['verbose']):0; - - pg_head("$bddb_label - Browse database" . ($verbose?" (verbose)":"")); -?> -<p></p> -<?php - $limit=isset($_REQUEST['limit'])?abs(intval($_REQUEST['limit'])):20; - $offset=isset($_REQUEST['offset'])?abs(intval($_REQUEST['offset'])):0; - - if ($serno == '') { - - $lr=mysql_query("select count(*) as n from boards"); - $lrow=mysql_fetch_array($lr); - - if($lrow['n']>$limit){ - $preoffset=max(0,$offset-$limit); - $postoffset=$offset+$limit; - echo "<table width=\"100%\">\n<tr>\n"; - printf("<td align=left><%sa href=\"%s?submit=Browse&offset=%d&verbose=%d\"><img border=0 alt=\"<\" src=\"/icons/left.gif\"></a></td>\n", $offset>0?"":"no", $PHP_SELF, $preoffset, $verbose); - printf("<td align=right><%sa href=\"%s?submit=Browse&offset=%d&verbose=%d\"><img border=0 alt=\">\" src=\"/icons/right.gif\"></a></td>\n", $postoffset<$lrow['n']?"":"no", $PHP_SELF, $postoffset, $offset); - echo "</tr>\n</table>\n"; - } - - mysql_free_result($lr); - } -?> -<table align=center border=1 cellpadding=10> -<tr> -<th></th> -<th>serno / edit</th> -<th>ethaddr</th> -<th>date</th> -<th>batch</th> -<th>type</th> -<th>rev</th> -<th>location</th> -<?php - if ($verbose) { - echo "<th>comments</th>\n"; - echo "<th>sdram</th>\n"; - echo "<th>flash</th>\n"; - echo "<th>zbt</th>\n"; - echo "<th>xlxtyp</th>\n"; - echo "<th>xlxspd</th>\n"; - echo "<th>xlxtmp</th>\n"; - echo "<th>xlxgrd</th>\n"; - echo "<th>cputyp</th>\n"; - echo "<th>cpuspd</th>\n"; - echo "<th>cpmspd</th>\n"; - echo "<th>busspd</th>\n"; - echo "<th>hstype</th>\n"; - echo "<th>hschin</th>\n"; - echo "<th>hschout</th>\n"; - } -?> -</tr> -<?php - $query = "select * from boards"; - if ($serno != '') { - $pre = " where "; - foreach (preg_split("/[\s,]+/", $serno) as $s) { - if (preg_match('/^[0-9]+$/',$s)) - $query .= $pre . "serno=" . $s; - else if (preg_match('/^([0-9]+)-([0-9]+)$/',$s,$m)) { - $m1 = intval($m[1]); $m2 = intval($m[2]); - if ($m2 <= $m1) - die("bad serial number range ($s)"); - $query .= $pre . "(serno>=$m[1] and serno<=$m[2])"; - } - else - die("illegal serial number ($s)"); - $pre = " or "; - } - } - $query .= " order by serno"; - if ($serno == '') - $query .= " limit $offset,$limit"; - - $r = mysql_query($query); - - function print_cell($str) { - if ($str == '') - $str = ' '; - echo "\t<td>$str</td>\n"; - } - - while($row=mysql_fetch_array($r)){ - foreach ($columns as $key) { - if (!key_in_array($key, $row)) - $row[$key] = ''; - } - - echo "<tr>\n"; - print_cell("<a href=\"brlog.php?serno=$row[serno]\">Log</a>"); - print_cell("<a href=\"edit.php?serno=$row[serno]\">$row[serno]</a>"); - print_cell($row['ethaddr']); - print_cell($row['date']); - print_cell($row['batch']); - print_cell($row['type']); - print_cell($row['rev']); - print_cell($row['location']); - if ($verbose) { - print_cell("<pre>\n" . urldecode($row['comments']) . - "\n\t</pre>"); - print_cell(gather_enum_multi_print("sdram", 4, $row)); - print_cell(gather_enum_multi_print("flash", 4, $row)); - print_cell(gather_enum_multi_print("zbt", 16, $row)); - print_cell(gather_enum_multi_print("xlxtyp", 4, $row)); - print_cell(gather_enum_multi_print("xlxspd", 4, $row)); - print_cell(gather_enum_multi_print("xlxtmp", 4, $row)); - print_cell(gather_enum_multi_print("xlxgrd", 4, $row)); - print_cell($row['cputyp']); - print_cell($row['cpuspd']); - print_cell($row['cpmspd']); - print_cell($row['busspd']); - print_cell($row['hstype']); - print_cell($row['hschin']); - print_cell($row['hschout']); - } - echo "</tr>\n"; - } -?> -</table> -<p></p> -<table width="100%"> -<tr> - <td align=center><?php - printf("<a href=\"%s?submit=Browse&offset=%d&verbose=%d%s\">%s Listing</a>\n", $PHP_SELF, $offset, $verbose?0:1, $serno!=''?"&serno=$serno":'', $verbose?"Terse":"Verbose"); - ?></td> - <td align=center><a href="index.php">Back to Start</a></td> -</tr> -</table> -<?php - pg_foot(); -?> diff --git a/tools/bddb/config.php b/tools/bddb/config.php deleted file mode 100644 index 6725757..0000000 --- a/tools/bddb/config.php +++ /dev/null @@ -1,16 +0,0 @@ -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - // mysql database access info - $mysql_user="fred"; - $mysql_pw="apassword"; - $mysql_db="mydbname"; - - // where to put the eeprom config files - $bddb_cfgdir = '/tftpboot/bddb'; - - // what this database is called - $bddb_label = 'Hymod Board Database'; -?> diff --git a/tools/bddb/create_tables.sql b/tools/bddb/create_tables.sql deleted file mode 100644 index a2a5788..0000000 --- a/tools/bddb/create_tables.sql +++ /dev/null @@ -1,90 +0,0 @@ -# phpMyAdmin MySQL-Dump -# http://phpwizard.net/phpMyAdmin/ -# -# Host: localhost Database : hymod_bddb - -# (C) Copyright 2001 -# Murray Jensen <Murray.Jensen@csiro.au> -# CSIRO Manufacturing and Infrastructure Technology, Preston Lab - -# -------------------------------------------------------- -# -# Table structure for table 'boards' -# - -DROP TABLE IF EXISTS boards; -CREATE TABLE boards ( - serno int(10) unsigned zerofill NOT NULL auto_increment, - ethaddr char(17), - date date NOT NULL, - batch char(32), - type enum('IO','CLP','DSP','INPUT','ALT-INPUT','DISPLAY') NOT NULL, - rev tinyint(3) unsigned zerofill NOT NULL, - location char(64), - comments text, - sdram0 enum('32M','64M','128M','256M','512M','1G','2G','4G'), - sdram1 enum('32M','64M','128M','256M','512M','1G','2G','4G'), - sdram2 enum('32M','64M','128M','256M','512M','1G','2G','4G'), - sdram3 enum('32M','64M','128M','256M','512M','1G','2G','4G'), - flash0 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'), - flash1 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'), - flash2 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'), - flash3 enum('4M','8M','16M','32M','64M','128M','256M','512M','1G'), - zbt0 enum('512K','1M','2M','4M','8M','16M'), - zbt1 enum('512K','1M','2M','4M','8M','16M'), - zbt2 enum('512K','1M','2M','4M','8M','16M'), - zbt3 enum('512K','1M','2M','4M','8M','16M'), - zbt4 enum('512K','1M','2M','4M','8M','16M'), - zbt5 enum('512K','1M','2M','4M','8M','16M'), - zbt6 enum('512K','1M','2M','4M','8M','16M'), - zbt7 enum('512K','1M','2M','4M','8M','16M'), - zbt8 enum('512K','1M','2M','4M','8M','16M'), - zbt9 enum('512K','1M','2M','4M','8M','16M'), - zbta enum('512K','1M','2M','4M','8M','16M'), - zbtb enum('512K','1M','2M','4M','8M','16M'), - zbtc enum('512K','1M','2M','4M','8M','16M'), - zbtd enum('512K','1M','2M','4M','8M','16M'), - zbte enum('512K','1M','2M','4M','8M','16M'), - zbtf enum('512K','1M','2M','4M','8M','16M'), - xlxtyp0 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'), - xlxtyp1 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'), - xlxtyp2 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'), - xlxtyp3 enum('XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'), - xlxspd0 enum('6','7','8','4','5','9','10','11','12'), - xlxspd1 enum('6','7','8','4','5','9','10','11','12'), - xlxspd2 enum('6','7','8','4','5','9','10','11','12'), - xlxspd3 enum('6','7','8','4','5','9','10','11','12'), - xlxtmp0 enum('COM','IND'), - xlxtmp1 enum('COM','IND'), - xlxtmp2 enum('COM','IND'), - xlxtmp3 enum('COM','IND'), - xlxgrd0 enum('NORMAL','ENGSAMP'), - xlxgrd1 enum('NORMAL','ENGSAMP'), - xlxgrd2 enum('NORMAL','ENGSAMP'), - xlxgrd3 enum('NORMAL','ENGSAMP'), - cputyp enum('MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)','MPC8560'), - cpuspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ'), - cpmspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ'), - busspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ'), - hstype enum('AMCC-S2064A','Xilinx-Rockets'), - hschin enum('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16'), - hschout enum('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16'), - PRIMARY KEY (serno), - KEY serno (serno), - UNIQUE serno_2 (serno) -); - -# -# Table structure for table 'log' -# - -DROP TABLE IF EXISTS log; -CREATE TABLE log ( - logno int(10) unsigned zerofill NOT NULL auto_increment, - serno int(10) unsigned zerofill NOT NULL, - date date NOT NULL, - details text NOT NULL, - PRIMARY KEY (logno), - KEY logno (logno, serno, date), - UNIQUE logno_2 (logno) -); diff --git a/tools/bddb/defs.php b/tools/bddb/defs.php deleted file mode 100644 index 0b50602..0000000 --- a/tools/bddb/defs.php +++ /dev/null @@ -1,710 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - // contains mysql user id and password - keep secret - require("config.php"); - - if (isset($_REQUEST['logout'])) { - Header("status: 401 Unauthorized"); - Header("HTTP/1.0 401 Unauthorized"); - Header("WWW-authenticate: basic realm=\"$bddb_label\""); - - echo "<html><head><title>" . - "Access to '$bddb_label' Denied" . - "</title></head>\n"; - echo "<body bgcolor=#ffffff><br></br><br></br><center><h1>" . - "You must be an Authorised User " . - "to access the '$bddb_label'" . - "</h1>\n</center></body></html>\n"; - exit; - } - - // contents of the various enumerated types - if first item is - // empty ('') then the enum is allowed to be null (ie "not null" - // is not set on the column) - - // all column names in the database table - $columns = array( - 'serno','ethaddr','date','batch', - 'type','rev','location','comments', - 'sdram0','sdram1','sdram2','sdram3', - 'flash0','flash1','flash2','flash3', - 'zbt0','zbt1','zbt2','zbt3','zbt4','zbt5','zbt6','zbt7', - 'zbt8','zbt9','zbta','zbtb','zbtc','zbtd','zbte','zbtf', - 'xlxtyp0','xlxtyp1','xlxtyp2','xlxtyp3', - 'xlxspd0','xlxspd1','xlxspd2','xlxspd3', - 'xlxtmp0','xlxtmp1','xlxtmp2','xlxtmp3', - 'xlxgrd0','xlxgrd1','xlxgrd2','xlxgrd3', - 'cputyp','cpuspd','cpmspd','busspd', - 'hstype','hschin','hschout' - ); - - // board type - $type_vals = array('IO','CLP','DSP','INPUT','ALT-INPUT','DISPLAY'); - - // Xilinx fpga types - $xlxtyp_vals = array('','XCV300E','XCV400E','XCV600E','XC2V2000','XC2V3000','XC2V4000','XC2V6000','XC2VP2','XC2VP4','XC2VP7','XC2VP20','XC2VP30','XC2VP50','XC4VFX20','XC4VFX40','XC4VFX60','XC4VFX100','XC4VFX140'); - - // Xilinx fpga speeds - $xlxspd_vals = array('','6','7','8','4','5','9','10','11','12'); - - // Xilinx fpga temperatures (commercial or industrial) - $xlxtmp_vals = array('','COM','IND'); - - // Xilinx fpga grades (normal or engineering sample) - $xlxgrd_vals = array('','NORMAL','ENGSAMP'); - - // CPU types - $cputyp_vals = array('','MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)','MPC8560'); - - // CPU/BUS/CPM clock speeds - $clk_vals = array('','33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ','300MHZ','333MHZ','366MHZ','400MHZ','433MHZ','466MHZ','500MHZ','533MHZ','566MHZ','600MHZ','633MHZ','666MHZ','700MHZ','733MHZ','766MHZ','800MHZ','833MHZ','866MHZ','900MHZ','933MHZ','966MHZ','1000MHZ','1033MHZ','1066MHZ','1100MHZ','1133MHZ','1166MHZ','1200MHZ','1233MHZ','1266MHZ','1300MHZ','1333MHZ'); - - // sdram sizes (nbits array is for eeprom config file) - $sdram_vals = array('','32M','64M','128M','256M','512M','1G','2G','4G'); - $sdram_nbits = array(0,25,26,27,28,29,30,31,32); - - // flash sizes (nbits array is for eeprom config file) - $flash_vals = array('','4M','8M','16M','32M','64M','128M','256M','512M','1G'); - $flash_nbits = array(0,22,23,24,25,26,27,28,29,30); - - // zbt ram sizes (nbits array is for write into eeprom config file) - $zbt_vals = array('','512K','1M','2M','4M','8M','16M'); - $zbt_nbits = array(0,19,20,21,22,23,24); - - // high-speed serial attributes - $hstype_vals = array('','AMCC-S2064A','Xilinx-Rockets'); - $hschin_vals = array('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16'); - $hschout_vals = array('0','1','2','3','4','5','6','7','8','9','10','11','12','13','14','15','16'); - - // value filters - used when outputting html - function rev_filter($num) { - if ($num == 0) - return "001"; - else - return sprintf("%03d", $num); - } - - function text_filter($str) { - return urldecode($str); - } - - mt_srand(time() | getmypid()); - - // set up MySQL connection - mysql_connect("", $mysql_user, $mysql_pw) || die("cannot connect"); - mysql_select_db($mysql_db) || die("cannot select db"); - - // page header - function pg_head($title) - { - echo "<html>\n<head>\n"; - echo "<link rel=stylesheet href=\"bddb.css\" type=\"text/css\" title=\"style sheet\"></link>\n"; - echo "<title>$title</title>\n"; - echo "</head>\n"; - echo "<body>\n"; - echo "<center><h1>$title</h1></center>\n"; - echo "<hr></hr>\n"; - } - - // page footer - function pg_foot() - { - echo "<hr></hr>\n"; - echo "<table width=\"100%\"><tr><td align=left>\n<address>" . - "If you have any problems, email " . - "<a href=\"mailto:Murray.Jensen@csiro.au\">" . - "Murray Jensen" . - "</a></address>\n" . - "</td><td align=right>\n" . - "<a href=\"index.php?logout=true\">logout</a>\n" . - "</td></tr></table>\n"; - echo "<p><small><i>Made with " . - "<a href=\"http://kyber.dk/phpMyBuilder/\">" . - "Kyber phpMyBuilder</a></i></small></p>\n"; - echo "</body>\n"; - echo "</html>\n"; - } - - // some support functions - - if (!function_exists('array_search')) { - - function array_search($needle, $haystack, $strict = false) { - - if (is_array($haystack) && count($haystack)) { - - $ntype = gettype($needle); - - foreach ($haystack as $key => $value) { - - if ($value == $needle && (!$strict || - gettype($value) == $ntype)) - return $key; - } - } - - return false; - } - } - - if (!function_exists('in_array')) { - - function in_array($needle, $haystack, $strict = false) { - - if (is_array($haystack) && count($haystack)) { - - $ntype = gettype($needle); - - foreach ($haystack as $key => $value) { - - if ($value == $needle && (!$strict || - gettype($value) == $ntype)) - return true; - } - } - - return false; - } - } - - function key_in_array($key, $array) { - return in_array($key, array_keys($array), true); - } - - function enum_to_index($name, $vals) { - $index = array_search($GLOBALS[$name], $vals); - if ($vals[0] != '') - $index++; - return $index; - } - - // fetch a value from an array - return empty string is not present - function get_key_value($key, $array) { - if (key_in_array($key, $array)) - return $array[$key]; - else - return ''; - } - - function fprintf() { - $n = func_num_args(); - if ($n < 2) - return FALSE; - $a = func_get_args(); - $fp = array_shift($a); - $x = "\$s = sprintf"; - $sep = '('; - foreach ($a as $z) { - $x .= "$sep'$z'"; - $sep = ','; - } - $x .= ');'; - eval($x); - $l = strlen($s); - $r = fwrite($fp, $s, $l); - if ($r != $l) - return FALSE; - else - return TRUE; - } - - // functions to display (print) a database table and its columns - - function begin_table($ncols) { - global $table_ncols; - $table_ncols = $ncols; - echo "<table align=center width=\"100%\"" - . " border=1 cellpadding=4 cols=$table_ncols>\n"; - } - - function begin_field($name, $span = 0) { - global $table_ncols; - echo "<tr valign=top>\n"; - echo "\t<th align=center>$name</th>\n"; - if ($span <= 0) - $span = $table_ncols - 1; - if ($span > 1) - echo "\t<td colspan=$span>\n"; - else - echo "\t<td>\n"; - } - - function cont_field($span = 1) { - echo "\t</td>\n"; - if ($span > 1) - echo "\t<td colspan=$span>\n"; - else - echo "\t<td>\n"; - } - - function end_field() { - echo "\t</td>\n"; - echo "</tr>\n"; - } - - function end_table() { - echo "</table>\n"; - } - - function print_field($name, $array, $size = 0, $filt='') { - - begin_field($name); - - if (key_in_array($name, $array)) - $value = $array[$name]; - else - $value = ''; - - if ($filt != '') - $value = $filt($value); - - echo "\t\t<input name=$name value=\"$value\""; - if ($size > 0) - echo " size=$size maxlength=$size"; - echo "></input>\n"; - - end_field(); - } - - function print_field_multiline($name, $array, $cols, $rows, $filt='') { - - begin_field($name); - - if (key_in_array($name, $array)) - $value = $array[$name]; - else - $value = ''; - - if ($filt != '') - $value = $filt($value); - - echo "\t\t<textarea name=$name " . - "cols=$cols rows=$rows wrap=off>\n"; - echo "$value"; - echo "</textarea>\n"; - - end_field(); - } - - // print a mysql ENUM as an html RADIO INPUT - function print_enum($name, $array, $vals, $def = -1) { - - begin_field($name); - - if (key_in_array($name, $array)) - $chk = array_search($array[$name], $vals, FALSE); - else - $chk = $def; - - $nval = count($vals); - - for ($i = 0; $i < $nval; $i++) { - - $val = $vals[$i]; - if ($val == '') - $pval = "none"; - else - $pval = "$val"; - - printf("\t\t<input type=radio name=$name" - . " value=\"$val\"%s>$pval</input>\n", - $i == $chk ? " checked" : ""); - } - - end_field(); - } - - // print a mysql ENUM as an html SELECT INPUT - function print_enum_select($name, $array, $vals, $def = -1) { - - begin_field($name); - - echo "\t\t<select name=$name>\n"; - - if (key_in_array($name, $array)) - $chk = array_search($array[$name], $vals, FALSE); - else - $chk = $def; - - $nval = count($vals); - - for ($i = 0; $i < $nval; $i++) { - - $val = $vals[$i]; - if ($val == '') - $pval = "none"; - else - $pval = "$val"; - - printf("\t\t\t<option " . - "value=\"%s\"%s>%s</option>\n", - $val, $i == $chk ? " selected" : "", $pval); - } - - echo "\t\t</select>\n"; - - end_field(); - } - - // print a group of mysql ENUMs (e.g. name0,name1,...) as an html SELECT - function print_enum_multi($base, $array, $vals, $cnt, $defs, $grp = 0) { - - global $table_ncols; - - if ($grp <= 0) - $grp = $cnt; - $ncell = $cnt / $grp; - $span = ($table_ncols - 1) / $ncell; - - begin_field($base, $span); - - $nval = count($vals); - - for ($i = 0; $i < $cnt; $i++) { - - if ($i > 0 && ($i % $grp) == 0) - cont_field($span); - - $name = sprintf("%s%x", $base, $i); - - echo "\t\t<select name=$name>\n"; - - if (key_in_array($name, $array)) - $ai = array_search($array[$name], $vals, FALSE); - else { - if (key_in_array($i, $defs)) - $ai = $defs[$i]; - else - $ai = 0; - } - - for ($j = 0; $j < $nval; $j++) { - - $val = $vals[$j]; - if ($val == '') - $pval = " "; - else - $pval = "$val"; - - printf("\t\t\t<option " . - "value=\"%s\"%s>%s</option>\n", - $val, - $j == $ai ? " selected" : "", - $pval); - } - - echo "\t\t</select>\n"; - } - - end_field(); - } - - // functions to handle the form input - - // fetch all the parts of an "enum_multi" into a string suitable - // for a MySQL query - function gather_enum_multi_query($base, $cnt) { - - $retval = ''; - - for ($i = 0; $i < $cnt; $i++) { - - $name = sprintf("%s%x", $base, $i); - - if (isset($_REQUEST[$name])) { - $retval .= sprintf(", %s='%s'", - $name, $_REQUEST[$name]); - } - } - - return $retval; - } - - // fetch all the parts of an "enum_multi" into a string suitable - // for a display e.g. in an html table cell - function gather_enum_multi_print($base, $cnt, $array) { - - $retval = ''; - - for ($i = 0; $i < $cnt; $i++) { - - $name = sprintf("%s%x", $base, $i); - - if ($array[$name] != '') { - if ($retval != '') - $retval .= ','; - $retval .= $array[$name]; - } - } - - return $retval; - } - - // fetch all the parts of an "enum_multi" into a string suitable - // for writing to the eeprom data file - function gather_enum_multi_write($base, $cnt, $vals, $xfrm = array()) { - - $retval = ''; - - for ($i = 0; $i < $cnt; $i++) { - - $name = sprintf("%s%x", $base, $i); - - if ($GLOBALS[$name] != '') { - if ($retval != '') - $retval .= ','; - $index = enum_to_index($name, $vals); - if ($xfrm != array()) - $retval .= $xfrm[$index]; - else - $retval .= $index; - } - } - - return $retval; - } - - // count how many parts of an "enum_multi" are actually set - function count_enum_multi($base, $cnt) { - - $retval = 0; - - for ($i = 0; $i < $cnt; $i++) { - - $name = sprintf("%s%x", $base, $i); - - if (isset($_REQUEST[$name])) - $retval++; - } - - return $retval; - } - - // ethernet address functions - - // generate a (possibly not unique) random vendor ethernet address - // (setting bit 6 in the ethernet address - motorola wise i.e. bit 0 - // is the most significant bit - means it is not an assigned ethernet - // address - it is a "locally administered" address). Also, make sure - // it is NOT a multicast ethernet address (by setting bit 7 to 0). - // e.g. the first byte of all ethernet addresses generated here will - // have 2 in the bottom two bits (incidentally, these are the first - // two bits transmitted on the wire, since the octets in ethernet - // addresses are transmitted LSB first). - - function gen_eth_addr($serno) { - - $ethaddr_hgh = (mt_rand(0, 65535) & 0xfeff) | 0x0200; - $ethaddr_mid = mt_rand(0, 65535); - $ethaddr_low = mt_rand(0, 65535); - - return sprintf("%02lx:%02lx:%02lx:%02lx:%02lx:%02lx", - $ethaddr_hgh >> 8, $ethaddr_hgh & 0xff, - $ethaddr_mid >> 8, $ethaddr_mid & 0xff, - $ethaddr_low >> 8, $ethaddr_low & 0xff); - } - - // check that an ethernet address is valid - function eth_addr_is_valid($ethaddr) { - - $ethbytes = split(':', $ethaddr); - - if (count($ethbytes) != 6) - return FALSE; - - for ($i = 0; $i < 6; $i++) { - $ethbyte = $ethbytes[$i]; - if (!ereg('^[0-9a-f][0-9a-f]$', $ethbyte)) - return FALSE; - } - - return TRUE; - } - - // write a simple eeprom configuration file - function write_eeprom_cfg_file() { - - global $sernos, $nsernos, $bddb_cfgdir, $numerrs, $cfgerrs; - global $date, $batch, $type_vals, $rev; - global $sdram_vals, $sdram_nbits; - global $flash_vals, $flash_nbits; - global $zbt_vals, $zbt_nbits; - global $xlxtyp_vals, $xlxspd_vals, $xlxtmp_vals, $xlxgrd_vals; - global $cputyp, $cputyp_vals, $clk_vals; - global $hstype, $hstype_vals, $hschin, $hschout; - - $numerrs = 0; - $cfgerrs = array(); - - for ($i = 0; $i < $nsernos; $i++) { - - $serno = sprintf("%010d", $sernos[$i]); - - $wfp = @fopen($bddb_cfgdir . "/$serno.cfg", "w"); - if (!$wfp) { - $cfgerrs[$i] = 'file create fail'; - $numerrs++; - continue; - } - set_file_buffer($wfp, 0); - - if (!fprintf($wfp, "serno=%d\n", $sernos[$i])) { - $cfgerrs[$i] = 'cfg wr fail (serno)'; - fclose($wfp); - $numerrs++; - continue; - } - - if (!fprintf($wfp, "date=%s\n", $date)) { - $cfgerrs[$i] = 'cfg wr fail (date)'; - fclose($wfp); - $numerrs++; - continue; - } - - if ($batch != '') { - if (!fprintf($wfp, "batch=%s\n", $batch)) { - $cfgerrs[$i] = 'cfg wr fail (batch)'; - fclose($wfp); - $numerrs++; - continue; - } - } - - $typei = enum_to_index("type", $type_vals); - if (!fprintf($wfp, "type=%d\n", $typei)) { - $cfgerrs[$i] = 'cfg wr fail (type)'; - fclose($wfp); - $numerrs++; - continue; - } - - if (!fprintf($wfp, "rev=%d\n", $rev)) { - $cfgerrs[$i] = 'cfg wr fail (rev)'; - fclose($wfp); - $numerrs++; - continue; - } - - $s = gather_enum_multi_write("sdram", 4, - $sdram_vals, $sdram_nbits); - if ($s != '') { - $b = fprintf($wfp, "sdram=%s\n", $s); - if (!$b) { - $cfgerrs[$i] = 'cfg wr fail (sdram)'; - fclose($wfp); - $numerrs++; - continue; - } - } - - $s = gather_enum_multi_write("flash", 4, - $flash_vals, $flash_nbits); - if ($s != '') { - $b = fprintf($wfp, "flash=%s\n", $s); - if (!$b) { - $cfgerrs[$i] = 'cfg wr fail (flash)'; - fclose($wfp); - $numerrs++; - continue; - } - } - - $s = gather_enum_multi_write("zbt", 16, - $zbt_vals, $zbt_nbits); - if ($s != '') { - $b = fprintf($wfp, "zbt=%s\n", $s); - if (!$b) { - $cfgerrs[$i] = 'cfg wr fail (zbt)'; - fclose($wfp); - $numerrs++; - continue; - } - } - - $s = gather_enum_multi_write("xlxtyp", 4, $xlxtyp_vals); - if ($s != '') { - $b = fprintf($wfp, "xlxtyp=%s\n", $s); - if (!$b) { - $cfgerrs[$i] = 'cfg wr fail (xlxtyp)'; - fclose($wfp); - $numerrs++; - continue; - } - } - - $s = gather_enum_multi_write("xlxspd", 4, $xlxspd_vals); - if ($s != '') { - $b = fprintf($wfp, "xlxspd=%s\n", $s); - if (!$b) { - $cfgerrs[$i] = 'cfg wr fail (xlxspd)'; - fclose($wfp); - $numerrs++; - continue; - } - } - - $s = gather_enum_multi_write("xlxtmp", 4, $xlxtmp_vals); - if ($s != '') { - $b = fprintf($wfp, "xlxtmp=%s\n", $s); - if (!$b) { - $cfgerrs[$i] = 'cfg wr fail (xlxtmp)'; - fclose($wfp); - $numerrs++; - continue; - } - } - - $s = gather_enum_multi_write("xlxgrd", 4, $xlxgrd_vals); - if ($s != '') { - $b = fprintf($wfp, "xlxgrd=%s\n", $s); - if (!$b) { - $cfgerrs[$i] = 'cfg wr fail (xlxgrd)'; - fclose($wfp); - $numerrs++; - continue; - } - } - - if ($cputyp != '') { - $cputypi = enum_to_index("cputyp",$cputyp_vals); - $cpuspdi = enum_to_index("cpuspd", $clk_vals); - $busspdi = enum_to_index("busspd", $clk_vals); - $cpmspdi = enum_to_index("cpmspd", $clk_vals); - $b = fprintf($wfp, "cputyp=%d\ncpuspd=%d\n" . - "busspd=%d\ncpmspd=%d\n", - $cputypi, $cpuspdi, $busspdi, $cpmspdi); - if (!$b) { - $cfgerrs[$i] = 'cfg wr fail (cputyp)'; - fclose($wfp); - $numerrs++; - continue; - } - } - - if ($hstype != '') { - $hstypei = enum_to_index("hstype",$hstype_vals); - $b = fprintf($wfp, "hstype=%d\n" . - "hschin=%s\nhschout=%s\n", - $hstypei, $hschin, $hschout); - if (!$b) { - $cfgerrs[$i] = 'cfg wr fail (hstype)'; - fclose($wfp); - $numerrs++; - continue; - } - } - - if (!fclose($wfp)) { - $cfgerrs[$i] = 'file cls fail'; - $numerrs++; - } - } - - return $numerrs; - } -?> diff --git a/tools/bddb/dodelete.php b/tools/bddb/dodelete.php deleted file mode 100644 index 4839e36..0000000 --- a/tools/bddb/dodelete.php +++ /dev/null @@ -1,65 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - // dodelete page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - Delete Board Results"); - - if (!isset($_REQUEST['serno'])) - die("the board serial number was not specified"); - $serno=intval($_REQUEST['serno']); - - mysql_query("delete from boards where serno=$serno"); - - if(mysql_errno()) { - $errstr = mysql_error(); - echo "\t<font size=+4>\n"; - echo "\t\t<p>\n"; - echo "\t\t\tThe following error was encountered:\n"; - echo "\t\t</p>\n"; - echo "\t\t<center>\n"; - printf("\t\t\t<b>%s</b>\n", $errstr); - echo "\t\t</center>\n"; - echo "\t</font>\n"; - } - else { - echo "\t<font size=+2>\n"; - echo "\t\t<p>\n"; - echo "\t\t\tThe board with serial number <b>$serno</b> was" - . " successfully deleted\n"; - mysql_query("delete from log where serno=$serno"); - if (mysql_errno()) { - $errstr = mysql_error(); - echo "\t\t\t<font size=+4>\n"; - echo "\t\t\t\t<p>\n"; - echo "\t\t\t\t\tBut the following error occurred " . - "when deleting the log entries:\n"; - echo "\t\t\t\t</p>\n"; - echo "\t\t\t\t<center>\n"; - printf("\t\t\t\t\t<b>%s</b>\n", $errstr); - echo "\t\t\t\t</center>\n"; - echo "\t\t\t</font>\n"; - } - echo "\t\t</p>\n"; - echo "\t</font>\n"; - } -?> -<p> -<table width="100%"> -<tr> - <td align=center> - <a href="browse.php">Back to Browse</a> - </td> - <td align=center> - <a href="index.php">Back to Start</a> - </td> -</tr> -</table> -<?php - pg_foot(); -?> diff --git a/tools/bddb/dodellog.php b/tools/bddb/dodellog.php deleted file mode 100644 index 9dd78c1..0000000 --- a/tools/bddb/dodellog.php +++ /dev/null @@ -1,57 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - // dodelete page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - Delete Log Entry Results"); - - if (!isset($_REQUEST['serno'])) - die("the board serial number was not specified"); - $serno=intval($_REQUEST['serno']); - - if (!isset($_REQUEST['logno']) || $_REQUEST['logno'] == 0) - die("the log entry number not specified!"); - $logno=$_REQUEST['logno']; - - mysql_query("delete from log where serno=$serno and logno=$logno"); - - if(mysql_errno()) { - $errstr = mysql_error(); - echo "\t<font size=+4>\n"; - echo "\t\t<p>\n"; - echo "\t\t\tThe following error was encountered:\n"; - echo "\t\t</p>\n"; - echo "\t\t<center>\n"; - printf("\t\t\t<b>%s</b>\n", $errstr); - echo "\t\t</center>\n"; - echo "\t</font>\n"; - } - else { - echo "\t<font size=+2>\n"; - echo "\t\t<p>\n"; - echo "\t\t\tThe log entry with log number <b>$logno</b>\n"; - echo "\t\t\tand serial number <b>$serno</b> "; - echo "was successfully deleted\n"; - echo "\t\t</p>\n"; - echo "\t</font>\n"; - } -?> -<p> -<table width="100%"> -<tr> - <td align=center> - <a href="brlog.php?serno=<?php echo "$serno"; ?>">Back to Log</a> - </td> - <td align=center> - <a href="index.php">Back to Start</a> - </td> -</tr> -</table> -<?php - pg_foot(); -?> diff --git a/tools/bddb/doedit.php b/tools/bddb/doedit.php deleted file mode 100644 index 13fbb69..0000000 --- a/tools/bddb/doedit.php +++ /dev/null @@ -1,186 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - // doedit page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - Edit Board Results"); - - if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '') - die("the board serial number was not specified"); - $serno=intval($_REQUEST['serno']); - - $query="update boards set"; - - if (isset($_REQUEST['ethaddr'])) { - $ethaddr=$_REQUEST['ethaddr']; - if (!eth_addr_is_valid($ethaddr)) - die("ethaddr is invalid ('$ethaddr')"); - $query.=" ethaddr='$ethaddr',"; - } - - if (isset($_REQUEST['date'])) { - $date=$_REQUEST['date']; - list($y, $m, $d) = split("-", $date); - if (!checkdate($m, $d, $y) || $y < 1999) - die("date is invalid (input '$date', " . - "yyyy-mm-dd '$y-$m-$d')"); - $query.=" date='$date'"; - } - - if (isset($_REQUEST['batch'])) { - $batch=$_REQUEST['batch']; - if (strlen($batch) > 32) - die("batch field too long (>32)"); - $query.=", batch='$batch'"; - } - - if (isset($_REQUEST['type'])) { - $type=$_REQUEST['type']; - if (!in_array($type, $type_vals)) - die("Invalid type ($type) specified"); - $query.=", type='$type'"; - } - - if (isset($_REQUEST['rev'])) { - $rev=$_REQUEST['rev']; - if (($rev = intval($rev)) <= 0 || $rev > 255) - die("Revision number is invalid ($rev)"); - $query.=sprintf(", rev=%d", $rev); - } - - if (isset($_REQUEST['location'])) { - $location=$_REQUEST['location']; - if (strlen($location) > 64) - die("location field too long (>64)"); - $query.=", location='$location'"; - } - - if (isset($_REQUEST['comments'])) - $comments=$_REQUEST['comments']; - $query.=", comments='" . rawurlencode($comments) . "'"; - - $query.=gather_enum_multi_query("sdram", 4); - - $query.=gather_enum_multi_query("flash", 4); - - $query.=gather_enum_multi_query("zbt", 16); - - $query.=gather_enum_multi_query("xlxtyp", 4); - $nxlx = count_enum_multi("xlxtyp", 4); - - $query.=gather_enum_multi_query("xlxspd", 4); - if (count_enum_multi("xlxspd", 4) != $nxlx) - die("number of xilinx speeds not same as number of types"); - - $query.=gather_enum_multi_query("xlxtmp", 4); - if (count_enum_multi("xlxtmp", 4) != $nxlx) - die("number of xilinx temps. not same as number of types"); - - $query.=gather_enum_multi_query("xlxgrd", 4); - if (count_enum_multi("xlxgrd", 4) != $nxlx) - die("number of xilinx grades not same as number of types"); - - if (isset($_REQUEST['cputyp'])) { - $cputyp=$_REQUEST['cputyp']; - $query.=", cputyp='$cputyp'"; - if (!isset($_REQUEST['cpuspd']) || $_REQUEST['cpuspd'] == '') - die("must specify cpu speed if cpu type is defined"); - $cpuspd=$_REQUEST['cpuspd']; - $query.=", cpuspd='$cpuspd'"; - if (!isset($_REQUEST['cpmspd']) || $_REQUEST['cpmspd'] == '') - die("must specify cpm speed if cpu type is defined"); - $cpmspd=$_REQUEST['cpmspd']; - $query.=", cpmspd='$cpmspd'"; - if (!isset($_REQUEST['busspd']) || $_REQUEST['busspd'] == '') - die("must specify bus speed if cpu type is defined"); - $busspd=$_REQUEST['busspd']; - $query.=", busspd='$busspd'"; - } - else { - if (isset($_REQUEST['cpuspd'])) - die("can't specify cpu speed if there is no cpu"); - if (isset($_REQUEST['cpmspd'])) - die("can't specify cpm speed if there is no cpu"); - if (isset($_REQUEST['busspd'])) - die("can't specify bus speed if there is no cpu"); - } - - if (isset($_REQUEST['hschin'])) { - $hschin=$_REQUEST['hschin']; - if (($hschin = intval($hschin)) < 0 || $hschin > 4) - die("Invalid number of hs input chans ($hschin)"); - } - else - $hschin = 0; - if (isset($_REQUEST['hschout'])) { - $hschout=$_REQUEST['hschout']; - if (($hschout = intval($hschout)) < 0 || $hschout > 4) - die("Invalid number of hs output chans ($hschout)"); - } - else - $hschout = 0; - if (isset($_REQUEST['hstype'])) { - $hstype=$_REQUEST['hstype']; - $query.=", hstype='$hstype'"; - } - else { - if ($_REQUEST['hschin'] != 0) - die("number of high-speed input channels must be zero" - . " if high-speed chip is not present"); - if ($_REQUEST['hschout'] != 0) - die("number of high-speed output channels must be zero" - . " if high-speed chip is not present"); - } - $query.=", hschin='$hschin'"; - $query.=", hschout='$hschout'"; - - $query.=" where serno=$serno"; - - mysql_query($query); - if(mysql_errno()) { - $errstr = mysql_error(); - echo "\t<font size=+4>\n"; - echo "\t\t<p>\n"; - echo "\t\t\tThe following error was encountered:\n"; - echo "\t\t</p>\n"; - echo "\t\t<center>\n"; - printf("\t\t\t<b>%s</b>\n", $errstr); - echo "\t\t</center>\n"; - echo "\t</font>\n"; - } - else { - $sernos = array($serno); - $nsernos = 1; - - write_eeprom_cfg_file(); - - echo "\t<font size=+2>\n"; - echo "\t\t<p>\n"; - echo "\t\t\tThe board with serial number <b>$serno</b> was" - . " successfully updated"; - if ($numerrs > 0) { - $errstr = $cfgerrs[0]; - echo "<br>\n\t\t\t"; - echo "(but the cfg file update failed: $errstr)"; - } - echo "\n"; - echo "\t\t</p>\n"; - echo "\t</font>\n"; - } - -?> -<p> -<table align=center width="100%"> -<tr> - <td align=center><a href="browse.php">Back to Browse</a></td> - <td align=center><a href="index.php">Back to Start</a></td> -</tr> -</table> -<?php - pg_foot(); -?> diff --git a/tools/bddb/doedlog.php b/tools/bddb/doedlog.php deleted file mode 100644 index 7009aa7..0000000 --- a/tools/bddb/doedlog.php +++ /dev/null @@ -1,76 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - // doedit page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - Edit Log Entry Results"); - - if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '') - die("the board serial number was not specified"); - $serno=intval($_REQUEST['serno']); - - if (!isset($_REQUEST['logno']) || $_REQUEST['logno'] == '') - die("log number not specified!"); - $logno=intval($_REQUEST['logno']); - - $query="update log set"; - - if (isset($_REQUEST['date'])) { - $date=$_REQUEST['date']; - list($y, $m, $d) = split("-", $date); - if (!checkdate($m, $d, $y) || $y < 1999) - die("date is invalid (input '$date', " . - "yyyy-mm-dd '$y-$m-$d')"); - $query.=" date='$date'"; - } - - if (isset($_REQUEST['who'])) { - $who=$_REQUEST['who']; - $query.=", who='" . $who . "'"; - } - - if (isset($_REQUEST['details'])) { - $details=$_REQUEST['details']; - $query.=", details='" . rawurlencode($details) . "'"; - } - - $query.=" where serno=$serno and logno=$logno"; - - mysql_query($query); - if(mysql_errno()) { - $errstr = mysql_error(); - echo "\t<font size=+4>\n"; - echo "\t\t<p>\n"; - echo "\t\t\tThe following error was encountered:\n"; - echo "\t\t</p>\n"; - echo "\t\t<center>\n"; - printf("\t\t\t<b>%s</b>\n", $errstr); - echo "\t\t</center>\n"; - echo "\t</font>\n"; - } - else { - echo "\t<font size=+2>\n"; - echo "\t\t<p>\n"; - echo "\t\t\tThe log entry with log number <b>$logno</b> and\n"; - echo "\t\t\tserial number <b>$serno</b> "; - echo "was successfully updated\n"; - echo "\t\t</p>\n"; - echo "\t</font>\n"; - } - -?> -<p> -<table align=center width="100%"> -<tr> - <td align=center><a href="brlog.php?serno=<?php echo "$serno"; ?>">Back to Log</a></td> - <td align=center><a href="index.php">Back to Start</a></td> -</tr> -</table> -<?php - pg_foot(); -?> diff --git a/tools/bddb/donew.php b/tools/bddb/donew.php deleted file mode 100644 index 39b2c78..0000000 --- a/tools/bddb/donew.php +++ /dev/null @@ -1,230 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - // doedit page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - Board Registration Results"); - - if (isset($_REQUEST['serno'])) { - $serno=$_REQUEST['serno']; - die("serial number must not be set ($serno) when Creating!"); - } - - $query="update boards set"; - - list($y, $m, $d) = split("-", $date); - if (!checkdate($m, $d, $y) || $y < 1999) - die("date is invalid (input '$date', yyyy-mm-dd '$y-$m-$d')"); - $query.=" date='$date'"; - - if ($batch != '') { - if (strlen($batch) > 32) - die("batch field too long (>32)"); - $query.=", batch='$batch'"; - } - - if (!in_array($type, $type_vals)) - die("Invalid type ($type) specified"); - $query.=", type='$type'"; - - if (($rev = intval($rev)) <= 0 || $rev > 255) - die("Revision number is invalid ($rev)"); - $query.=sprintf(", rev=%d", $rev); - - $query.=gather_enum_multi_query("sdram", 4); - - $query.=gather_enum_multi_query("flash", 4); - - $query.=gather_enum_multi_query("zbt", 16); - - $query.=gather_enum_multi_query("xlxtyp", 4); - $nxlx = count_enum_multi("xlxtyp", 4); - - $query.=gather_enum_multi_query("xlxspd", 4); - if (count_enum_multi("xlxspd", 4) != $nxlx) - die("number of xilinx speeds not same as number of types"); - - $query.=gather_enum_multi_query("xlxtmp", 4); - if (count_enum_multi("xlxtmp", 4) != $nxlx) - die("number of xilinx temps. not same as number of types"); - - $query.=gather_enum_multi_query("xlxgrd", 4); - if (count_enum_multi("xlxgrd", 4) != $nxlx) - die("number of xilinx grades not same as number of types"); - - if ($cputyp == '') { - if ($cpuspd != '') - die("can't specify cpu speed if there is no cpu"); - if ($cpmspd != '') - die("can't specify cpm speed if there is no cpu"); - if ($busspd != '') - die("can't specify bus speed if there is no cpu"); - } - else { - $query.=", cputyp='$cputyp'"; - if ($cpuspd == '') - die("must specify cpu speed if cpu type is defined"); - $query.=", cpuspd='$cpuspd'"; - if ($cpmspd == '') - die("must specify cpm speed if cpu type is defined"); - $query.=", cpmspd='$cpmspd'"; - if ($busspd == '') - die("must specify bus speed if cpu type is defined"); - $query.=", busspd='$busspd'"; - } - - if (($hschin = intval($hschin)) < 0 || $hschin > 4) - die("Invalid number of hs input chans ($hschin)"); - if (($hschout = intval($hschout)) < 0 || $hschout > 4) - die("Invalid number of hs output chans ($hschout)"); - if ($hstype == '') { - if ($hschin != 0) - die("number of high-speed input channels must be zero" - . " if high-speed chip is not present"); - if ($hschout != 0) - die("number of high-speed output channels must be zero" - . " if high-speed chip is not present"); - } - else - $query.=", hstype='$hstype'"; - $query.=", hschin='$hschin'"; - $query.=", hschout='$hschout'"; - - // echo "final query = '$query'<br>\n"; - - $quant = intval($quant); - if ($quant <= 0) $quant = 1; - - $sernos = array(); - if ($geneths) - $ethaddrs = array(); - - $sqlerr = ''; - - while ($quant-- > 0) { - - mysql_query("insert into boards (serno) values (null)"); - if (mysql_errno()) { - $sqlerr = mysql_error(); - break; - } - - $serno = mysql_insert_id(); - if (!$serno) { - $sqlerr = "couldn't allocate new serial number"; - break; - } - - mysql_query($query . " where serno=$serno"); - if (mysql_errno()) { - $sqlerr = mysql_error(); - break; - } - - array_push($sernos, $serno); - - if ($geneths) { - - $ethaddr = gen_eth_addr($serno); - - mysql_query("update boards set ethaddr='$ethaddr'" . - " where serno=$serno"); - if (mysql_errno()) { - $sqlerr = mysql_error(); - - array_push($ethaddrs, - "<font color=#ff0000><b>" . - "db save fail" . - "</b></font>"); - break; - } - - array_push($ethaddrs, $ethaddr); - } - } - - $nsernos = count($sernos); - - if ($nsernos > 0) { - - write_eeprom_cfg_file(); - - echo "<font size=+2>\n"; - echo "\t<p>\n"; - echo "\t\tThe following board serial numbers were" - . " successfully allocated"; - if ($numerrs > 0) - echo " (but with $numerrs cfg file error" . - ($numerrs > 1 ? "s" : "") . ")"; - echo ":\n"; - echo "\t</p>\n"; - - echo "</font>\n"; - - echo "<table align=center width=\"100%\">\n"; - echo "<tr>\n"; - echo "\t<th>Serial Number</th>\n"; - if ($numerrs > 0) - echo "\t<th>Cfg File Errs</th>\n"; - if ($geneths) - echo "\t<th>Ethernet Address</th>\n"; - echo "</tr>\n"; - - for ($i = 0; $i < $nsernos; $i++) { - - $serno = sprintf("%010d", $sernos[$i]); - - echo "<tr>\n"; - - echo "\t<td align=center><font size=+2>" . - "<b>$serno</b></font></td>\n"; - - if ($numerrs > 0) { - if (($errstr = $cfgerrs[$i]) == '') - $errstr = ' '; - echo "\t<td align=center>" . - "<font size=+2 color=#ff0000><b>" . - $errstr . - "</b></font></td>\n"; - } - - if ($geneths) { - echo "\t<td align=center>" . - "<font size=+2 color=#00ff00><b>" . - $ethaddrs[$i] . - "</b></font></td>\n"; - } - - echo "</tr>\n"; - } - - echo "</table>\n"; - } - - if ($sqlerr != '') { - echo "\t<font size=+4>\n"; - echo "\t\t<p>\n"; - echo "\t\t\tThe following SQL error was encountered:\n"; - echo "\t\t</p>\n"; - echo "\t\t<center>\n"; - printf("\t\t\t<b>%s</b>\n", $sqlerr); - echo "\t\t</center>\n"; - echo "\t</font>\n"; - } - -?> -<p> -<table align=center width="100%"> -<tr> - <td align=center><a href="browse.php">Go to Browse</a></td> - <td align=center><a href="index.php">Back to Start</a></td> -</tr> -</table> -<?php - pg_foot(); -?> diff --git a/tools/bddb/donewlog.php b/tools/bddb/donewlog.php deleted file mode 100644 index 7635d29..0000000 --- a/tools/bddb/donewlog.php +++ /dev/null @@ -1,86 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - // doedit page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - Add Log Entry Results"); - - if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '') - die("serial number not specified!"); - $serno=intval($_REQUEST['serno']); - - if (isset($_REQUEST['logno'])) { - $logno=$_REQUEST['logno']; - die("log number must not be set ($logno) when Creating!"); - } - - $query="update log set serno=$serno"; - - list($y, $m, $d) = split("-", $date); - if (!checkdate($m, $d, $y) || $y < 1999) - die("date is invalid (input '$date', yyyy-mm-dd '$y-$m-$d')"); - $query.=", date='$date'"; - - if (isset($_REQUEST['who'])) { - $who=$_REQUEST['who']; - $query.=", who='" . $who . "'"; - } - - if (isset($_REQUEST['details'])) { - $details=$_REQUEST['details']; - $query.=", details='" . rawurlencode($details) . "'"; - } - - // echo "final query = '$query'<br>\n"; - - $sqlerr = ''; - - mysql_query("insert into log (logno) values (null)"); - if (mysql_errno()) - $sqlerr = mysql_error(); - else { - $logno = mysql_insert_id(); - if (!$logno) - $sqlerr = "couldn't allocate new serial number"; - else { - mysql_query($query . " where logno=$logno"); - if (mysql_errno()) - $sqlerr = mysql_error(); - } - } - - if ($sqlerr == '') { - echo "<font size=+2>\n"; - echo "\t<p>\n"; - echo "\t\tA log entry with log number '$logno' was " . - "added to the board with serial number '$serno'\n"; - echo "\t</p>\n"; - echo "</font>\n"; - } - else { - echo "\t<font size=+4>\n"; - echo "\t\t<p>\n"; - echo "\t\t\tThe following SQL error was encountered:\n"; - echo "\t\t</p>\n"; - echo "\t\t<center>\n"; - printf("\t\t\t<b>%s</b>\n", $sqlerr); - echo "\t\t</center>\n"; - echo "\t</font>\n"; - } - -?> -<p></p> -<table width="100%"> -<tr> - <td align=center><a href="brlog.php?serno=<?php echo "$serno"; ?>">Go to Browse</a></td> - <td align=center><a href="index.php">Back to Start</a></td> -</tr> -</table> -<?php - pg_foot(); -?> diff --git a/tools/bddb/edit.php b/tools/bddb/edit.php deleted file mode 100644 index dd8c26c..0000000 --- a/tools/bddb/edit.php +++ /dev/null @@ -1,131 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - // edit page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - Edit Board Registration"); - - if ($serno == 0) - die("serial number not specified or invalid!"); - - $pserno = sprintf("%010d", $serno); - - echo "<center><b><font size=+2>"; - echo "Board Serial Number: $pserno"; - echo "</font></b></center>\n"; - -?> -<p> -<form action=doedit.php method=POST> -<?php - echo "<input type=hidden name=serno value=$serno>\n"; - - $r=mysql_query("select * from boards where serno=$serno"); - $row=mysql_fetch_array($r); - if(!$row) die("no record of serial number '$serno' in database"); - - begin_table(5); - - // ethaddr char(17) - print_field("ethaddr", $row, 17); - - // date date - print_field("date", $row); - - // batch char(32) - print_field("batch", $row, 32); - - // type enum('IO','CLP','DSP','INPUT','ALT-INPUT','DISPLAY') - print_enum("type", $row, $type_vals); - - // rev tinyint(3) unsigned zerofill - print_field("rev", $row, 3, 'rev_filter'); - - // location char(64) - print_field("location", $row, 64); - - // comments text - print_field_multiline("comments", $row, 60, 10, 'text_filter'); - - // sdram[0-3] enum('32M','64M','128M','256M') - print_enum_multi("sdram", $row, $sdram_vals, 4, array()); - - // flash[0-3] enum('4M','8M','16M','32M','64M') - print_enum_multi("flash", $row, $flash_vals, 4, array()); - - // zbt[0-f] enum('512K','1M','2M','4M') - print_enum_multi("zbt", $row, $zbt_vals, 16, array()); - - // xlxtyp[0-3] enum('XCV300E','XCV400E','XCV600E') - print_enum_multi("xlxtyp", $row, $xlxtyp_vals, 4, array(), 1); - - // xlxspd[0-3] enum('6','7','8') - print_enum_multi("xlxspd", $row, $xlxspd_vals, 4, array(), 1); - - // xlxtmp[0-3] enum('COM','IND') - print_enum_multi("xlxtmp", $row, $xlxtmp_vals, 4, array(), 1); - - // xlxgrd[0-3] enum('NORMAL','ENGSAMP') - print_enum_multi("xlxgrd", $row, $xlxgrd_vals, 4, array(), 1); - - // cputyp enum('MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)') - print_enum("cputyp", $row, $cputyp_vals); - - // cpuspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ') - print_enum_select("cpuspd", $row, $clk_vals); - - // cpmspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ') - print_enum_select("cpmspd", $row, $clk_vals); - - // busspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ') - print_enum_select("busspd", $row, $clk_vals); - - // hstype enum('AMCC-S2064A') - print_enum("hstype", $row, $hstype_vals); - - // hschin enum('0','1','2','3','4') - print_enum("hschin", $row, $hschin_vals); - - // hschout enum('0','1','2','3','4') - print_enum("hschout", $row, $hschout_vals); - - end_table(); - - echo "<p>\n"; - echo "<center><b>"; - echo "<font color=#ff0000>WARNING: NO UNDO ON DELETE!</font>"; - echo "<br></br>\n"; - echo "<tt>[ <a href=\"dodelete.php?serno=$serno\">delete</a> ]</tt>"; - echo "</b></center>\n"; - echo "</p>\n"; -?> -<p> -<table align=center width="100%"> -<tr> - <td align=center> - <input type=submit value=Edit> - </td> - <td> - - </td> - <td align=center> - <input type=reset value=Reset> - </td> - <td> - - </td> - <td align=center> - <a href="index.php">Back to Start</a> - </td> -</tr> -</table> -</p> -</form> -<?php - pg_foot(); -?> diff --git a/tools/bddb/edlog.php b/tools/bddb/edlog.php deleted file mode 100644 index 8befd35..0000000 --- a/tools/bddb/edlog.php +++ /dev/null @@ -1,86 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - // edit page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - Edit Board Log Entry"); - - if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '') - die("serial number not specified!"); - $serno=intval($_REQUEST['serno']); - - if (!isset($_REQUEST['logno']) || $_REQUEST['logno'] == '') - die("log number not specified!"); - $logno=intval($_REQUEST['logno']); - - $pserno = sprintf("%010d", $serno); - $plogno = sprintf("%010d", $logno); - - echo "<center><b><font size=+2>"; - echo "Board Serial Number: $pserno, Log Number: $plogno"; - echo "</font></b></center>\n"; - -?> -<p> -<form action=doedlog.php method=POST> -<?php - echo "<input type=hidden name=serno value=$serno>\n"; - echo "<input type=hidden name=logno value=$logno>\n"; - - $r=mysql_query("select * from log where serno=$serno and logno=$logno"); - $row=mysql_fetch_array($r); - if(!$row) - die("no record of log entry with serial number '$serno' " . - "and log number '$logno' in database"); - - begin_table(3); - - // date date - print_field("date", $row); - - // who char(20) - print_field("who", $row); - - // details text - print_field_multiline("details", $row, 60, 10, 'text_filter'); - - end_table(); - - echo "<p>\n"; - echo "<center><b>"; - echo "<font color=#ff0000>WARNING: NO UNDO ON DELETE!</font>"; - echo "<br></br>\n"; - echo "<tt>[ <a href=\"dodellog.php?serno=$serno&logno=$logno\">delete</a> ]</tt>"; - echo "</b></center>\n"; - echo "</p>\n"; -?> -<p> -<table align=center width="100%"> -<tr> - <td align=center> - <input type=submit value=Edit> - </td> - <td> - - </td> - <td align=center> - <input type=reset value=Reset> - </td> - <td> - - </td> - <td align=center> - <a href="index.php">Back to Start</a> - </td> -</tr> -</table> -</p> -</form> -<?php - pg_foot(); -?> diff --git a/tools/bddb/execute.php b/tools/bddb/execute.php deleted file mode 100644 index 0b62882..0000000 --- a/tools/bddb/execute.php +++ /dev/null @@ -1,33 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - $serno=isset($_REQUEST['serno'])?$_REQUEST['serno']:''; - - $submit=isset($_REQUEST['submit'])?$_REQUEST['submit']:"[NOT SET]"; - - switch ($submit) { - - case "New": - require("new.php"); - break; - - case "Edit": - require("edit.php"); - break; - - case "Browse": - require("browse.php"); - break; - - case "Log": - require("brlog.php"); - break; - - default: - require("badsubmit.php"); - break; - } -?> diff --git a/tools/bddb/index.php b/tools/bddb/index.php deleted file mode 100644 index 842aed5..0000000 --- a/tools/bddb/index.php +++ /dev/null @@ -1,38 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - require("defs.php"); - pg_head("$bddb_label"); -?> -<font size="+4"> - <form action=execute.php method=POST> - <table width="100%" cellspacing=10 cellpadding=10> - <tr> - <td align=center> - <input type=submit name=submit value="New"></input> - </td> - <td align=center> - <input type=submit name=submit value="Edit"></input> - </td> - <td align=center> - <input type=submit name=submit value="Browse"></input> - </td> - <td align=center> - <input type=submit name=submit value="Log"></input> - </td> - </tr> - <tr> - <td align=center colspan=4> - <b>Serial Number:</b> - <input type=text name=serno size=10 maxsize=10 value=""></input> - </td> - </tr> - </table> - </form> -</font> -<?php - pg_foot(); -?> diff --git a/tools/bddb/new.php b/tools/bddb/new.php deleted file mode 100644 index 30323ff..0000000 --- a/tools/bddb/new.php +++ /dev/null @@ -1,120 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - // edit page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - New Board Registration"); -?> -<form action=donew.php method=POST> -<p></p> -<?php - $serno=intval($serno); - // if a serial number was supplied, fetch the record - // and use its contents as defaults - if ($serno != 0) { - $r=mysql_query("select * from boards where serno=$serno"); - $row=mysql_fetch_array($r); - if(!$row)die("no record of serial number '$serno' in database"); - } - else - $row = array(); - - begin_table(5); - - // date date - print_field("date", array('date' => date("Y-m-d"))); - - // batch char(32) - print_field("batch", $row, 32); - - // type enum('IO','CLP','DSP','INPUT','ALT-INPUT','DISPLAY') - print_enum("type", $row, $type_vals, 0); - - // rev tinyint(3) unsigned zerofill - print_field("rev", $row, 3, 'rev_filter'); - - // sdram[0-3] enum('32M','64M','128M','256M') - print_enum_multi("sdram", $row, $sdram_vals, 4, array(2)); - - // flash[0-3] enum('4M','8M','16M','32M','64M') - print_enum_multi("flash", $row, $flash_vals, 4, array(2)); - - // zbt[0-f] enum('512K','1M','2M','4M') - print_enum_multi("zbt", $row, $zbt_vals, 16, array(2, 2)); - - // xlxtyp[0-3] enum('XCV300E','XCV400E','XCV600E') - print_enum_multi("xlxtyp", $row, $xlxtyp_vals, 4, array(1), 1); - - // xlxspd[0-3] enum('6','7','8') - print_enum_multi("xlxspd", $row, $xlxspd_vals, 4, array(1), 1); - - // xlxtmp[0-3] enum('COM','IND') - print_enum_multi("xlxtmp", $row, $xlxtmp_vals, 4, array(1), 1); - - // xlxgrd[0-3] enum('NORMAL','ENGSAMP') - print_enum_multi("xlxgrd", $row, $xlxgrd_vals, 4, array(1), 1); - - // cputyp enum('MPC8260(HIP3)','MPC8260A(HIP4)','MPC8280(HIP7)') - print_enum("cputyp", $row, $cputyp_vals, 1); - - // cpuspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ') - print_enum_select("cpuspd", $row, $clk_vals, 4); - - // cpmspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ') - print_enum_select("cpmspd", $row, $clk_vals, 4); - - // busspd enum('33MHZ','66MHZ','100MHZ','133MHZ','166MHZ','200MHZ','233MHZ','266MHZ') - print_enum_select("busspd", $row, $clk_vals, 2); - - // hstype enum('AMCC-S2064A') - print_enum("hstype", $row, $hstype_vals, 1); - - // hschin enum('0','1','2','3','4') - print_enum("hschin", $row, $hschin_vals, 4); - - // hschout enum('0','1','2','3','4') - print_enum("hschout", $row, $hschout_vals, 4); - - end_table(); -?> -<p></p> -<table width="100%"> -<tr> - <td align=center colspan=3> - Allocate - <input type=text name=quant size=2 maxlength=2 value=" 1"> - board serial number(s) - </td> -</tr> -<tr> - <td align=center colspan=3> - <input type=checkbox name=geneths checked> - Generate Ethernet Address(es) - </td> -</tr> -<tr> - <td colspan=3> - - </td> -</tr> -<tr> - <td align=center> - <input type=submit value="Register Board"> - </td> - <td> - - </td> - <td align=center> - <input type=reset value="Reset Form Contents"> - </td> -</tr> -</table> -</form> -<?php - pg_foot(); -?> diff --git a/tools/bddb/newlog.php b/tools/bddb/newlog.php deleted file mode 100644 index 609bb85..0000000 --- a/tools/bddb/newlog.php +++ /dev/null @@ -1,54 +0,0 @@ -<?php // php pages made with phpMyBuilder <http://kyber.dk/phpMyBuilder> ?> -<?php - // (C) Copyright 2001 - // Murray Jensen <Murray.Jensen@csiro.au> - // CSIRO Manufacturing Science and Technology, Preston Lab - - // edit page (hymod_bddb / boards) - - require("defs.php"); - - pg_head("$bddb_label - New Log Entry"); - - if (!isset($_REQUEST['serno']) || $_REQUEST['serno'] == '') - die("serial number not specified or invalid!"); - $serno=intval($_REQUEST['serno']); - - if (isset($_REQUEST['logno'])) { - $logno=$_REQUEST['logno']; - die("log number must not be specified when adding! ($logno)"); - } -?> -<form action=donewlog.php method=POST> -<p></p> -<?php - echo "<input type=hidden name=serno value=$serno>\n"; - - begin_table(3); - - // date date - print_field("date", array('date' => date("Y-m-d"))); - - // who char(20) - print_field("who", array()); - - // details text - print_field_multiline("details", array(), 60, 10, 'text_filter'); - - end_table(); -?> -<p></p> -<table width="100%"> -<tr> - <td align=center> - <input type=submit value="Add Log Entry"> - </td> - <td align=center> - <input type=reset value="Reset Form Contents"> - </td> -</tr> -</table> -</form> -<?php - pg_foot(); -?> |