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authorFabio Estevam <fabio.estevam@freescale.com>2014-08-01 11:50:00 (GMT)
committerStefano Babic <sbabic@denx.de>2014-08-08 08:29:40 (GMT)
commit338c9da6053c7e02264fbec7568c271bb503ab1a (patch)
treefb33f8471eec6486a9692f9e96336befc496a26b
parent28344902457f453da08133f2eb684221a1b8ab91 (diff)
downloadu-boot-338c9da6053c7e02264fbec7568c271bb503ab1a.tar.xz
mx6: crm_regs: Fix CDCDR_SPDIF0_CLK_PODF mask and offset
According to the Reference Manual the 'spdif0_clk_podf' field of register CCM_CDCDR corresponds to bits 22, 23 and 24, so fix the mask and offset definitions accordingly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
-rw-r--r--arch/arm/include/asm/arch-mx6/crm_regs.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 0fcef69..9afe788 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -335,8 +335,8 @@ struct mxc_ccm_reg {
#endif
#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 19)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 19
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 22)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 22
#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20)
#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20
#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12)