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| author | Calvin Johnson <calvin.johnson@nxp.com> | 2018-01-16 05:47:03 (GMT) |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2018-01-17 12:33:14 (GMT) |
| commit | 36f0e61d606edbea6db5a5f56763d2d6b7b9b5a7 (patch) | |
| tree | e2b08e5ea9fca70c420d9aa7ca83a0c805c55027 | |
| parent | 6cf0730266f5a4d1f851b148ed2b71e3a2141e61 (diff) | |
| download | u-boot-36f0e61d606edbea6db5a5f56763d2d6b7b9b5a7.tar.xz | |
board: freescale: ls1012ardb: enable network support on ls1012ardb
This patch enables ethernet support for ls1012ardb.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
Changes in v2:
-split from original patch "board: freescale: ls1012a: enable network
support on ls1012a platforms"
-fix RGMII TX-delay issue
| -rw-r--r-- | board/freescale/ls1012ardb/Makefile | 1 | ||||
| -rw-r--r-- | board/freescale/ls1012ardb/eth.c | 68 | ||||
| -rw-r--r-- | board/freescale/ls1012ardb/ls1012ardb.c | 4 | ||||
| -rw-r--r-- | include/configs/ls1012ardb.h | 4 |
4 files changed, 73 insertions, 4 deletions
diff --git a/board/freescale/ls1012ardb/Makefile b/board/freescale/ls1012ardb/Makefile index 05fa9d9..bd80ce5 100644 --- a/board/freescale/ls1012ardb/Makefile +++ b/board/freescale/ls1012ardb/Makefile @@ -5,3 +5,4 @@ # obj-y += ls1012ardb.o +obj-y += eth.o diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c new file mode 100644 index 0000000..713f830 --- /dev/null +++ b/board/freescale/ls1012ardb/eth.c @@ -0,0 +1,68 @@ +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <netdev.h> +#include <fm_eth.h> +#include <fsl_mdio.h> +#include <malloc.h> +#include <fsl_dtsec.h> +#include <asm/arch/soc.h> +#include <asm/arch-fsl-layerscape/config.h> +#include <asm/arch-fsl-layerscape/immap_lsch2.h> +#include <asm/arch/fsl_serdes.h> +#include <pfe_eth/pfe_eth.h> +#include <i2c.h> + +#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO" + +void reset_phy(void) +{ + /* Through reset IO expander reset both RGMII and SGMII PHYs */ + i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK); + i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK); + mdelay(10); + i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH1_MASK); + mdelay(10); + i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF); + mdelay(50); +} + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FSL_PFE + struct mii_dev *bus; + struct mdio_info mac1_mdio_info; + + reset_phy(); + + init_pfe_scfg_dcfg_regs(); + + mac1_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR; + mac1_mdio_info.name = DEFAULT_PFE_MDIO_NAME; + + bus = pfe_mdio_init(&mac1_mdio_info); + if (!bus) { + printf("Failed to register mdio\n"); + return -1; + } + + /* MAC1 */ + pfe_set_mdio(0, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME)); + pfe_set_phy_address_mode(0, EMAC1_PHY_ADDR, + PHY_INTERFACE_MODE_SGMII); + + /* MAC2 */ + pfe_set_mdio(1, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME)); + pfe_set_phy_address_mode(1, EMAC2_PHY_ADDR, + PHY_INTERFACE_MODE_RGMII_TXID); + + cpu_eth_init(bis); +#endif + return pci_eth_init(bis); +} diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index c9557bb..ed5a8e6 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -114,10 +114,6 @@ int dram_init(void) return 0; } -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} int board_early_init_f(void) { diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index 550865b..e3b020f 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -25,6 +25,7 @@ */ #define I2C_MUX_IO_ADDR 0x24 +#define I2C_MUX_IO2_ADDR 0x25 #define I2C_MUX_IO_0 0 #define I2C_MUX_IO_1 1 #define SW_BOOT_MASK 0x03 @@ -39,6 +40,9 @@ #define SW_REV_C2 0xD8 #define SW_REV_D 0xD0 #define SW_REV_E 0xC8 +#define __PHY_MASK 0xF9 +#define __PHY_ETH2_MASK 0xFB +#define __PHY_ETH1_MASK 0xFD /* MMC */ #ifdef CONFIG_MMC |