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authorCalvin Johnson <calvin.johnson@nxp.com>2018-01-16 05:51:34 (GMT)
committerPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>2018-01-17 12:33:14 (GMT)
commit3c8ddb20c3eff8b47807d09393ba92fc59b2a6c0 (patch)
treeb2e815ad6650577ae566e972dc57016b0d28f1ba
parentbec6a126ba150701868e553ab709a7aab5d20d85 (diff)
downloadu-boot-3c8ddb20c3eff8b47807d09393ba92fc59b2a6c0.tar.xz
armv8: layerscape: csu: enable ns access to PFE registers
Enable all types of non-secure access to PFE block registers. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com> Changes in v2: -Improved commit message to provide more description
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/ns_access.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
index f46f1d8..fe97a93 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
@@ -26,6 +26,7 @@ enum csu_cslx_ind {
CSU_CSLX_PCIE3_IO,
CSU_CSLX_USB3 = 20,
CSU_CSLX_USB2,
+ CSU_CSLX_PFE = 23,
CSU_CSLX_SERDES = 32,
CSU_CSLX_QDMA,
CSU_CSLX_LPUART2,
@@ -105,6 +106,7 @@ static struct csu_ns_dev ns_dev[] = {
{CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
{CSU_CSLX_USB3, CSU_ALL_RW},
{CSU_CSLX_USB2, CSU_ALL_RW},
+ {CSU_CSLX_PFE, CSU_ALL_RW},
{CSU_CSLX_SERDES, CSU_ALL_RW},
{CSU_CSLX_QDMA, CSU_ALL_RW},
{CSU_CSLX_LPUART2, CSU_ALL_RW},