diff options
| author | Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> | 2014-07-28 06:07:44 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-08-09 15:17:01 (GMT) |
| commit | 53022c3113a6670d21f55262f511ae6a07bb3dc4 (patch) | |
| tree | 2a1df6874acffac3d13ef8c2d5064ded1248c501 | |
| parent | 1a223c93240fd4bfaa05cc998b261d9560ca0f09 (diff) | |
| download | u-boot-53022c3113a6670d21f55262f511ae6a07bb3dc4.tar.xz | |
serial: sh: Add support External Clock mode
R8A7780 and R7A7791 of rmobile supports External Clock mode, and these uses
different from Internal Clock mode registers and calculations to the baud rate
setting. This adds function for External Clock mode.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| -rw-r--r-- | drivers/serial/serial_sh.c | 8 | ||||
| -rw-r--r-- | drivers/serial/serial_sh.h | 4 |
2 files changed, 9 insertions, 3 deletions
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index 0826d59..144a925 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -49,9 +49,15 @@ static struct uart_port sh_sci = { static void sh_serial_setbrg(void) { DECLARE_GLOBAL_DATA_PTR; - +#ifdef CONFIG_SCIF_USE_EXT_CLK + unsigned short dl = DL_VALUE(gd->baudrate, CONFIG_SH_SCIF_CLK_FREQ); + sci_out(&sh_sci, DL, dl); + /* Need wait: Clock * 1/dl × 1/16 */ + udelay((1000000 * dl * 16 / CONFIG_SYS_CLK_FREQ) * 1000 + 1); +#else sci_out(&sh_sci, SCBRR, SCBRR_VALUE(gd->baudrate, CONFIG_SH_SCIF_CLK_FREQ)); +#endif } static int sh_serial_init(void) diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index 4f3e225..fe8cde4 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -735,8 +735,8 @@ static inline int scbrr_calc(struct uart_port port, int bps, int clk) #elif defined(__H8300H__) || defined(__H8300S__) #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1) #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) -#define SCBRR DL -#define SCBRR_VALUE(bps, clk) (clk / bps / 16) +#define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */ +#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) /* Internal Clock */ #else /* Generic SH */ #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) #endif |