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| author | Rajesh Bhagat <rajesh.bhagat@nxp.com> | 2017-11-30 06:30:54 (GMT) |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2018-01-18 05:29:08 (GMT) |
| commit | 55540f32f937416ae2e1879663d354a264939584 (patch) | |
| tree | 8d78860187c3ed9d0b7a30d5cd65d8a93fcff47a | |
| parent | 2586b3ab5805d1a13c24660500f2a9fe63e3d786 (diff) | |
| download | u-boot-55540f32f937416ae2e1879663d354a264939584.tar.xz | |
ddr: fsl: set cdr1 first in case 0.9v VDD is enabled for some SoCs
Sets DDR configuration parameter cdr1 before all other settings
to support case 0.9v VDD is enabled for some SoCs
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
| -rw-r--r-- | drivers/ddr/fsl/fsl_ddr_gen4.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 058c9b9..b3a27ec 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -95,6 +95,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, if (step == 2) goto step2; + /* Set cdr1 first in case 0.9v VDD is enabled for some SoCs*/ + ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); + if (regs->ddr_eor) ddr_out32(&ddr->eor, regs->ddr_eor); @@ -183,7 +186,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4); ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5); ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6); - ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); #ifdef CONFIG_DEEP_SLEEP if (is_warm_boot()) { ddr_out32(&ddr->sdram_cfg_2, |