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| author | Minghuan Lian <Minghuan.Lian@nxp.com> | 2017-10-20 02:45:50 (GMT) |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2018-01-18 05:29:08 (GMT) |
| commit | 621dd4759183088dafefc8d6bf8570de9ceb50b0 (patch) | |
| tree | f03269ae9a735fbf1ce148e0b9494d3661985b15 | |
| parent | f5285a88d1e673c3c14d16d5ab298ef70ef91f25 (diff) | |
| download | u-boot-621dd4759183088dafefc8d6bf8570de9ceb50b0.tar.xz | |
dm: pci: change bus number register setting compliant with Linux
This patch is to change U-Boot PCI bus assignement compliant with Linux.
It means each PCIe controller's bus number is 0, not the current maximum
PCI bus number, when start to scan this controller.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| -rw-r--r-- | drivers/pci/pci_auto.c | 6 | ||||
| -rw-r--r-- | drivers/pci/pcie_dw_mvebu.c | 1 | ||||
| -rw-r--r-- | drivers/pci/pcie_layerscape.c | 2 |
3 files changed, 5 insertions, 4 deletions
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index ee9a854..c2bc326 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -181,8 +181,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) /* Configure bus number registers */ dm_pci_write_config8(dev, PCI_PRIMARY_BUS, - PCI_BUS(dm_pci_get_bdf(dev))); - dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus); + PCI_BUS(dm_pci_get_bdf(dev)) - ctlr->seq); + dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus - ctlr->seq); dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff); if (pci_mem) { @@ -257,7 +257,7 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus) pci_io = ctlr_hose->pci_io; /* Configure bus number registers */ - dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus); + dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus - ctlr->seq); if (pci_mem) { /* Round memory allocator to 1MB boundary */ diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c index 202cfe9..a198855 100644 --- a/drivers/pci/pcie_dw_mvebu.c +++ b/drivers/pci/pcie_dw_mvebu.c @@ -162,6 +162,7 @@ static uintptr_t set_cfg_address(struct pcie_dw_mvebu *pcie, /* Accessing root port configuration space. */ va_address = (uintptr_t)pcie->ctrl_base; } else { + d = PCI_MASK_BUS(d) | (PCI_BUS(d) - pcie->first_busno); writel(d << 8, pcie->ctrl_base + PCIE_ATU_LOWER_TARGET); va_address = (uintptr_t)pcie->cfg_base; } diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 0cb7f6d..503fd5e 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -255,7 +255,7 @@ int ls_pcie_conf_address(struct udevice *bus, pci_dev_t bdf, return 0; } - busdev = PCIE_ATU_BUS(PCI_BUS(bdf)) | + busdev = PCIE_ATU_BUS(PCI_BUS(bdf) - bus->seq) | PCIE_ATU_DEV(PCI_DEV(bdf)) | PCIE_ATU_FUNC(PCI_FUNC(bdf)); |