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| author | Bao Xiaowei <xiaowei.bao@nxp.com> | 2017-12-15 09:43:53 (GMT) |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2018-01-10 04:04:10 (GMT) |
| commit | 9e4e679a7730fdd322b1dae79181e446c82daa13 (patch) | |
| tree | 28367dafb112a67dfa6efadeaefb2df21bd56609 | |
| parent | 582a8f96d0925f0f6cab07ee3897cdb129583def (diff) | |
| download | u-boot-9e4e679a7730fdd322b1dae79181e446c82daa13.tar.xz | |
Powerpc: T208xQDS: Modify the comment of the CONFIG_FSL_PCIE_RESET macro
Remove duplicate macro CONFIG_FSL_PCIE_RESET and update its comment.
It enables PCIe reset to fix link width 2x - 4x.
Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
| -rw-r--r-- | include/configs/T208xQDS.h | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 15d1f5f..08f22d5 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -534,7 +534,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_PCIE4 /* PCIE controller 4 */ -#define CONFIG_FSL_PCIE_RESET +#define CONFIG_FSL_PCIE_RESET /* pcie reset fix link width 2x-4x*/ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ @@ -578,7 +578,6 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif |