diff options
| author | SRICHARAN R <r.sricharan@ti.com> | 2012-03-12 02:25:46 (GMT) |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-05-15 06:31:25 (GMT) |
| commit | aaec44874f607db3cb19985f0b977cc6f13fd11f (patch) | |
| tree | 9cac1730c49bcbf1cee556b4cf5bafe65080fcb4 | |
| parent | 971f2ba21a6fb8b2b7d4696b6c4ca43bda20d366 (diff) | |
| download | u-boot-aaec44874f607db3cb19985f0b977cc6f13fd11f.tar.xz | |
OMAP4/5: emif: Correct the emif power mgt shadow register bit fields.
PD_TIM bit field which specifies the power down timing is defined
to occupy bits 8-11, where as it is actually from 12-15 bits.
So correcting this.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
| -rw-r--r-- | arch/arm/include/asm/emif.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index aab15d8..f1e3ad2 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -226,8 +226,8 @@ #define EMIF_REG_CS_TIM_MASK (0xf << 0) /* PWR_MGMT_CTRL_SHDW */ -#define EMIF_REG_PD_TIM_SHDW_SHIFT 8 -#define EMIF_REG_PD_TIM_SHDW_MASK (0xf << 8) +#define EMIF_REG_PD_TIM_SHDW_SHIFT 12 +#define EMIF_REG_PD_TIM_SHDW_MASK (0xf << 12) #define EMIF_REG_SR_TIM_SHDW_SHIFT 4 #define EMIF_REG_SR_TIM_SHDW_MASK (0xf << 4) #define EMIF_REG_CS_TIM_SHDW_SHIFT 0 |