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| author | Simon Glass <sjg@chromium.org> | 2012-10-17 13:24:56 (GMT) |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2012-11-19 15:15:39 (GMT) |
| commit | ad16617f74326ee860243ba0aca6b7a01dd25a1f (patch) | |
| tree | 736ca87d96d89f5584b82326419c53126743bf6c | |
| parent | 9a8efc4604b32221ea362ea41b38d714e4b4ab7a (diff) | |
| download | u-boot-ad16617f74326ee860243ba0aca6b7a01dd25a1f.tar.xz | |
tegra: Align LCD frame buffer to section boundary
For tegra we want to enable the cache for the LCD. This is easier if
we can avoid using L2 page tages, so align the LCD to a section
boundary.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
| -rw-r--r-- | include/configs/tegra20-common.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 15bd9bb..72b661a 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -38,6 +38,9 @@ #include <asm/arch/tegra.h> /* get chip and board defs */ +/* Align LCD to 1MB boundary */ +#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE + /* * Display CPU and Board information */ |