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authorMarek Vasut <marex@denx.de>2012-11-12 14:34:31 (GMT)
committerTom Rini <trini@ti.com>2012-12-11 20:17:30 (GMT)
commitaff36ea92ec0700cd9241bf01e72956a3ab9600e (patch)
tree407ce5d73e7c38787f55b7278d2d1b47bd288b6d
parenta157e0d5f6aa0b86bd7b6ae09d11b12a4a736d97 (diff)
downloadu-boot-aff36ea92ec0700cd9241bf01e72956a3ab9600e.tar.xz
i2c: mxs: Fix TIMING2 register value
According to FSL, the value in the TIMING2 register shall be 0x00300030 instead of what's written in the datasheet. This new value correlates with older STMP36xx datasheet. Issues were detected in Linux when this register was misconfigured, so write this correct value. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
-rw-r--r--drivers/i2c/mxs_i2c.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/i2c/mxs_i2c.c b/drivers/i2c/mxs_i2c.c
index 3771452..006fb91 100644
--- a/drivers/i2c/mxs_i2c.c
+++ b/drivers/i2c/mxs_i2c.c
@@ -267,8 +267,8 @@ int i2c_set_bus_speed(unsigned int speed)
writel(spd->timing0, &i2c_regs->hw_i2c_timing0);
writel(spd->timing1, &i2c_regs->hw_i2c_timing1);
- writel((0x0015 << I2C_TIMING2_BUS_FREE_OFFSET) |
- (0x000d << I2C_TIMING2_LEADIN_COUNT_OFFSET),
+ writel((0x0030 << I2C_TIMING2_BUS_FREE_OFFSET) |
+ (0x0030 << I2C_TIMING2_LEADIN_COUNT_OFFSET),
&i2c_regs->hw_i2c_timing2);
return 0;