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| author | Rajesh Bhagat <rajesh.bhagat@nxp.com> | 2017-11-30 06:30:55 (GMT) |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2018-01-18 05:29:08 (GMT) |
| commit | d0d1638952c85878c40b6cbb10adccb316d818ac (patch) | |
| tree | 624192ccb70f80ee0cca8e7f87c19413ff2b3398 | |
| parent | 55540f32f937416ae2e1879663d354a264939584 (diff) | |
| download | u-boot-d0d1638952c85878c40b6cbb10adccb316d818ac.tar.xz | |
ls1088a: ddr: configure DDR for 0.9v for VID support
When VID feature is supported, check the contents of fuse register
and configure DDR operate at 0.9v.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
| -rw-r--r-- | board/freescale/ls1088a/ddr.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/board/freescale/ls1088a/ddr.c b/board/freescale/ls1088a/ddr.c index e24bfd5..f3e70b5 100644 --- a/board/freescale/ls1088a/ddr.c +++ b/board/freescale/ls1088a/ddr.c @@ -13,6 +13,23 @@ DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) +void fsl_ddr_setup_0v9_volt(memctl_options_t *popts) +{ + int vdd; + + vdd = get_core_volt_from_fuse(); + /* Nothing to do for silicons doesn't support VID */ + if (vdd < 0) + return; + + if (vdd == 900) { + popts->ddr_cdr1 |= DDR_CDR1_V0PT9_EN; + printf("VID: configure DDR to support 900 mV\n"); + } +} +#endif + void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) @@ -87,6 +104,10 @@ found: popts->addr_hash = 1; popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); +#if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) + fsl_ddr_setup_0v9_volt(popts); +#endif + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2; } |