diff options
| author | Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> | 2018-01-17 08:59:21 (GMT) |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2018-01-19 10:18:55 (GMT) |
| commit | ec53bd983a19de1fe16050b1b26b381e412b42d9 (patch) | |
| tree | e11068f836127e5fd1af6298998fdfbf0014c49f | |
| parent | cce1563af8889e14469642e926b6990a9132c2e0 (diff) | |
| download | u-boot-ec53bd983a19de1fe16050b1b26b381e412b42d9.tar.xz | |
board: ls1012a: update mdio, phy parameters based on serdes protocol
mdio bus and phy-id needs to be configured based on serdes protocol
3508, 2208 selected via RCW.
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
| -rw-r--r-- | board/freescale/ls1012ardb/eth.c | 44 |
1 files changed, 34 insertions, 10 deletions
diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c index b1fc5fa..572c674 100644 --- a/board/freescale/ls1012ardb/eth.c +++ b/board/freescale/ls1012ardb/eth.c @@ -40,9 +40,14 @@ int board_eth_init(bd_t *bis) #ifdef CONFIG_FSL_PFE struct mii_dev *bus; struct mdio_info mac1_mdio_info; + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; reset_phy(); + int srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + init_pfe_scfg_dcfg_regs(); mac1_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR; @@ -54,16 +59,35 @@ int board_eth_init(bd_t *bis) return -1; } - /* MAC1 */ - pfe_set_mdio(0, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME)); - pfe_set_phy_address_mode(0, EMAC1_PHY_ADDR, - PHY_INTERFACE_MODE_SGMII); - - /* MAC2 */ - pfe_set_mdio(1, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME)); - pfe_set_phy_address_mode(1, EMAC2_PHY_ADDR, - PHY_INTERFACE_MODE_RGMII_TXID); - + switch (srds_s1) { + case 0x3508: + /* MAC1 */ + pfe_set_mdio(0, miiphy_get_dev_by_name( + DEFAULT_PFE_MDIO_NAME)); + pfe_set_phy_address_mode(0, EMAC1_PHY_ADDR, + PHY_INTERFACE_MODE_SGMII); + /* MAC2 */ + pfe_set_mdio(1, miiphy_get_dev_by_name( + DEFAULT_PFE_MDIO_NAME)); + pfe_set_phy_address_mode(1, EMAC2_PHY_ADDR, + PHY_INTERFACE_MODE_RGMII_TXID); + break; + case 0x2208: + /* MAC1 */ + pfe_set_mdio(0, miiphy_get_dev_by_name( + DEFAULT_PFE_MDIO_NAME)); + pfe_set_phy_address_mode(0, EMAC1_PHY_ADDR, + PHY_INTERFACE_MODE_SGMII_2500); + /* MAC2 */ + pfe_set_mdio(1, miiphy_get_dev_by_name( + DEFAULT_PFE_MDIO_NAME)); + pfe_set_phy_address_mode(1, EMAC2_PHY_ADDR, + PHY_INTERFACE_MODE_SGMII_2500); + break; + default: + printf("unsupported SerDes PRCTL= %d\n", srds_s1); + break; + } cpu_eth_init(bis); #endif return pci_eth_init(bis); |