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| author | Stephen Warren <swarren@nvidia.com> | 2015-02-24 21:08:27 (GMT) |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2015-03-04 17:09:00 (GMT) |
| commit | b2cd3d810387095e525522de6cae2716f4c20870 (patch) | |
| tree | 83a0c0ba0d23cb01a7bfa72bb9c9b6b8cb3dc94b | |
| parent | bc13472867beaf350b569a98c49a102476537e4f (diff) | |
| download | u-boot-b2cd3d810387095e525522de6cae2716f4c20870.tar.xz | |
ARM: tegra: pinmux: partially handle varying register layouts
Tegra210 moves some bits around in the pinmux registers. Update the code
to handle this.
This doesn't attempt to address the issues with the group-to-group varying
drive group register layout mentioned earlier. This patch handles the
SoC-to-SoC differences in the mux register layout.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/pinmux-common.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c index 843c688..1730d20 100644 --- a/arch/arm/mach-tegra/pinmux-common.c +++ b/arch/arm/mach-tegra/pinmux-common.c @@ -101,11 +101,23 @@ #define DRV_REG(group) _R(0x868 + ((group) * 4)) +/* + * We could force arch-tegraNN/pinmux.h to define all of these. However, + * that's a lot of defines, and for now it's manageable to just put a + * special case here. It's possible this decision will change with future + * SoCs. + */ +#ifdef CONFIG_TEGRA210 +#define IO_SHIFT 6 +#define LOCK_SHIFT 7 +#define OD_SHIFT 11 +#else #define IO_SHIFT 5 #define OD_SHIFT 6 #define LOCK_SHIFT 7 #define IO_RESET_SHIFT 8 #define RCV_SEL_SHIFT 9 +#endif #ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING /* This register/field only exists on Tegra114 and later */ |