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authorMarek Vasut <marex@denx.de>2015-08-19 05:46:49 (GMT)
committerMarek Vasut <marex@denx.de>2015-08-23 09:56:21 (GMT)
commit29aa439759ed2e5dfa45cd8d6d5a1d51604e3820 (patch)
treebfda5c57dc97c8c8f49849e572ef649ebaa2b1f5 /api
parent9238b52abd788cf4c2311896a5ada34ecff5499c (diff)
downloadu-boot-29aa439759ed2e5dfa45cd8d6d5a1d51604e3820.tar.xz
arm: socfpga: Fix ArriaV SoCDK PLL config
Pull out the ArriaV SoCDK clock config from ancient Altera U-Boot "rel_socfpga_v2013.01.01_15.05.01_pr" and implant those values into mainline to get a booting ArriaV SoCDK. Signed-off-by: Marek Vasut <marex@denx.de>
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