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| author | Alexey Brodkin <abrodkin@synopsys.com> | 2016-06-08 05:04:03 (GMT) |
|---|---|---|
| committer | Alexey Brodkin <abrodkin@synopsys.com> | 2016-06-13 12:38:05 (GMT) |
| commit | a4a43fcf9cca1ebd3d26f9a01b923b7393d69c54 (patch) | |
| tree | 0195cdd23b61125ac21e0bdbb3fbeaea75794da3 /arch/arc | |
| parent | bd91508b50ade5c73b3749bf4e5ede31d2da7ef8 (diff) | |
| download | u-boot-a4a43fcf9cca1ebd3d26f9a01b923b7393d69c54.tar.xz | |
arc/cache: Flush & invalidate all caches right before enabling IOC
According to ARC HS databook it is required to flush and disable
caches prior programming IOC registers. Otherwise ongoing coherent
memory operations may not observe the coherency protocols as
expected.
But since in ARC HS v2.1 there's no way to disable SLC (AKA L2 cache)
we're doing our best flushing and invalidating it.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Diffstat (limited to 'arch/arc')
| -rw-r--r-- | arch/arc/lib/cache.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index a27499e..b6ec831 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -209,6 +209,9 @@ void cache_init(void) read_decode_cache_bcr_arcv2(); if (ioc_exists) { + flush_dcache_all(); + invalidate_dcache_all(); + /* IO coherency base - 0x8z */ write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, 0x80000); /* IO coherency aperture size - 512Mb: 0x8z-0xAz */ |