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| author | Bo Shen <voice.shen@atmel.com> | 2012-07-05 17:21:46 (GMT) |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-09-01 12:58:14 (GMT) |
| commit | f7fa2f3740083bbdf9f57b0e0495eb07899db5e8 (patch) | |
| tree | 549c9794154e0fda6a6618491ce4e74d4b235c06 /arch/arm/cpu/arm926ejs/at91/clock.c | |
| parent | 963333e92c30c3321b80ec7953ca7fa64a707a02 (diff) | |
| download | u-boot-f7fa2f3740083bbdf9f57b0e0495eb07899db5e8.tar.xz | |
arm : Atmel : add at91sam9x5ek board support
Add at91sam9x5ek board support, this board support the following SoCs
AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, AT91SAM9X25, AT91SAM9X35
Using at91sam9x5ek_nandflash to configure for the board
Now only supports NAND with software ECC boot up
Signed-off-by: Bo Shen <voice.shen@atmel.com>
[move MAINTAINERS entry to right place]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Diffstat (limited to 'arch/arm/cpu/arm926ejs/at91/clock.c')
| -rw-r--r-- | arch/arm/cpu/arm926ejs/at91/clock.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/cpu/arm926ejs/at91/clock.c index a7085de..dc5c6c4 100644 --- a/arch/arm/cpu/arm926ejs/at91/clock.c +++ b/arch/arm/cpu/arm926ejs/at91/clock.c @@ -154,7 +154,8 @@ int at91_clock_init(unsigned long main_clock) * For now, assume this parentage won't change. */ mckr = readl(&pmc->mckr); -#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) +#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \ + || defined(CONFIG_AT91SAM9X5) /* plla divisor by 2 */ gd->plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12)); #endif @@ -168,7 +169,14 @@ int at91_clock_init(unsigned long main_clock) freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq; if (mckr & AT91_PMC_MCKR_MDIV_MASK) freq /= 2; /* processor clock division */ -#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) +#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \ + || defined(CONFIG_AT91SAM9X5) + /* mdiv <==> divisor + * 0 <==> 1 + * 1 <==> 2 + * 2 <==> 4 + * 3 <==> 3 + */ gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) == (AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4) ? freq / 3 |