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authorSimon Glass <sjg@chromium.org>2012-12-13 20:48:33 (GMT)
committerTom Rini <trini@ti.com>2013-02-01 20:07:50 (GMT)
commit8ff43b03e9f38a6e136e2e20eec4e8b2eb4a1d3d (patch)
tree15e1efcbbead4e7612e8b084f9fcee4f0d5e2bd1 /arch/arm/cpu/arm926ejs
parentb339051c0d45599c3c874141c52d912d78991dd4 (diff)
downloadu-boot-8ff43b03e9f38a6e136e2e20eec4e8b2eb4a1d3d.tar.xz
arm: Move tbu to arch_global_data
Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/cpu/arm926ejs')
-rw-r--r--arch/arm/cpu/arm926ejs/armada100/timer.c12
-rw-r--r--arch/arm/cpu/arm926ejs/at91/timer.c6
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/timer.c4
-rw-r--r--arch/arm/cpu/arm926ejs/pantheon/timer.c12
4 files changed, 17 insertions, 17 deletions
diff --git a/arch/arm/cpu/arm926ejs/armada100/timer.c b/arch/arm/cpu/arm926ejs/armada100/timer.c
index 355cd6d..18ffd0c 100644
--- a/arch/arm/cpu/arm926ejs/armada100/timer.c
+++ b/arch/arm/cpu/arm926ejs/armada100/timer.c
@@ -61,7 +61,7 @@ struct armd1tmr_registers {
#define COUNT_RD_REQ 0x1
DECLARE_GLOBAL_DATA_PTR;
-/* Using gd->tbu from timestamp and gd->tbl for lastdec */
+/* Using gd->arch.tbu from timestamp and gd->tbl for lastdec */
/* For preventing risk of instability in reading counter value,
* first set read request to register cvwr and then read same
@@ -84,14 +84,14 @@ ulong get_timer_masked(void)
if (now >= gd->tbl) {
/* normal mode */
- gd->tbu += now - gd->tbl;
+ gd->arch.tbu += now - gd->tbl;
} else {
/* we have an overflow ... */
- gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
+ gd->arch.tbu += now + TIMER_LOAD_VAL - gd->tbl;
}
gd->tbl = now;
- return gd->tbu;
+ return gd->arch.tbu;
}
ulong get_timer(ulong base)
@@ -135,9 +135,9 @@ int timer_init(void)
/* Enable timer 0 */
writel(0x1, &armd1timers->cer);
- /* init the gd->tbu and gd->tbl value */
+ /* init the gd->arch.tbu and gd->tbl value */
gd->tbl = read_timer();
- gd->tbu = 0;
+ gd->arch.tbu = 0;
return 0;
}
diff --git a/arch/arm/cpu/arm926ejs/at91/timer.c b/arch/arm/cpu/arm926ejs/at91/timer.c
index 061ccaf..f691518 100644
--- a/arch/arm/cpu/arm926ejs/at91/timer.c
+++ b/arch/arm/cpu/arm926ejs/at91/timer.c
@@ -80,7 +80,7 @@ int timer_init(void)
writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
- gd->tbu = gd->tbl = 0;
+ gd->arch.tbu = gd->tbl = 0;
return 0;
}
@@ -96,9 +96,9 @@ unsigned long long get_ticks(void)
/* increment tbu if tbl has rolled over */
if (now < gd->tbl)
- gd->tbu++;
+ gd->arch.tbu++;
gd->tbl = now;
- return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
+ return (((unsigned long long)gd->arch.tbu) << 32) | gd->tbl;
}
void __udelay(unsigned long usec)
diff --git a/arch/arm/cpu/arm926ejs/davinci/timer.c b/arch/arm/cpu/arm926ejs/davinci/timer.c
index 7e852b5..e28e6e3 100644
--- a/arch/arm/cpu/arm926ejs/davinci/timer.c
+++ b/arch/arm/cpu/arm926ejs/davinci/timer.c
@@ -75,10 +75,10 @@ unsigned long long get_ticks(void)
/* increment tbu if tbl has rolled over */
if (now < gd->tbl)
- gd->tbu++;
+ gd->arch.tbu++;
gd->tbl = now;
- return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
+ return (((unsigned long long)gd->arch.tbu) << 32) | gd->tbl;
}
ulong get_timer(ulong base)
diff --git a/arch/arm/cpu/arm926ejs/pantheon/timer.c b/arch/arm/cpu/arm926ejs/pantheon/timer.c
index 28aadad..701d439 100644
--- a/arch/arm/cpu/arm926ejs/pantheon/timer.c
+++ b/arch/arm/cpu/arm926ejs/pantheon/timer.c
@@ -60,7 +60,7 @@ struct panthtmr_registers {
#define COUNT_RD_REQ 0x1
DECLARE_GLOBAL_DATA_PTR;
-/* Using gd->tbu from timestamp and gd->tbl for lastdec */
+/* Using gd->arch.tbu from timestamp and gd->tbl for lastdec */
/*
* For preventing risk of instability in reading counter value,
@@ -92,14 +92,14 @@ ulong get_timer_masked(void)
if (now >= gd->tbl) {
/* normal mode */
- gd->tbu += now - gd->tbl;
+ gd->arch.tbu += now - gd->tbl;
} else {
/* we have an overflow ... */
- gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
+ gd->arch.tbu += now + TIMER_LOAD_VAL - gd->tbl;
}
gd->tbl = now;
- return gd->tbu;
+ return gd->arch.tbu;
}
ulong get_timer(ulong base)
@@ -144,9 +144,9 @@ int timer_init(void)
/* Enable timer 0 */
writel(0x1, &panthtimers->cer);
- /* init the gd->tbu and gd->tbl value */
+ /* init the gd->arch.tbu and gd->tbl value */
gd->tbl = read_timer();
- gd->tbu = 0;
+ gd->arch.tbu = 0;
return 0;
}