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| author | Chandan Nath <chandan.nath@ti.com> | 2012-01-09 20:38:59 (GMT) |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-01-16 07:40:12 (GMT) |
| commit | 8a8f084e4ffa0e2357790cd92b69301eaeb2834d (patch) | |
| tree | f29a8f6bb0d33ec4041d64f761623f4215fe8417 /arch/arm/cpu/armv7/am33xx/board.c | |
| parent | 876bdd6d460cfcb7dc3b3c52291e20d322a939d5 (diff) | |
| download | u-boot-8a8f084e4ffa0e2357790cd92b69301eaeb2834d.tar.xz | |
ARM:AM33XX: Add SPL support for AM335X EVM
This patch is added to support SPL feature on AM335X
platform. In this patch, MMC1 is configured as boot
device for SPL and support for other devices will be
added in the next patch series.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Diffstat (limited to 'arch/arm/cpu/armv7/am33xx/board.c')
| -rw-r--r-- | arch/arm/cpu/armv7/am33xx/board.c | 51 |
1 files changed, 47 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 312643c..d64ae69 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -19,19 +19,31 @@ #include <common.h> #include <asm/arch/cpu.h> #include <asm/arch/hardware.h> +#include <asm/arch/omap.h> #include <asm/arch/ddr_defs.h> #include <asm/arch/clock.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/common_def.h> #include <asm/io.h> +#include <asm/omap_common.h> DECLARE_GLOBAL_DATA_PTR; struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE; +struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; + +/* UART Defines */ +#ifdef CONFIG_SPL_BUILD +#define UART_RESET (0x1 << 1) +#define UART_CLK_RUNNING_MASK 0x1 +#define UART_SMART_IDLE_EN (0x1 << 0x3) +#endif /* * early system init of muxing and clocks. */ -void s_init(u32 in_ddr) +void s_init(void) { /* WDT1 is already running when the bootloader gets control * Disable it to avoid "random" resets @@ -43,12 +55,37 @@ void s_init(u32 in_ddr) while (readl(&wdtimer->wdtwwps) != 0x0) ; +#ifdef CONFIG_SPL_BUILD /* Setup the PLLs and the clocks for the peripherals */ -#ifdef CONFIG_SETUP_PLL pll_init(); + + /* UART softreset */ + u32 regVal; + + enable_uart0_pin_mux(); + + regVal = readl(&uart_base->uartsyscfg); + regVal |= UART_RESET; + writel(regVal, &uart_base->uartsyscfg); + while ((readl(&uart_base->uartsyssts) & + UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) + ; + + /* Disable smart idle */ + regVal = readl(&uart_base->uartsyscfg); + regVal |= UART_SMART_IDLE_EN; + writel(regVal, &uart_base->uartsyscfg); + + /* Initialize the Timer */ + init_timer(); + + preloader_console_init(); + + config_ddr(); #endif - if (!in_ddr) - config_ddr(); + + /* Enable MMC0 */ + enable_mmc0_pin_mux(); } /* Initialize timer */ @@ -71,3 +108,9 @@ int board_mmc_init(bd_t *bis) return omap_mmc_init(0); } #endif + +void setup_clocks_for_console(void) +{ + /* Not yet implemented */ + return; +} |