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| author | Tom Rini <trini@ti.com> | 2012-07-30 18:49:47 (GMT) |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-09-01 12:58:13 (GMT) |
| commit | a74f0c7cb505d3e2184bfd2ab42c3a6e45a1d54a (patch) | |
| tree | 23885e01becaecb7258d20cb9077c4831877539f /arch/arm/cpu/armv7/am33xx/emif4.c | |
| parent | 82afcc9efd4a734f550381fab311644de2c4c524 (diff) | |
| download | u-boot-a74f0c7cb505d3e2184bfd2ab42c3a6e45a1d54a.tar.xz | |
am33xx: Correct and clean up ddr_regs struct
The ddr_regs struct was incorrectly offset after the dt0wiratio0 entry.
Correct this by documenting a missing register that will be used at some
point in the future (when write leveling is supported). Further, the
cmdNcs{force,delay} fields are undocumented and we have been setting
them to zero, remove. Next, setting of the
'DATAn_REG_PHY_USE_RANK0_DELAYS field belongs with the rest of the
ddr_data entries, so program it there. Finally, comment on how we are
configuring the DATA1 registers that correspond to the DATA0 (dt0)
registers defined in the struct.
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/am33xx/emif4.c')
| -rw-r--r-- | arch/arm/cpu/armv7/am33xx/emif4.c | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index ace3d26..3bb91d3 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -61,25 +61,20 @@ static const struct ddr_data ddr2_data = { |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)), .datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20) |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)), + .datauserank0delay = DDR2_PHY_RANK0_DELAY, .datadldiff0 = PHY_DLL_LOCK_DIFF, }; static const struct cmd_control ddr2_cmd_ctrl_data = { .cmd0csratio = DDR2_RATIO, - .cmd0csforce = CMD_FORCE, - .cmd0csdelay = CMD_DELAY, .cmd0dldiff = DDR2_DLL_LOCK_DIFF, .cmd0iclkout = DDR2_INVERT_CLKOUT, .cmd1csratio = DDR2_RATIO, - .cmd1csforce = CMD_FORCE, - .cmd1csdelay = CMD_DELAY, .cmd1dldiff = DDR2_DLL_LOCK_DIFF, .cmd1iclkout = DDR2_INVERT_CLKOUT, .cmd2csratio = DDR2_RATIO, - .cmd2csforce = CMD_FORCE, - .cmd2csdelay = CMD_DELAY, .cmd2dldiff = DDR2_DLL_LOCK_DIFF, .cmd2iclkout = DDR2_INVERT_CLKOUT, }; @@ -121,9 +116,6 @@ void config_ddr(short ddr_type) config_ddr_data(0, &ddr2_data); config_ddr_data(1, &ddr2_data); - writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt0rdelays0); - writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt1rdelays0); - config_io_ctrl(DDR2_IOCTRL_VALUE); /* Set CKE to be controlled by EMIF/DDR PHY */ |