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authorChandan Nath <chandan.nath@ti.com>2011-10-14 02:58:22 (GMT)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2011-10-27 19:56:36 (GMT)
commit5655108a8215123bac7154f64c29109fd63d86be (patch)
tree831db55068a11dc32379d6d0113cd9c170d80cd8 /arch/arm/cpu/armv7/am33xx
parent40b95c8956d4125e36a864c673616fa98247d5e1 (diff)
downloadu-boot-5655108a8215123bac7154f64c29109fd63d86be.tar.xz
ARM:AM33XX: Added support for AM33xx
This patch adds basic support for AM33xx which is based on ARMV7 Cortex A8 CPU. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/am33xx')
-rw-r--r--arch/arm/cpu/armv7/am33xx/Makefile44
-rw-r--r--arch/arm/cpu/armv7/am33xx/lowlevel_init.S72
-rw-r--r--arch/arm/cpu/armv7/am33xx/sys_info.c130
3 files changed, 246 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile
new file mode 100644
index 0000000..498df78
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -0,0 +1,44 @@
+#
+# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed "as is" WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+SOBJS := lowlevel_init.o
+
+COBJS += sys_info.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/am33xx/lowlevel_init.S b/arch/arm/cpu/armv7/am33xx/lowlevel_init.S
new file mode 100644
index 0000000..17c962f
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/lowlevel_init.S
@@ -0,0 +1,72 @@
+/*
+ * lowlevel_init.S
+ *
+ * AM33XX low level initialization.
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * Initial Code by:
+ * Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <config.h>
+#include <asm/arch/hardware.h>
+
+_mark1:
+ .word mark1
+_lowlevel_init1:
+ .word lowlevel_init
+_s_init_start:
+ .word s_init_start
+
+_TEXT_BASE:
+ .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
+
+/*****************************************************************************
+ * lowlevel_init: - Platform low level init.
+ ****************************************************************************/
+.globl lowlevel_init
+lowlevel_init:
+
+ /* The link register is saved in ip by start.S */
+ mov r6, ip
+ /* check if we are already running from RAM */
+ ldr r2, _lowlevel_init1
+ ldr r3, _TEXT_BASE
+ sub r4, r2, r3
+ sub r0, pc, r4
+ ldr sp, SRAM_STACK
+mark1:
+ ldr r5, _mark1
+ sub r5, r5, r2 /* bytes between mark1 and lowlevel_init */
+ sub r0, r0, r5 /* r0 <- _start w.r.t current place of execution */
+ mov r10, #0x0 /* r10 has in_ddr used by s_init() */
+
+ ands r0, r0, #0xC0000000
+ /* MSB 2 bits <> 0 then we are in ocmc or DDR */
+ cmp r0, #0x80000000
+ bne s_init_start
+ mov r10, #0x01
+ b s_init_start
+
+s_init_start:
+ mov r0, r10 /* passing in_ddr in r0 */
+ bl s_init
+ /* back to arch calling code */
+ mov pc, r6
+ /* the literal pools origin */
+ .ltorg
+
+SRAM_STACK:
+ /* Place stack at the top */
+ .word LOW_LEVEL_SRAM_STACK
diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c b/arch/arm/cpu/armv7/am33xx/sys_info.c
new file mode 100644
index 0000000..507b618
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/sys_info.c
@@ -0,0 +1,130 @@
+/*
+ * sys_info.c
+ *
+ * System information functions
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+
+struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
+
+/**
+ * get_cpu_rev(void) - extract rev info
+ */
+u32 get_cpu_rev(void)
+{
+ u32 id;
+ u32 rev;
+
+ id = readl(DEVICE_ID);
+ rev = (id >> 28) & 0xff;
+
+ return rev;
+}
+
+/**
+ * get_cpu_type(void) - extract cpu info
+ */
+u32 get_cpu_type(void)
+{
+ u32 id = 0;
+ u32 partnum;
+
+ id = readl(DEVICE_ID);
+ partnum = (id >> 12) & 0xffff;
+
+ return partnum;
+}
+
+/**
+ * get_board_rev() - setup to pass kernel board revision information
+ * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
+ */
+u32 get_board_rev(void)
+{
+ return BOARD_REV_ID;
+}
+
+/**
+ * get_device_type(): tell if GP/HS/EMU/TST
+ */
+u32 get_device_type(void)
+{
+ int mode;
+ mode = readl(&cstat->statusreg) & (DEVICE_MASK);
+ return mode >>= 8;
+}
+
+/**
+ * get_sysboot_value(void) - return SYS_BOOT[4:0]
+ */
+u32 get_sysboot_value(void)
+{
+ int mode;
+ mode = readl(&cstat->statusreg) & (SYSBOOT_MASK);
+ return mode;
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+/**
+ * Print CPU information
+ */
+int print_cpuinfo(void)
+{
+ char *cpu_s, *sec_s;
+ int arm_freq, ddr_freq;
+
+ switch (get_cpu_type()) {
+ case AM335X:
+ cpu_s = "AM335X";
+ break;
+ default:
+ cpu_s = "Unknown cpu type";
+ break;
+ }
+
+ switch (get_device_type()) {
+ case TST_DEVICE:
+ sec_s = "TST";
+ break;
+ case EMU_DEVICE:
+ sec_s = "EMU";
+ break;
+ case HS_DEVICE:
+ sec_s = "HS";
+ break;
+ case GP_DEVICE:
+ sec_s = "GP";
+ break;
+ default:
+ sec_s = "?";
+ }
+
+ printf("AM%s-%s rev %d\n",
+ cpu_s, sec_s, get_cpu_rev());
+
+ /* TODO: Print ARM and DDR frequencies */
+
+ return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */