Exynos542x: add L2 control register configuration

This patch does 3 things:
1. Enables ECC by setting 21st bit of L2CTLR.
2. Restore data and tag RAM latencies to 3 cycles because iROM sets
   0x3000400 L2CTLR value during switching.
3. Disable clean/evict push to external by setting 3rd bit of L2ACTLR.
   We need to restore this here due to switching.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

1 files changed, 50 insertions, 1 deletions

diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
index b94e49f..0504576 100644
--- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
+++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
@@ -47,6 +47,42 @@ enum {
 
 #ifdef CONFIG_EXYNOS5420
 /*
+ * Enable ECC by setting L2CTLR[21].
+ * Set L2CTLR[7] to make tag ram latency 3 cycles and
+ * set L2CTLR[1] to make data ram latency 3 cycles.
+ * We need to make RAM latency of 3 cycles here because cores
+ * power ON and OFF while switching. And everytime a core powers
+ * ON, iROM provides it a default L2CTLR value 0x400 which stands
+ * for TAG RAM setup of 1 cycle. Hence, we face a need of
+ * restoring data and tag latency values.
+ */
+static void configure_l2_ctlr(void)
+{
+	uint32_t val;
+
+	mrc_l2_ctlr(val);
+	val |= (1 << 21);
+	val |= (1 << 7);
+	val |= (1 << 1);
+	mcr_l2_ctlr(val);
+}
+
+/*
+ * Set L2ACTLR[27] to prevent the clock generator from stopping
+ * the L2 logic clock.
+ * Set L2ACTLR[3] to disable clean/evict push to external.
+ */
+static void configure_l2_actlr(void)
+{
+	uint32_t val;
+
+	mrc_l2_aux_ctlr(val);
+	val |= (1 << 27);
+	val |= (1 << 3);
+	mcr_l2_aux_ctlr(val);
+}
+
+/*
  * Power up secondary CPUs.
  */
 static void secondary_cpu_start(void)
@@ -80,7 +116,19 @@ static void low_power_start(void)
 
 	/* Set the CPU to SVC32 mode */
 	svc32_mode_en();
-	v7_enable_l2_hazard_detect();
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+	/* Read MIDR for Primary Part Number */
+	mrc_midr(val);
+	val = (val >> 4);
+	val &= 0xf;
+
+	if (val == 0xf) {
+		configure_l2_ctlr();
+		configure_l2_actlr();
+		v7_enable_l2_hazard_detect();
+	}
+#endif
 
 	/* Invalidate L1 & TLB */
 	val = 0x0;
@@ -138,6 +186,7 @@ static void power_down_core(void)
 static void secondary_cores_configure(void)
 {
 	/* Setup L2 cache */
+	configure_l2_ctlr();
 	v7_enable_l2_hazard_detect();
 
 	/* Clear secondary boot iRAM base */